[AArch64] Omit SEH directives for the epilogue if none are needed

[mstorsjo]

Summary

For these cases, we already omit the prologue directives, if (!AFI->hasStackFrame() && !windowsRequiresStackProbe && !NumBytes).

When writing the epilogue (after the prolog has been written), if the function doesn't have the WinCFI flag set (i.e. if no prologue was generated), assume that no epilogue will be needed either, and don't emit any epilog start pseudo instruction. After completing the epilogue, make sure that we end up with matching epilog start/end.

Previously, when epilog start/end was generated, but no prologue, the unwind info for such functions actually was huge; 12 bytes xdata (4 bytes header, 4 bytes for one non-folded epilogue, 4 bytes for padded opcodes) and 8 bytes pdata. Because the epilog consisted of one opcode (end) but the prolog was empty (no .seh_endprologue), the epilogue couldn't be folded into the prologue, and thus couldn't be considered for packed form either.

On a 6.5 MB DLL with 110 KB pdata and 166 KB xdata, this gets rid of 38 KB pdata and 62 KB xdata.

[mstorsjo]

llvm/lib/Target/AArch64/AArch64FrameLowering.cpp

1641

I guess an alternative, assert-less approach, would be not to set HaveWinCFI here, and remove the EpilogStart at the end, if it turns out not to be needed.

[efriedma]

That explains what was happening in llvm/test/CodeGen/AArch64/lround-conv-fp16-win.ll etc.

llvm/lib/Target/AArch64/AArch64FrameLowering.cpp

1527

Not sure the HasEpilogStart boolean is useful here; could you just assert(HasWinCFI == MF.hasWinCFI())? And we shouldn't ever need to call setHasWinCFI().

1634

Simplify to if (MF.hasWinCFI()) {?

1734

Simplify this to if (HasWinCFI) {?

[mstorsjo]

llvm/lib/Target/AArch64/AArch64FrameLowering.cpp

1527

Right, that'd behave equivalently in the end - will try such a change.

[mstorsjo]

Simplified the assert and conditionals.

[efriedma]

LGTM

llvm/lib/Target/AArch64/AArch64FrameLowering.cpp

void AArch64FrameLowering::emitEpilogue(MachineFunction &MF,
   MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
   MachineFrameInfo &MFI = MF.getFrameInfo();
   const AArch64Subtarget &Subtarget = MF.getSubtarget<AArch64Subtarget>();
   const TargetInstrInfo *TII = Subtarget.getInstrInfo();
   DebugLoc DL;
   bool NeedsWinCFI = needsWinCFI(MF);
   bool HasWinCFI = false;
   bool IsFunclet = false;
-  auto WinCFI = make_scope_exit([&]() {
-    if (!MF.hasWinCFI())
-      MF.setHasWinCFI(HasWinCFI);
-  });
+  auto WinCFI = make_scope_exit([&]() { assert(HasWinCFI == MF.hasWinCFI()); });
 
   if (MBB.end() != MBBI) {
     DL = MBBI->getDebugLoc();
     IsFunclet = isFuncletReturnInstr(*MBBI);
   }
 
   int64_t NumBytes = IsFunclet ? getWinEHFuncletFrameSize(MF)
                                : MFI.getStackSize();
if (!LastPopI->getFlag(MachineInstr::FrameDestroy) ||
         IsSVECalleeSave(LastPopI)) {
       ++LastPopI;
       break;
     } else if (CombineSPBump)
       fixupCalleeSaveRestoreStackOffset(*LastPopI, AFI->getLocalStackSize(),
                                         NeedsWinCFI, &HasWinCFI);
   }
 
-  if (NeedsWinCFI) {
+  if (MF.hasWinCFI()) {
+    // If the prologue didn't contain any SEH opcodes and didn't set the
+    // MF.hasWinCFI() flag, assume the epilogue won't either, and skip the
+    // EpilogStart - to avoid generating CFI for functions that don't need it.
+    // (And as we didn't generate any prologue at all, it would be assymetrical
+    // to the epilogue.) By the end of the function, we assert that
+    // HasWinCFI is equal to MF.hasWinCFI(), to verify this assumption.
     HasWinCFI = true;
     BuildMI(MBB, LastPopI, DL, TII->get(AArch64::SEH_EpilogStart))
         .setMIFlag(MachineInstr::FrameDestroy);
   }
 
   const StackOffset &SVEStackSize = getSVEStackSize(MF);
 
   // If there is a single SP update, insert it before the ret and we're done.
   if (CombineSPBump) {
     assert(!SVEStackSize && "Cannot combine SP bump with SVE");
     emitFrameOffset(MBB, MBB.getFirstTerminator(), DL, AArch64::SP, AArch64::SP,
                     {NumBytes + (int64_t)AfterCSRPopSize, MVT::i8}, TII,
                     MachineInstr::FrameDestroy, false, NeedsWinCFI, &HasWinCFI);
-    if (NeedsWinCFI && HasWinCFI)
+    if (HasWinCFI)
       BuildMI(MBB, MBB.getFirstTerminator(), DL,
               TII->get(AArch64::SEH_EpilogEnd))
           .setMIFlag(MachineInstr::FrameDestroy);
     return;
   }
 
   NumBytes -= PrologueSaveSize;
   assert(NumBytes >= 0 && "Negative stack allocation size!?");
if (!hasFP(MF)) {
     // If we're done after this, make sure to help the load store optimizer.
     if (Done)
       adaptForLdStOpt(MBB, MBB.getFirstTerminator(), LastPopI);
 
     emitFrameOffset(MBB, LastPopI, DL, AArch64::SP, AArch64::SP,
                     {StackRestoreBytes, MVT::i8}, TII,
                     MachineInstr::FrameDestroy, false, NeedsWinCFI, &HasWinCFI);
     if (Done) {
-      if (NeedsWinCFI) {
-        HasWinCFI = true;
+      if (HasWinCFI) {
         BuildMI(MBB, MBB.getFirstTerminator(), DL,
                 TII->get(AArch64::SEH_EpilogEnd))
             .setMIFlag(MachineInstr::FrameDestroy);
       }
       return;
     }
 
     NumBytes = 0;
   }
 
   // Restore the original stack pointer.
   // FIXME: Rather than doing the math here, we should instead just use
   // non-post-indexed loads for the restores if we aren't actually going to
   // be able to save any instructions.
   if (!IsFunclet && (MFI.hasVarSizedObjects() || AFI->isStackRealigned())) {
     emitFrameOffset(MBB, LastPopI, DL, AArch64::SP, AArch64::FP,
if (AfterCSRPopSize) {
     }
 
     adaptForLdStOpt(MBB, FirstSPPopI, LastPopI);
 
     emitFrameOffset(MBB, FirstSPPopI, DL, AArch64::SP, AArch64::SP,
                     {(int64_t)AfterCSRPopSize, MVT::i8}, TII,
                     MachineInstr::FrameDestroy, false, NeedsWinCFI, &HasWinCFI);
   }
-  if (NeedsWinCFI && HasWinCFI)
+  if (HasWinCFI)
     BuildMI(MBB, MBB.getFirstTerminator(), DL, TII->get(AArch64::SEH_EpilogEnd))
         .setMIFlag(MachineInstr::FrameDestroy);
 }
 
 /// getFrameIndexReference - Provide a base+offset reference to an FI slot for
 /// debug info.  It's the same as what we use for resolving the code-gen
 /// references for now.  FIXME: This can go wrong when references are
 /// SP-relative and simple call frames aren't used.

llvm/test/CodeGen/AArch64/lrint-conv-fp16-win.ll

 ; RUN: llc < %s -mtriple=aarch64-windows -mattr=+fullfp16 | FileCheck %s
 
 ; CHECK-LABEL: testmhhs:
 ; CHECK:       frintx  h0, h0
 ; CHECK-NEXT:  fcvtzs  w0, h0
-; CHECK-NEXT:  .seh_startepilogue
-; CHECK-NEXT:  .seh_endepilogue
 ; CHECK-NEXT:  ret
 define i16 @testmhhs(half %x) {
 entry:
   %0 = tail call i32 @llvm.lrint.i32.f16(half %x)
   %conv = trunc i32 %0 to i16
   ret i16 %conv
 }
 
 ; CHECK-LABEL: testmhws:
 ; CHECK:       frintx  h0, h0
 ; CHECK-NEXT:  fcvtzs  w0, h0
-; CHECK-NEXT:  .seh_startepilogue
-; CHECK-NEXT:  .seh_endepilogue
 ; CHECK-NEXT:  ret
 define i32 @testmhws(half %x) {
 entry:
   %0 = tail call i32 @llvm.lrint.i32.f16(half %x)
   ret i32 %0
 }
 
 ; CHECK-LABEL: testmhxs:
 ; CHECK:       frintx  h0, h0
 ; CHECK-NEXT:  fcvtzs  w8, h0
 ; CHECK-NEXT:  sxtw    x0, w8
-; CHECK-NEXT:  .seh_startepilogue
-; CHECK-NEXT:  .seh_endepilogue
 ; CHECK-NEXT:  ret
 define i64 @testmhxs(half %x) {
 entry:
   %0 = tail call i32 @llvm.lrint.i32.f16(half %x)
   %conv = sext i32 %0 to i64
   ret i64 %conv
 }
 
 declare i32 @llvm.lrint.i32.f16(half) nounwind readnone

llvm/test/CodeGen/AArch64/lrint-conv-win.ll

 ; RUN: llc < %s -mtriple=aarch64-windows -mattr=+neon | FileCheck %s
 
 ; CHECK-LABEL: testmsxs:
 ; CHECK:       frintx  [[SREG:s[0-9]+]], s0
 ; CHECK-NEXT:  fcvtzs  [[WREG:w[0-9]+]], [[SREG]]
 ; CHECK-NEXT:  sxtw    x0, [[WREG]]
-; CHECK-NEXT:  .seh_startepilogue
-; CHECK-NEXT:  .seh_endepilogue
 ; CHECK-NEXT:  ret
 define i64 @testmsxs(float %x) {
 entry:
   %0 = tail call i32 @llvm.lrint.i32.f32(float %x)
   %conv = sext i32 %0 to i64
   ret i64 %conv
 }
 
 ; CHECK-LABEL: testmsws:
 ; CHECK:       frintx  [[SREG:s[0-9]+]], s0
 ; CHECK-NEXT:  fcvtzs  [[WREG:w[0-9]+]], [[SREG]]
-; CHECK-NEXT:  .seh_startepilogue
-; CHECK-NEXT:  .seh_endepilogue
 ; CHECK-NEXT:  ret
 define i32 @testmsws(float %x) {
 entry:
   %0 = tail call i32 @llvm.lrint.i32.f32(float %x)
   ret i32 %0
 }
 
 ; CHECK-LABEL: testmsxd:
 ; CHECK:       frintx  [[DREG:d[0-9]+]], d0
 ; CHECK-NEXT:  fcvtzs  [[WREG:w[0-9]+]], [[DREG]]
 ; CHECK-NEXT:  sxtw    x0, [[WREG]]
-; CHECK-NEXT:  .seh_startepilogue
-; CHECK-NEXT:  .seh_endepilogue
 ; CHECK-NEXT:  ret
 define i64 @testmsxd(double %x) {
 entry:
   %0 = tail call i32 @llvm.lrint.i32.f64(double %x)
   %conv = sext i32 %0 to i64
   ret i64 %conv
 }
 
 ; CHECK-LABEL: testmswd:
 ; CHECK:       frintx  [[DREG:d[0-9]+]], d0
 ; CHECK-NEXT:  fcvtzs  [[WREG:w[0-9]+]], [[DREG]]
-; CHECK-NEXT:  .seh_startepilogue
-; CHECK-NEXT:  .seh_endepilogue
 ; CHECK-NEXT:  ret
 define i32 @testmswd(double %x) {
 entry:
   %0 = tail call i32 @llvm.lrint.i32.f64(double %x)
   ret i32 %0
 }
 
 declare i32 @llvm.lrint.i32.f32(float) nounwind readnone
 declare i32 @llvm.lrint.i32.f64(double) nounwind readnone

llvm/test/CodeGen/AArch64/lround-conv-fp16-win.ll

 entry:
   %0 = tail call i32 @llvm.lround.i32.f16(half %x)
   ret i32 %0
 }
 
 ; CHECK-LABEL: testmhxs:
 ; CHECK:       fcvtas  w8, h0
 ; CHECK-NEXT:  sxtw    x0, w8
-; CHECK-NEXT:  .seh_startepilogue
-; CHECK-NEXT:  .seh_endepilogue
 ; CHECK-NEXT:  ret
 define i64 @testmhxs(half %x) {
 entry:
   %0 = tail call i32 @llvm.lround.i32.f16(half %x)
   %conv = sext i32 %0 to i64
   ret i64 %conv
 }
 
 declare i32 @llvm.lround.i32.f16(half) nounwind readnone

llvm/test/CodeGen/AArch64/lround-conv-win.ll

 ; RUN: llc < %s -mtriple=aarch64-windows -mattr=+neon | FileCheck %s
 
 ; CHECK-LABEL: testmsxs:
 ; CHECK:       fcvtas  w8, s0
 ; CHECK-NEXT:  sxtw    x0, w8
-; CHECK-NEXT:  .seh_startepilogue
-; CHECK-NEXT:  .seh_endepilogue
 ; CHECK-NEXT:  ret
 define i64 @testmsxs(float %x) {
 entry:
   %0 = tail call i32 @llvm.lround.i32.f32(float %x)
   %conv = sext i32 %0 to i64
   ret i64 %conv
 }
 
 ; CHECK-LABEL: testmsws:
 ; CHECK:       fcvtas  w0, s0
-; CHECK-NEXT:  .seh_startepilogue
-; CHECK-NEXT:  .seh_endepilogue
 ; CHECK-NEXT:  ret
 define i32 @testmsws(float %x) {
 entry:
   %0 = tail call i32 @llvm.lround.i32.f32(float %x)
   ret i32 %0
 }
 
 ; CHECK-LABEL: testmsxd:
 ; CHECK:       fcvtas  w8, d0
 ; CHECK-NEXT:  sxtw    x0, w8
-; CHECK-NEXT:  .seh_startepilogue
-; CHECK-NEXT:  .seh_endepilogue
 ; CHECK-NEXT:  ret
 define i64 @testmsxd(double %x) {
 entry:
   %0 = tail call i32 @llvm.lround.i32.f64(double %x)
   %conv = sext i32 %0 to i64
   ret i64 %conv
 }
 
 ; CHECK-LABEL: testmswd:
 ; CHECK:       fcvtas  w0, d0
-; CHECK-NEXT:  .seh_startepilogue
-; CHECK-NEXT:  .seh_endepilogue
 ; CHECK-NEXT:  ret
 define i32 @testmswd(double %x) {
 entry:
   %0 = tail call i32 @llvm.lround.i32.f64(double %x)
   ret i32 %0
 }
 
 declare i32 @llvm.lround.i32.f32(float) nounwind readnone
 declare i32 @llvm.lround.i32.f64(double) nounwind readnone

llvm/test/CodeGen/AArch64/powi-windows.ll

 ; RUN: llc -mtriple aarch64-windows < %s | FileCheck %s
 
 declare double @llvm.powi.f64(double, i32)
 declare float @llvm.powi.f32(float, i32)
 
 define double @d(double %d, i32 %i) {
 entry:
   %0 = tail call double @llvm.powi.f64(double %d, i32 %i)
   ret double %0
 }
 
 ; CHECK-LABEL: d:
 ; CHECK: scvtf d1, w0
-; CHECK-NEXT:  .seh_startepilogue
-; CHECK-NEXT:  .seh_endepilogue
 ; CHECK-NEXT: b pow
 
 define float @f(float %f, i32 %i) {
 entry:
   %0 = tail call float @llvm.powi.f32(float %f, i32 %i)
   ret float %0
 }
 
 ; CHECK-LABEL: f:
 ; CHECK: scvtf s1, w0
-; CHECK-NEXT:  .seh_startepilogue
-; CHECK-NEXT:  .seh_endepilogue
 ; CHECK-NEXT: b powf
 
 define float @g(double %d, i32 %i) {
 entry:
   %0 = tail call double @llvm.powi.f64(double %d, i32 %i)
   %conv = fptrunc double %0 to float
   ret float %conv
 }

llvm/test/CodeGen/AArch64/win64-nocfi.ll

 ; RUN: llc < %s -mtriple=aarch64-pc-windows-msvc | FileCheck %s
 
 define dso_local void @"?f@@YAXXZ"() nounwind sspstrong uwtable {
 ; CHECK-LABEL: f@@YAXXZ
 ; CHECK-NOT: .seh_proc
 ; CHECK-NOT: .seh_handlerdata
 ; CHECK-NOT: .seh_endproc
 entry:
   call void @llvm.trap()
   ret void
 }
 
 declare void @llvm.trap() noreturn nounwind 
+
+define dso_local i32 @getValue() nounwind sspstrong uwtable {
+; CHECK-LABEL: getValue
+; CHECK-NOT: .seh_proc
+; CHECK-NOT: .seh_endprologue
+; CHECK-NOT: .seh_startepilogue
+; CHECK-NOT: .seh_endepilogue
+; CHECK-NOT: .seh_endproc
+entry:
+  ret i32 42
+}

llvm/test/CodeGen/AArch64/win_cst_pool.ll

 ; RUN: llc < %s -mtriple=aarch64-win32-msvc | FileCheck %s
 ; RUN: llc < %s -mtriple=aarch64-win32-gnu | FileCheck -check-prefix=MINGW %s
 
 define double @double() {
   ret double 0x2000000000800001
 }
 ; CHECK:              .globl  __real@2000000000800001
 ; CHECK-NEXT:         .section        .rdata,"dr",discard,__real@2000000000800001
 ; CHECK-NEXT:         .p2align  3
 ; CHECK-NEXT: __real@2000000000800001:
 ; CHECK-NEXT:         .xword   0x2000000000800001
 ; CHECK:      double:
 ; CHECK:               adrp    x8, __real@2000000000800001
 ; CHECK-NEXT:          ldr     d0, [x8, __real@2000000000800001]
-; CHECK-NEXT:          .seh_startepilogue
-; CHECK-NEXT:          .seh_endepilogue
 ; CHECK-NEXT:          ret
 
 ; MINGW:              .section        .rdata,"dr"
 ; MINGW-NEXT:         .p2align  3
 ; MINGW-NEXT: [[LABEL:\.LC.*]]:
 ; MINGW-NEXT:         .xword  0x2000000000800001
 ; MINGW:      double:
 ; MINGW:               adrp    x8, [[LABEL]]
 ; MINGW-NEXT:          ldr     d0, [x8, [[LABEL]]]
-; MINGW-NEXT:          .seh_startepilogue
-; MINGW-NEXT:          .seh_endepilogue
 ; MINGW-NEXT:          ret