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Differential D88587

[mlir][openacc] Remove -allow-unregistred-dialect from ops and invalid tests
ClosedPublic

Authored by clementval on Sep 30 2020, 9:15 AM.

Details

Reviewers
mehdi_amini
rriddle
ftynse
Commits
rGdd4fb7c8cfe3: [mlir][openacc] Remove -allow-unregistred-dialect from ops and invalid tests
Summary

Switch to a dummy op in the test dialect so we can remove the -allow-unregistred-dialect
on ops.mlir and invalid.mlir. Change after comment on D88272.

Diff Detail

Revision Contents

PathSize
mlir/
test/
Dialect/
OpenACC/
18 lines
62 lines

Diff 295322

mlir/test/Dialect/OpenACC/invalid.mlir

// RUN: mlir-opt -allow-unregistered-dialect -split-input-file -verify-diagnostics %s // RUN: mlir-opt -split-input-file -verify-diagnostics %s
// expected-error@+1 {{gang, worker or vector cannot appear with the seq attr}} // expected-error@+1 {{gang, worker or vector cannot appear with the seq attr}}
acc.loop gang { acc.loop gang {
"some.op"() : () -> () "test.openacc_dummy_op"() : () -> ()
acc.yield acc.yield
} attributes {seq} } attributes {seq}
// ----- // -----
// expected-error@+1 {{gang, worker or vector cannot appear with the seq attr}} // expected-error@+1 {{gang, worker or vector cannot appear with the seq attr}}
acc.loop worker { acc.loop worker {
"some.op"() : () -> () "test.openacc_dummy_op"() : () -> ()
acc.yield acc.yield
} attributes {seq} } attributes {seq}
// ----- // -----
// expected-error@+1 {{gang, worker or vector cannot appear with the seq attr}} // expected-error@+1 {{gang, worker or vector cannot appear with the seq attr}}
acc.loop vector { acc.loop vector {
"some.op"() : () -> () "test.openacc_dummy_op"() : () -> ()
acc.yield acc.yield
} attributes {seq} } attributes {seq}
// ----- // -----
// expected-error@+1 {{gang, worker or vector cannot appear with the seq attr}} // expected-error@+1 {{gang, worker or vector cannot appear with the seq attr}}
acc.loop gang worker { acc.loop gang worker {
"some.op"() : () -> () "test.openacc_dummy_op"() : () -> ()
acc.yield acc.yield
} attributes {seq} } attributes {seq}
// ----- // -----
// expected-error@+1 {{gang, worker or vector cannot appear with the seq attr}} // expected-error@+1 {{gang, worker or vector cannot appear with the seq attr}}
acc.loop gang vector { acc.loop gang vector {
"some.op"() : () -> () "test.openacc_dummy_op"() : () -> ()
acc.yield acc.yield
} attributes {seq} } attributes {seq}
// ----- // -----
// expected-error@+1 {{gang, worker or vector cannot appear with the seq attr}} // expected-error@+1 {{gang, worker or vector cannot appear with the seq attr}}
acc.loop worker vector { acc.loop worker vector {
"some.op"() : () -> () "test.openacc_dummy_op"() : () -> ()
acc.yield acc.yield
} attributes {seq} } attributes {seq}
// ----- // -----
// expected-error@+1 {{gang, worker or vector cannot appear with the seq attr}} // expected-error@+1 {{gang, worker or vector cannot appear with the seq attr}}
acc.loop gang worker vector { acc.loop gang worker vector {
"some.op"() : () -> () "test.openacc_dummy_op"() : () -> ()
acc.yield acc.yield
} attributes {seq} } attributes {seq}
// ----- // -----
// expected-error@+1 {{expected non-empty body.}} // expected-error@+1 {{expected non-empty body.}}
acc.loop { acc.loop {
} }
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// expected-error@+1 {{'acc.shutdown' op cannot be nested in a compute operation}} // expected-error@+1 {{'acc.shutdown' op cannot be nested in a compute operation}}
acc.shutdown acc.shutdown
acc.yield acc.yield
} }
// ----- // -----
acc.loop { acc.loop {
"some.op"() ({ "test.openacc_dummy_op"() ({
// expected-error@+1 {{'acc.shutdown' op cannot be nested in a compute operation}} // expected-error@+1 {{'acc.shutdown' op cannot be nested in a compute operation}}
acc.shutdown acc.shutdown
}) : () -> () }) : () -> ()
acc.yield acc.yield
} }

mlir/test/Dialect/OpenACC/ops.mlir

// RUN: mlir-opt -split-input-file -allow-unregistered-dialect %s | FileCheck %s // RUN: mlir-opt -split-input-file %s | FileCheck %s
// Verify the printed output can be parsed. // Verify the printed output can be parsed.
// RUN: mlir-opt -split-input-file -allow-unregistered-dialect %s | mlir-opt -allow-unregistered-dialect | FileCheck %s // RUN: mlir-opt -split-input-file %s | mlir-opt -allow-unregistered-dialect | FileCheck %s
// Verify the generic form can be parsed. // Verify the generic form can be parsed.
// RUN: mlir-opt -split-input-file -allow-unregistered-dialect -mlir-print-op-generic %s | mlir-opt -allow-unregistered-dialect | FileCheck %s // RUN: mlir-opt -split-input-file -mlir-print-op-generic %s | mlir-opt -allow-unregistered-dialect | FileCheck %s
func @compute1(%A: memref<10x10xf32>, %B: memref<10x10xf32>, %C: memref<10x10xf32>) -> memref<10x10xf32> { func @compute1(%A: memref<10x10xf32>, %B: memref<10x10xf32>, %C: memref<10x10xf32>) -> memref<10x10xf32> {
%c0 = constant 0 : index %c0 = constant 0 : index
%c10 = constant 10 : index %c10 = constant 10 : index
%c1 = constant 1 : index %c1 = constant 1 : index
%async = constant 1 : i64 %async = constant 1 : i64
acc.parallel async(%async: i64) { acc.parallel async(%async: i64) {
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// ----- // -----
func @testloopop() -> () { func @testloopop() -> () {
%i64Value = constant 1 : i64 %i64Value = constant 1 : i64
%i32Value = constant 128 : i32 %i32Value = constant 128 : i32
%idxValue = constant 8 : index %idxValue = constant 8 : index
acc.loop gang worker vector { acc.loop gang worker vector {
"some.op"() : () -> () "test.openacc_dummy_op"() : () -> ()
acc.yield acc.yield
} }
acc.loop gang(num=%i64Value: i64) { acc.loop gang(num=%i64Value: i64) {
"some.op"() : () -> () "test.openacc_dummy_op"() : () -> ()
acc.yield acc.yield
} }
acc.loop gang(static=%i64Value: i64) { acc.loop gang(static=%i64Value: i64) {
"some.op"() : () -> () "test.openacc_dummy_op"() : () -> ()
acc.yield acc.yield
} }
acc.loop worker(%i64Value: i64) { acc.loop worker(%i64Value: i64) {
"some.op"() : () -> () "test.openacc_dummy_op"() : () -> ()
acc.yield acc.yield
} }
acc.loop worker(%i32Value: i32) { acc.loop worker(%i32Value: i32) {
"some.op"() : () -> () "test.openacc_dummy_op"() : () -> ()
acc.yield acc.yield
} }
acc.loop worker(%idxValue: index) { acc.loop worker(%idxValue: index) {
"some.op"() : () -> () "test.openacc_dummy_op"() : () -> ()
acc.yield acc.yield
} }
acc.loop vector(%i64Value: i64) { acc.loop vector(%i64Value: i64) {
"some.op"() : () -> () "test.openacc_dummy_op"() : () -> ()
acc.yield acc.yield
} }
acc.loop vector(%i32Value: i32) { acc.loop vector(%i32Value: i32) {
"some.op"() : () -> () "test.openacc_dummy_op"() : () -> ()
acc.yield acc.yield
} }
acc.loop vector(%idxValue: index) { acc.loop vector(%idxValue: index) {
"some.op"() : () -> () "test.openacc_dummy_op"() : () -> ()
acc.yield acc.yield
} }
acc.loop gang(num=%i64Value: i64) worker vector { acc.loop gang(num=%i64Value: i64) worker vector {
"some.op"() : () -> () "test.openacc_dummy_op"() : () -> ()
acc.yield acc.yield
} }
acc.loop gang(num=%i64Value: i64, static=%i64Value: i64) worker(%i64Value: i64) vector(%i64Value: i64) { acc.loop gang(num=%i64Value: i64, static=%i64Value: i64) worker(%i64Value: i64) vector(%i64Value: i64) {
"some.op"() : () -> () "test.openacc_dummy_op"() : () -> ()
acc.yield acc.yield
} }
acc.loop gang(num=%i32Value: i32, static=%idxValue: index) { acc.loop gang(num=%i32Value: i32, static=%idxValue: index) {
"some.op"() : () -> () "test.openacc_dummy_op"() : () -> ()
acc.yield acc.yield
} }
acc.loop tile(%i64Value: i64, %i64Value: i64) { acc.loop tile(%i64Value: i64, %i64Value: i64) {
"some.op"() : () -> () "test.openacc_dummy_op"() : () -> ()
acc.yield acc.yield
} }
acc.loop tile(%i32Value: i32, %i32Value: i32) { acc.loop tile(%i32Value: i32, %i32Value: i32) {
"some.op"() : () -> () "test.openacc_dummy_op"() : () -> ()
acc.yield acc.yield
} }
return return
} }
// CHECK: [[I64VALUE:%.*]] = constant 1 : i64 // CHECK: [[I64VALUE:%.*]] = constant 1 : i64
// CHECK-NEXT: [[I32VALUE:%.*]] = constant 128 : i32 // CHECK-NEXT: [[I32VALUE:%.*]] = constant 128 : i32
// CHECK-NEXT: [[IDXVALUE:%.*]] = constant 8 : index // CHECK-NEXT: [[IDXVALUE:%.*]] = constant 8 : index
// CHECK: acc.loop gang worker vector { // CHECK: acc.loop gang worker vector {
// CHECK-NEXT: "some.op"() : () -> () // CHECK-NEXT: "test.openacc_dummy_op"() : () -> ()
// CHECK-NEXT: acc.yield // CHECK-NEXT: acc.yield
// CHECK-NEXT: } // CHECK-NEXT: }
// CHECK: acc.loop gang(num=[[I64VALUE]]: i64) { // CHECK: acc.loop gang(num=[[I64VALUE]]: i64) {
// CHECK-NEXT: "some.op"() : () -> () // CHECK-NEXT: "test.openacc_dummy_op"() : () -> ()
// CHECK-NEXT: acc.yield // CHECK-NEXT: acc.yield
// CHECK-NEXT: } // CHECK-NEXT: }
// CHECK: acc.loop gang(static=[[I64VALUE]]: i64) { // CHECK: acc.loop gang(static=[[I64VALUE]]: i64) {
// CHECK-NEXT: "some.op"() : () -> () // CHECK-NEXT: "test.openacc_dummy_op"() : () -> ()
// CHECK-NEXT: acc.yield // CHECK-NEXT: acc.yield
// CHECK-NEXT: } // CHECK-NEXT: }
// CHECK: acc.loop worker([[I64VALUE]]: i64) { // CHECK: acc.loop worker([[I64VALUE]]: i64) {
// CHECK-NEXT: "some.op"() : () -> () // CHECK-NEXT: "test.openacc_dummy_op"() : () -> ()
// CHECK-NEXT: acc.yield // CHECK-NEXT: acc.yield
// CHECK-NEXT: } // CHECK-NEXT: }
// CHECK: acc.loop worker([[I32VALUE]]: i32) { // CHECK: acc.loop worker([[I32VALUE]]: i32) {
// CHECK-NEXT: "some.op"() : () -> () // CHECK-NEXT: "test.openacc_dummy_op"() : () -> ()
// CHECK-NEXT: acc.yield // CHECK-NEXT: acc.yield
// CHECK-NEXT: } // CHECK-NEXT: }
// CHECK: acc.loop worker([[IDXVALUE]]: index) { // CHECK: acc.loop worker([[IDXVALUE]]: index) {
// CHECK-NEXT: "some.op"() : () -> () // CHECK-NEXT: "test.openacc_dummy_op"() : () -> ()
// CHECK-NEXT: acc.yield // CHECK-NEXT: acc.yield
// CHECK-NEXT: } // CHECK-NEXT: }
// CHECK: acc.loop vector([[I64VALUE]]: i64) { // CHECK: acc.loop vector([[I64VALUE]]: i64) {
// CHECK-NEXT: "some.op"() : () -> () // CHECK-NEXT: "test.openacc_dummy_op"() : () -> ()
// CHECK-NEXT: acc.yield // CHECK-NEXT: acc.yield
// CHECK-NEXT: } // CHECK-NEXT: }
// CHECK: acc.loop vector([[I32VALUE]]: i32) { // CHECK: acc.loop vector([[I32VALUE]]: i32) {
// CHECK-NEXT: "some.op"() : () -> () // CHECK-NEXT: "test.openacc_dummy_op"() : () -> ()
// CHECK-NEXT: acc.yield // CHECK-NEXT: acc.yield
// CHECK-NEXT: } // CHECK-NEXT: }
// CHECK: acc.loop vector([[IDXVALUE]]: index) { // CHECK: acc.loop vector([[IDXVALUE]]: index) {
// CHECK-NEXT: "some.op"() : () -> () // CHECK-NEXT: "test.openacc_dummy_op"() : () -> ()
// CHECK-NEXT: acc.yield // CHECK-NEXT: acc.yield
// CHECK-NEXT: } // CHECK-NEXT: }
// CHECK: acc.loop gang(num=[[I64VALUE]]: i64) worker vector { // CHECK: acc.loop gang(num=[[I64VALUE]]: i64) worker vector {
// CHECK-NEXT: "some.op"() : () -> () // CHECK-NEXT: "test.openacc_dummy_op"() : () -> ()
// CHECK-NEXT: acc.yield // CHECK-NEXT: acc.yield
// CHECK-NEXT: } // CHECK-NEXT: }
// CHECK: acc.loop gang(num=[[I64VALUE]]: i64, static=[[I64VALUE]]: i64) worker([[I64VALUE]]: i64) vector([[I64VALUE]]: i64) { // CHECK: acc.loop gang(num=[[I64VALUE]]: i64, static=[[I64VALUE]]: i64) worker([[I64VALUE]]: i64) vector([[I64VALUE]]: i64) {
// CHECK-NEXT: "some.op"() : () -> () // CHECK-NEXT: "test.openacc_dummy_op"() : () -> ()
// CHECK-NEXT: acc.yield // CHECK-NEXT: acc.yield
// CHECK-NEXT: } // CHECK-NEXT: }
// CHECK: acc.loop gang(num=[[I32VALUE]]: i32, static=[[IDXVALUE]]: index) { // CHECK: acc.loop gang(num=[[I32VALUE]]: i32, static=[[IDXVALUE]]: index) {
// CHECK-NEXT: "some.op"() : () -> () // CHECK-NEXT: "test.openacc_dummy_op"() : () -> ()
// CHECK-NEXT: acc.yield // CHECK-NEXT: acc.yield
// CHECK-NEXT: } // CHECK-NEXT: }
// CHECK: acc.loop tile([[I64VALUE]]: i64, [[I64VALUE]]: i64) { // CHECK: acc.loop tile([[I64VALUE]]: i64, [[I64VALUE]]: i64) {
// CHECK-NEXT: "some.op"() : () -> () // CHECK-NEXT: "test.openacc_dummy_op"() : () -> ()
// CHECK-NEXT: acc.yield // CHECK-NEXT: acc.yield
// CHECK-NEXT: } // CHECK-NEXT: }
// CHECK: acc.loop tile([[I32VALUE]]: i32, [[I32VALUE]]: i32) { // CHECK: acc.loop tile([[I32VALUE]]: i32, [[I32VALUE]]: i32) {
// CHECK-NEXT: "some.op"() : () -> () // CHECK-NEXT: "test.openacc_dummy_op"() : () -> ()
// CHECK-NEXT: acc.yield // CHECK-NEXT: acc.yield
// CHECK-NEXT: } // CHECK-NEXT: }
// ----- // -----
func @testparallelop(%a: memref<10xf32>, %b: memref<10xf32>, %c: memref<10x10xf32>) -> () { func @testparallelop(%a: memref<10xf32>, %b: memref<10xf32>, %c: memref<10x10xf32>) -> () {
%i64value = constant 1 : i64 %i64value = constant 1 : i64
%i32value = constant 1 : i32 %i32value = constant 1 : i32
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