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Differential D88545

[ARM] Removed hasSideEffects from signed/unsigned saturates
ClosedPublic

Authored by MeeraN on Sep 30 2020, 2:13 AM.

Details

Reviewers
dmgreen
SjoerdMeijer
samparker
andreadb
Commits
rG48c9e8244b6b: [ARM] Removed hasSideEffects from signed/unsigned saturates
Summary

Removed hasSideEffects from SSAT and USAT so that they are no longer
marked as unpredictable

Diff Detail

Event Timeline

MeeraN created this revision.Sep 30 2020, 2:13 AM
Herald added a reviewer: andreadb. · View Herald TranscriptSep 30 2020, 2:13 AM
Herald added a project: Restricted Project. · View Herald Transcript
Herald added subscribers: danielkiss, gbedwell, hiraditya, kristof.beyls. · View Herald Transcript
MeeraN requested review of this revision.Sep 30 2020, 2:13 AM
Harbormaster completed remote builds in B73478: Diff 295208.Sep 30 2020, 2:14 AM
MeeraN removed a reviewer: andreadb.Sep 30 2020, 2:14 AM
Herald added a reviewer: andreadb. · View Herald TranscriptSep 30 2020, 2:14 AM
MeeraN removed a reviewer: andreadb.Sep 30 2020, 2:14 AM
MeeraN removed a project: Restricted Project.
Herald added a reviewer: andreadb. · View Herald TranscriptSep 30 2020, 2:14 AM
Herald added a project: Restricted Project. · View Herald Transcript
MeeraN added a comment.Sep 30 2020, 2:18 AM

Sorry, didn't realise tags and reviewers were automatically added. Thought it was a mistake. Apologies for the few extra emails notifications that would have been sent.

dmgreen accepted this revision.Oct 1 2020, 12:20 AM

Yeah, Looks good to me. It brings us into line with the other instructions like qadd.

This revision is now accepted and ready to land.Oct 1 2020, 12:20 AM
This revision was landed with ongoing or failed builds.Oct 1 2020, 7:56 AM
Closed by commit rG48c9e8244b6b: [ARM] Removed hasSideEffects from signed/unsigned saturates (authored by MeeraN). · Explain Why
This revision was automatically updated to reflect the committed changes.
MeeraN added a commit: rG48c9e8244b6b: [ARM] Removed hasSideEffects from signed/unsigned saturates.

Revision Contents

PathSize
llvm/
lib/
Target/
ARM/
ARMInstrThumb2.td
ARMInstrThumb2.td
1 line
test/
tools/
llvm-mca/
ARM/
m4-int.s
m4-int.s
12 lines

Diff 295208

llvm/lib/Target/ARM/ARMInstrThumb2.td

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} }
def t2USADA8 : T2FourReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd), def t2USADA8 : T2FourReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
(ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), NoItinerary, (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), NoItinerary,
"usada8", "\t$Rd, $Rn, $Rm, $Ra", "usada8", "\t$Rd, $Rn, $Rm, $Ra",
[(set rGPR:$Rd, (int_arm_usada8 rGPR:$Rn, rGPR:$Rm, rGPR:$Ra))]>, [(set rGPR:$Rd, (int_arm_usada8 rGPR:$Rn, rGPR:$Rm, rGPR:$Ra))]>,
Requires<[IsThumb2, HasDSP]>; Requires<[IsThumb2, HasDSP]>;
// Signed/Unsigned saturate. // Signed/Unsigned saturate.
let hasSideEffects = 1 in
class T2SatI<dag iops, string opc, string asm> class T2SatI<dag iops, string opc, string asm>
: T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, []> { : T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, []> {
bits<4> Rd; bits<4> Rd;
bits<4> Rn; bits<4> Rn;
bits<5> sat_imm; bits<5> sat_imm;
bits<6> sh; bits<6> sh;
let Inst{31-24} = 0b11110011; let Inst{31-24} = 0b11110011;
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llvm/test/tools/llvm-mca/ARM/m4-int.s

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# CHECK-NEXT: 1 1 1.00 smulbt r0, r1, r2 # CHECK-NEXT: 1 1 1.00 smulbt r0, r1, r2
# CHECK-NEXT: 1 1 1.00 smultb r0, r1, r2 # CHECK-NEXT: 1 1 1.00 smultb r0, r1, r2
# CHECK-NEXT: 1 1 1.00 smultt r0, r1, r2 # CHECK-NEXT: 1 1 1.00 smultt r0, r1, r2
# CHECK-NEXT: 2 1 2.00 smull r0, r1, r2, r3 # CHECK-NEXT: 2 1 2.00 smull r0, r1, r2, r3
# CHECK-NEXT: 1 1 1.00 smulwb r0, r1, r2 # CHECK-NEXT: 1 1 1.00 smulwb r0, r1, r2
# CHECK-NEXT: 1 1 1.00 smulwt r0, r1, r2 # CHECK-NEXT: 1 1 1.00 smulwt r0, r1, r2
# CHECK-NEXT: 1 2 1.00 smusd r0, r1, r2 # CHECK-NEXT: 1 2 1.00 smusd r0, r1, r2
# CHECK-NEXT: 1 2 1.00 smusdx r0, r1, r2 # CHECK-NEXT: 1 2 1.00 smusdx r0, r1, r2
# CHECK-NEXT: 1 1 1.00 U ssat r0, #1, r2 # CHECK-NEXT: 1 1 1.00 ssat r0, #1, r2
# CHECK-NEXT: 1 1 1.00 U ssat r0, #1, r2, lsl #1 # CHECK-NEXT: 1 1 1.00 ssat r0, #1, r2, lsl #1
# CHECK-NEXT: 1 1 1.00 U ssat16 r0, #1, r1 # CHECK-NEXT: 1 1 1.00 ssat16 r0, #1, r1
# CHECK-NEXT: 1 1 1.00 * * U ssax r0, r1, r2 # CHECK-NEXT: 1 1 1.00 * * U ssax r0, r1, r2
# CHECK-NEXT: 1 1 1.00 * * U ssbb # CHECK-NEXT: 1 1 1.00 * * U ssbb
# CHECK-NEXT: 1 1 1.00 * * U ssub16 r0, r1, r2 # CHECK-NEXT: 1 1 1.00 * * U ssub16 r0, r1, r2
# CHECK-NEXT: 1 1 1.00 * * U ssub8 r0, r1, r2 # CHECK-NEXT: 1 1 1.00 * * U ssub8 r0, r1, r2
# CHECK-NEXT: 1 1 1.00 * stm r0!, {r1} # CHECK-NEXT: 1 1 1.00 * stm r0!, {r1}
# CHECK-NEXT: 1 1 1.00 * stm.w r0, {r1} # CHECK-NEXT: 1 1 1.00 * stm.w r0, {r1}
# CHECK-NEXT: 1 1 1.00 * stm.w r0!, {r1} # CHECK-NEXT: 1 1 1.00 * stm.w r0!, {r1}
# CHECK-NEXT: 1 1 1.00 * stmdb r0, {r1} # CHECK-NEXT: 1 1 1.00 * stmdb r0, {r1}
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# CHECK-NEXT: 1 1 1.00 uqadd16 r0, r1, r2 # CHECK-NEXT: 1 1 1.00 uqadd16 r0, r1, r2
# CHECK-NEXT: 1 1 1.00 uqadd8 r0, r1, r2 # CHECK-NEXT: 1 1 1.00 uqadd8 r0, r1, r2
# CHECK-NEXT: 1 1 1.00 uqasx r0, r1, r2 # CHECK-NEXT: 1 1 1.00 uqasx r0, r1, r2
# CHECK-NEXT: 1 1 1.00 uqsax r0, r1, r2 # CHECK-NEXT: 1 1 1.00 uqsax r0, r1, r2
# CHECK-NEXT: 1 1 1.00 uqsub16 r0, r1, r2 # CHECK-NEXT: 1 1 1.00 uqsub16 r0, r1, r2
# CHECK-NEXT: 1 1 1.00 uqsub8 r0, r1, r2 # CHECK-NEXT: 1 1 1.00 uqsub8 r0, r1, r2
# CHECK-NEXT: 1 1 1.00 usad8 r0, r1, r2 # CHECK-NEXT: 1 1 1.00 usad8 r0, r1, r2
# CHECK-NEXT: 1 1 1.00 usada8 r0, r1, r2, r3 # CHECK-NEXT: 1 1 1.00 usada8 r0, r1, r2, r3
# CHECK-NEXT: 1 1 1.00 U usat r0, #1, r1 # CHECK-NEXT: 1 1 1.00 usat r0, #1, r1
# CHECK-NEXT: 1 1 1.00 U usat r0, #1, r1, lsl #1 # CHECK-NEXT: 1 1 1.00 usat r0, #1, r1, lsl #1
# CHECK-NEXT: 1 1 1.00 U usat16 r0, #1, r1 # CHECK-NEXT: 1 1 1.00 usat16 r0, #1, r1
# CHECK-NEXT: 1 1 1.00 * * U usax r0, r1, r2 # CHECK-NEXT: 1 1 1.00 * * U usax r0, r1, r2
# CHECK-NEXT: 1 1 1.00 * * U usub16 r0, r1, r2 # CHECK-NEXT: 1 1 1.00 * * U usub16 r0, r1, r2
# CHECK-NEXT: 1 1 1.00 * * U usub8 r0, r1, r2 # CHECK-NEXT: 1 1 1.00 * * U usub8 r0, r1, r2
# CHECK-NEXT: 1 1 1.00 uxtab r0, r1, r2 # CHECK-NEXT: 1 1 1.00 uxtab r0, r1, r2
# CHECK-NEXT: 1 1 1.00 uxtab r0, r1, r2, ror #8 # CHECK-NEXT: 1 1 1.00 uxtab r0, r1, r2, ror #8
# CHECK-NEXT: 1 1 1.00 uxtab16 r0, r1, r2 # CHECK-NEXT: 1 1 1.00 uxtab16 r0, r1, r2
# CHECK-NEXT: 1 1 1.00 uxtab16 r0, r1, r2, ror #8 # CHECK-NEXT: 1 1 1.00 uxtab16 r0, r1, r2, ror #8
# CHECK-NEXT: 1 1 1.00 uxtah r0, r1, r2 # CHECK-NEXT: 1 1 1.00 uxtah r0, r1, r2
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