[PowerPC] Put the CR field in low bits of GRC during copying CRRC to GRC.

[Esme]

Summary

********** EXPANDING POST-RA PSEUDO INSTRS **********
real copy:  renamable $r3 = COPY killed renamable $cr0
replaced by: $r3 = MFOCRF $cr0

As shown above, how we copying the CRRC to GRC is using a single MFOCRF to copy the contents of CR field n (CR bits 4×n+32:4×n+35) into bits 4×n+32:4×n+35 of register GRC. That's not correct because we expect the value of destination register equals to source so we have to put the the contents of CR field in the lowest 4 bits.

This patch adds a RLWINM after MFOCRF to achieve that.

In fact, the problem came up when adding builtins for xvtdivdp, xvtdivsp, xvtsqrtdp, xvtsqrtsp, as posted in D88278.
We need to move the outputs (in CR register) to GRC. However outputs of these instructions may not in a fixed CR# register, so we can't directly add a rotation instruction in the .td patterns, but need to wait until the CR register is determined. Then we confirmed this should be a bug in POST-RA PSEUDO PASS.

[shchenz]

llvm/test/CodeGen/PowerPC/reg_copy.mir

83 ↗

(On Diff #294218)

Maybe we can save the rlwinm when cr field is cr7. Rotate left 32 equals to no rotate?

[Esme]

Skip rotation if CR7.

[nemanjai]

LGTM. The code here is correct, but I do have a couple of questions:

1. Do these copies come up in real code? And if so, under which circumstances. We don't have copies in the other direction implemented, so that makes me wonder when these ever come up.
2. Does this solve a problem seen in real code? If so, is there a bugzilla report? At the very least, the conditions under which this causes a problem should be added to the description.
3. Is there any follow up required/planned for this?

[Esme]

In D88274#2300438, @nemanjai wrote:

LGTM. The code here is correct, but I do have a couple of questions:

1. Do these copies come up in real code? And if so, under which circumstances. We don't have copies in the other direction implemented, so that makes me wonder when these ever come up.
2. Does this solve a problem seen in real code? If so, is there a bugzilla report? At the very least, the conditions under which this causes a problem should be added to the description.
3. Is there any follow up required/planned for this?

Thanks for your comments!
Sorry that I forgot to mention the real scenarios where the problem occurred.
The problem came up when adding builtins for xvtdivdp, xvtdivsp, xvtsqrtdp, xvtsqrtsp, as posted in D88278.
Outputs of these instructions will not be placed into a fixed CR# register, so I can't directly add a rotation instruction in the .td patterns, but need to wait until the CR register is determined.
So D88278 has to depend on this patch.

[shchenz]

LGTM too. Thanks for sharing the background. Before committing this, it's better to update the description for later reference like @nemanjai pointed out?

[Esme]

In D88274#2305121, @shchenz wrote:

LGTM too. Thanks for sharing the background. Before committing this, it's better to update the description for later reference like @nemanjai pointed out?

Yes, thanks for your help! I'll commit soon.

llvm/lib/Target/PowerPC/PPCInstrHTM.td

 
 def : Pat<(int_ppc_tresume),
           (TSR 1)>;
 
 def : Pat<(int_ppc_tsuspend),
           (TSR 0)>;
 
 def : Pat<(i64 (int_ppc_ttest)),
-          (RLDICL (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
-                                      (TABORTWCI 0, (LI 0), 0), sub_32)),
-                   36, 28)>;
+          (i64 (INSERT_SUBREG
+                (i64 (IMPLICIT_DEF)), (TABORTWCI 0, (LI 0), 0), sub_32))>;
 
 } // [HasHTM]
 
 def : InstAlias<"tend.", (TEND 0)>, Requires<[HasHTM]>;
 def : InstAlias<"tendall.", (TEND 1)>, Requires<[HasHTM]>;
 def : InstAlias<"tsuspend.", (TSR 0)>, Requires<[HasHTM]>;
 def : InstAlias<"tresume.", (TSR 1)>, Requires<[HasHTM]>;

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

if (PPC::CRBITRCRegClass.contains(SrcReg) &&
     // then mask with 0x1 (MB = ME = 31).
     BuildMI(MBB, I, DL, get(PPC::RLWINM), DestReg)
        .addReg(DestReg, RegState::Kill)
        .addImm(TRI->getEncodingValue(CRReg) * 4 + (4 - getCRBitValue(SrcReg)))
        .addImm(31)
        .addImm(31);
     return;
   } else if (PPC::CRRCRegClass.contains(SrcReg) &&
-      PPC::G8RCRegClass.contains(DestReg)) {
-    BuildMI(MBB, I, DL, get(PPC::MFOCRF8), DestReg).addReg(SrcReg);
+             (PPC::G8RCRegClass.contains(DestReg) ||
+              PPC::GPRCRegClass.contains(DestReg))) {
+    bool Is64Bit = PPC::G8RCRegClass.contains(DestReg);
+    unsigned MvCode = Is64Bit ? PPC::MFOCRF8 : PPC::MFOCRF;
+    unsigned ShCode = Is64Bit ? PPC::RLWINM8 : PPC::RLWINM;
+    unsigned CRNum = TRI->getEncodingValue(SrcReg);
+    BuildMI(MBB, I, DL, get(MvCode), DestReg).addReg(SrcReg);
     getKillRegState(KillSrc);
+    if (CRNum == 7)
       return;
-  } else if (PPC::CRRCRegClass.contains(SrcReg) &&
-      PPC::GPRCRegClass.contains(DestReg)) {
-    BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg).addReg(SrcReg);
-    getKillRegState(KillSrc);
+    // Shift the CR bits to make the CR field in the lowest 4 bits of GRC.
+    BuildMI(MBB, I, DL, get(ShCode), DestReg)
+        .addReg(DestReg, RegState::Kill)
+        .addImm(CRNum * 4 + 4)
+        .addImm(28)
+        .addImm(31);
     return;
   } else if (PPC::G8RCRegClass.contains(SrcReg) &&
              PPC::VSFRCRegClass.contains(DestReg)) {
     assert(Subtarget.hasDirectMove() &&
            "Subtarget doesn't support directmove, don't know how to copy.");
     BuildMI(MBB, I, DL, get(PPC::MTVSRD), DestReg).addReg(SrcReg);
     NumGPRtoVSRSpill++;
     getKillRegState(KillSrc);

llvm/test/CodeGen/PowerPC/htm-ttest.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs \
 ; RUN:     -mcpu=pwr8 -mattr=+htm < %s | FileCheck %s
 
 define dso_local void @main() #0 {
 ; CHECK-LABEL: main:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    tabortwci. 0, 3, 0
 ; CHECK-NEXT:    mfocrf 3, 128
-; CHECK-NEXT:    rldicl 3, 3, 36, 28
+; CHECK-NEXT:    srwi 3, 3, 28
 ; CHECK-NEXT:    rlwinm. 3, 3, 31, 30, 31
 ; CHECK-NEXT:    beqlr+ 0
 ; CHECK-NEXT:  # %bb.1:
   %1 = call i64 @llvm.ppc.ttest() #1
   %2 = lshr i64 %1, 1
   %3 = and i64 %2, 3
   %4 = icmp eq i64 %3, 0
   br i1 %4, label %5, label %6