Differential D87873

[RISCV] Merge the pipeline models for Rocket
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Authored by evandro on Sep 17 2020, 4:58 PM.

Details

Reviewers

HsiangKai
compilerguy
asb
lenary

Commits

rG1e66e723eb66: [RISCV] Merge the pipeline models for Rocket

Summary

Merge the 32 and 64 bit pipeline models for Rocket into a single file.

Diff Detail

Repository: rG LLVM Github Monorepo

Event Timeline

evandro created this revision.Sep 17 2020, 4:58 PM

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evandro requested review of this revision.Sep 17 2020, 4:58 PM

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evandro added a commit: rG838a28e234e0: [RISCV] Scheduler description for the Rocket core.Sep 18 2020, 8:46 AM

evandro removed a commit: rG838a28e234e0: [RISCV] Scheduler description for the Rocket core.

Why not delete RISCVSchedRocket32.td?

In D87873#2284396, @HsiangKai wrote:

Why not delete RISCVSchedRocket32.td?

Of course!

evandro updated this revision to Diff 293300.Sep 21 2020, 5:38 PM

LGTM.

This revision is now accepted and ready to land.Sep 23 2020, 4:16 PM

Closed by commit rG1e66e723eb66: [RISCV] Merge the pipeline models for Rocket (authored by evandro). · Explain WhySep 24 2020, 3:36 PM

This revision was automatically updated to reflect the committed changes.

evandro added a commit: rG1e66e723eb66: [RISCV] Merge the pipeline models for Rocket.

Herald added a subscriber: jrtc27. · View Herald TranscriptSep 24 2020, 3:36 PM

Revision Contents
Changeset List

Path

Size

llvm/

lib/

Target/

RISCV/

25 lines

RISCVSchedRocket.td

233 lines

RISCVSchedRocket32.td

RISCVSchedRocket64.td

Diff 294191

llvm/lib/Target/RISCV/RISCV.td

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llvm/lib/Target/RISCV/RISCVSchedRocket.td

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llvm/lib/Target/RISCV/RISCVSchedRocket32.td

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llvm/lib/Target/RISCV/RISCVSchedRocket64.td

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