CodeGen: Move split block utility to MachineBasicBlock

[arsenm]

Summary

AMDGPU needs this in several places, so consolidate them here.

[qcolombet]

LGTM

[arsenm]

3105d0f84bfa6b765bb88cbf090f557e588764ea

llvm/include/llvm/CodeGen/MachineBasicBlock.h

 class MachineFunction;
 class MCSymbol;
 class ModuleSlotTracker;
 class Pass;
 class Printable;
 class SlotIndexes;
 class StringRef;
 class raw_ostream;
+class LiveIntervals;
 class TargetRegisterClass;
 class TargetRegisterInfo;
 
 // This structure uniquely identifies a basic block section.
 // Possible values are
 //  {Type: Default, Number: (unsigned)} (These are regular section IDs)
 //  {Type: Exception, Number: 0}  (ExceptionSectionID)
 //  {Type: Cold, Number: 0}  (ColdSectionID)
#endif
   }
 
   /// Convenience function that returns true if the bock ends in a EH scope
   /// return instruction.
   bool isEHScopeReturnBlock() const {
     return !empty() && back().isEHScopeReturn();
   }
 
+  /// Split a basic block into 2 pieces at \p SplitPoint. A new block will be
+  /// inserted after this block, and all instructions after \p SplitInst moved
+  /// to it (\p SplitInst will be in the original block). If \p LIS is provided,
+  /// LiveIntervals will be appropriately updated. \return the newly inserted
+  /// block.
+  ///
+  /// If \p UpdateLiveIns is true, this will ensure the live ins list is
+  /// accurate, including for physreg uses/defs in the original block.
+  MachineBasicBlock *splitAt(MachineInstr &SplitInst, bool UpdateLiveIns = true,
+                             LiveIntervals *LIS = nullptr);
+
   /// Split the critical edge from this block to the given successor block, and
   /// return the newly created block, or null if splitting is not possible.
   ///
   /// This function updates LiveVariables, MachineDominatorTree, and
   /// MachineLoopInfo, as applicable.
   MachineBasicBlock *
   SplitCriticalEdge(MachineBasicBlock *Succ, Pass &P,
                     std::vector<SparseBitVector<>> *LiveInSets = nullptr);

llvm/lib/CodeGen/MachineBasicBlock.cpp

MachineBasicBlock *MachineBasicBlock::getFallThrough() {
   // through.
   return (FBB == nullptr) ? &*Fallthrough : nullptr;
 }
 
 bool MachineBasicBlock::canFallThrough() {
   return getFallThrough() != nullptr;
 }
 
+MachineBasicBlock *MachineBasicBlock::splitAt(MachineInstr &MI,
+                                              bool UpdateLiveIns,
+                                              LiveIntervals *LIS) {
+  MachineBasicBlock::iterator SplitPoint(&MI);
+  ++SplitPoint;
+
+  if (SplitPoint == end()) {
+    // Don't bother with a new block.
+    return this;
+  }
+
+  MachineFunction *MF = getParent();
+
+  LivePhysRegs LiveRegs;
+  if (UpdateLiveIns) {
+    // Make sure we add any physregs we define in the block as liveins to the
+    // new block.
+    LiveRegs.init(*MF->getSubtarget().getRegisterInfo());
+    LiveRegs.addLiveOuts(*this);
+    for (auto I = rbegin(), E = SplitPoint.getReverse(); I != E; ++I)
+      LiveRegs.stepBackward(*I);
+  }
+
+  MachineBasicBlock *SplitBB = MF->CreateMachineBasicBlock(getBasicBlock());
+
+  MF->insert(++MachineFunction::iterator(this), SplitBB);
+  SplitBB->splice(SplitBB->begin(), this, SplitPoint, end());
+
+  SplitBB->transferSuccessorsAndUpdatePHIs(this);
+  addSuccessor(SplitBB);
+
+  if (UpdateLiveIns)
+    addLiveIns(*SplitBB, LiveRegs);
+
+  if (LIS)
+    LIS->insertMBBInMaps(SplitBB, &MI);
+
+  return SplitBB;
+}
+
 MachineBasicBlock *MachineBasicBlock::SplitCriticalEdge(
     MachineBasicBlock *Succ, Pass &P,
     std::vector<SparseBitVector<>> *LiveInSets) {
   if (!canSplitCriticalEdge(Succ))
     return nullptr;
 
   MachineFunction *MF = getParent();
   MachineBasicBlock *PrevFallthrough = getNextNode();

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

Register SITargetLowering::getRegisterByName(const char* RegName, LLT VT,
   }
 
   report_fatal_error(Twine("invalid type for register \""
                            + StringRef(RegName) + "\"."));
 }
 
 // If kill is not the last instruction, split the block so kill is always a
 // proper terminator.
-MachineBasicBlock *SITargetLowering::splitKillBlock(MachineInstr &MI,
-                                                    MachineBasicBlock *BB) const {
+MachineBasicBlock *
+SITargetLowering::splitKillBlock(MachineInstr &MI,
+  MachineBasicBlock *SplitBB = BB->splitAt(MI, false /*UpdateLiveIns*/);
   const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
-
-  MachineBasicBlock::iterator SplitPoint(&MI);
-  ++SplitPoint;
-
-  if (SplitPoint == BB->end()) {
-    // Don't bother with a new block.
-    MI.setDesc(TII->getKillTerminatorFromPseudo(MI.getOpcode()));
-    return BB;
-  }
-
-  MachineFunction *MF = BB->getParent();
-  MachineBasicBlock *SplitBB
-    = MF->CreateMachineBasicBlock(BB->getBasicBlock());
-
-  MF->insert(++MachineFunction::iterator(BB), SplitBB);
-  SplitBB->splice(SplitBB->begin(), BB, SplitPoint, BB->end());
-
-  SplitBB->transferSuccessorsAndUpdatePHIs(BB);
-  BB->addSuccessor(SplitBB);
-
   MI.setDesc(TII->getKillTerminatorFromPseudo(MI.getOpcode()));
   return SplitBB;
 }
 
 // Split block \p MBB at \p MI, as to insert a loop. If \p InstInLoop is true,
 // \p MI will be the only instruction in the loop body block. Otherwise, it will
 // be the first instruction in the remainder block.
 //

llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp

private:
   unsigned OrSaveExecOpc;
   unsigned Exec;
 
   void emitIf(MachineInstr &MI);
   void emitElse(MachineInstr &MI);
   void emitIfBreak(MachineInstr &MI);
   void emitLoop(MachineInstr &MI);
 
-  MachineBasicBlock *splitBlock(MachineInstr &MI, MachineBasicBlock *BB,
-                                LiveIntervals *LIS);
   MachineBasicBlock *emitEndCf(MachineInstr &MI);
 
   void findMaskOperands(MachineInstr &MI, unsigned OpNo,
                         SmallVectorImpl<MachineOperand> &Src) const;
 
   void combineMasks(MachineInstr &MI);
 
   bool removeMBBifRedundant(MachineBasicBlock &MBB);
do {
     // If there is one trivial successor, advance to the next block.
     MachineBasicBlock *Succ = *B->succ_begin();
 
     It = Succ->begin();
     B = Succ;
   } while (true);
 }
 
-MachineBasicBlock *SILowerControlFlow::splitBlock(MachineInstr &MI,
-                                                  MachineBasicBlock *BB,
-                                                  LiveIntervals *LIS) {
-  MachineBasicBlock::iterator SplitPoint(&MI);
-  ++SplitPoint;
-
-  if (SplitPoint == BB->end()) {
-    // Don't bother with a new block.
-    return BB;
-  }
-
-  // Make sure we add any physregs we define in the block as liveins to the new
-  // block.
-  LivePhysRegs LiveRegs(*TRI);
-  LiveRegs.addLiveOuts(*BB);
-  for (auto I = BB->rbegin(), E = SplitPoint.getReverse(); I != E; ++I)
-    LiveRegs.stepBackward(*I);
-
-  MachineFunction *MF = BB->getParent();
-  MachineBasicBlock *SplitBB
-    = MF->CreateMachineBasicBlock(BB->getBasicBlock());
-
-  MF->insert(++MachineFunction::iterator(BB), SplitBB);
-  SplitBB->splice(SplitBB->begin(), BB, SplitPoint, BB->end());
-
-  SplitBB->transferSuccessorsAndUpdatePHIs(BB);
-  BB->addSuccessor(SplitBB);
-
-  addLiveIns(*SplitBB, LiveRegs);
-
-  if (LIS)
-    LIS->insertMBBInMaps(SplitBB, &MI);
-
-  return SplitBB;
-}
-
 MachineBasicBlock *SILowerControlFlow::emitEndCf(MachineInstr &MI) {
   MachineBasicBlock &MBB = *MI.getParent();
   const DebugLoc &DL = MI.getDebugLoc();
 
   MachineBasicBlock::iterator InsPt = MBB.begin();
 
   // If we have instructions that aren't prolog instructions, split the block
   // and emit a terminator instruction. This ensures correct spill placement.
   // FIXME: We should unconditionally split the block here.
   bool NeedBlockSplit = false;
   Register DataReg = MI.getOperand(0).getReg();
   for (MachineBasicBlock::iterator I = InsPt, E = MI.getIterator();
        I != E; ++I) {
     if (I->modifiesRegister(DataReg, TRI)) {
       NeedBlockSplit = true;
       break;
     }
   }
 
   unsigned Opcode = OrOpc;
   MachineBasicBlock *SplitBB = &MBB;
   if (NeedBlockSplit) {
-    SplitBB = splitBlock(MI, &MBB, LIS);
+    SplitBB = MBB.splitAt(MI, /*UpdateLiveIns*/true, LIS);
     Opcode = OrTermrOpc;
     InsPt = MI;
   }
 
   MachineInstr *NewMI =
     BuildMI(MBB, InsPt, DL, TII->get(Opcode), Exec)
     .addReg(Exec)
     .add(MI.getOperand(0));