[ARM] VPT validForTailPredication

[samparker]

Summary

Mark all VPT instructions as valid.

[dmgreen]

Sounds good, providing we are dealing with the predicated correctly.

llvm/lib/Target/ARM/ARMInstrMVE.td

   let Inst{16} = 0b1;
   let Inst{15-13} = Mk{2-0};
   let Inst{12} = fc{2};
   let Inst{11-8} = 0b1111;
   let Inst{7} = fc{0};
   let Inst{4} = 0b0;
 
   let Defs = [VPR];
+  let validForTailPredication=1;
 }
 
 class MVE_VPTt1<string suffix, bits<2> size, dag iops>
   : MVE_VPT<suffix, size, iops, "$fc, $Qn, $Qm"> {
   bits<4> Qm;
   bits<4> Mk;
 
   let Inst{6} = 0b0;

   let Inst{15-13} = Mk{2-0};
   let Inst{12} = fc{2};
   let Inst{11-8} = 0b1111;
   let Inst{7} = fc{0};
   let Inst{4} = 0b0;
 
   let Defs = [VPR];
   let Predicates = [HasMVEFloat];
+  let validForTailPredication=1;
 }
 
 class MVE_VPTft1<string suffix, bit size>
   : MVE_VPTf<suffix, size, (ins vpt_mask:$Mk, MQPR:$Qn, MQPR:$Qm, pred_basic_fp:$fc),
           "$fc, $Qn, $Qm"> {
   bits<3> fc;
   bits<4> Qm;
 

llvm/unittests/Target/ARM/MachineInstrTest.cpp

auto IsValidTPOpcode = [](unsigned Opcode) {
     case MVE_VNEGs16:
     case MVE_VNEGs32:
     case MVE_VNEGs8:
     case MVE_VORN:
     case MVE_VORR:
     case MVE_VORRimmi16:
     case MVE_VORRimmi32:
     case MVE_VPST:
+    case MVE_VPTv16i8:
+    case MVE_VPTv8i16:
+    case MVE_VPTv4i32:
+    case MVE_VPTv16i8r:
+    case MVE_VPTv8i16r:
+    case MVE_VPTv4i32r:
+    case MVE_VPTv16s8:
+    case MVE_VPTv8s16:
+    case MVE_VPTv4s32:
+    case MVE_VPTv16s8r:
+    case MVE_VPTv8s16r:
+    case MVE_VPTv4s32r:
+    case MVE_VPTv16u8:
+    case MVE_VPTv8u16:
+    case MVE_VPTv4u32:
+    case MVE_VPTv16u8r:
+    case MVE_VPTv8u16r:
+    case MVE_VPTv4u32r:
+    case MVE_VPTv8f16:
+    case MVE_VPTv4f32:
+    case MVE_VPTv8f16r:
+    case MVE_VPTv4f32r:
     case MVE_VQABSs16:
     case MVE_VQABSs32:
     case MVE_VQABSs8:
     case MVE_VQADD_qr_s16:
     case MVE_VQADD_qr_s32:
     case MVE_VQADD_qr_s8:
     case MVE_VQADD_qr_u16:
     case MVE_VQADD_qr_u32: