[X86] Use the same sequence for i128 ISD::ABS on 64-bit targets as we use for i64 on 32-bit targets.

[RKSimon]

LGTM

llvm/test/CodeGen/X86/iabs.ll

123

precommit this test?

llvm/lib/Target/X86/X86ISelLowering.cpp

X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
   }
 
   // Integer absolute.
   if (Subtarget.hasCMov()) {
     setOperationAction(ISD::ABS            , MVT::i16  , Custom);
     setOperationAction(ISD::ABS            , MVT::i32  , Custom);
   }
   setOperationAction(ISD::ABS              , MVT::i64  , Custom);
+  if (Subtarget.is64Bit())
+    setOperationAction(ISD::ABS            , MVT::i128 , Custom);
 
   // Funnel shifts.
   for (auto ShiftOp : {ISD::FSHL, ISD::FSHR}) {
     // For slow shld targets we only lower for code size.
     LegalizeAction ShiftDoubleAction = Subtarget.isSHLDSlow() ? Custom : Legal;
 
     setOperationAction(ShiftOp             , MVT::i8   , Custom);
     setOperationAction(ShiftOp             , MVT::i16  , Custom);
case X86ISD::AVG: {
     Ops[0] = N->getOperand(1);
     SDValue InVec1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, InWideVT, Ops);
 
     SDValue Res = DAG.getNode(N->getOpcode(), dl, WideVT, InVec0, InVec1);
     Results.push_back(Res);
     return;
   }
   case ISD::ABS: {
-    assert(N->getValueType(0) == MVT::i64 &&
+    assert((Subtarget.is64Bit() || N->getValueType(0) == MVT::i64) &&
            "Unexpected type (!= i64) on ABS.");
-    MVT HalfT = MVT::i32;
+    assert((!Subtarget.is64Bit() || N->getValueType(0) == MVT::i128) &&
+           "Unexpected type (!= i128) on ABS.");
+    MVT VT = N->getSimpleValueType(0);
+    MVT HalfT = VT == MVT::i128 ? MVT::i64 : MVT::i32;
     SDValue Lo, Hi, Tmp;
     SDVTList VTList = DAG.getVTList(HalfT, MVT::i1);
 
     Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(0),
                      DAG.getConstant(0, dl, HalfT));
     Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(0),
                      DAG.getConstant(1, dl, HalfT));
     Tmp = DAG.getNode(
         ISD::SRA, dl, HalfT, Hi,
         DAG.getShiftAmountConstant(HalfT.getSizeInBits() - 1, HalfT, dl));
     Lo = DAG.getNode(ISD::UADDO, dl, VTList, Tmp, Lo);
     Hi = DAG.getNode(ISD::ADDCARRY, dl, VTList, Tmp, Hi,
                      SDValue(Lo.getNode(), 1));
     Hi = DAG.getNode(ISD::XOR, dl, HalfT, Tmp, Hi);
     Lo = DAG.getNode(ISD::XOR, dl, HalfT, Tmp, Lo);
-    Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi));
+    Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, VT, Lo, Hi));
     return;
   }
   // We might have generated v2f32 FMIN/FMAX operations. Widen them to v4f32.
   case X86ISD::FMINC:
   case X86ISD::FMIN:
   case X86ISD::FMAXC:
   case X86ISD::FMAX: {
     EVT VT = N->getValueType(0);

llvm/test/CodeGen/X86/abs.ll

 ; X86-NEXT:    retl
   %r = call i64 @llvm.abs.i64(i64 %a, i1 false)
   ret i64 %r
 }
 
 define i128 @test_i128(i128 %a) nounwind {
 ; X64-LABEL: test_i128:
 ; X64:       # %bb.0:
-; X64-NEXT:    xorl %edx, %edx
+; X64-NEXT:    movq %rsi, %rdx
 ; X64-NEXT:    movq %rdi, %rax
-; X64-NEXT:    negq %rax
-; X64-NEXT:    sbbq %rsi, %rdx
-; X64-NEXT:    testq %rsi, %rsi
-; X64-NEXT:    cmovnsq %rdi, %rax
-; X64-NEXT:    cmovnsq %rsi, %rdx
+; X64-NEXT:    movq %rsi, %rcx
+; X64-NEXT:    sarq $63, %rcx
+; X64-NEXT:    addq %rcx, %rax
+; X64-NEXT:    adcq %rcx, %rdx
+; X64-NEXT:    xorq %rcx, %rax
+; X64-NEXT:    xorq %rcx, %rdx
 ; X64-NEXT:    retq
 ;
 ; X86-LABEL: test_i128:
 ; X86:       # %bb.0:
 ; X86-NEXT:    pushl %ebp
 ; X86-NEXT:    pushl %ebx
 ; X86-NEXT:    pushl %edi
 ; X86-NEXT:    pushl %esi

llvm/test/CodeGen/X86/iabs.ll

 ; X64-NEXT:    cmovlq %rdi, %rax
 ; X64-NEXT:    retq
   %tmp1neg = sub i64 0, %a
   %b = icmp sgt i64 %a, -1
   %abs = select i1 %b, i64 %a, i64 %tmp1neg
   ret i64 %abs
 }
 
 define i128 @test_i128(i128 %a) nounwind {
 ; X86-NO-CMOV-LABEL: test_i128:
 ; X86-NO-CMOV:       # %bb.0:
 ; X86-NO-CMOV-NEXT:    pushl %ebp
 ; X86-NO-CMOV-NEXT:    pushl %ebx
 ; X86-NO-CMOV-NEXT:    pushl %edi
 ; X86-NO-CMOV-NEXT:    pushl %esi
 ; X86-NO-CMOV-NEXT:    movl {{[0-9]+}}(%esp), %ebp
 ; X86-NO-CMOV-NEXT:    movl {{[0-9]+}}(%esp), %edx

 ; X86-CMOV-NEXT:    popl %esi
 ; X86-CMOV-NEXT:    popl %edi
 ; X86-CMOV-NEXT:    popl %ebx
 ; X86-CMOV-NEXT:    popl %ebp
 ; X86-CMOV-NEXT:    retl $4
 ;
 ; X64-LABEL: test_i128:
 ; X64:       # %bb.0:
-; X64-NEXT:    xorl %edx, %edx
+; X64-NEXT:    movq %rsi, %rdx
 ; X64-NEXT:    movq %rdi, %rax
-; X64-NEXT:    negq %rax
-; X64-NEXT:    sbbq %rsi, %rdx
-; X64-NEXT:    testq %rsi, %rsi
-; X64-NEXT:    cmovnsq %rdi, %rax
-; X64-NEXT:    cmovnsq %rsi, %rdx
+; X64-NEXT:    movq %rsi, %rcx
+; X64-NEXT:    sarq $63, %rcx
+; X64-NEXT:    addq %rcx, %rax
+; X64-NEXT:    adcq %rcx, %rdx
+; X64-NEXT:    xorq %rcx, %rax
+; X64-NEXT:    xorq %rcx, %rdx
 ; X64-NEXT:    retq
   %tmp1neg = sub i128 0, %a
   %b = icmp sgt i128 %a, -1
   %abs = select i1 %b, i128 %a, i128 %tmp1neg
   ret i128 %abs
 }