[APInt] New member function setBitVal

[lebedev.ri]

LGTM

llvm/include/llvm/ADT/APInt.h

1454

I think setBitVal() might be better.

[RKSimon]

llvm/include/llvm/ADT/APInt.h

1454

+1

[RKSimon]

llvm/include/llvm/ADT/APInt.h

1454

Would it be simpler if we just did:

if (BitValue)
  setBit(BitPosition);
else
  clearBit(BitPosition);

[foad]

llvm/include/llvm/ADT/APInt.h

1454

OK. I was trying to reduce the number of conditional branches but maybe it's not helpful in this case.

[foad]

Rename to setBitVal and change implementation.

[andreadb]

Looks good to me.

llvm/include/llvm/ADT/APInt.h

else
       U.pVal[whichWord(BitPosition)] |= Mask;
   }
 
   /// Set the sign bit to 1.
   void setSignBit() {
     setBit(BitWidth - 1);
   }
 
+  /// Set a given bit to a given value.
+  void setBitTo(unsigned BitPosition, bool BitValue) {
+    assert(BitPosition < BitWidth && "BitPosition out of range");
+    WordType Mask = ~maskBit(BitPosition);
+    WordType ShiftedBit = WordType(BitValue) << whichBit(BitPosition);
+    if (isSingleWord()) {
+      U.VAL = (U.VAL & Mask) | ShiftedBit;
+    } else {
+      U.pVal[whichWord(BitPosition)] =
+          (U.pVal[whichWord(BitPosition)] & Mask) | ShiftedBit;
+    }
+  }
+
   /// Set the bits from loBit (inclusive) to hiBit (exclusive) to 1.
   /// This function handles "wrap" case when \p loBit >= \p hiBit, and calls
   /// setBits when \p loBit < \p hiBit.
   /// For \p loBit == \p hiBit wrap case, set every bit to 1.
   void setBitsWithWrap(unsigned loBit, unsigned hiBit) {
     assert(hiBit <= BitWidth && "hiBit out of range");
     assert(loBit <= BitWidth && "loBit out of range");
     if (loBit < hiBit) {

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

if (CIdx && CIdx->getAPIntValue().ult(NumElts)) {
         return TLO.CombineTo(Op, Vec);
 
       APInt DemandedVecElts(DemandedElts);
       DemandedVecElts.clearBit(Idx);
       if (SimplifyDemandedVectorElts(Vec, DemandedVecElts, KnownUndef,
                                      KnownZero, TLO, Depth + 1))
         return true;
 
-      KnownUndef.clearBit(Idx);
-      if (Scl.isUndef())
-        KnownUndef.setBit(Idx);
-
-      KnownZero.clearBit(Idx);
-      if (isNullConstant(Scl) || isNullFPConstant(Scl))
-        KnownZero.setBit(Idx);
+      KnownUndef.setBitTo(Idx, Scl.isUndef());
+
+      KnownZero.setBitTo(Idx, isNullConstant(Scl) || isNullFPConstant(Scl));
       break;
     }
 
     APInt VecUndef, VecZero;
     if (SimplifyDemandedVectorElts(Vec, DemandedElts, VecUndef, VecZero, TLO,
                                    Depth + 1))
       return true;
     // Without knowing the insertion index we can't set KnownUndef/KnownZero.

llvm/lib/MCA/HardwareUnits/RegisterFile.cpp

if (!WS.clearsSuperRegisters()) {
         OtherWS->addUser(OtherWrite.getSourceIndex(), &WS);
       }
     }
   }
 
   // Update zero registers.
   MCPhysReg ZeroRegisterID =
       WS.clearsSuperRegisters() ? RegID : WS.getRegisterID();
-  if (IsWriteZero) {
-    ZeroRegisters.setBit(ZeroRegisterID);
-    for (MCSubRegIterator I(ZeroRegisterID, &MRI); I.isValid(); ++I)
-      ZeroRegisters.setBit(*I);
-  } else {
-    ZeroRegisters.clearBit(ZeroRegisterID);
-    for (MCSubRegIterator I(ZeroRegisterID, &MRI); I.isValid(); ++I)
-      ZeroRegisters.clearBit(*I);
-  }
+  ZeroRegisters.setBitTo(ZeroRegisterID, IsWriteZero);
+    ZeroRegisters.setBitTo(*I, IsWriteZero);
 
   // If this is move has been eliminated, then the call to tryEliminateMove
   // should have already updated all the register mappings.
   if (!IsEliminated) {
     // Update the mapping for register RegID including its sub-registers.
     RegisterMappings[RegID].first = Write;
     RegisterMappings[RegID].second.AliasRegID = 0U;
     for (MCSubRegIterator I(RegID, &MRI); I.isValid(); ++I) {
if (!WS.clearsSuperRegisters())
     return;
 
   for (MCSuperRegIterator I(RegID, &MRI); I.isValid(); ++I) {
     if (!IsEliminated) {
       RegisterMappings[*I].first = Write;
       RegisterMappings[*I].second.AliasRegID = 0U;
     }
 
-    if (IsWriteZero)
-      ZeroRegisters.setBit(*I);
-    else
-      ZeroRegisters.clearBit(*I);
+    ZeroRegisters.setBitTo(*I, IsWriteZero);
   }
 }
 
 void RegisterFile::removeRegisterWrite(
     const WriteState &WS, MutableArrayRef<unsigned> FreedPhysRegs) {
   // Early exit if this write was eliminated. A write eliminated at register
   // renaming stage generates an alias, and it is not added to the PRF.
   if (WS.isEliminated())

llvm/lib/Support/APInt.cpp

void APInt::flipAllBitsSlowCase() {
   clearUnusedBits();
 }
 
 /// Toggle a given bit to its opposite value whose position is given
 /// as "bitPosition".
 /// Toggles a given bit to its opposite value.
 void APInt::flipBit(unsigned bitPosition) {
   assert(bitPosition < BitWidth && "Out of the bit-width range!");
-  if ((*this)[bitPosition]) clearBit(bitPosition);
-  else setBit(bitPosition);
+  setBitTo(bitPosition, !(*this)[bitPosition]);
 }
 
 void APInt::insertBits(const APInt &subBits, unsigned bitPosition) {
   unsigned subBitWidth = subBits.getBitWidth();
   assert(0 < subBitWidth && (subBitWidth + bitPosition) <= BitWidth &&
          "Illegal bit insertion");
 
   // Insertion is a direct copy.
if (remainingBits != 0) {
       U.pVal[hi1Word] |= subBits.getWord(subBitWidth - 1);
     }
     return;
   }
 
   // General case - set/clear individual bits in dst based on src.
   // TODO - there is scope for optimization here, but at the moment this code
   // path is barely used so prefer readability over performance.
-  for (unsigned i = 0; i != subBitWidth; ++i) {
-    if (subBits[i])
-      setBit(bitPosition + i);
-    else
-      clearBit(bitPosition + i);
-  }
+  for (unsigned i = 0; i != subBitWidth; ++i)
+    setBitTo(bitPosition + i, subBits[i]);
 }
 
 void APInt::insertBits(uint64_t subBits, unsigned bitPosition, unsigned numBits) {
   uint64_t maskBits = maskTrailingOnes<uint64_t>(numBits);
   subBits &= maskBits;
   if (isSingleWord()) {
     U.VAL &= ~(maskBits << bitPosition);
     U.VAL |= subBits << bitPosition;