[PowerPC] Implement builtins for xvcvspbf16 and xvcvbf16spn

[amyk]

Summary

This patch adds the builtin implementation for the xvcvspbf16 and xvcvbf16spn instructions.

Depends on D86794.

[bsaleil]

LGTM, thanks for adding that.

clang/include/clang/Basic/BuiltinsPPC.def

 BUILTIN(__builtin_vsx_xvcvspdp, "V2dV4f", "")
 BUILTIN(__builtin_vsx_xvcvsxdsp, "V4fV2SLLi", "")
 BUILTIN(__builtin_vsx_xvcvuxdsp, "V4fV2ULLi", "")
 BUILTIN(__builtin_vsx_xvcvdpsp, "V4fV2d", "")
 
 BUILTIN(__builtin_vsx_xvcvsphp, "V4fV4f", "")
 BUILTIN(__builtin_vsx_xvcvhpsp, "V4fV8Us", "")
 
+BUILTIN(__builtin_vsx_xvcvspbf16, "V16UcV16Uc", "")
+BUILTIN(__builtin_vsx_xvcvbf16spn, "V16UcV16Uc", "")
+
 // Vector Test Data Class builtins
 BUILTIN(__builtin_vsx_xvtstdcdp, "V2ULLiV2dIi", "")
 BUILTIN(__builtin_vsx_xvtstdcsp, "V4UiV4fIi", "")
 
 BUILTIN(__builtin_vsx_insertword, "V16UcV4UiV16UcIi", "")
 BUILTIN(__builtin_vsx_extractuword, "V2ULLiV16UcIi", "")
 
 BUILTIN(__builtin_vsx_xxpermdi, "v.", "t")

clang/test/CodeGen/builtins-ppc-p10vector.c

 }
 
 vector unsigned long long test_vec_mod_ull(void) {
   // CHECK: urem <2 x i64>
   // CHECK-NEXT: ret <2 x i64>
   return vec_mod(vulla, vullb);
 }
 
+vector unsigned char test_xvcvspbf16(vector unsigned char vc) {
+  // CHECK-LABEL: @test_xvcvspbf16(
+  // CHECK:    [[TMP0:%.*]] = call <16 x i8> @llvm.ppc.vsx.xvcvspbf16(<16 x i8> [[VC:%.*]])
+  return __builtin_vsx_xvcvspbf16(vc);
+}
+
+vector unsigned char test_xvcvbf16spn(vector unsigned char vc) {
+  // CHECK-LABEL: @test_xvcvbf16spn(
+  // CHECK:    [[TMP0:%.*]] = call <16 x i8> @llvm.ppc.vsx.xvcvbf16spn(<16 x i8> [[VC:%.*]])
+  return __builtin_vsx_xvcvbf16spn(vc);
+}
+
 vector unsigned long long test_vpdepd(void) {
   // CHECK: @llvm.ppc.altivec.vpdepd(<2 x i64>
   // CHECK-NEXT: ret <2 x i64>
   return vec_pdep(vulla, vullb);
 }
 
 vector unsigned long long test_vpextd(void) {
   // CHECK: @llvm.ppc.altivec.vpextd(<2 x i64>

llvm/include/llvm/IR/IntrinsicsPowerPC.td

def int_ppc_vsx_xvtstdcdp :
       PowerPC_VSX_Intrinsic<"xvtstdcdp", [llvm_v2i64_ty],
                             [llvm_v2f64_ty, llvm_i32_ty], [IntrNoMem, ImmArg<ArgIndex<1>>]>;
 def int_ppc_vsx_xvtstdcsp :
       PowerPC_VSX_Intrinsic<"xvtstdcsp", [llvm_v4i32_ty],
                             [llvm_v4f32_ty,llvm_i32_ty], [IntrNoMem, ImmArg<ArgIndex<1>>]>;
 def int_ppc_vsx_xvcvhpsp :
       PowerPC_VSX_Intrinsic<"xvcvhpsp", [llvm_v4f32_ty],
                             [llvm_v8i16_ty],[IntrNoMem]>;
+def int_ppc_vsx_xvcvspbf16 :
+      PowerPC_VSX_Intrinsic<"xvcvspbf16", [llvm_v16i8_ty],
+                            [llvm_v16i8_ty], [IntrNoMem]>;
+def int_ppc_vsx_xvcvbf16spn :
+      PowerPC_VSX_Intrinsic<"xvcvbf16spn", [llvm_v16i8_ty],
+                            [llvm_v16i8_ty], [IntrNoMem]>;
 def int_ppc_vsx_xxextractuw :
       PowerPC_VSX_Intrinsic<"xxextractuw",[llvm_v2i64_ty],
                             [llvm_v2i64_ty,llvm_i32_ty], [IntrNoMem]>;
 def int_ppc_vsx_xxinsertw :
       PowerPC_VSX_Intrinsic<"xxinsertw",[llvm_v4i32_ty],
                             [llvm_v4i32_ty,llvm_v2i64_ty,llvm_i32_ty],
                             [IntrNoMem]>;
 def int_ppc_vsx_xvtlsbb :

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

def pc : 8LS_DForm_R_SI34_XT6_RA5<opcode, OOL, PCRel_IOL,
                                     isPCRel;
 }
 
 def PrefixInstrs : Predicate<"Subtarget->hasPrefixInstrs()">;
 def IsISA3_1 : Predicate<"Subtarget->isISA3_1()">;
 def PairedVectorMemops : Predicate<"PPCSubTarget->pairedVectorMemops()">;
 def MMA : Predicate<"PPCSubTarget->hasMMA()">;
 
+def RCCp {
+  dag AToVSRC = (COPY_TO_REGCLASS $XA, VSRC);
+  dag BToVSRC = (COPY_TO_REGCLASS $XB, VSRC);
+}
+
 let Predicates = [PrefixInstrs] in {
   let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
     defm PADDI8 :
       MLS_DForm_R_SI34_RTA5_p<14, (outs g8rc:$RT), (ins g8rc:$RA, s34imm:$SI),
                               (ins immZero:$RA, s34imm_pcrel:$SI),
                               "paddi $RT, $RA, $SI", IIC_LdStLFD>;
     let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
       def PLI8 : MLS_DForm_SI34_RT5<14, (outs g8rc:$RT),
let Predicates = [IsISA3_1] in {
   def : Pat <(v1i128 (PPClxvrzx xoaddr:$src, 16)),
              (v1i128 (COPY_TO_REGCLASS (LXVRHX xoaddr:$src), VRRC))>;
   def : Pat <(v1i128 (PPClxvrzx xoaddr:$src, 32)),
              (v1i128 (COPY_TO_REGCLASS (LXVRWX xoaddr:$src), VRRC))>;
   def : Pat <(v1i128 (PPClxvrzx xoaddr:$src, 64)),
              (v1i128 (COPY_TO_REGCLASS (LXVRDX xoaddr:$src), VRRC))>;
 }
 
+let Predicates = [IsISA3_1, HasVSX] in {
+  def : Pat<(v16i8 (int_ppc_vsx_xvcvspbf16 v16i8:$XA)),
+            (COPY_TO_REGCLASS (XVCVSPBF16 RCCp.AToVSRC), VRRC)>;
+  def : Pat<(v16i8 (int_ppc_vsx_xvcvbf16spn v16i8:$XA)),
+            (COPY_TO_REGCLASS (XVCVBF16SPN RCCp.AToVSRC), VRRC)>;
+}
+
 let AddedComplexity = 400, Predicates = [IsISA3_1] in {
   def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$rS, 0)), xoaddr:$src),
             (STXVRBX (COPY_TO_REGCLASS $rS, VSRC), xoaddr:$src)>;
   def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$rS, 0)), xoaddr:$src),
             (STXVRHX (COPY_TO_REGCLASS $rS, VSRC), xoaddr:$src)>;
   def : Pat<(store (i32 (vector_extract v4i32:$rS, 0)), xoaddr:$src),
             (STXVRWX (COPY_TO_REGCLASS $rS, VSRC), xoaddr:$src)>;
   def : Pat<(store (i64 (vector_extract v2i64:$rS, 0)), xoaddr:$src),

llvm/test/CodeGen/PowerPC/bfloat16-outer-product.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names \
+; RUN:   -ppc-vsr-nums-as-vr < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names \
+; RUN:   -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-BE
+
+; Function Attrs: nofree nounwind writeonly
+define dso_local void @test60(i8* nocapture readnone %vqp, i8* nocapture readnone %vpp, <16 x i8> %vc, i8* nocapture %resp) {
+; CHECK-LABEL: test60:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xvcvspbf16 vs0, v2
+; CHECK-NEXT:    stxv vs0, 0(r7)
+; CHECK-NEXT:    blr
+;
+; CHECK-BE-LABEL: test60:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    xvcvspbf16 vs0, v2
+; CHECK-BE-NEXT:    stxv vs0, 0(r7)
+; CHECK-BE-NEXT:    blr
+entry:
+  %0 = tail call <16 x i8> @llvm.ppc.vsx.xvcvspbf16(<16 x i8> %vc)
+  %1 = bitcast i8* %resp to <16 x i8>*
+  store <16 x i8> %0, <16 x i8>* %1, align 16
+  ret void
+}
+; Function Attrs: nounwind readnone
+declare <16 x i8> @llvm.ppc.vsx.xvcvspbf16(<16 x i8>)
+
+; Function Attrs: nofree nounwind writeonly
+define dso_local void @test61(i8* nocapture readnone %vqp, i8* nocapture readnone %vpp, <16 x i8> %vc, i8* nocapture %resp) {
+; CHECK-LABEL: test61:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xvcvbf16spn vs0, v2
+; CHECK-NEXT:    stxv vs0, 0(r7)
+; CHECK-NEXT:    blr
+;
+; CHECK-BE-LABEL: test61:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    xvcvbf16spn vs0, v2
+; CHECK-BE-NEXT:    stxv vs0, 0(r7)
+; CHECK-BE-NEXT:    blr
+entry:
+  %0 = tail call <16 x i8> @llvm.ppc.vsx.xvcvbf16spn(<16 x i8> %vc)
+  %1 = bitcast i8* %resp to <16 x i8>*
+  store <16 x i8> %0, <16 x i8>* %1, align 16
+  ret void
+}
+
+; Function Attrs: nounwind readnone
+declare <16 x i8> @llvm.ppc.vsx.xvcvbf16spn(<16 x i8>)