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Differential D85824

[ARM] Predicated VFMA patterns
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Authored by dmgreen on Aug 12 2020, 2:49 AM.

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Reviewers
SjoerdMeijer
samparker
efriedma
simon_tatham
samtebbs
ostannard
Commits
rG1bb348868501: [ARM] Predicated VFMA patterns
Summary

Similar to the Two op + select patterns that were added recently, the adds some patterns for select + fma to turn them into predicated operations.

Diff Detail

Event Timeline

dmgreen created this revision.Aug 12 2020, 2:49 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 12 2020, 2:49 AM
Herald added subscribers: danielkiss, hiraditya, kristof.beyls. · View Herald Transcript
dmgreen requested review of this revision.Aug 12 2020, 2:49 AM
samparker accepted this revision.Aug 12 2020, 3:52 AM
This revision is now accepted and ready to land.Aug 12 2020, 3:52 AM
Closed by commit rG1bb348868501: [ARM] Predicated VFMA patterns (authored by dmgreen). · Explain WhyAug 12 2020, 10:36 AM
This revision was automatically updated to reflect the committed changes.
dmgreen added a commit: rG1bb348868501: [ARM] Predicated VFMA patterns.

Revision Contents

PathSize
llvm/
lib/
Target/
ARM/
24 lines
test/
CodeGen/
Thumb2/
60 lines

Diff 285138

llvm/lib/Target/ARM/ARMInstrMVE.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 3,646 Lines • ▼ Show 20 Linesmulticlass MVE_VFMA_fp_multi<string iname, bit fms, MVEVectorVTInfo VTI> {
defvar pred = (VTI.Pred VCCR:$pred); defvar pred = (VTI.Pred VCCR:$pred);
let Predicates = [HasMVEFloat] in { let Predicates = [HasMVEFloat] in {
if fms then { if fms then {
def : Pat<(VTI.Vec (fma (fneg m1), m2, add)), def : Pat<(VTI.Vec (fma (fneg m1), m2, add)),
(Inst $add, $m1, $m2)>; (Inst $add, $m1, $m2)>;
def : Pat<(VTI.Vec (fma m1, (fneg m2), add)), def : Pat<(VTI.Vec (fma m1, (fneg m2), add)),
(Inst $add, $m1, $m2)>; (Inst $add, $m1, $m2)>;
def : Pat<(VTI.Vec (vselect (VTI.Pred VCCR:$pred),
(VTI.Vec (fma (fneg m1), m2, add)),
add)),
(Inst $add, $m1, $m2, ARMVCCThen, $pred)>;
def : Pat<(VTI.Vec (vselect (VTI.Pred VCCR:$pred),
(VTI.Vec (fma m1, (fneg m2), add)),
add)),
(Inst $add, $m1, $m2, ARMVCCThen, $pred)>;
def : Pat<(VTI.Vec (pred_int (fneg m1), m2, add, pred)), def : Pat<(VTI.Vec (pred_int (fneg m1), m2, add, pred)),
(Inst $add, $m1, $m2, ARMVCCThen, $pred)>; (Inst $add, $m1, $m2, ARMVCCThen, $pred)>;
def : Pat<(VTI.Vec (pred_int m1, (fneg m2), add, pred)), def : Pat<(VTI.Vec (pred_int m1, (fneg m2), add, pred)),
(Inst $add, $m1, $m2, ARMVCCThen, $pred)>; (Inst $add, $m1, $m2, ARMVCCThen, $pred)>;
} else { } else {
def : Pat<(VTI.Vec (fma m1, m2, add)), def : Pat<(VTI.Vec (fma m1, m2, add)),
(Inst $add, $m1, $m2)>; (Inst $add, $m1, $m2)>;
def : Pat<(VTI.Vec (vselect (VTI.Pred VCCR:$pred),
(VTI.Vec (fma m1, m2, add)),
add)),
(Inst $add, $m1, $m2, ARMVCCThen, $pred)>;
def : Pat<(VTI.Vec (pred_int m1, m2, add, pred)), def : Pat<(VTI.Vec (pred_int m1, m2, add, pred)),
(Inst $add, $m1, $m2, ARMVCCThen, $pred)>; (Inst $add, $m1, $m2, ARMVCCThen, $pred)>;
} }
} }
} }
defm MVE_VFMAf32 : MVE_VFMA_fp_multi<"vfma", 0, MVE_v4f32>; defm MVE_VFMAf32 : MVE_VFMA_fp_multi<"vfma", 0, MVE_v4f32>;
defm MVE_VFMAf16 : MVE_VFMA_fp_multi<"vfma", 0, MVE_v8f16>; defm MVE_VFMAf16 : MVE_VFMA_fp_multi<"vfma", 0, MVE_v8f16>;
▲ Show 20 Lines • Show All 1,863 Lines • ▼ Show 20 Linesmulticlass MVE_VFMA_qr_multi<string iname, MVEVectorVTInfo VTI,
defvar vs = (VTI.Vec (ARMvdup (i32 rGPR:$s))); defvar vs = (VTI.Vec (ARMvdup (i32 rGPR:$s)));
defvar is = (i32 rGPR:$s); defvar is = (i32 rGPR:$s);
defvar pred = (VTI.Pred VCCR:$pred); defvar pred = (VTI.Pred VCCR:$pred);
let Predicates = [HasMVEFloat] in { let Predicates = [HasMVEFloat] in {
if scalar_addend then { if scalar_addend then {
def : Pat<(VTI.Vec (fma v1, v2, vs)), def : Pat<(VTI.Vec (fma v1, v2, vs)),
(VTI.Vec (Inst v1, v2, is))>; (VTI.Vec (Inst v1, v2, is))>;
def : Pat<(VTI.Vec (vselect (VTI.Pred VCCR:$pred),
(VTI.Vec (fma v1, v2, vs)),
v1)),
(VTI.Vec (Inst v1, v2, is, ARMVCCThen, $pred))>;
def : Pat<(VTI.Vec (pred_int v1, v2, vs, pred)), def : Pat<(VTI.Vec (pred_int v1, v2, vs, pred)),
(VTI.Vec (Inst v1, v2, is, ARMVCCThen, pred))>; (VTI.Vec (Inst v1, v2, is, ARMVCCThen, pred))>;
} else { } else {
def : Pat<(VTI.Vec (fma v1, vs, v2)), def : Pat<(VTI.Vec (fma v1, vs, v2)),
(VTI.Vec (Inst v2, v1, is))>; (VTI.Vec (Inst v2, v1, is))>;
def : Pat<(VTI.Vec (fma vs, v1, v2)), def : Pat<(VTI.Vec (fma vs, v1, v2)),
(VTI.Vec (Inst v2, v1, is))>; (VTI.Vec (Inst v2, v1, is))>;
def : Pat<(VTI.Vec (vselect (VTI.Pred VCCR:$pred),
(VTI.Vec (fma vs, v2, v1)),
v1)),
(VTI.Vec (Inst v1, v2, is, ARMVCCThen, $pred))>;
def : Pat<(VTI.Vec (vselect (VTI.Pred VCCR:$pred),
(VTI.Vec (fma v2, vs, v1)),
v1)),
(VTI.Vec (Inst v1, v2, is, ARMVCCThen, $pred))>;
def : Pat<(VTI.Vec (pred_int v1, vs, v2, pred)), def : Pat<(VTI.Vec (pred_int v1, vs, v2, pred)),
(VTI.Vec (Inst v2, v1, is, ARMVCCThen, pred))>; (VTI.Vec (Inst v2, v1, is, ARMVCCThen, pred))>;
def : Pat<(VTI.Vec (pred_int vs, v1, v2, pred)), def : Pat<(VTI.Vec (pred_int vs, v1, v2, pred)),
(VTI.Vec (Inst v2, v1, is, ARMVCCThen, pred))>; (VTI.Vec (Inst v2, v1, is, ARMVCCThen, pred))>;
} }
} }
} }
▲ Show 20 Lines • Show All 1,737 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-fmas.ll

Show First 20 Lines • Show All 475 Lines • ▼ Show 20 Lines
; CHECK-MVE-FP: @ %bb.0: @ %entry ; CHECK-MVE-FP: @ %bb.0: @ %entry
; CHECK-MVE-FP-NEXT: vmul.f16 q2, q1, q2 ; CHECK-MVE-FP-NEXT: vmul.f16 q2, q1, q2
; CHECK-MVE-FP-NEXT: vpt.f16 lt, q1, zr ; CHECK-MVE-FP-NEXT: vpt.f16 lt, q1, zr
; CHECK-MVE-FP-NEXT: vaddt.f16 q0, q0, q2 ; CHECK-MVE-FP-NEXT: vaddt.f16 q0, q0, q2
; CHECK-MVE-FP-NEXT: bx lr ; CHECK-MVE-FP-NEXT: bx lr
; ;
; CHECK-MVE-VMLA-LABEL: vfma16_v1_pred: ; CHECK-MVE-VMLA-LABEL: vfma16_v1_pred:
; CHECK-MVE-VMLA: @ %bb.0: @ %entry ; CHECK-MVE-VMLA: @ %bb.0: @ %entry
; CHECK-MVE-VMLA-NEXT: vmov q3, q0 ; CHECK-MVE-VMLA-NEXT: vpt.f16 lt, q1, zr
; CHECK-MVE-VMLA-NEXT: vcmp.f16 lt, q1, zr ; CHECK-MVE-VMLA-NEXT: vfmat.f16 q0, q1, q2
; CHECK-MVE-VMLA-NEXT: vfma.f16 q3, q1, q2
; CHECK-MVE-VMLA-NEXT: vpsel q0, q3, q0
; CHECK-MVE-VMLA-NEXT: bx lr ; CHECK-MVE-VMLA-NEXT: bx lr
; ;
; CHECK-MVE-LABEL: vfma16_v1_pred: ; CHECK-MVE-LABEL: vfma16_v1_pred:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11}
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
▲ Show 20 Lines • Show All 127 Lines • ▼ Show 20 Lines
; CHECK-MVE-FP: @ %bb.0: @ %entry ; CHECK-MVE-FP: @ %bb.0: @ %entry
; CHECK-MVE-FP-NEXT: vmul.f16 q2, q1, q2 ; CHECK-MVE-FP-NEXT: vmul.f16 q2, q1, q2
; CHECK-MVE-FP-NEXT: vpt.f16 lt, q1, zr ; CHECK-MVE-FP-NEXT: vpt.f16 lt, q1, zr
; CHECK-MVE-FP-NEXT: vaddt.f16 q0, q2, q0 ; CHECK-MVE-FP-NEXT: vaddt.f16 q0, q2, q0
; CHECK-MVE-FP-NEXT: bx lr ; CHECK-MVE-FP-NEXT: bx lr
; ;
; CHECK-MVE-VMLA-LABEL: vfma16_v2_pred: ; CHECK-MVE-VMLA-LABEL: vfma16_v2_pred:
; CHECK-MVE-VMLA: @ %bb.0: @ %entry ; CHECK-MVE-VMLA: @ %bb.0: @ %entry
; CHECK-MVE-VMLA-NEXT: vmov q3, q0 ; CHECK-MVE-VMLA-NEXT: vpt.f16 lt, q1, zr
; CHECK-MVE-VMLA-NEXT: vcmp.f16 lt, q1, zr ; CHECK-MVE-VMLA-NEXT: vfmat.f16 q0, q1, q2
; CHECK-MVE-VMLA-NEXT: vfma.f16 q3, q1, q2
; CHECK-MVE-VMLA-NEXT: vpsel q0, q3, q0
; CHECK-MVE-VMLA-NEXT: bx lr ; CHECK-MVE-VMLA-NEXT: bx lr
; ;
; CHECK-MVE-LABEL: vfma16_v2_pred: ; CHECK-MVE-LABEL: vfma16_v2_pred:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11}
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
▲ Show 20 Lines • Show All 127 Lines • ▼ Show 20 Lines
; CHECK-MVE-FP: @ %bb.0: @ %entry ; CHECK-MVE-FP: @ %bb.0: @ %entry
; CHECK-MVE-FP-NEXT: vmul.f16 q2, q1, q2 ; CHECK-MVE-FP-NEXT: vmul.f16 q2, q1, q2
; CHECK-MVE-FP-NEXT: vpt.f16 lt, q1, zr ; CHECK-MVE-FP-NEXT: vpt.f16 lt, q1, zr
; CHECK-MVE-FP-NEXT: vsubt.f16 q0, q0, q2 ; CHECK-MVE-FP-NEXT: vsubt.f16 q0, q0, q2
; CHECK-MVE-FP-NEXT: bx lr ; CHECK-MVE-FP-NEXT: bx lr
; ;
; CHECK-MVE-VMLA-LABEL: vfms16_pred: ; CHECK-MVE-VMLA-LABEL: vfms16_pred:
; CHECK-MVE-VMLA: @ %bb.0: @ %entry ; CHECK-MVE-VMLA: @ %bb.0: @ %entry
; CHECK-MVE-VMLA-NEXT: vmov q3, q0 ; CHECK-MVE-VMLA-NEXT: vpt.f16 lt, q1, zr
; CHECK-MVE-VMLA-NEXT: vcmp.f16 lt, q1, zr ; CHECK-MVE-VMLA-NEXT: vfmst.f16 q0, q1, q2
; CHECK-MVE-VMLA-NEXT: vfms.f16 q3, q1, q2
; CHECK-MVE-VMLA-NEXT: vpsel q0, q3, q0
; CHECK-MVE-VMLA-NEXT: bx lr ; CHECK-MVE-VMLA-NEXT: bx lr
; ;
; CHECK-MVE-LABEL: vfms16_pred: ; CHECK-MVE-LABEL: vfms16_pred:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11}
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
▲ Show 20 Lines • Show All 131 Lines • ▼ Show 20 Lines
; CHECK-MVE-FP-NEXT: vmul.f16 q1, q1, r0 ; CHECK-MVE-FP-NEXT: vmul.f16 q1, q1, r0
; CHECK-MVE-FP-NEXT: vpst ; CHECK-MVE-FP-NEXT: vpst
; CHECK-MVE-FP-NEXT: vaddt.f16 q0, q0, q1 ; CHECK-MVE-FP-NEXT: vaddt.f16 q0, q0, q1
; CHECK-MVE-FP-NEXT: bx lr ; CHECK-MVE-FP-NEXT: bx lr
; ;
; CHECK-MVE-VMLA-LABEL: vfmar16_pred: ; CHECK-MVE-VMLA-LABEL: vfmar16_pred:
; CHECK-MVE-VMLA: @ %bb.0: @ %entry ; CHECK-MVE-VMLA: @ %bb.0: @ %entry
; CHECK-MVE-VMLA-NEXT: vcvtb.f16.f32 s8, s8 ; CHECK-MVE-VMLA-NEXT: vcvtb.f16.f32 s8, s8
; CHECK-MVE-VMLA-NEXT: vcmp.f16 lt, q1, zr
; CHECK-MVE-VMLA-NEXT: vmov.f16 r0, s8 ; CHECK-MVE-VMLA-NEXT: vmov.f16 r0, s8
; CHECK-MVE-VMLA-NEXT: vmov q2, q0 ; CHECK-MVE-VMLA-NEXT: vpt.f16 lt, q1, zr
; CHECK-MVE-VMLA-NEXT: vfma.f16 q2, q1, r0 ; CHECK-MVE-VMLA-NEXT: vfmat.f16 q0, q1, r0
; CHECK-MVE-VMLA-NEXT: vpsel q0, q2, q0
; CHECK-MVE-VMLA-NEXT: bx lr ; CHECK-MVE-VMLA-NEXT: bx lr
; ;
; CHECK-MVE-LABEL: vfmar16_pred: ; CHECK-MVE-LABEL: vfmar16_pred:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
▲ Show 20 Lines • Show All 127 Lines • ▼ Show 20 Lines
; CHECK-MVE-FP-NEXT: vmul.f16 q2, q0, q1 ; CHECK-MVE-FP-NEXT: vmul.f16 q2, q0, q1
; CHECK-MVE-FP-NEXT: vpt.f16 lt, q1, zr ; CHECK-MVE-FP-NEXT: vpt.f16 lt, q1, zr
; CHECK-MVE-FP-NEXT: vaddt.f16 q0, q2, r0 ; CHECK-MVE-FP-NEXT: vaddt.f16 q0, q2, r0
; CHECK-MVE-FP-NEXT: bx lr ; CHECK-MVE-FP-NEXT: bx lr
; ;
; CHECK-MVE-VMLA-LABEL: vfma16_pred: ; CHECK-MVE-VMLA-LABEL: vfma16_pred:
; CHECK-MVE-VMLA: @ %bb.0: @ %entry ; CHECK-MVE-VMLA: @ %bb.0: @ %entry
; CHECK-MVE-VMLA-NEXT: vcvtb.f16.f32 s8, s8 ; CHECK-MVE-VMLA-NEXT: vcvtb.f16.f32 s8, s8
; CHECK-MVE-VMLA-NEXT: vcmp.f16 lt, q1, zr
; CHECK-MVE-VMLA-NEXT: vmov.f16 r0, s8 ; CHECK-MVE-VMLA-NEXT: vmov.f16 r0, s8
; CHECK-MVE-VMLA-NEXT: vmov q2, q0 ; CHECK-MVE-VMLA-NEXT: vpt.f16 lt, q1, zr
; CHECK-MVE-VMLA-NEXT: vfmas.f16 q2, q1, r0 ; CHECK-MVE-VMLA-NEXT: vfmast.f16 q0, q1, r0
; CHECK-MVE-VMLA-NEXT: vpsel q0, q2, q0
; CHECK-MVE-VMLA-NEXT: bx lr ; CHECK-MVE-VMLA-NEXT: bx lr
; ;
; CHECK-MVE-LABEL: vfma16_pred: ; CHECK-MVE-LABEL: vfma16_pred:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f16 s4, #0 ; CHECK-MVE-NEXT: vcmp.f16 s4, #0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcvtb.f16.f32 s12, s8 ; CHECK-MVE-NEXT: vcvtb.f16.f32 s12, s8
▲ Show 20 Lines • Show All 123 Lines • ▼ Show 20 Lines
; CHECK-MVE-FP: @ %bb.0: @ %entry ; CHECK-MVE-FP: @ %bb.0: @ %entry
; CHECK-MVE-FP-NEXT: vmul.f32 q2, q1, q2 ; CHECK-MVE-FP-NEXT: vmul.f32 q2, q1, q2
; CHECK-MVE-FP-NEXT: vpt.f32 lt, q1, zr ; CHECK-MVE-FP-NEXT: vpt.f32 lt, q1, zr
; CHECK-MVE-FP-NEXT: vaddt.f32 q0, q0, q2 ; CHECK-MVE-FP-NEXT: vaddt.f32 q0, q0, q2
; CHECK-MVE-FP-NEXT: bx lr ; CHECK-MVE-FP-NEXT: bx lr
; ;
; CHECK-MVE-VMLA-LABEL: vfma32_v1_pred: ; CHECK-MVE-VMLA-LABEL: vfma32_v1_pred:
; CHECK-MVE-VMLA: @ %bb.0: @ %entry ; CHECK-MVE-VMLA: @ %bb.0: @ %entry
; CHECK-MVE-VMLA-NEXT: vmov q3, q0 ; CHECK-MVE-VMLA-NEXT: vpt.f32 lt, q1, zr
; CHECK-MVE-VMLA-NEXT: vcmp.f32 lt, q1, zr ; CHECK-MVE-VMLA-NEXT: vfmat.f32 q0, q1, q2
; CHECK-MVE-VMLA-NEXT: vfma.f32 q3, q1, q2
; CHECK-MVE-VMLA-NEXT: vpsel q0, q3, q0
; CHECK-MVE-VMLA-NEXT: bx lr ; CHECK-MVE-VMLA-NEXT: bx lr
; ;
; CHECK-MVE-LABEL: vfma32_v1_pred: ; CHECK-MVE-LABEL: vfma32_v1_pred:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s4, #0 ; CHECK-MVE-NEXT: vcmp.f32 s4, #0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines
; CHECK-MVE-FP: @ %bb.0: @ %entry ; CHECK-MVE-FP: @ %bb.0: @ %entry
; CHECK-MVE-FP-NEXT: vmul.f32 q2, q1, q2 ; CHECK-MVE-FP-NEXT: vmul.f32 q2, q1, q2
; CHECK-MVE-FP-NEXT: vpt.f32 lt, q1, zr ; CHECK-MVE-FP-NEXT: vpt.f32 lt, q1, zr
; CHECK-MVE-FP-NEXT: vaddt.f32 q0, q2, q0 ; CHECK-MVE-FP-NEXT: vaddt.f32 q0, q2, q0
; CHECK-MVE-FP-NEXT: bx lr ; CHECK-MVE-FP-NEXT: bx lr
; ;
; CHECK-MVE-VMLA-LABEL: vfma32_v2_pred: ; CHECK-MVE-VMLA-LABEL: vfma32_v2_pred:
; CHECK-MVE-VMLA: @ %bb.0: @ %entry ; CHECK-MVE-VMLA: @ %bb.0: @ %entry
; CHECK-MVE-VMLA-NEXT: vmov q3, q0 ; CHECK-MVE-VMLA-NEXT: vpt.f32 lt, q1, zr
; CHECK-MVE-VMLA-NEXT: vcmp.f32 lt, q1, zr ; CHECK-MVE-VMLA-NEXT: vfmat.f32 q0, q1, q2
; CHECK-MVE-VMLA-NEXT: vfma.f32 q3, q1, q2
; CHECK-MVE-VMLA-NEXT: vpsel q0, q3, q0
; CHECK-MVE-VMLA-NEXT: bx lr ; CHECK-MVE-VMLA-NEXT: bx lr
; ;
; CHECK-MVE-LABEL: vfma32_v2_pred: ; CHECK-MVE-LABEL: vfma32_v2_pred:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s4, #0 ; CHECK-MVE-NEXT: vcmp.f32 s4, #0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines
; CHECK-MVE-FP: @ %bb.0: @ %entry ; CHECK-MVE-FP: @ %bb.0: @ %entry
; CHECK-MVE-FP-NEXT: vmul.f32 q2, q1, q2 ; CHECK-MVE-FP-NEXT: vmul.f32 q2, q1, q2
; CHECK-MVE-FP-NEXT: vpt.f32 lt, q1, zr ; CHECK-MVE-FP-NEXT: vpt.f32 lt, q1, zr
; CHECK-MVE-FP-NEXT: vsubt.f32 q0, q0, q2 ; CHECK-MVE-FP-NEXT: vsubt.f32 q0, q0, q2
; CHECK-MVE-FP-NEXT: bx lr ; CHECK-MVE-FP-NEXT: bx lr
; ;
; CHECK-MVE-VMLA-LABEL: vfms32_pred: ; CHECK-MVE-VMLA-LABEL: vfms32_pred:
; CHECK-MVE-VMLA: @ %bb.0: @ %entry ; CHECK-MVE-VMLA: @ %bb.0: @ %entry
; CHECK-MVE-VMLA-NEXT: vmov q3, q0 ; CHECK-MVE-VMLA-NEXT: vpt.f32 lt, q1, zr
; CHECK-MVE-VMLA-NEXT: vcmp.f32 lt, q1, zr ; CHECK-MVE-VMLA-NEXT: vfmst.f32 q0, q1, q2
; CHECK-MVE-VMLA-NEXT: vfms.f32 q3, q1, q2
; CHECK-MVE-VMLA-NEXT: vpsel q0, q3, q0
; CHECK-MVE-VMLA-NEXT: bx lr ; CHECK-MVE-VMLA-NEXT: bx lr
; ;
; CHECK-MVE-LABEL: vfms32_pred: ; CHECK-MVE-LABEL: vfms32_pred:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s4, #0 ; CHECK-MVE-NEXT: vcmp.f32 s4, #0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
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; CHECK-MVE-FP-NEXT: vmul.f32 q1, q1, r0 ; CHECK-MVE-FP-NEXT: vmul.f32 q1, q1, r0
; CHECK-MVE-FP-NEXT: vpst ; CHECK-MVE-FP-NEXT: vpst
; CHECK-MVE-FP-NEXT: vaddt.f32 q0, q0, q1 ; CHECK-MVE-FP-NEXT: vaddt.f32 q0, q0, q1
; CHECK-MVE-FP-NEXT: bx lr ; CHECK-MVE-FP-NEXT: bx lr
; ;
; CHECK-MVE-VMLA-LABEL: vfmar32_pred: ; CHECK-MVE-VMLA-LABEL: vfmar32_pred:
; CHECK-MVE-VMLA: @ %bb.0: @ %entry ; CHECK-MVE-VMLA: @ %bb.0: @ %entry
; CHECK-MVE-VMLA-NEXT: vmov r0, s8 ; CHECK-MVE-VMLA-NEXT: vmov r0, s8
; CHECK-MVE-VMLA-NEXT: vmov q2, q0 ; CHECK-MVE-VMLA-NEXT: vpt.f32 lt, q1, zr
; CHECK-MVE-VMLA-NEXT: vcmp.f32 lt, q1, zr ; CHECK-MVE-VMLA-NEXT: vfmat.f32 q0, q1, r0
; CHECK-MVE-VMLA-NEXT: vfma.f32 q2, q1, r0
; CHECK-MVE-VMLA-NEXT: vpsel q0, q2, q0
; CHECK-MVE-VMLA-NEXT: bx lr ; CHECK-MVE-VMLA-NEXT: bx lr
; ;
; CHECK-MVE-LABEL: vfmar32_pred: ; CHECK-MVE-LABEL: vfmar32_pred:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s4, #0 ; CHECK-MVE-NEXT: vcmp.f32 s4, #0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
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; CHECK-MVE-FP-NEXT: vmul.f32 q2, q0, q1 ; CHECK-MVE-FP-NEXT: vmul.f32 q2, q0, q1
; CHECK-MVE-FP-NEXT: vpt.f32 lt, q1, zr ; CHECK-MVE-FP-NEXT: vpt.f32 lt, q1, zr
; CHECK-MVE-FP-NEXT: vaddt.f32 q0, q2, r0 ; CHECK-MVE-FP-NEXT: vaddt.f32 q0, q2, r0
; CHECK-MVE-FP-NEXT: bx lr ; CHECK-MVE-FP-NEXT: bx lr
; ;
; CHECK-MVE-VMLA-LABEL: vfmas32_pred: ; CHECK-MVE-VMLA-LABEL: vfmas32_pred:
; CHECK-MVE-VMLA: @ %bb.0: @ %entry ; CHECK-MVE-VMLA: @ %bb.0: @ %entry
; CHECK-MVE-VMLA-NEXT: vmov r0, s8 ; CHECK-MVE-VMLA-NEXT: vmov r0, s8
; CHECK-MVE-VMLA-NEXT: vmov q2, q0 ; CHECK-MVE-VMLA-NEXT: vpt.f32 lt, q1, zr
; CHECK-MVE-VMLA-NEXT: vcmp.f32 lt, q1, zr ; CHECK-MVE-VMLA-NEXT: vfmast.f32 q0, q1, r0
; CHECK-MVE-VMLA-NEXT: vfmas.f32 q2, q1, r0
; CHECK-MVE-VMLA-NEXT: vpsel q0, q2, q0
; CHECK-MVE-VMLA-NEXT: bx lr ; CHECK-MVE-VMLA-NEXT: bx lr
; ;
; CHECK-MVE-LABEL: vfmas32_pred: ; CHECK-MVE-LABEL: vfmas32_pred:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s4, #0 ; CHECK-MVE-NEXT: vcmp.f32 s4, #0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
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