[GlobalISel][InlineAsm] Fix matching input constraint to physreg

[Petar.Avramovic]

Summary

Simply add given input and mark it as tied.
Doesn't create additional copy compared to
matching input constraint to virtual register.

[kschwarz]

LGTM, might be worth to include this also for the 11.x release.

llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp

467

I think the else branch needs braces, since one of the branches need them.

[Petar.Avramovic]

Remove else branch.

[Petar.Avramovic]

might be worth to include this also for the 11.x release.

What is the procedure for that?

[kschwarz]

Either you can create a bug in Bugzilla (https://bugs.llvm.org/), asking for this revision to be merged to the release branch and mark it as a release blocker of the 11.0.0 release, or you can contact the release manager directly ([e-mail]).

@jrtc27, does this fix the issue you are seeing in sel4?

[jrtc27]

In D85122#2192902, @kschwarz wrote:

Either you can create a bug in Bugzilla (https://bugs.llvm.org/), asking for this revision to be merged to the release branch and mark it as a release blocker of the 11.0.0 release, or you can contact the release manager directly ([e-mail]).

@jrtc27, does this fix the issue you are seeing in sel4?

I was only acting as messenger (and diagnoser of the reduced test case). @sorear ?

[sorear]

In D85122#2192902, @kschwarz wrote:

Either you can create a bug in Bugzilla (https://bugs.llvm.org/), asking for this revision to be merged to the release branch and mark it as a release blocker of the 11.0.0 release, or you can contact the release manager directly ([e-mail]).

@jrtc27, does this fix the issue you are seeing in sel4?

Yes, when applied on top of llvmorg-11.0.0-rc1.

[Petar.Avramovic]

@hans, could you please commit this patch for 11.x release?

[hans]

In D85122#2198934, @Petar.Avramovic wrote:

@hans, could you please commit this patch for 11.x release?

It needs to be committed to trunk first, then I'll merge it after a day or two.

[sorear]

For completeness I just filed https://bugs.llvm.org/show_bug.cgi?id=47021 for this issue. I missed the "contact the release manager directly" as a viable alternative on my first reading, so that was probably unnecessary, apologies if this creates a problem.

[hans]

In D85122#2200616, @sorear wrote:

For completeness I just filed https://bugs.llvm.org/show_bug.cgi?id=47021 for this issue. I missed the "contact the release manager directly" as a viable alternative on my first reading, so that was probably unnecessary, apologies if this creates a problem.

No problem at all. Pushed to 11.x as b067f5eb56684476b5dad4ebd8d6bc5291603d4e.

llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp

case InlineAsm::isInput: {
           LLVM_DEBUG(dbgs() << "Unknown matching constraint\n");
           return false;
         }
 
         // We want to tie input to register in next operand.
         unsigned DefRegIdx = InstFlagIdx + 1;
         Register Def = Inst->getOperand(DefRegIdx).getReg();
 
-        // Copy input to new vreg with same reg class as Def
-        const TargetRegisterClass *RC = MRI->getRegClass(Def);
         ArrayRef<Register> SrcRegs = GetOrCreateVRegs(*OpInfo.CallOperandVal);
         assert(SrcRegs.size() == 1 && "Single register is expected here");
-        Register Tmp = MRI->createVirtualRegister(RC);
-        if (!buildAnyextOrCopy(Tmp, SrcRegs[0], MIRBuilder))
+
+        // When Def is physreg: use given input.
+        Register In = SrcRegs[0];
+        // When Def is vreg: copy input to new vreg with same reg class as Def.
+        if (Def.isVirtual()) {
+          In = MRI->createVirtualRegister(MRI->getRegClass(Def));
+          if (!buildAnyextOrCopy(In, SrcRegs[0], MIRBuilder))
             return false;
+        }
 
-        // Add Flag and input register operand (Tmp) to Inst. Tie Tmp to Def.
+        // Add Flag and input register operand (In) to Inst. Tie In to Def.
         unsigned UseFlag = InlineAsm::getFlagWord(InlineAsm::Kind_RegUse, 1);
         unsigned Flag = InlineAsm::getFlagWordForMatchingOp(UseFlag, DefIdx);
         Inst.addImm(Flag);
-        Inst.addReg(Tmp);
+        Inst.addReg(In);
         Inst->tieOperands(DefRegIdx, Inst->getNumOperands() - 1);
         break;
       }
 
       if (OpInfo.ConstraintType == TargetLowering::C_Other &&
           OpInfo.isIndirect) {
         LLVM_DEBUG(dbgs() << "Indirect input operands with unknown constraint "
                              "not supported yet\n");

llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll

define i16 @test_anyext_input_with_matching_constraint() {
   ; CHECK:   [[COPY1:%[0-9]+]]:_(s32) = COPY %0
   ; CHECK:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
   ; CHECK:   [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s16)
   ; CHECK:   $w0 = COPY [[ANYEXT1]](s32)
   ; CHECK:   RET_ReallyLR implicit $w0
   %1 = call i16 asm sideeffect "", "=r,0"(i16 1)
   ret i16 %1
 }
+
+define i64 @test_input_with_matching_constraint_to_physical_register() {
+  ; CHECK-LABEL: name: test_input_with_matching_constraint_to_physical_register
+  ; CHECK: bb.1 (%ir-block.0):
+  ; CHECK:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+  ; CHECK:   INLINEASM &"", 0 /* attdialect */, 10 /* regdef */, implicit-def $x2, 2147483657 /* reguse tiedto:$0 */, [[C]](tied-def 3)(s64)
+  ; CHECK:   [[COPY:%[0-9]+]]:_(s64) = COPY $x2
+  ; CHECK:   $x0 = COPY [[COPY]](s64)
+  ; CHECK:   RET_ReallyLR implicit $x0
+  %1 = tail call i64 asm "", "={x2},0"(i64 0)
+  ret i64 %1
+}