[AArch64] Refactor AArch64NamedImmMapper to become dependent on subtarget features.

[vsukharev]

Summary

In order to introduce v8.1a-specific entities, Mappers should be aware of SubtargetFeatures available.
This patch introduces refactoring, that will then allow to easily introduce:
- v8.1-specific "pan" PState for PStateMapper (PAN extension)
- v8.1-specific sysregs for SysRegMapper (LOR,VHE extensions)

[jmolloy]

Hi Vladimir,

Thanks for doing this. I think there's nothing massively contentious in your patch, but it's difficult to review because it's a merge of three different patches, as far as I can see:

1. Adding SubTargetFeatureBits everywhere.
2. Changing the AsmParser to take a string for barriers etc (this seems orthogonal to me)
3. Re-bikeshedding (Pair->Mapper, if/else -> ?:)

So please separate it out into three patches, each of which can be trivially reviewed.

Cheers,

James

lib/Target/AArch64/Utils/AArch64BaseInfo.h

308

Why "SubTargetFeature == 0"? This seems strange. I would have expected just:

return SubTargetFeature & FeatureBits;

[vsukharev]

Hi James,
thank you for comments. I will update the revision with

2. Changing the AsmParser to take a string for barriers etc

and then provide two more patches for

1. Adding SubTargetFeatureBits everywhere.
2. Re-bikeshedding (Pair->Mapper, if/else -> ?:)

Thanks, Vladimir

lib/Target/AArch64/Utils/AArch64BaseInfo.h

308

It is intended way to use for vast majority of Mappers, that don't depend on any subtargetfeature , and are present permanently. For those, SubTargetFeature field will be as default, i.e. 0. and no FeatureBits equal to 0. This makes all current mappers to remain correct, like
DAIFClr : {"daifclr", DAIFClr}
will mean
struct Mapping {
const char *Name = "daifclr";
uint32_t Value = DAIFClr;
uint64_t SubTargetFeature = 0;
};
and this hasFeature will always return true, no matter of subtargetfeatures

[vsukharev]

Patch has been separated by four parts:

• http://reviews.llvm.org/D8579 [AArch64] Move initializations of AArch64NamedImmMapper out of void AArch64Operand::print(...)
• http://reviews.llvm.org/D8582 [AArch64] Rename Pairs to Mappings in AArch64NamedImmMapper
• (this revision) introduction of FeatureBits to AArch64NamedImmMapper::Mapping
• http://reviews.llvm.org/D8584 [AArch64] Handle Cyclone-specific register in common way

[echristo]

I'm going to ask you to hold on for a second on these. I'm not such a huge
fan of having asm parsers be subtarget dependent and would like to take a
look at it.

-eric

[vsukharev]

Eric, thank you for taking care.
Considering this, would you also take a look on chain of patches that are intended to use this subtarget dependency ?
http://reviews.llvm.org/D8498
http://reviews.llvm.org/D8499
http://reviews.llvm.org/D8500
Thanks, Vladimir

[vsukharev]

Eric, AsmParser is already dependent on subtargetfeatures since http://reviews.llvm.org/rL207742 .
The approach has just been extended from SysRegMapper (plus its children MSRMapper, MRSMapper) to other mappers.
Would you comment on your doubts?

[echristo]

Why are you effectively reimplementing the feature sets for this class?

-eric

[echristo]

A better question might be:

Why are all of these classes copying the feature sets and using them with
their own API?

-eric

[vsukharev]

As per echristo request, subtarget features are no longer stored into Mappers.

New revision is based on http://reviews.llvm.org/D8655

[vsukharev]

Eric, (or Tim?)
would you please review my last version? This had blocked the approved chain to commit
http://reviews.llvm.org/D8584 [AArch64] Handle Cyclone-specific register in common way
http://reviews.llvm.org/D8498 [AArch64] Add v8.1a "Privileged Access Never" extension
http://reviews.llvm.org/D8500 [AArch64] Add v8.1a "Virtualization Host Extensions"
http://reviews.llvm.org/D8499 [AArch64] Add v8.1a "Limited Ordering Regions" extension

[vsukharev]

ping...

[jmolloy]

Hi Vlad,

Looks like a mostly mechanical change. I don't like one aspect of it, but if you change that you can commit.

Cheers,

James

lib/Target/AArch64/Utils/AArch64BaseInfo.h

285

I think this is overly convoluted for such a simple function. The same function name does different things depending on the overload (one checks Name and the other Value). I don't think this is intuitive.

Just simply:

bool isNameEqual(std::string Other, uint64_t FeatureBits=~0ULL) {
  if (AvailableForFeatures && !(AvailableForFeatures & FeatureBits))
    return false;
  return Name == Other;
}

And similarly for Value, would be more clear.

[echristo]

Some comments inline.

-eric

lib/Target/AArch64/Utils/AArch64BaseInfo.h

283

This is a pretty terrible name. What do you mean here?

284

Comments are full sentences.

286

I'm not a fan of this interface name. isEqual taking features and not changing the name isn't very descriptive.

297

If you're taking FeatureBits now this should probably change names to make the interface more clear.

Also (and I realize this was already like this) the functions need a comment as to what they're for.

[vsukharev]

Eric, thank you for your feedback
in fact, I have already committed that as http://reviews.llvm.org/rL235089, with slight re-work, addressing last jmolloy's comment
I suspect a line of text after "Differential Revision:" line has prevented post-commit script to process auto-closing this DiffRevision properly. And I don't know at the time how should I fix that: close Revision and put links to commit and back. (Is it a way to do that at all?)
Anyway, should I address your comments as a separate follow-up patch? If so, would you please comment directly to http://reviews.llvm.org/rL235089, because things are changed a bit.

[echristo]

Please just make the changes I've requested in a follow-up commit. I don't
see the need to reply on another commit.

[Eugene.Zelenko]

Committed in rL235089.

lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

if (Hash || Tok.is(AsmToken::Integer)) {
     }
     unsigned prfop = MCE->getValue();
     if (prfop > 31) {
       TokError("prefetch operand out of range, [0,31] expected");
       return MatchOperand_ParseFail;
     }
 
     bool Valid;
-    auto Mapper = AArch64PRFM::PRFMMapper();
+    auto Mapper = AArch64PRFM::PRFMMapper(STI.getFeatureBits());
     StringRef Name = Mapper.toString(MCE->getValue(), Valid);
     Operands.push_back(AArch64Operand::CreatePrefetch(prfop, Name,
                                                       S, getContext()));
     return MatchOperand_Success;
   }
 
   if (Tok.isNot(AsmToken::Identifier)) {
     TokError("pre-fetch hint expected");
     return MatchOperand_ParseFail;
   }
 
   bool Valid;
-  auto Mapper = AArch64PRFM::PRFMMapper();
+  auto Mapper = AArch64PRFM::PRFMMapper(STI.getFeatureBits());
   unsigned prfop = Mapper.fromString(Tok.getString(), Valid);
   if (!Valid) {
     TokError("pre-fetch hint expected");
     return MatchOperand_ParseFail;
   }
 
   Parser.Lex(); // Eat identifier token.
   Operands.push_back(AArch64Operand::CreatePrefetch(prfop, Tok.getString(),
if (!MCE) {
       Error(ExprLoc, "immediate value expected for barrier operand");
       return MatchOperand_ParseFail;
     }
     if (MCE->getValue() < 0 || MCE->getValue() > 15) {
       Error(ExprLoc, "barrier operand out of range");
       return MatchOperand_ParseFail;
     }
     bool Valid;
-    auto Mapper = AArch64DB::DBarrierMapper();
+    auto Mapper = AArch64DB::DBarrierMapper(STI.getFeatureBits());
     StringRef Name = Mapper.toString(MCE->getValue(), Valid);
     Operands.push_back( AArch64Operand::CreateBarrier(MCE->getValue(), Name,
                                                       ExprLoc, getContext()));
     return MatchOperand_Success;
   }
 
   if (Tok.isNot(AsmToken::Identifier)) {
     TokError("invalid operand for instruction");
     return MatchOperand_ParseFail;
   }
 
   bool Valid;
-  auto Mapper = AArch64DB::DBarrierMapper();
+  auto Mapper = AArch64DB::DBarrierMapper(STI.getFeatureBits());
   unsigned Opt = Mapper.fromString(Tok.getString(), Valid);
   if (!Valid) {
     TokError("invalid barrier option name");
     return MatchOperand_ParseFail;
   }
 
   // The only valid named option for ISB is 'sy'
   if (Mnemonic == "isb" && Opt != AArch64DB::SY) {
AArch64AsmParser::tryParseSysReg(OperandVector &Operands) {
   assert(IsKnown == (MRSReg != -1U) &&
          "register should be -1 if and only if it's unknown");
 
   auto MSRMapper = AArch64SysReg::MSRMapper(STI.getFeatureBits());
   uint32_t MSRReg = MSRMapper.fromString(Tok.getString(), IsKnown);
   assert(IsKnown == (MSRReg != -1U) &&
          "register should be -1 if and only if it's unknown");
 
-  auto PStateMapper = AArch64PState::PStateMapper();
+  auto PStateMapper = AArch64PState::PStateMapper(STI.getFeatureBits());
   uint32_t PStateField = PStateMapper.fromString(Tok.getString(), IsKnown);
   assert(IsKnown == (PStateField != -1U) &&
          "register should be -1 if and only if it's unknown");
 
   Operands.push_back(AArch64Operand::CreateSysReg(
       Tok.getString(), getLoc(), MRSReg, MSRReg, PStateField, getContext()));
   Parser.Lex(); // Eat identifier
 

lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp

static DecodeStatus DecodeSystemPStateInstruction(llvm::MCInst &Inst,
   uint64_t crm = fieldFromInstruction(insn, 8, 4);
 
   uint64_t pstate_field = (op1 << 3) | op2;
 
   Inst.addOperand(MCOperand::CreateImm(pstate_field));
   Inst.addOperand(MCOperand::CreateImm(crm));
 
   bool ValidNamed;
-  (void)AArch64PState::PStateMapper().toString(pstate_field, ValidNamed);
+  const AArch64Disassembler *Dis =
+      static_cast<const AArch64Disassembler *>(Decoder);
+  AArch64PState::PStateMapper Mapper(Dis->getSubtargetInfo().getFeatureBits());
+  Mapper.toString(pstate_field, ValidNamed);
 
   return ValidNamed ? Success : Fail;
 }
 
 static DecodeStatus DecodeTestAndBranch(llvm::MCInst &Inst, uint32_t insn,
                                         uint64_t Addr, const void *Decoder) {
   uint64_t Rt = fieldFromInstruction(insn, 0, 5);
   uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5;

lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp

void AArch64InstPrinter::printAMIndexedWB(const MCInst *MI, unsigned OpNum,
   }
   O << ']';
 }
 
 void AArch64InstPrinter::printPrefetchOp(const MCInst *MI, unsigned OpNum,
                                          raw_ostream &O) {
   unsigned prfop = MI->getOperand(OpNum).getImm();
   bool Valid;
-  StringRef Name = AArch64PRFM::PRFMMapper().toString(prfop, Valid);
+  AArch64PRFM::PRFMMapper PRFMMapper(getAvailableFeatures());
+  StringRef Name = PRFMMapper.toString(prfop, Valid);
   if (Valid)
     O << Name;
   else
     O << '#' << prfop;
 }
 
 void AArch64InstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
                                            raw_ostream &O) {

 void AArch64InstPrinter::printBarrierOption(const MCInst *MI, unsigned OpNo,
                                             raw_ostream &O) {
   unsigned Val = MI->getOperand(OpNo).getImm();
   unsigned Opcode = MI->getOpcode();
 
   bool Valid;
   StringRef Name;
   if (Opcode == AArch64::ISB)
-    Name = AArch64ISB::ISBMapper().toString(Val, Valid);
+    Name = AArch64ISB::ISBMapper(getAvailableFeatures()).toString(Val,
+                                                                  Valid);
   else
-    Name = AArch64DB::DBarrierMapper().toString(Val, Valid);
+    Name = AArch64DB::DBarrierMapper(getAvailableFeatures()).toString(Val, 
+                                                                      Valid);
   if (Valid)
     O << Name;
   else
     O << "#" << Val;
 }
 
 void AArch64InstPrinter::printMRSSystemRegister(const MCInst *MI, unsigned OpNo,
                                                 raw_ostream &O) {
void AArch64InstPrinter::printMSRSystemRegister(const MCInst *MI, unsigned OpNo,
   O << StringRef(Name).upper();
 }
 
 void AArch64InstPrinter::printSystemPStateField(const MCInst *MI, unsigned OpNo,
                                                 raw_ostream &O) {
   unsigned Val = MI->getOperand(OpNo).getImm();
 
   bool Valid;
-  StringRef Name = AArch64PState::PStateMapper().toString(Val, Valid);
+  auto Mapper = AArch64PState::PStateMapper(getAvailableFeatures());
+  StringRef Name = Mapper.toString(Val, Valid);
   if (Valid)
     O << StringRef(Name.str()).upper();
   else
     O << "#" << Val;
 }
 
 void AArch64InstPrinter::printSIMDType10Operand(const MCInst *MI, unsigned OpNo,
                                                 raw_ostream &O) {
   unsigned RawVal = MI->getOperand(OpNo).getImm();
   uint64_t Val = AArch64_AM::decodeAdvSIMDModImmType10(RawVal);
   O << format("#%#016llx", Val);
 }

lib/Target/AArch64/Utils/AArch64BaseInfo.h

 #ifndef LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H
 #define LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H
 
 // FIXME: Is it easiest to fix this layering violation by moving the .inc
 // #includes from AArch64MCTargetDesc.h to here?
 #include "MCTargetDesc/AArch64MCTargetDesc.h" // For AArch64::X0 and friends.
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/StringSwitch.h"
+#include "llvm/MC/SubtargetFeature.h"
 #include "llvm/Support/ErrorHandling.h"
 
 namespace llvm {
 
 class FeatureBitset;
 
 inline static unsigned getWRegFromXReg(unsigned Reg) {
   switch (Reg) {

 /// duplicated and remains in sync.
 ///
 /// FIXME: currently the algorithm is a completely unoptimised linear
 /// search. Obviously this could be improved, but we would probably want to work
 /// out just how often these instructions are emitted before working on it. It
 /// might even be optimal to just reorder the tables for the common instructions
 /// rather than changing the algorithm.
 struct AArch64NamedImmMapper {
   struct Mapping {
     const char *Name;
     uint32_t Value;
+    FeatureBitset FeatureBits;  // like "struct SubtargetFeatureKV"
   };
 
   template<int N>
-  AArch64NamedImmMapper(const Mapping (&Mappings)[N], uint32_t TooBigImm)
-    : Mappings(&Mappings[0]), NumMappings(N), TooBigImm(TooBigImm) {}
+  AArch64NamedImmMapper(const FeatureBitset &FeatureBits, 
+                        const Mapping (&Mappings)[N], uint32_t TooBigImm)
+    : FeatureBits(FeatureBits), Mappings(&Mappings[0]), NumMappings(N), 
+      TooBigImm(TooBigImm) {}
 
   StringRef toString(uint32_t Value, bool &Valid) const;
   uint32_t fromString(StringRef Name, bool &Valid) const;
 
   /// Many of the instructions allow an alternative assembly form consisting of
   /// a simple immediate. Currently the only valid forms are ranges [0, N) where
   /// N being 0 indicates no immediate syntax-form is allowed.
   bool validImm(uint32_t Value) const;
 protected:
+  const FeatureBitset &FeatureBits;
   const Mapping *Mappings;
   size_t NumMappings;
   uint32_t TooBigImm;
+  bool hasFeature(const FeatureBitset &Features) const {
+    // empty Features means "always-on"
+    return Features.none() || (FeatureBits & Features).any();
+  }
 };
 
 namespace AArch64AT {
   enum ATValues {
     Invalid = -1,    // Op0 Op1  CRn   CRm   Op2
     S1E1R = 0x43c0,  // 01  000  0111  1000  000
     S1E2R = 0x63c0,  // 01  100  0111  1000  000
     S1E3R = 0x73c0,  // 01  110  0111  1000  000
     S1E1W = 0x43c1,  // 01  000  0111  1000  001
     S1E2W = 0x63c1,  // 01  100  0111  1000  001
     S1E3W = 0x73c1,  // 01  110  0111  1000  001
     S1E0R = 0x43c2,  // 01  000  0111  1000  010
     S1E0W = 0x43c3,  // 01  000  0111  1000  011
     S12E1R = 0x63c4, // 01  100  0111  1000  100
     S12E1W = 0x63c5, // 01  100  0111  1000  101
     S12E0R = 0x63c6, // 01  100  0111  1000  110
     S12E0W = 0x63c7  // 01  100  0111  1000  111
   };
 
   struct ATMapper : AArch64NamedImmMapper {
     const static Mapping ATMappings[];
 
-    ATMapper();
+    ATMapper(const FeatureBitset &FeatureBits);
   };
 
 }
 namespace AArch64DB {
   enum DBValues {
     Invalid = -1,
     OSHLD = 0x1,
     OSHST = 0x2,
     OSH =   0x3,
     NSHLD = 0x5,
     NSHST = 0x6,
     NSH =   0x7,
     ISHLD = 0x9,
     ISHST = 0xa,
     ISH =   0xb,
     LD =    0xd,
     ST =    0xe,
     SY =    0xf
   };
 
   struct DBarrierMapper : AArch64NamedImmMapper {
     const static Mapping DBarrierMappings[];
 
-    DBarrierMapper();
+    DBarrierMapper(const FeatureBitset &FeatureBits);
   };
 }
 
 namespace  AArch64DC {
   enum DCValues {
     Invalid = -1,   // Op1  CRn   CRm   Op2
     ZVA   = 0x5ba1, // 01  011  0111  0100  001
     IVAC  = 0x43b1, // 01  000  0111  0110  001
     ISW   = 0x43b2, // 01  000  0111  0110  010
     CVAC  = 0x5bd1, // 01  011  0111  1010  001
     CSW   = 0x43d2, // 01  000  0111  1010  010
     CVAU  = 0x5bd9, // 01  011  0111  1011  001
     CIVAC = 0x5bf1, // 01  011  0111  1110  001
     CISW  = 0x43f2  // 01  000  0111  1110  010
   };
 
   struct DCMapper : AArch64NamedImmMapper {
     const static Mapping DCMappings[];
 
-    DCMapper();
+    DCMapper(const FeatureBitset &FeatureBits);
   };
 
 }
 
 namespace  AArch64IC {
   enum ICValues {
     Invalid = -1,     // Op1  CRn   CRm   Op2
     IALLUIS = 0x0388, // 000  0111  0001  000
     IALLU = 0x03a8,   // 000  0111  0101  000
     IVAU = 0x1ba9     // 011  0111  0101  001
   };
 
 
   struct ICMapper : AArch64NamedImmMapper {
     const static Mapping ICMappings[];
 
-    ICMapper();
+    ICMapper(const FeatureBitset &FeatureBits);
   };
 
   static inline bool NeedsRegister(ICValues Val) {
     return Val == IVAU;
   }
 }
 
 namespace  AArch64ISB {
   enum ISBValues {
     Invalid = -1,
     SY = 0xf
   };
   struct ISBMapper : AArch64NamedImmMapper {
     const static Mapping ISBMappings[];
 
-    ISBMapper();
+    ISBMapper(const FeatureBitset &FeatureBits);
   };
 }
 
 namespace AArch64PRFM {
   enum PRFMValues {
     Invalid = -1,
     PLDL1KEEP = 0x00,
     PLDL1STRM = 0x01,
enum PRFMValues {
     PSTL2STRM = 0x13,
     PSTL3KEEP = 0x14,
     PSTL3STRM = 0x15
   };
 
   struct PRFMMapper : AArch64NamedImmMapper {
     const static Mapping PRFMMappings[];
 
-    PRFMMapper();
+    PRFMMapper(const FeatureBitset &FeatureBits);
   };
 }
 
 namespace AArch64PState {
   enum PStateValues {
     Invalid = -1,
     SPSel = 0x05,
     DAIFSet = 0x1e,
     DAIFClr = 0x1f
   };
 
   struct PStateMapper : AArch64NamedImmMapper {
     const static Mapping PStateMappings[];
 
-    PStateMapper();
+    PStateMapper(const FeatureBitset &FeatureBits);
   };
 
 }
 
 namespace AArch64SE {
     enum ShiftExtSpecifiers {
         Invalid = -1,
         LSL,
namespace AArch64SysReg {
   // this one case.
   struct SysRegMapper {
     static const AArch64NamedImmMapper::Mapping SysRegMappings[];
     static const AArch64NamedImmMapper::Mapping CycloneSysRegMappings[];
 
     const AArch64NamedImmMapper::Mapping *InstMappings;
     size_t NumInstMappings;
     const FeatureBitset &FeatureBits;
+    bool hasFeature(const FeatureBitset &Features) const {
+      // empty Features means "always-on"
+      return Features.none() || (FeatureBits & Features).any();
+    }
 
     SysRegMapper(const FeatureBitset &FeatureBits) : FeatureBits(FeatureBits) { }
     uint32_t fromString(StringRef Name, bool &Valid) const;
     std::string toString(uint32_t Bits) const;
   };
 
   struct MSRMapper : SysRegMapper {
     static const AArch64NamedImmMapper::Mapping MSRMappings[];
enum TLBIValues {
     VALE3        = 0x743d, // 01  110  1000  0111  101
     VMALLS12E1   = 0x643e, // 01  100  1000  0111  110
     VAALE1       = 0x443f  // 01  000  1000  0111  111
   };
 
   struct TLBIMapper : AArch64NamedImmMapper {
     const static Mapping TLBIMappings[];
 
-    TLBIMapper();
+    TLBIMapper(const FeatureBitset &FeatureBits);
   };
 
   static inline bool NeedsRegister(TLBIValues Val) {
     switch (Val) {
     case VMALLE1IS:
     case ALLE2IS:
     case ALLE3IS:
     case ALLE1IS:

lib/Target/AArch64/Utils/AArch64BaseInfo.cpp

 #include "llvm/ADT/StringExtras.h"
 #include "llvm/MC/SubtargetFeature.h"
 #include "llvm/Support/Regex.h"
 
 using namespace llvm;
 
 StringRef AArch64NamedImmMapper::toString(uint32_t Value, bool &Valid) const {
   for (unsigned i = 0; i < NumMappings; ++i) {
-    if (Mappings[i].Value == Value) {
+    if (hasFeature(Mappings[i].FeatureBits) && 
+        Mappings[i].Value == Value) {
       Valid = true;
       return Mappings[i].Name;
     }
   }
 
   Valid = false;
   return StringRef();
 }
 
 uint32_t AArch64NamedImmMapper::fromString(StringRef Name, bool &Valid) const {
   std::string LowerCaseName = Name.lower();
   for (unsigned i = 0; i < NumMappings; ++i) {
-    if (Mappings[i].Name == LowerCaseName) {
+    if (hasFeature(Mappings[i].FeatureBits) && 
+        Mappings[i].Name == LowerCaseName) {
       Valid = true;
       return Mappings[i].Value;
     }
   }
 
   Valid = false;
   return -1;
 }
const AArch64NamedImmMapper::Mapping AArch64AT::ATMapper::ATMappings[] = {
   {"s1e0r", S1E0R},
   {"s1e0w", S1E0W},
   {"s12e1r", S12E1R},
   {"s12e1w", S12E1W},
   {"s12e0r", S12E0R},
   {"s12e0w", S12E0W},
 };
 
-AArch64AT::ATMapper::ATMapper()
-  : AArch64NamedImmMapper(ATMappings, 0) {}
+AArch64AT::ATMapper::ATMapper(const FeatureBitset &FeatureBits)
+  : AArch64NamedImmMapper(FeatureBits, ATMappings, 0) {}
 
 const AArch64NamedImmMapper::Mapping AArch64DB::DBarrierMapper::DBarrierMappings[] = {
   {"oshld", OSHLD},
   {"oshst", OSHST},
   {"osh", OSH},
   {"nshld", NSHLD},
   {"nshst", NSHST},
   {"nsh", NSH},
   {"ishld", ISHLD},
   {"ishst", ISHST},
   {"ish", ISH},
   {"ld", LD},
   {"st", ST},
   {"sy", SY}
 };
 
-AArch64DB::DBarrierMapper::DBarrierMapper()
-  : AArch64NamedImmMapper(DBarrierMappings, 16u) {}
+AArch64DB::DBarrierMapper::DBarrierMapper(const FeatureBitset &FeatureBits)
+  : AArch64NamedImmMapper(FeatureBits, DBarrierMappings, 16u) {}
 
 const AArch64NamedImmMapper::Mapping AArch64DC::DCMapper::DCMappings[] = {
   {"zva", ZVA},
   {"ivac", IVAC},
   {"isw", ISW},
   {"cvac", CVAC},
   {"csw", CSW},
   {"cvau", CVAU},
   {"civac", CIVAC},
   {"cisw", CISW}
 };
 
-AArch64DC::DCMapper::DCMapper()
-  : AArch64NamedImmMapper(DCMappings, 0) {}
+AArch64DC::DCMapper::DCMapper(const FeatureBitset &FeatureBits)
+  : AArch64NamedImmMapper(FeatureBits, DCMappings, 0) {}
 
 const AArch64NamedImmMapper::Mapping AArch64IC::ICMapper::ICMappings[] = {
   {"ialluis",  IALLUIS},
   {"iallu", IALLU},
   {"ivau", IVAU}
 };
 
-AArch64IC::ICMapper::ICMapper()
-  : AArch64NamedImmMapper(ICMappings, 0) {}
+AArch64IC::ICMapper::ICMapper(const FeatureBitset &FeatureBits)
+  : AArch64NamedImmMapper(FeatureBits, ICMappings, 0) {}
 
 const AArch64NamedImmMapper::Mapping AArch64ISB::ISBMapper::ISBMappings[] = {
   {"sy",  SY},
 };
 
-AArch64ISB::ISBMapper::ISBMapper()
-  : AArch64NamedImmMapper(ISBMappings, 16) {}
+AArch64ISB::ISBMapper::ISBMapper(const FeatureBitset &FeatureBits)
+  : AArch64NamedImmMapper(FeatureBits, ISBMappings, 16) {}
 
 const AArch64NamedImmMapper::Mapping AArch64PRFM::PRFMMapper::PRFMMappings[] = {
   {"pldl1keep", PLDL1KEEP},
   {"pldl1strm", PLDL1STRM},
   {"pldl2keep", PLDL2KEEP},
   {"pldl2strm", PLDL2STRM},
   {"pldl3keep", PLDL3KEEP},
   {"pldl3strm", PLDL3STRM},
   {"plil1keep", PLIL1KEEP},
   {"plil1strm", PLIL1STRM},
   {"plil2keep", PLIL2KEEP},
   {"plil2strm", PLIL2STRM},
   {"plil3keep", PLIL3KEEP},
   {"plil3strm", PLIL3STRM},
   {"pstl1keep", PSTL1KEEP},
   {"pstl1strm", PSTL1STRM},
   {"pstl2keep", PSTL2KEEP},
   {"pstl2strm", PSTL2STRM},
   {"pstl3keep", PSTL3KEEP},
   {"pstl3strm", PSTL3STRM}
 };
 
-AArch64PRFM::PRFMMapper::PRFMMapper()
-  : AArch64NamedImmMapper(PRFMMappings, 32) {}
+AArch64PRFM::PRFMMapper::PRFMMapper(const FeatureBitset &FeatureBits)
+  : AArch64NamedImmMapper(FeatureBits, PRFMMappings, 32) {}
 
 const AArch64NamedImmMapper::Mapping AArch64PState::PStateMapper::PStateMappings[] = {
   {"spsel", SPSel},
   {"daifset", DAIFSet},
   {"daifclr", DAIFClr}
 };
 
-AArch64PState::PStateMapper::PStateMapper()
-  : AArch64NamedImmMapper(PStateMappings, 0) {}
+AArch64PState::PStateMapper::PStateMapper(const FeatureBitset &FeatureBits)
+  : AArch64NamedImmMapper(FeatureBits, PStateMappings, 0) {}
 
 const AArch64NamedImmMapper::Mapping AArch64SysReg::MRSMapper::MRSMappings[] = {
   {"mdccsr_el0", MDCCSR_EL0},
   {"dbgdtrrx_el0", DBGDTRRX_EL0},
   {"mdrar_el1", MDRAR_EL1},
   {"oslsr_el1", OSLSR_EL1},
   {"dbgauthstatus_el1", DBGAUTHSTATUS_EL1},
   {"pmceid0_el0", PMCEID0_EL0},

 };
 
 uint32_t
 AArch64SysReg::SysRegMapper::fromString(StringRef Name, bool &Valid) const {
   std::string NameLower = Name.lower();
 
   // First search the registers shared by all
   for (unsigned i = 0; i < array_lengthof(SysRegMappings); ++i) {
-    if (SysRegMappings[i].Name == NameLower) {
+    if (hasFeature(SysRegMappings[i].FeatureBits) &&
+        SysRegMappings[i].Name == NameLower) {
       Valid = true;
       return SysRegMappings[i].Value;
     }
   }
 
   // Next search for target specific registers
   if (FeatureBits[AArch64::ProcCyclone]) {
     for (unsigned i = 0; i < array_lengthof(CycloneSysRegMappings); ++i) {
       if (CycloneSysRegMappings[i].Name == NameLower) {
         Valid = true;
         return CycloneSysRegMappings[i].Value;
       }
     }
   }
 
   // Now try the instruction-specific registers (either read-only or
   // write-only).
   for (unsigned i = 0; i < NumInstMappings; ++i) {
-    if (InstMappings[i].Name == NameLower) {
+    if (hasFeature(InstMappings[i].FeatureBits) &&
+        InstMappings[i].Name == NameLower) {
       Valid = true;
       return InstMappings[i].Value;
     }
   }
 
   // Try to parse an S<op0>_<op1>_<Cn>_<Cm>_<op2> register name
   Regex GenericRegPattern("^s([0-3])_([0-7])_c([0-9]|1[0-5])_c([0-9]|1[0-5])_([0-7])$");
 
AArch64SysReg::SysRegMapper::fromString(StringRef Name, bool &Valid) const {
   Valid = true;
   return Bits;
 }
 
 std::string
 AArch64SysReg::SysRegMapper::toString(uint32_t Bits) const {
   // First search the registers shared by all
   for (unsigned i = 0; i < array_lengthof(SysRegMappings); ++i) {
-    if (SysRegMappings[i].Value == Bits) {
+    if (hasFeature(SysRegMappings[i].FeatureBits) &&
+        SysRegMappings[i].Value == Bits) {
       return SysRegMappings[i].Name;
     }
   }
 
   // Next search for target specific registers
   if (FeatureBits[AArch64::ProcCyclone]) {
     for (unsigned i = 0; i < array_lengthof(CycloneSysRegMappings); ++i) {
       if (CycloneSysRegMappings[i].Value == Bits) {
         return CycloneSysRegMappings[i].Name;
       }
     }
   }
 
   // Now try the instruction-specific registers (either read-only or
   // write-only).
   for (unsigned i = 0; i < NumInstMappings; ++i) {
-    if (InstMappings[i].Value == Bits) {
+    if (hasFeature(InstMappings[i].FeatureBits) &&
+        InstMappings[i].Value == Bits) {
       return InstMappings[i].Name;
     }
   }
 
   assert(Bits < 0x10000);
   uint32_t Op0 = (Bits >> 14) & 0x3;
   uint32_t Op1 = (Bits >> 11) & 0x7;
   uint32_t CRn = (Bits >> 7) & 0xf;
const AArch64NamedImmMapper::Mapping AArch64TLBI::TLBIMapper::TLBIMappings[] = {
   {"alle1", ALLE1},
   {"vale1", VALE1},
   {"vale2", VALE2},
   {"vale3", VALE3},
   {"vmalls12e1", VMALLS12E1},
   {"vaale1", VAALE1}
 };
 
-AArch64TLBI::TLBIMapper::TLBIMapper()
-  : AArch64NamedImmMapper(TLBIMappings, 0) {}
+AArch64TLBI::TLBIMapper::TLBIMapper(const FeatureBitset &FeatureBits)
+  : AArch64NamedImmMapper(FeatureBits, TLBIMappings, 0) {}