[AArch64] Add v8.1a "Privileged Access Never" extension

[vsukharev]

Summary

Based on http://reviews.llvm.org/D8496

[jmolloy]

Hi Vladimir,

With the above nits picked, looks fine to me!

Cheers,

James

lib/Target/AArch64/Utils/AArch64BaseInfo.h

446 ↗

(On Diff #22383)

Please add a comment like "// Added in v8.1a", to signify why PAN is out of numeric order.

test/MC/AArch64/armv8-extension-pan.s

1 ↗

(On Diff #22383)

I know it's picky, but please add a space after the // like all other files.

llvm/trunk/lib/Target/AArch64/Utils/AArch64BaseInfo.h

namespace AArch64PRFM {
   };
 }
 
 namespace AArch64PState {
   enum PStateValues {
     Invalid = -1,
     SPSel = 0x05,
     DAIFSet = 0x1e,
-    DAIFClr = 0x1f
+    DAIFClr = 0x1f,
+
+    // v8.1a "Privileged Access Never" extension-specific PStates
+    PAN = 0x04,
   };
 
   struct PStateMapper : AArch64NamedImmMapper {
     const static Mapping PStateMappings[];
 
     PStateMapper();
   };
 
enum SysRegValues {
     ICH_LR9_EL2       = 0xe669, // 11  100  1100  1101  001
     ICH_LR10_EL2      = 0xe66a, // 11  100  1100  1101  010
     ICH_LR11_EL2      = 0xe66b, // 11  100  1100  1101  011
     ICH_LR12_EL2      = 0xe66c, // 11  100  1100  1101  100
     ICH_LR13_EL2      = 0xe66d, // 11  100  1100  1101  101
     ICH_LR14_EL2      = 0xe66e, // 11  100  1100  1101  110
     ICH_LR15_EL2      = 0xe66f, // 11  100  1100  1101  111
 
+    // v8.1a "Privileged Access Never" extension-specific system registers
+    PAN               = 0xc213, // 11  000  0100  0010  011
+
     // Cyclone specific system registers
     CPM_IOACC_CTL_EL3 = 0xff90,
   };
 
   // Note that these do not inherit from AArch64NamedImmMapper. This class is
   // sufficiently different in its behaviour that I don't believe it's worth
   // burdening the common AArch64NamedImmMapper with abstractions only needed in
   // this one case.

llvm/trunk/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp

 };
 
 AArch64PRFM::PRFMMapper::PRFMMapper()
   : AArch64NamedImmMapper(PRFMMappings, 32) {}
 
 const AArch64NamedImmMapper::Mapping AArch64PState::PStateMapper::PStateMappings[] = {
   {"spsel", SPSel, 0},
   {"daifset", DAIFSet, 0},
-  {"daifclr", DAIFClr, 0}
+  {"daifclr", DAIFClr, 0},
+
+  // v8.1a "Privileged Access Never" extension-specific PStates
+  {"pan", PAN, AArch64::HasV8_1aOps},
 };
 
 AArch64PState::PStateMapper::PStateMapper()
   : AArch64NamedImmMapper(PStateMappings, 0) {}
 
 const AArch64NamedImmMapper::Mapping AArch64SysReg::MRSMapper::MRSMappings[] = {
   {"mdccsr_el0", MDCCSR_EL0, 0},
   {"dbgdtrrx_el0", DBGDTRRX_EL0, 0},
const AArch64NamedImmMapper::Mapping AArch64SysReg::MSRMapper::MSRMappings[] = {
   {"trclar", TRCLAR, 0},
 
   // GICv3 registers
   {"icc_eoir1_el1", ICC_EOIR1_EL1, 0},
   {"icc_eoir0_el1", ICC_EOIR0_EL1, 0},
   {"icc_dir_el1", ICC_DIR_EL1, 0},
   {"icc_sgi1r_el1", ICC_SGI1R_EL1, 0},
   {"icc_asgi1r_el1", ICC_ASGI1R_EL1, 0},
-  {"icc_sgi0r_el1", ICC_SGI0R_EL1, 0}
+  {"icc_sgi0r_el1", ICC_SGI0R_EL1, 0},
+
+  // v8.1a "Privileged Access Never" extension-specific system registers
+  {"pan", PAN, AArch64::HasV8_1aOps},
 };
 
 AArch64SysReg::MSRMapper::MSRMapper() {
     InstMappings = &MSRMappings[0];
     NumInstMappings = llvm::array_lengthof(MSRMappings);
 }
 
 
const AArch64NamedImmMapper::Mapping AArch64SysReg::SysRegMapper::SysRegMappings[] = {
   {"ich_lr11_el2", ICH_LR11_EL2, 0},
   {"ich_lr12_el2", ICH_LR12_EL2, 0},
   {"ich_lr13_el2", ICH_LR13_EL2, 0},
   {"ich_lr14_el2", ICH_LR14_EL2, 0},
   {"ich_lr15_el2", ICH_LR15_EL2, 0},
 
   // Cyclone registers
   {"cpm_ioacc_ctl_el3", CPM_IOACC_CTL_EL3, AArch64::ProcCyclone},
+
+  // v8.1a "Privileged Access Never" extension-specific system registers
+  {"pan", PAN, AArch64::HasV8_1aOps},
 };
 
 uint32_t
 AArch64SysReg::SysRegMapper::fromString(StringRef Name, uint64_t FeatureBits, 
                                         bool &Valid) const {
   std::string NameLower = Name.lower();
 
   // First search the registers shared by all

llvm/trunk/test/MC/AArch64/armv8.1a-pan.s

+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.1a -show-encoding < %s 2> %t | FileCheck %s
+// RUN: FileCheck --check-prefix=CHECK-ERROR %s < %t
+
+  .text
+
+  msr pan, #0
+// CHECK:  msr PAN, #0           // encoding: [0x9f,0x40,0x00,0xd5]
+  msr pan, #1
+// CHECK:  msr PAN, #1           // encoding: [0x9f,0x41,0x00,0xd5]
+  msr pan, x5
+// CHECK:  msr PAN, x5           // encoding: [0x65,0x42,0x18,0xd5]
+  mrs x13, pan
+// CHECK:  mrs x13, PAN          // encoding: [0x6d,0x42,0x38,0xd5]
+
+  msr pan, #-1
+  msr pan, #20
+  msr pan, w0
+  mrs w0, pan
+// CHECK-ERROR: error: immediate must be an integer in range [0, 15].
+// CHECK-ERROR:   msr pan, #-1
+// CHECK-ERROR:            ^
+// CHECK-ERROR: error: immediate must be an integer in range [0, 15].
+// CHECK-ERROR:   msr pan, #20
+// CHECK-ERROR:            ^
+// CHECK-ERROR: error: immediate must be an integer in range [0, 15].
+// CHECK-ERROR:   msr pan, w0
+// CHECK-ERROR:            ^
+// CHECK-ERROR: error: invalid operand for instruction
+// CHECK-ERROR:   mrs w0, pan
+// CHECK-ERROR:       ^

llvm/trunk/test/MC/Disassembler/AArch64/armv8.1a-pan.txt

+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.1a --disassemble < %s | FileCheck %s
+
+0x9f,0x40,0x00,0xd5
+0x9f,0x41,0x00,0xd5
+0x65,0x42,0x18,0xd5
+0x6d,0x42,0x38,0xd5
+# CHECK:  msr PAN, #0
+# CHECK:  msr PAN, #1
+# CHECK:  msr PAN, x5
+# CHECK:  mrs x13, PAN