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Differential D8500

[AArch64] Add v8.1a "Virtualization Host Extensions"
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Authored by vsukharev on Mar 20 2015, 2:59 PM.

Details

Reviewers
t.p.northover
Commits
rG6334cf3d697a: [AArch64] Add v8.1a "Virtualization Host Extensions"
Summary

Based on http://reviews.llvm.org/D8499

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Event Timeline

vsukharev updated this revision to Diff 22385.Mar 20 2015, 2:59 PM
vsukharev retitled this revision from to [AArch64] Add v8.1a "Virtualization Host Extensions".
vsukharev updated this object.
vsukharev edited the test plan for this revision. (Show Details)
vsukharev set the repository for this revision to rL LLVM.
vsukharev added a subscriber: Unknown Object (MLST).
Herald added subscribers: aemerson, rengolin. · View Herald TranscriptMar 20 2015, 2:59 PM
vsukharev added a parent revision: D8499: [AArch64] Add v8.1a "Limited Ordering Regions" extension.Mar 20 2015, 3:10 PM
vsukharev added a reviewer: t.p.northover.Mar 24 2015, 2:17 AM
emaste added a subscriber: emaste.Mar 24 2015, 8:45 AM
vsukharev added a comment.Mar 31 2015, 8:59 AM

ping..

t.p.northover accepted this revision.Mar 31 2015, 9:02 AM
t.p.northover edited edge metadata.

This looks fine.

Tim.

This revision is now accepted and ready to land.Mar 31 2015, 9:02 AM
Eugene.Zelenko closed this revision.Sep 27 2016, 6:51 PM
Eugene.Zelenko added a subscriber: Eugene.Zelenko.

Committed in rL235107.

Revision Contents

PathSize
lib/
Target/
AArch64/
Utils/
29 lines
29 lines
test/
MC/
AArch64/
61 lines
Disassembler/
AArch64/
56 lines

Diff 22385

lib/Target/AArch64/Utils/AArch64BaseInfo.h

Show First 20 Lines • Show All 1,135 Lines • ▼ Show 20 Lines enum SysRegValues {
// Limited Ordering Regions extension system registers // Limited Ordering Regions extension system registers
LORSA_EL1 = 0xc520, // 11 000 1010 0100 000 LORSA_EL1 = 0xc520, // 11 000 1010 0100 000
LOREA_EL1 = 0xc521, // 11 000 1010 0100 001 LOREA_EL1 = 0xc521, // 11 000 1010 0100 001
LORN_EL1 = 0xc522, // 11 000 1010 0100 010 LORN_EL1 = 0xc522, // 11 000 1010 0100 010
LORC_EL1 = 0xc523, // 11 000 1010 0100 011 LORC_EL1 = 0xc523, // 11 000 1010 0100 011
LORID_EL1 = 0xc527, // 11 000 1010 0100 111 LORID_EL1 = 0xc527, // 11 000 1010 0100 111
// Virtualization host extensions system registers
TTBR1_EL2 = 0xe101, // 11 100 0010 0000 001
CONTEXTIDR_EL2 = 0xe681, // 11 100 1101 0000 001
CNTHV_TVAL_EL2 = 0xe718, // 11 100 1110 0011 000
CNTHV_CVAL_EL2 = 0xe71a, // 11 100 1110 0011 010
CNTHV_CTL_EL2 = 0xe719, // 11 100 1110 0011 001
SCTLR_EL12 = 0xe880, // 11 101 0001 0000 000
CPACR_EL12 = 0xe882, // 11 101 0001 0000 010
TTBR0_EL12 = 0xe900, // 11 101 0010 0000 000
TTBR1_EL12 = 0xe901, // 11 101 0010 0000 001
TCR_EL12 = 0xe902, // 11 101 0010 0000 010
AFSR0_EL12 = 0xea88, // 11 101 0101 0001 000
AFSR1_EL12 = 0xea89, // 11 101 0101 0001 001
ESR_EL12 = 0xea90, // 11 101 0101 0010 000
FAR_EL12 = 0xeb00, // 11 101 0110 0000 000
MAIR_EL12 = 0xed10, // 11 101 1010 0010 000
AMAIR_EL12 = 0xed18, // 11 101 1010 0011 000
VBAR_EL12 = 0xee00, // 11 101 1100 0000 000
CONTEXTIDR_EL12 = 0xee81, // 11 101 1101 0000 001
CNTKCTL_EL12 = 0xef08, // 11 101 1110 0001 000
CNTP_TVAL_EL02 = 0xef10, // 11 101 1110 0010 000
CNTP_CTL_EL02 = 0xef11, // 11 101 1110 0010 001
CNTP_CVAL_EL02 = 0xef12, // 11 101 1110 0010 010
CNTV_TVAL_EL02 = 0xef18, // 11 101 1110 0011 000
CNTV_CTL_EL02 = 0xef19, // 11 101 1110 0011 001
CNTV_CVAL_EL02 = 0xef1a, // 11 101 1110 0011 010
SPSR_EL12 = 0xea00, // 11 101 0100 0000 000
ELR_EL12 = 0xea01, // 11 101 0100 0000 001
// Cyclone specific system registers // Cyclone specific system registers
CPM_IOACC_CTL_EL3 = 0xff90 CPM_IOACC_CTL_EL3 = 0xff90
}; };
// Note that these do not inherit from AArch64NamedImmMapper. This class is // Note that these do not inherit from AArch64NamedImmMapper. This class is
// sufficiently different in its behaviour that I don't believe it's worth // sufficiently different in its behaviour that I don't believe it's worth
// burdening the common AArch64NamedImmMapper with abstractions only needed in // burdening the common AArch64NamedImmMapper with abstractions only needed in
// this one case. // this one case.
▲ Show 20 Lines • Show All 158 Lines • Show Last 20 Lines

lib/Target/AArch64/Utils/AArch64BaseInfo.cpp

Show First 20 Lines • Show All 762 Lines • ▼ Show 20 Linesconst AArch64NamedImmMapper::Mapping AArch64SysReg::SysRegMapper::SysRegMappings[] = {
{"pan", PAN, AArch64::FeatureV8_1a}, {"pan", PAN, AArch64::FeatureV8_1a},
// Limited Ordering Regions extension system registers // Limited Ordering Regions extension system registers
{"lorsa_el1", LORSA_EL1, AArch64::FeatureV8_1a}, {"lorsa_el1", LORSA_EL1, AArch64::FeatureV8_1a},
{"lorea_el1", LOREA_EL1, AArch64::FeatureV8_1a}, {"lorea_el1", LOREA_EL1, AArch64::FeatureV8_1a},
{"lorn_el1", LORN_EL1, AArch64::FeatureV8_1a}, {"lorn_el1", LORN_EL1, AArch64::FeatureV8_1a},
{"lorc_el1", LORC_EL1, AArch64::FeatureV8_1a}, {"lorc_el1", LORC_EL1, AArch64::FeatureV8_1a},
{"lorid_el1", LORID_EL1, AArch64::FeatureV8_1a}, {"lorid_el1", LORID_EL1, AArch64::FeatureV8_1a},
// Virtualization host extensions system registers
{"ttbr1_el2", TTBR1_EL2, AArch64::FeatureV8_1a},
{"contextidr_el2", CONTEXTIDR_EL2, AArch64::FeatureV8_1a},
{"cnthv_tval_el2", CNTHV_TVAL_EL2, AArch64::FeatureV8_1a},
{"cnthv_cval_el2", CNTHV_CVAL_EL2, AArch64::FeatureV8_1a},
{"cnthv_ctl_el2", CNTHV_CTL_EL2, AArch64::FeatureV8_1a},
{"sctlr_el12", SCTLR_EL12, AArch64::FeatureV8_1a},
{"cpacr_el12", CPACR_EL12, AArch64::FeatureV8_1a},
{"ttbr0_el12", TTBR0_EL12, AArch64::FeatureV8_1a},
{"ttbr1_el12", TTBR1_EL12, AArch64::FeatureV8_1a},
{"tcr_el12", TCR_EL12, AArch64::FeatureV8_1a},
{"afsr0_el12", AFSR0_EL12, AArch64::FeatureV8_1a},
{"afsr1_el12", AFSR1_EL12, AArch64::FeatureV8_1a},
{"esr_el12", ESR_EL12, AArch64::FeatureV8_1a},
{"far_el12", FAR_EL12, AArch64::FeatureV8_1a},
{"mair_el12", MAIR_EL12, AArch64::FeatureV8_1a},
{"amair_el12", AMAIR_EL12, AArch64::FeatureV8_1a},
{"vbar_el12", VBAR_EL12, AArch64::FeatureV8_1a},
{"contextidr_el12", CONTEXTIDR_EL12, AArch64::FeatureV8_1a},
{"cntkctl_el12", CNTKCTL_EL12, AArch64::FeatureV8_1a},
{"cntp_tval_el02", CNTP_TVAL_EL02, AArch64::FeatureV8_1a},
{"cntp_ctl_el02", CNTP_CTL_EL02, AArch64::FeatureV8_1a},
{"cntp_cval_el02", CNTP_CVAL_EL02, AArch64::FeatureV8_1a},
{"cntv_tval_el02", CNTV_TVAL_EL02, AArch64::FeatureV8_1a},
{"cntv_ctl_el02", CNTV_CTL_EL02, AArch64::FeatureV8_1a},
{"cntv_cval_el02", CNTV_CVAL_EL02, AArch64::FeatureV8_1a},
{"spsr_el12", SPSR_EL12, AArch64::FeatureV8_1a},
{"elr_el12", ELR_EL12, AArch64::FeatureV8_1a},
}; };
uint32_t uint32_t
AArch64SysReg::SysRegMapper::fromString(StringRef Name, bool &Valid) const { AArch64SysReg::SysRegMapper::fromString(StringRef Name, bool &Valid) const {
std::string NameLower = Name.lower(); std::string NameLower = Name.lower();
// First search the registers shared by all // First search the registers shared by all
for (unsigned i = 0; i < array_lengthof(SysRegMappings); ++i) { for (unsigned i = 0; i < array_lengthof(SysRegMappings); ++i) {
▲ Show 20 Lines • Show All 106 Lines • Show Last 20 Lines

test/MC/AArch64/armv8-extension-vhe.s

  • This file was added.
// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.1a < %s | FileCheck %s
//------------------------------------------------------------------------------
// Virtualization Host Extensions
//------------------------------------------------------------------------------
msr TTBR1_EL2, x0
msr CONTEXTIDR_EL2, x0
msr CNTHV_TVAL_EL2, x0
msr CNTHV_CVAL_EL2, x0
msr CNTHV_CTL_EL2, x0
msr SCTLR_EL12, x0
msr CPACR_EL12, x0
msr TTBR0_EL12, x0
msr TTBR1_EL12, x0
msr TCR_EL12, x0
msr AFSR0_EL12, x0
msr AFSR1_EL12, x0
msr ESR_EL12, x0
msr FAR_EL12, x0
msr MAIR_EL12, x0
msr AMAIR_EL12, x0
msr VBAR_EL12, x0
msr CONTEXTIDR_EL12, x0
msr CNTKCTL_EL12, x0
msr CNTP_TVAL_EL02, x0
msr CNTP_CTL_EL02, x0
msr CNTP_CVAL_EL02, x0
msr CNTV_TVAL_EL02, x0
msr CNTV_CTL_EL02, x0
msr CNTV_CVAL_EL02, x0
msr SPSR_EL12, x0
msr ELR_EL12, x0
// CHECK: msr TTBR1_EL2, x0 // encoding: [0x20,0x20,0x1c,0xd5]
// CHECK: msr CONTEXTIDR_EL2, x0 // encoding: [0x20,0xd0,0x1c,0xd5]
// CHECK: msr CNTHV_TVAL_EL2, x0 // encoding: [0x00,0xe3,0x1c,0xd5]
// CHECK: msr CNTHV_CVAL_EL2, x0 // encoding: [0x40,0xe3,0x1c,0xd5]
// CHECK: msr CNTHV_CTL_EL2, x0 // encoding: [0x20,0xe3,0x1c,0xd5]
// CHECK: msr SCTLR_EL12, x0 // encoding: [0x00,0x10,0x1d,0xd5]
// CHECK: msr CPACR_EL12, x0 // encoding: [0x40,0x10,0x1d,0xd5]
// CHECK: msr TTBR0_EL12, x0 // encoding: [0x00,0x20,0x1d,0xd5]
// CHECK: msr TTBR1_EL12, x0 // encoding: [0x20,0x20,0x1d,0xd5]
// CHECK: msr TCR_EL12, x0 // encoding: [0x40,0x20,0x1d,0xd5]
// CHECK: msr AFSR0_EL12, x0 // encoding: [0x00,0x51,0x1d,0xd5]
// CHECK: msr AFSR1_EL12, x0 // encoding: [0x20,0x51,0x1d,0xd5]
// CHECK: msr ESR_EL12, x0 // encoding: [0x00,0x52,0x1d,0xd5]
// CHECK: msr FAR_EL12, x0 // encoding: [0x00,0x60,0x1d,0xd5]
// CHECK: msr MAIR_EL12, x0 // encoding: [0x00,0xa2,0x1d,0xd5]
// CHECK: msr AMAIR_EL12, x0 // encoding: [0x00,0xa3,0x1d,0xd5]
// CHECK: msr VBAR_EL12, x0 // encoding: [0x00,0xc0,0x1d,0xd5]
// CHECK: msr CONTEXTIDR_EL12, x0 // encoding: [0x20,0xd0,0x1d,0xd5]
// CHECK: msr CNTKCTL_EL12, x0 // encoding: [0x00,0xe1,0x1d,0xd5]
// CHECK: msr CNTP_TVAL_EL02, x0 // encoding: [0x00,0xe2,0x1d,0xd5]
// CHECK: msr CNTP_CTL_EL02, x0 // encoding: [0x20,0xe2,0x1d,0xd5]
// CHECK: msr CNTP_CVAL_EL02, x0 // encoding: [0x40,0xe2,0x1d,0xd5]
// CHECK: msr CNTV_TVAL_EL02, x0 // encoding: [0x00,0xe3,0x1d,0xd5]
// CHECK: msr CNTV_CTL_EL02, x0 // encoding: [0x20,0xe3,0x1d,0xd5]
// CHECK: msr CNTV_CVAL_EL02, x0 // encoding: [0x40,0xe3,0x1d,0xd5]
// CHECK: msr SPSR_EL12, x0 // encoding: [0x00,0x40,0x1d,0xd5]
// CHECK: msr ELR_EL12, x0 // encoding: [0x20,0x40,0x1d,0xd5]

test/MC/Disassembler/AArch64/armv8-extension-vhe.txt

  • This file was added.
# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.1a --disassemble < %s | FileCheck %s
0x20,0x20,0x1c,0xd5
0x20,0xd0,0x1c,0xd5
0x00,0xe3,0x1c,0xd5
0x40,0xe3,0x1c,0xd5
0x20,0xe3,0x1c,0xd5
0x00,0x10,0x1d,0xd5
0x40,0x10,0x1d,0xd5
0x00,0x20,0x1d,0xd5
0x20,0x20,0x1d,0xd5
0x40,0x20,0x1d,0xd5
0x00,0x51,0x1d,0xd5
0x20,0x51,0x1d,0xd5
0x00,0x52,0x1d,0xd5
0x00,0x60,0x1d,0xd5
0x00,0xa2,0x1d,0xd5
0x00,0xa3,0x1d,0xd5
0x00,0xc0,0x1d,0xd5
0x20,0xd0,0x1d,0xd5
0x00,0xe1,0x1d,0xd5
0x00,0xe2,0x1d,0xd5
0x20,0xe2,0x1d,0xd5
0x40,0xe2,0x1d,0xd5
0x00,0xe3,0x1d,0xd5
0x20,0xe3,0x1d,0xd5
0x40,0xe3,0x1d,0xd5
0x00,0x40,0x1d,0xd5
0x20,0x40,0x1d,0xd5
# CHECK: msr TTBR1_EL2, x0
# CHECK: msr CONTEXTIDR_EL2, x0
# CHECK: msr CNTHV_TVAL_EL2, x0
# CHECK: msr CNTHV_CVAL_EL2, x0
# CHECK: msr CNTHV_CTL_EL2, x0
# CHECK: msr SCTLR_EL12, x0
# CHECK: msr CPACR_EL12, x0
# CHECK: msr TTBR0_EL12, x0
# CHECK: msr TTBR1_EL12, x0
# CHECK: msr TCR_EL12, x0
# CHECK: msr AFSR0_EL12, x0
# CHECK: msr AFSR1_EL12, x0
# CHECK: msr ESR_EL12, x0
# CHECK: msr FAR_EL12, x0
# CHECK: msr MAIR_EL12, x0
# CHECK: msr AMAIR_EL12, x0
# CHECK: msr VBAR_EL12, x0
# CHECK: msr CONTEXTIDR_EL12, x0
# CHECK: msr CNTKCTL_EL12, x0
# CHECK: msr CNTP_TVAL_EL02, x0
# CHECK: msr CNTP_CTL_EL02, x0
# CHECK: msr CNTP_CVAL_EL02, x0
# CHECK: msr CNTV_TVAL_EL02, x0
# CHECK: msr CNTV_CTL_EL02, x0
# CHECK: msr CNTV_CVAL_EL02, x0
# CHECK: msr SPSR_EL12, x0
# CHECK: msr ELR_EL12, x0