[TargetPassConfig] Run MachineVerifier after more passes

[ZhangKang]

Summary

Some patches has upstreamed to fix the bug for MachineVerifier, now we can
run MachineVerifier after more passes.

[arsenm]

llvm/lib/CodeGen/TargetPassConfig.cpp

1176

I thought there were deeper problems here that prevented this, but it's great if that's not the case anymore

1201

I assume there's still a problem for TwoAddressInstructionPass?

[MaskRay]

If your build is configured with -DLLVM_ENABLE_EXPENSIVE_CHECKS=on, verifyer passes may be added even without -verify-machineinstrs. I assume you have tested them...

[ZhangKang]

In D84927#2185618, @MaskRay wrote:

If your build is configured with -DLLVM_ENABLE_EXPENSIVE_CHECKS=on, verifyer passes may be added even without -verify-machineinstrs. I assume you have tested them...

Yes, I have used -DLLVM_ENABLE_EXPENSIVE_CHECKS=on to test this patch. Now there are 28 lit errors and 78 lnt errors, and this patch doesn't cause new errors.

llvm/lib/CodeGen/TargetPassConfig.cpp

1176

All the test can be passes when enable verification for this pass.

1201

Yes, there still are errors for TwoAddressInstructionPass?.

[MaskRay]

This never landed but was obsoleted by some cleanups and D111872

llvm/lib/CodeGen/TargetPassConfig.cpp

if (MISchedPostRA)
       addPass(&PostMachineSchedulerID);
     else
       addPass(&PostRASchedulerID);
   }
 
   // GC
   if (addGCPasses()) {
     if (PrintGCInfo)
-      addPass(createGCInfoPrinter(dbgs()), false);
+      addPass(createGCInfoPrinter(dbgs()));
   }
 
   // Basic block placement.
   if (getOptLevel() != CodeGenOpt::None)
     addBlockPlacement();
 
   // Insert before XRay Instrumentation.
   addPass(&FEntryInserterID);

 /// has not be overriden on the command line with '-regalloc=...'
 bool TargetPassConfig::usingDefaultRegAlloc() const {
   return RegAlloc.getNumOccurrences() == 0;
 }
 
 /// Add the minimum set of target-independent passes that are required for
 /// register allocation. No coalescing or scheduling.
 void TargetPassConfig::addFastRegAlloc() {
-  addPass(&PHIEliminationID, false);
+  addPass(&PHIEliminationID);
   addPass(&TwoAddressInstructionPassID, false);
 
   addRegAssignmentFast();
 }
 
 /// Add standard target-independent passes that are tightly coupled with
 /// optimized register allocation, including coalescing, machine instruction
 /// scheduling, and register allocation itself.
 void TargetPassConfig::addOptimizedRegAlloc() {
-  addPass(&DetectDeadLanesID, false);
+  addPass(&DetectDeadLanesID);
 
-  addPass(&ProcessImplicitDefsID, false);
+  addPass(&ProcessImplicitDefsID);
 
   // LiveVariables currently requires pure SSA form.
   //
   // FIXME: Once TwoAddressInstruction pass no longer uses kill flags,
   // LiveVariables can be removed completely, and LiveIntervals can be directly
   // computed. (We still either need to regenerate kill flags after regalloc, or
   // preferably fix the scavenger to not depend on them).
   // FIXME: UnreachableMachineBlockElim is a dependant pass of LiveVariables.
   // When LiveVariables is removed this has to be removed/moved either.
   // Explicit addition of UnreachableMachineBlockElim allows stopping before or
   // after it with -stop-before/-stop-after.
-  addPass(&UnreachableMachineBlockElimID, false);
-  addPass(&LiveVariablesID, false);
+  addPass(&UnreachableMachineBlockElimID);
+  addPass(&LiveVariablesID);
 
   // Edge splitting is smarter with machine loop info.
-  addPass(&MachineLoopInfoID, false);
-  addPass(&PHIEliminationID, false);
+  addPass(&MachineLoopInfoID);
+  addPass(&PHIEliminationID);
 
   // Eventually, we want to run LiveIntervals before PHI elimination.
   if (EarlyLiveIntervals)
-    addPass(&LiveIntervalsID, false);
+    addPass(&LiveIntervalsID);
 
   addPass(&TwoAddressInstructionPassID, false);
   addPass(&RegisterCoalescerID);
 
   // The machine scheduler may accidentally create disconnected components
   // when moving subregister definitions around, avoid this by splitting them to
   // separate vregs before. Splitting can also improve reg. allocation quality.
   addPass(&RenameIndependentSubregsID);
 
   // PreRA instruction scheduling.
if (!TM->requiresStructuredCFG())
     addPass(&TailDuplicateID);
 
   // Copy propagation.
   addPass(&MachineCopyPropagationID);
 }
 
 /// Add standard GC passes.
 bool TargetPassConfig::addGCPasses() {
-  addPass(&GCMachineCodeAnalysisID, false);
+  addPass(&GCMachineCodeAnalysisID);
   return true;
 }
 
 /// Add standard basic block placement passes.
 void TargetPassConfig::addBlockPlacement() {
   if (addPass(&MachineBlockPlacementID)) {
     // Run a separate pass to collect block placement statistics.
     if (EnableBlockPlacementStats)