[PowerPC] Add intrinsic to read or set FPSCR register

[qiucf]

Summary

This patch introduces two intrinsics: llvm.ppc.setflm and llvm.ppc.readflm. They read from or write to FPSCR register (floating-point status & control) which contains rounding mode and exception status.

To ensure correctness of program, we need to prevent FP operations from being moved across these intrinsics (mffs/mtfsf instruction), so here I set them as scheduling boundaries. We can relax such restriction if FPSCR is modeled well in the future.

[steven.zhang]

LGTM. But even we mark these two bif as boundary, there is still possible that, the pass after ISEL might move the MI across them. Some follow up work is needed to confirm this.

llvm/include/llvm/IR/IntrinsicsPowerPC.td

let TargetPrefix = "ppc" in {  // All intrinsics start with "llvm.ppc.".
   def int_ppc_sync : Intrinsic<[], [], []>;
   // isync instruction
   def int_ppc_isync : Intrinsic<[], [], []>;
   // lwsync is sync 1
   def int_ppc_lwsync : Intrinsic<[], [], []>;
   // eieio instruction
   def int_ppc_eieio : Intrinsic<[],[],[]>;
 
+  // Get content from current FPSCR register
+  def int_ppc_readflm : Intrinsic<[llvm_double_ty], [], [IntrNoMem]>;
+  // Set FPSCR register, and return previous content
+  def int_ppc_setflm : Intrinsic<[llvm_double_ty], [llvm_double_ty], []>;
+
   // Intrinsics for [double]word extended forms of divide instructions
   def int_ppc_divwe : GCCBuiltin<"__builtin_divwe">,
                       Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
                                 [IntrNoMem]>;
   def int_ppc_divweu : GCCBuiltin<"__builtin_divweu">,
                        Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
                                  [IntrNoMem]>;
   def int_ppc_divde : GCCBuiltin<"__builtin_divde">,

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

else if (MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
 
     // The mask 255 means that put the 32:63 bits of NewFPSCRReg to the 32:63
     // bits of FPSCR.
     BuildMI(*BB, MI, dl, TII->get(PPC::MTFSF))
       .addImm(255)
       .addReg(NewFPSCRReg)
       .addImm(0)
       .addImm(0);
+  } else if (MI.getOpcode() == PPC::SETFLM) {
+    DebugLoc Dl = MI.getDebugLoc();
+
+    // Result of setflm is previous FPSCR content, so we need to save it first.
+    Register OldFPSCRReg = MI.getOperand(0).getReg();
+    BuildMI(*BB, MI, Dl, TII->get(PPC::MFFS), OldFPSCRReg);
+
+    // Put bits in 32:63 to FPSCR.
+    Register NewFPSCRReg = MI.getOperand(1).getReg();
+    BuildMI(*BB, MI, Dl, TII->get(PPC::MTFSF))
+        .addImm(255)
+        .addReg(NewFPSCRReg)
+        .addImm(0)
+        .addImm(0);
   } else if (MI.getOpcode() == PPC::PROBED_ALLOCA_32 ||
              MI.getOpcode() == PPC::PROBED_ALLOCA_64) {
     return emitProbedAlloca(MI, BB);
   } else {
     llvm_unreachable("Unexpected instr type to insert");
   }
 
   MI.eraseFromParent(); // The pseudo instruction is gone now.

llvm/lib/Target/PowerPC/PPCInstrInfo.h

public:
   bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
                                  MachineBasicBlock &FMBB) const override {
     return false;
   }
 
   // Predication support.
   bool isPredicated(const MachineInstr &MI) const override;
 
+  bool isSchedulingBoundary(const MachineInstr &MI,
+                            const MachineBasicBlock *MBB,
+                            const MachineFunction &MF) const override;
+
   bool PredicateInstruction(MachineInstr &MI,
                             ArrayRef<MachineOperand> Pred) const override;
 
   bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
                          ArrayRef<MachineOperand> Pred2) const override;
 
   bool DefinesPredicate(MachineInstr &MI,
                         std::vector<MachineOperand> &Pred) const override;

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

bool PPCInstrInfo::isPredicated(const MachineInstr &MI) const {
   // predicated more than once. Because if conversion won't try to predicate
   // any instruction which already claims to be predicated (by returning true
   // here), always return false. In doing so, we let isPredicable() be the
   // final word on whether not the instruction can be (further) predicated.
 
   return false;
 }
 
+bool PPCInstrInfo::isSchedulingBoundary(const MachineInstr &MI,
+                                        const MachineBasicBlock *MBB,
+                                        const MachineFunction &MF) const {
+  // Set MFFS and MTFSF as scheduling boundary to avoid unexpected code motion
+  // across them, since some FP operations may change content of FPSCR.
+  // TODO: Model FPSCR in PPC instruction definitions and remove the workaround
+  if (MI.getOpcode() == PPC::MFFS || MI.getOpcode() == PPC::MTFSF)
+    return true;
+  return TargetInstrInfo::isSchedulingBoundary(MI, MBB, MF);
+}
+
 bool PPCInstrInfo::PredicateInstruction(MachineInstr &MI,
                                         ArrayRef<MachineOperand> Pred) const {
   unsigned OpC = MI.getOpcode();
   if (OpC == PPC::BLR || OpC == PPC::BLR8) {
     if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
       bool isPPC64 = Subtarget.isPPC64();
       MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZLR8 : PPC::BDNZLR)
                                       : (isPPC64 ? PPC::BDZLR8 : PPC::BDZLR)));

llvm/lib/Target/PowerPC/PPCInstrInfo.td

 
 // Set the float rounding mode.
 let Uses = [RM], Defs = [RM] in {
 def SETRNDi : PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins u2imm:$RND),
                     "#SETRNDi", [(set f64:$FRT, (int_ppc_setrnd (i32 imm:$RND)))]>;
 
 def SETRND : PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins gprc:$in),
                     "#SETRND", [(set f64:$FRT, (int_ppc_setrnd gprc :$in))]>;
+
+def SETFLM : PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins f8rc:$FLM),
+                    "#SETFLM", [(set f64:$FRT, (int_ppc_setflm f8rc:$FLM))]>;
 }
 
 let Defs = [LR] in
   def MovePCtoLR : PPCEmitTimePseudo<(outs), (ins), "#MovePCtoLR", []>,
                    PPC970_Unit_BRU;
 let Defs = [LR] in
   def MoveGOTtoLR : PPCEmitTimePseudo<(outs), (ins), "#MoveGOTtoLR", []>,
                     PPC970_Unit_BRU;
def : Pat<(PPCtc_return (i32 tglobaladdr:$dst),  imm:$imm),
           (TCRETURNdi tglobaladdr:$dst, imm:$imm)>;
 
 def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm),
           (TCRETURNdi texternalsym:$dst, imm:$imm)>;
 
 def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
           (TCRETURNri CTRRC:$dst, imm:$imm)>;
 
-
+def : Pat<(int_ppc_readflm), (MFFS)>;
 
 // Hi and Lo for Darwin Global Addresses.
 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
 def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
 def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
 def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
 def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
 def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;

llvm/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll

 ; CHECK-NEXT:    stw 3, 344(1)
 ; CHECK-NEXT:    lfd 3, 368(1)
 ; CHECK-NEXT:    lfd 4, 360(1)
 ; CHECK-NEXT:    lfd 1, 352(1)
 ; CHECK-NEXT:    lfd 2, 344(1)
 ; CHECK-NEXT:    bl __gcc_qsub
 ; CHECK-NEXT:    mffs 0
 ; CHECK-NEXT:    mtfsb1 31
-; CHECK-NEXT:    lis 3, .LCPI0_1@ha
 ; CHECK-NEXT:    mtfsb0 30
 ; CHECK-NEXT:    fadd 1, 2, 1
 ; CHECK-NEXT:    mtfsf 1, 0
 ; CHECK-NEXT:    fctiwz 0, 1
-; CHECK-NEXT:    mffs 1
 ; CHECK-NEXT:    stfd 0, 160(1)
+; CHECK-NEXT:    mffs 0
 ; CHECK-NEXT:    mtfsb1 31
+; CHECK-NEXT:    lis 3, .LCPI0_1@ha
 ; CHECK-NEXT:    mtfsb0 30
-; CHECK-NEXT:    fadd 0, 28, 29
-; CHECK-NEXT:    mtfsf 1, 1
-; CHECK-NEXT:    lfs 1, .LCPI0_1@l(3)
-; CHECK-NEXT:    fctiwz 0, 0
-; CHECK-NEXT:    stfd 0, 152(1)
+; CHECK-NEXT:    fadd 1, 28, 29
+; CHECK-NEXT:    mtfsf 1, 0
+; CHECK-NEXT:    lfs 0, .LCPI0_1@l(3)
+; CHECK-NEXT:    fctiwz 1, 1
+; CHECK-NEXT:    stfd 1, 152(1)
 ; CHECK-NEXT:    fcmpu 0, 28, 27
 ; CHECK-NEXT:    lwz 3, 164(1)
-; CHECK-NEXT:    fcmpu 1, 29, 1
+; CHECK-NEXT:    fcmpu 1, 29, 0
 ; CHECK-NEXT:    lwz 4, 156(1)
 ; CHECK-NEXT:    crandc 20, 6, 0
 ; CHECK-NEXT:    cror 20, 5, 20
 ; CHECK-NEXT:    addis 3, 3, -32768
 ; CHECK-NEXT:    bc 12, 20, .LBB0_4
 ; CHECK-NEXT:  # %bb.3: # %bb1
 ; CHECK-NEXT:    ori 30, 4, 0
 ; CHECK-NEXT:    b .LBB0_5

 ; CHECK-NEXT:    stw 3, 56(1)
 ; CHECK-NEXT:    lfd 3, 80(1)
 ; CHECK-NEXT:    lfd 4, 72(1)
 ; CHECK-NEXT:    lfd 1, 64(1)
 ; CHECK-NEXT:    lfd 2, 56(1)
 ; CHECK-NEXT:    bl __gcc_qsub
 ; CHECK-NEXT:    mffs 0
 ; CHECK-NEXT:    mtfsb1 31
-; CHECK-NEXT:    lis 3, .LCPI0_2@ha
 ; CHECK-NEXT:    mtfsb0 30
 ; CHECK-NEXT:    fadd 1, 2, 1
 ; CHECK-NEXT:    mtfsf 1, 0
 ; CHECK-NEXT:    fctiwz 0, 1
-; CHECK-NEXT:    mffs 1
 ; CHECK-NEXT:    stfd 0, 32(1)
+; CHECK-NEXT:    mffs 0
 ; CHECK-NEXT:    mtfsb1 31
-; CHECK-NEXT:    lfs 0, .LCPI0_2@l(3)
-; CHECK-NEXT:    lis 3, .LCPI0_3@ha
+; CHECK-NEXT:    lis 3, .LCPI0_2@ha
+; CHECK-NEXT:    lfs 2, .LCPI0_2@l(3)
 ; CHECK-NEXT:    mtfsb0 30
-; CHECK-NEXT:    fadd 2, 28, 29
-; CHECK-NEXT:    mtfsf 1, 1
-; CHECK-NEXT:    lfs 1, .LCPI0_3@l(3)
-; CHECK-NEXT:    fctiwz 2, 2
-; CHECK-NEXT:    stfd 2, 24(1)
-; CHECK-NEXT:    fcmpu 0, 30, 0
+; CHECK-NEXT:    lis 3, .LCPI0_3@ha
+; CHECK-NEXT:    fadd 1, 28, 29
+; CHECK-NEXT:    mtfsf 1, 0
+; CHECK-NEXT:    lfs 0, .LCPI0_3@l(3)
+; CHECK-NEXT:    fctiwz 1, 1
+; CHECK-NEXT:    stfd 1, 24(1)
+; CHECK-NEXT:    fcmpu 0, 30, 2
 ; CHECK-NEXT:    lwz 3, 36(1)
-; CHECK-NEXT:    fcmpu 1, 31, 1
+; CHECK-NEXT:    fcmpu 1, 31, 0
 ; CHECK-NEXT:    lwz 4, 28(1)
 ; CHECK-NEXT:    crandc 20, 6, 1
 ; CHECK-NEXT:    cror 20, 4, 20
 ; CHECK-NEXT:    addis 3, 3, -32768
 ; CHECK-NEXT:    bc 12, 20, .LBB0_13
 ; CHECK-NEXT:  # %bb.12: # %bb2
 ; CHECK-NEXT:    ori 3, 4, 0
 ; CHECK-NEXT:    b .LBB0_13

 ; CHECK-NEXT:    lwz 3, 104(1)
 ; CHECK-NEXT:    lfd 4, 136(1)
 ; CHECK-NEXT:    stw 3, 120(1)
 ; CHECK-NEXT:    lfd 1, 128(1)
 ; CHECK-NEXT:    lfd 2, 120(1)
 ; CHECK-NEXT:    bl __gcc_qsub
 ; CHECK-NEXT:    mffs 0
 ; CHECK-NEXT:    mtfsb1 31
-; CHECK-NEXT:    lis 3, .LCPI0_0@ha
 ; CHECK-NEXT:    mtfsb0 30
 ; CHECK-NEXT:    fadd 1, 2, 1
 ; CHECK-NEXT:    mtfsf 1, 0
 ; CHECK-NEXT:    fctiwz 0, 1
-; CHECK-NEXT:    mffs 1
 ; CHECK-NEXT:    stfd 0, 96(1)
+; CHECK-NEXT:    mffs 0
 ; CHECK-NEXT:    mtfsb1 31
-; CHECK-NEXT:    lfs 0, .LCPI0_0@l(3)
-; CHECK-NEXT:    lis 3, .LCPI0_1@ha
+; CHECK-NEXT:    lis 3, .LCPI0_0@ha
+; CHECK-NEXT:    lfs 2, .LCPI0_0@l(3)
 ; CHECK-NEXT:    mtfsb0 30
-; CHECK-NEXT:    fadd 2, 30, 31
-; CHECK-NEXT:    mtfsf 1, 1
-; CHECK-NEXT:    lfs 1, .LCPI0_1@l(3)
-; CHECK-NEXT:    fctiwz 2, 2
-; CHECK-NEXT:    stfd 2, 88(1)
-; CHECK-NEXT:    fcmpu 0, 30, 0
+; CHECK-NEXT:    lis 3, .LCPI0_1@ha
+; CHECK-NEXT:    fadd 1, 30, 31
+; CHECK-NEXT:    mtfsf 1, 0
+; CHECK-NEXT:    lfs 0, .LCPI0_1@l(3)
+; CHECK-NEXT:    fctiwz 1, 1
+; CHECK-NEXT:    stfd 1, 88(1)
+; CHECK-NEXT:    fcmpu 0, 30, 2
 ; CHECK-NEXT:    lwz 3, 100(1)
-; CHECK-NEXT:    fcmpu 1, 31, 1
+; CHECK-NEXT:    fcmpu 1, 31, 0
 ; CHECK-NEXT:    lwz 4, 92(1)
 ; CHECK-NEXT:    crandc 20, 6, 0
 ; CHECK-NEXT:    cror 20, 5, 20
 ; CHECK-NEXT:    addis 3, 3, -32768
 ; CHECK-NEXT:    bc 12, 20, .LBB0_15
 ; CHECK-NEXT:    b .LBB0_16
 ; CHECK-NEXT:  .LBB0_15: # %bb3
 ; CHECK-NEXT:    addi 4, 3, 0

llvm/test/CodeGen/PowerPC/read-set-flm.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple powerpc64le-unknown-linux | FileCheck %s
+; RUN: llc < %s -mtriple powerpc64le-unknown-linux -debug-only=machine-scheduler \
+; RUN:   2>&1 | FileCheck %s --check-prefix=LOG
+
+define double @in_nostrict(double %a, double %b, double %c, double %d) {
+; CHECK-LABEL: in_nostrict:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mffs 0
+; CHECK-NEXT:    xsdivdp 1, 1, 2
+; CHECK-NEXT:    xsadddp 1, 1, 3
+; CHECK-NEXT:    xsadddp 0, 1, 0
+; CHECK-NEXT:    mtfsf 255, 4
+; CHECK-NEXT:    xsdivdp 1, 3, 4
+; CHECK-NEXT:    xsadddp 1, 1, 2
+; CHECK-NEXT:    xsadddp 1, 0, 1
+; CHECK-NEXT:    blr
+;
+; LOG: *** MI Scheduling ***
+; LOG-NEXT: in_nostrict:%bb.0 entry
+; LOG: ExitSU: MTFSF 255, %{{[0-9]+}}:f8rc, 0, 0
+; LOG: *** MI Scheduling ***
+; LOG-NEXT: in_nostrict:%bb.0 entry
+; LOG: ExitSU: %{{[0-9]+}}:f8rc = MFFS implicit $rm
+;
+; LOG: *** MI Scheduling ***
+; LOG-NEXT: in_nostrict:%bb.0 entry
+; LOG: ExitSU: MTFSF 255, renamable $f{{[0-9]+}}, 0, 0
+entry:
+  %0 = tail call double @llvm.ppc.readflm()
+  %1 = fdiv double %a, %b
+  %2 = fadd double %1, %c
+  %3 = fadd double %2, %0
+  call double @llvm.ppc.setflm(double %d)
+  %5 = fdiv double %c, %d
+  %6 = fadd double %5, %b
+  %7 = fadd double %3, %6
+  ret double %7
+}
+
+define double @in_strict(double %a, double %b, double %c, double %d) #0 {
+; CHECK-LABEL: in_strict:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mffs 0
+; CHECK-NEXT:    xsdivdp 1, 1, 2
+; CHECK-NEXT:    xsadddp 1, 1, 3
+; CHECK-NEXT:    xsadddp 0, 1, 0
+; CHECK-NEXT:    mtfsf 255, 4
+; CHECK-NEXT:    xsdivdp 1, 3, 4
+; CHECK-NEXT:    xsadddp 1, 1, 2
+; CHECK-NEXT:    xsadddp 1, 0, 1
+; CHECK-NEXT:    blr
+;
+; LOG: ***** MI Scheduling *****
+; LOG-NEXT: in_strict:%bb.0 entry
+; LOG: ExitSU: MTFSF 255, %{{[0-9]+}}:f8rc, 0, 0
+; LOG: ***** MI Scheduling *****
+; LOG-NEXT: in_strict:%bb.0 entry
+; LOG: ExitSU: %{{[0-9]+}}:f8rc = MFFS implicit $rm
+;
+; LOG: ***** MI Scheduling *****
+; LOG-NEXT: in_strict:%bb.0 entry
+; LOG: ExitSU: MTFSF 255, renamable $f{{[0-9]+}}, 0, 0
+entry:
+  %0 = tail call double @llvm.ppc.readflm()
+  %1 = call double @llvm.experimental.constrained.fdiv.f64(double %a, double %b, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
+  %2 = call double @llvm.experimental.constrained.fadd.f64(double %1, double %c, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
+  %3 = call double @llvm.experimental.constrained.fadd.f64(double %2, double %0, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
+  call double @llvm.ppc.setflm(double %d)
+  %5 = call double @llvm.experimental.constrained.fdiv.f64(double %c, double %d, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
+  %6 = call double @llvm.experimental.constrained.fadd.f64(double %5, double %b, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
+  %7 = call double @llvm.experimental.constrained.fadd.f64(double %3, double %6, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
+  ret double %7
+}
+
+declare double @llvm.ppc.readflm()
+declare double @llvm.ppc.setflm(double)
+declare double @llvm.experimental.constrained.fadd.f64(double, double, metadata, metadata)
+declare double @llvm.experimental.constrained.fdiv.f64(double, double, metadata, metadata)
+
+attributes #0 = { strictfp }