AMDGPU/GlobalISel: Remove old hacks for boolean selection

[arsenm]

Summary

There were various hacks used to try to avoid making s1 SGPR vs. s1
VCC ambiguous after constraining the register before we had a strategy
to deal with this. This also attempted to handle undef operands, which
are now illegal gMIR.

[arsenm]

2414bab5d7d6b5b247f3f3b97140a2673fa8414b

llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

if (!isVCC(SrcReg, *MRI)) {
       return true;
     }
 
     const TargetRegisterClass *RC =
       TRI.getConstrainedRegClassForOperand(Dst, *MRI);
     if (RC && !RBI.constrainGenericRegister(DstReg, *RC, *MRI))
       return false;
 
-    // Don't constrain the source register to a class so the def instruction
-    // handles it (unless it's undef).
-    //
-    // FIXME: This is a hack. When selecting the def, we neeed to know
-    // specifically know that the result is VCCRegBank, and not just an SGPR
-    // with size 1. An SReg_32 with size 1 is ambiguous with wave32.
-    if (Src.isUndef()) {
-      const TargetRegisterClass *SrcRC =
-        TRI.getConstrainedRegClassForOperand(Src, *MRI);
-      if (SrcRC && !RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI))
-        return false;
-    }
-
     return true;
   }
 
   for (const MachineOperand &MO : I.operands()) {
     if (Register::isPhysicalRegister(MO.getReg()))
       continue;
 
     const TargetRegisterClass *RC =
static unsigned getLogicalBitOpcode(unsigned Opc, bool Is64) {
   case AMDGPU::G_XOR:
     return Is64 ? AMDGPU::S_XOR_B64 : AMDGPU::S_XOR_B32;
   default:
     llvm_unreachable("not a bit op");
   }
 }
 
 bool AMDGPUInstructionSelector::selectG_AND_OR_XOR(MachineInstr &I) const {
-  MachineOperand &Dst = I.getOperand(0);
-  MachineOperand &Src0 = I.getOperand(1);
-  MachineOperand &Src1 = I.getOperand(2);
-  Register DstReg = Dst.getReg();
+  Register DstReg = I.getOperand(0).getReg();
   unsigned Size = RBI.getSizeInBits(DstReg, *MRI, TRI);
 
   const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI);
-  if (DstRB->getID() == AMDGPU::VCCRegBankID) {
-    const TargetRegisterClass *RC = TRI.getBoolRC();
-    unsigned InstOpc = getLogicalBitOpcode(I.getOpcode(),
-                                           RC == &AMDGPU::SReg_64RegClass);
-    I.setDesc(TII.get(InstOpc));
-    // Dead implicit-def of scc
-    I.addOperand(MachineOperand::CreateReg(AMDGPU::SCC, true, // isDef
-                                           true, // isImp
-                                           false, // isKill
-                                           true)); // isDead
-
-    // FIXME: Hack to avoid turning the register bank into a register class.
-    // The selector for G_ICMP relies on seeing the register bank for the result
-    // is VCC. In wave32 if we constrain the registers to SReg_32 here, it will
-    // be ambiguous whether it's a scalar or vector bool.
-    if (Src0.isUndef() && !MRI->getRegClassOrNull(Src0.getReg()))
-      MRI->setRegClass(Src0.getReg(), RC);
-    if (Src1.isUndef() && !MRI->getRegClassOrNull(Src1.getReg()))
-      MRI->setRegClass(Src1.getReg(), RC);
+  if (DstRB->getID() != AMDGPU::SGPRRegBankID &&
+      DstRB->getID() != AMDGPU::VCCRegBankID)
+    return false;
 
-    return RBI.constrainGenericRegister(DstReg, *RC, *MRI);
-  }
+  bool Is64 = Size > 32 || (DstRB->getID() == AMDGPU::VCCRegBankID &&
+                            STI.isWave64());
+  I.setDesc(TII.get(getLogicalBitOpcode(I.getOpcode(), Is64)));
 
-  // TODO: Should this allow an SCC bank result, and produce a copy from SCC for
-  // the result?
-  if (DstRB->getID() == AMDGPU::SGPRRegBankID) {
-    unsigned InstOpc = getLogicalBitOpcode(I.getOpcode(), Size > 32);
-    I.setDesc(TII.get(InstOpc));
-    // Dead implicit-def of scc
-    I.addOperand(MachineOperand::CreateReg(AMDGPU::SCC, true, // isDef
-                                           true, // isImp
-                                           false, // isKill
-                                           true)); // isDead
-    return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
-  }
 
-  return false;
-}
-
 bool AMDGPUInstructionSelector::selectG_ADD_SUB(MachineInstr &I) const {
   MachineBasicBlock *BB = I.getParent();
   MachineFunction *MF = BB->getParent();
   Register DstReg = I.getOperand(0).getReg();
   const DebugLoc &DL = I.getDebugLoc();
   LLT Ty = MRI->getType(DstReg);
   if (Ty.isVector())
     return false;
bool AMDGPUInstructionSelector::selectG_BRCOND(MachineInstr &I) const {
   // RegBankSelect knows what it's doing if the branch condition is scc, even
   // though it currently does not.
   if (!isVCC(CondReg, *MRI)) {
     if (MRI->getType(CondReg) != LLT::scalar(32))
       return false;
 
     CondPhysReg = AMDGPU::SCC;
     BrOpcode = AMDGPU::S_CBRANCH_SCC1;
-    // FIXME: Hack for isSCC tests
-    ConstrainRC = &AMDGPU::SGPR_32RegClass;
+    ConstrainRC = &AMDGPU::SReg_32RegClass;
   } else {
     // FIXME: Do we have to insert an and with exec here, like in SelectionDAG?
     // We sort of know that a VCC producer based on the register bank, that ands
     // inactive lanes with 0. What if there was a logical operation with vcc
     // producers in different blocks/with different exec masks?
     // FIXME: Should scc->vcc copies and with exec?
     CondPhysReg = TRI.getVCC();
     BrOpcode = AMDGPU::S_CBRANCH_VCCNZ;

llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h

public:
   void getPostRAMutations(
       std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations)
       const override;
 
   bool isWave32() const {
     return getWavefrontSize() == 32;
   }
 
+  bool isWave64() const {
+    return getWavefrontSize() == 64;
+  }
+
   const TargetRegisterClass *getBoolRC() const {
     return getRegisterInfo()->getBoolRC();
   }
 
   /// \returns Maximum number of work groups per compute unit supported by the
   /// subtarget and limited by given \p FlatWorkGroupSize.
   unsigned getMaxWorkGroupsPerCU(unsigned FlatWorkGroupSize) const override {
     return AMDGPU::IsaInfo::getMaxWorkGroupsPerCU(this, FlatWorkGroupSize);

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-brcond.mir

 
 body: |
   ; GCN-LABEL: name: brcond_scc
   ; GCN: bb.0:
   ; GCN:   successors: %bb.1(0x80000000)
   ; GCN:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
   ; GCN:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
   ; GCN:   S_CMP_EQ_U32 [[COPY]], [[COPY1]], implicit-def $scc
-  ; GCN:   [[COPY2:%[0-9]+]]:sgpr_32 = COPY $scc
+  ; GCN:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $scc
   ; GCN:   $scc = COPY [[COPY2]]
   ; GCN:   S_CBRANCH_SCC1 %bb.1, implicit $scc
   ; GCN: bb.1:
   bb.0:
     liveins: $sgpr0, $sgpr1
 
     %0:sgpr(s32) = COPY $sgpr0
     %1:sgpr(s32) = COPY $sgpr1

 name:            brcond_scc_impdef
 legalized:       true
 regBankSelected: true
 
 body: |
   ; GCN-LABEL: name: brcond_scc_impdef
   ; GCN: bb.0:
   ; GCN:   successors: %bb.1(0x80000000)
-  ; GCN:   [[DEF:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
+  ; GCN:   [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
   ; GCN:   $scc = COPY [[DEF]]
   ; GCN:   S_CBRANCH_SCC1 %bb.1, implicit $scc
   ; GCN: bb.1:
   bb.0:
     liveins: $sgpr0, $sgpr1
 
     %0:sgpr(s32) = G_IMPLICIT_DEF
     G_BRCOND %0, %bb.1

 
 body: |
   ; GCN-LABEL: name: brcond_scc_br
   ; GCN: bb.0:
   ; GCN:   successors: %bb.1(0x80000000)
   ; GCN:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
   ; GCN:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
   ; GCN:   S_CMP_EQ_U32 [[COPY]], [[COPY1]], implicit-def $scc
-  ; GCN:   [[COPY2:%[0-9]+]]:sgpr_32 = COPY $scc
+  ; GCN:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $scc
   ; GCN:   $scc = COPY [[COPY2]]
   ; GCN:   S_CBRANCH_SCC1 %bb.1, implicit $scc
   ; GCN:   S_BRANCH %bb.1
   ; GCN: bb.1:
   ; GCN:   successors: %bb.2(0x80000000)
   ; GCN: bb.2:
   bb.0:
     liveins: $sgpr0, $sgpr1

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-phi.mir

body:             |
   ; GCN: bb.0:
   ; GCN:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; GCN:   liveins: $sgpr0, $sgpr1, $sgpr2
   ; GCN:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
   ; GCN:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
   ; GCN:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
   ; GCN:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
   ; GCN:   S_CMP_EQ_U32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
-  ; GCN:   [[COPY3:%[0-9]+]]:sgpr_32 = COPY $scc
+  ; GCN:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $scc
   ; GCN:   $scc = COPY [[COPY3]]
   ; GCN:   S_CBRANCH_SCC1 %bb.1, implicit $scc
   ; GCN:   S_BRANCH %bb.2
   ; GCN: bb.1:
   ; GCN:   successors: %bb.2(0x80000000)
   ; GCN:   S_BRANCH %bb.2
   ; GCN: bb.2:
   ; GCN:   [[PHI:%[0-9]+]]:sreg_32 = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
body:             |
   ; GCN: bb.0:
   ; GCN:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; GCN:   liveins: $vgpr0, $vgpr1, $sgpr2
   ; GCN:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
   ; GCN:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
   ; GCN:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
   ; GCN:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
   ; GCN:   S_CMP_EQ_U32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
-  ; GCN:   [[COPY3:%[0-9]+]]:sgpr_32 = COPY $scc
+  ; GCN:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $scc
   ; GCN:   $scc = COPY [[COPY3]]
   ; GCN:   S_CBRANCH_SCC1 %bb.1, implicit $scc
   ; GCN:   S_BRANCH %bb.2
   ; GCN: bb.1:
   ; GCN:   successors: %bb.2(0x80000000)
   ; GCN:   [[COPY4:%[0-9]+]]:sreg_32 = COPY [[COPY1]]
   ; GCN:   S_BRANCH %bb.2
   ; GCN: bb.2:
body:             |
   ; GCN: bb.0:
   ; GCN:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; GCN:   liveins: $sgpr0, $vgpr0, $sgpr1, $sgpr2
   ; GCN:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
   ; GCN:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
   ; GCN:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
   ; GCN:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
   ; GCN:   S_CMP_EQ_U32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
-  ; GCN:   [[COPY3:%[0-9]+]]:sgpr_32 = COPY $scc
+  ; GCN:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $scc
   ; GCN:   $scc = COPY [[COPY3]]
   ; GCN:   S_CBRANCH_SCC1 %bb.1, implicit $scc
   ; GCN:   S_BRANCH %bb.2
   ; GCN: bb.1:
   ; GCN:   successors: %bb.2(0x80000000)
   ; GCN:   S_BRANCH %bb.2
   ; GCN: bb.2:
   ; GCN:   [[PHI:%[0-9]+]]:vgpr_32 = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
body:             |
   ; GCN: bb.0:
   ; GCN:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; GCN:   liveins: $sgpr0, $vgpr0, $sgpr1
   ; GCN:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
   ; GCN:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
   ; GCN:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1
   ; GCN:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
   ; GCN:   S_CMP_EQ_U32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
-  ; GCN:   [[COPY3:%[0-9]+]]:sgpr_32 = COPY $scc
+  ; GCN:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $scc
   ; GCN:   $scc = COPY [[COPY3]]
   ; GCN:   S_CBRANCH_SCC1 %bb.1, implicit $scc
   ; GCN:   S_BRANCH %bb.2
   ; GCN: bb.1:
   ; GCN:   successors: %bb.2(0x80000000)
   ; GCN:   [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]
   ; GCN:   S_BRANCH %bb.2
   ; GCN: bb.2:
body:             |
   ; GCN: bb.0:
   ; GCN:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; GCN:   liveins: $sgpr0_sgpr1, $sgpr2_sgpr3, $sgpr4
   ; GCN:   [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
   ; GCN:   [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
   ; GCN:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4
   ; GCN:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
   ; GCN:   S_CMP_EQ_U32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
-  ; GCN:   [[COPY3:%[0-9]+]]:sgpr_32 = COPY $scc
+  ; GCN:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $scc
   ; GCN:   $scc = COPY [[COPY3]]
   ; GCN:   S_CBRANCH_SCC1 %bb.1, implicit $scc
   ; GCN:   S_BRANCH %bb.2
   ; GCN: bb.1:
   ; GCN:   successors: %bb.2(0x80000000)
   ; GCN:   S_BRANCH %bb.2
   ; GCN: bb.2:
   ; GCN:   [[PHI:%[0-9]+]]:sreg_64 = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
body:             |
   ; GCN: bb.0:
   ; GCN:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; GCN:   liveins: $vgpr0, $vgpr1, $sgpr2
   ; GCN:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
   ; GCN:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
   ; GCN:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
   ; GCN:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
   ; GCN:   S_CMP_EQ_U32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
-  ; GCN:   [[COPY3:%[0-9]+]]:sgpr_32 = COPY $scc
+  ; GCN:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $scc
   ; GCN:   $scc = COPY [[COPY3]]
   ; GCN:   S_CBRANCH_SCC1 %bb.1, implicit $scc
   ; GCN:   S_BRANCH %bb.2
   ; GCN: bb.1:
   ; GCN:   successors: %bb.2(0x80000000)
   ; GCN:   [[COPY4:%[0-9]+]]:sreg_32 = COPY [[COPY1]]
   ; GCN:   S_BRANCH %bb.2
   ; GCN: bb.2:
body:             |
   ; GCN:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; GCN:   liveins: $vgpr0, $vgpr1, $sgpr2
   ; GCN:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
   ; GCN:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
   ; GCN:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
   ; GCN:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
   ; GCN:   [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 [[COPY]], [[S_MOV_B32_]], implicit $exec
   ; GCN:   S_CMP_EQ_U32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
-  ; GCN:   [[COPY3:%[0-9]+]]:sgpr_32 = COPY $scc
+  ; GCN:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $scc
   ; GCN:   $scc = COPY [[COPY3]]
   ; GCN:   S_CBRANCH_SCC1 %bb.1, implicit $scc
   ; GCN:   S_BRANCH %bb.2
   ; GCN: bb.1:
   ; GCN:   successors: %bb.2(0x80000000)
   ; GCN:   [[V_CMP_EQ_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 [[COPY1]], [[S_MOV_B32_]], implicit $exec
   ; GCN:   S_BRANCH %bb.2
   ; GCN: bb.2:
body:             |
   ; GCN: bb.0:
   ; GCN:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; GCN:   liveins: $sgpr0, $sgpr1, $sgpr2
   ; GCN:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
   ; GCN:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
   ; GCN:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
   ; GCN:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
   ; GCN:   S_CMP_EQ_U32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
-  ; GCN:   [[COPY3:%[0-9]+]]:sgpr_32 = COPY $scc
+  ; GCN:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $scc
   ; GCN:   $scc = COPY [[COPY3]]
   ; GCN:   S_CBRANCH_SCC1 %bb.1, implicit $scc
   ; GCN:   S_BRANCH %bb.2
   ; GCN: bb.1:
   ; GCN:   successors: %bb.2(0x80000000)
   ; GCN:   S_BRANCH %bb.2
   ; GCN: bb.2:
   ; GCN:   [[PHI:%[0-9]+]]:sreg_32 = PHI [[COPY]], %bb.0, [[COPY1]], %bb.1
body:             |
   ; GCN: bb.0:
   ; GCN:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; GCN:   liveins: $vgpr0, $vgpr1, $sgpr2
   ; GCN:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
   ; GCN:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
   ; GCN:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
   ; GCN:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
   ; GCN:   S_CMP_EQ_U32 [[COPY2]], [[S_MOV_B32_]], implicit-def $scc
-  ; GCN:   [[COPY3:%[0-9]+]]:sgpr_32 = COPY $scc
+  ; GCN:   [[COPY3:%[0-9]+]]:sreg_32 = COPY $scc
   ; GCN:   $scc = COPY [[COPY3]]
   ; GCN:   S_CBRANCH_SCC1 %bb.1, implicit $scc
   ; GCN:   S_BRANCH %bb.2
   ; GCN: bb.1:
   ; GCN:   successors: %bb.2(0x80000000)
   ; GCN:   [[COPY4:%[0-9]+]]:sreg_32 = COPY [[COPY1]]
   ; GCN:   S_BRANCH %bb.2
   ; GCN: bb.2: