Prefix some AArch64/ARM passes with "aarch64-"/"arm-"

[aeubanks]

Summary

For consistency with other target specific passes.

[arsenm]

Target passes should probably all have target prefixes

llvm/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp

 #include "llvm/Support/DebugCounter.h"
 #include "llvm/Support/raw_ostream.h"
 #include <cassert>
 #include <iterator>
 #include <utility>
 
 using namespace llvm;
 
-#define DEBUG_TYPE "falkor-hwpf-fix"
+#define DEBUG_TYPE "aarch64-falkor-hwpf-fix"
 
 STATISTIC(NumStridedLoadsMarked, "Number of strided loads marked");
 STATISTIC(NumCollisionsAvoided,
           "Number of HW prefetch tag collisions avoided");
 STATISTIC(NumCollisionsNotAvoided,
           "Number of HW prefetch tag collisions not avoided due to lack of registers");
 DEBUG_COUNTER(FixCounter, "falkor-hwpf",
               "Controls which tag collisions are avoided");
struct LoadInfo {
   const MachineOperand *OffsetOpnd = nullptr;
   bool IsPrePost = false;
 };
 
 } // end anonymous namespace
 
 char FalkorHWPFFix::ID = 0;
 
-INITIALIZE_PASS_BEGIN(FalkorHWPFFix, "falkor-hwpf-fix-late",
+INITIALIZE_PASS_BEGIN(FalkorHWPFFix, "aarch64-falkor-hwpf-fix-late",
                       "Falkor HW Prefetch Fix Late Phase", false, false)
 INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
-INITIALIZE_PASS_END(FalkorHWPFFix, "falkor-hwpf-fix-late",
+INITIALIZE_PASS_END(FalkorHWPFFix, "aarch64-falkor-hwpf-fix-late",
                     "Falkor HW Prefetch Fix Late Phase", false, false)
 
 static unsigned makeTag(unsigned Dest, unsigned Base, unsigned Offset) {
   return (Dest & 0xf) | ((Base & 0xf) << 4) | ((Offset & 0x3f) << 8);
 }
 
 static Optional<LoadInfo> getLoadInfo(const MachineInstr &MI) {
   int DestRegIdx;

llvm/lib/Target/AArch64/AArch64StackTagging.cpp

 #include "llvm/Support/raw_ostream.h"
 #include "llvm/Transforms/Utils/Local.h"
 #include <cassert>
 #include <iterator>
 #include <utility>
 
 using namespace llvm;
 
-#define DEBUG_TYPE "stack-tagging"
+#define DEBUG_TYPE "aarch64-stack-tagging"
 
 static cl::opt<bool> ClMergeInit(
     "stack-tagging-merge-init", cl::Hidden, cl::init(true), cl::ZeroOrMore,
     cl::desc("merge stack variable initializers with tagging when possible"));
 
 static cl::opt<bool>
     ClUseStackSafety("stack-tagging-use-stack-safety", cl::Hidden,
                      cl::init(true), cl::ZeroOrMore,

llvm/lib/Target/AArch64/AArch64TargetMachine.cpp

EnableLoopDataPrefetch("aarch64-enable-loop-data-prefetch", cl::Hidden,
                            cl::desc("Enable the loop data prefetch pass"),
                            cl::init(true));
 
 static cl::opt<int> EnableGlobalISelAtO(
     "aarch64-enable-global-isel-at-O", cl::Hidden,
     cl::desc("Enable GlobalISel at or below an opt level (-1 to disable)"),
     cl::init(0));
 
-static cl::opt<bool> EnableSVEIntrinsicOpts(
-    "aarch64-sve-intrinsic-opts", cl::Hidden,
+static cl::opt<bool>
+    EnableSVEIntrinsicOpts("aarch64-enable-sve-intrinsic-opts", cl::Hidden,
                            cl::desc("Enable SVE intrinsic opts"),
                            cl::init(true));
 
 static cl::opt<bool> EnableFalkorHWPFFix("aarch64-enable-falkor-hwpf-fix",
                                          cl::init(true), cl::Hidden);
 
 static cl::opt<bool>
     EnableBranchTargets("aarch64-enable-branch-targets", cl::Hidden,
                         cl::desc("Enable the AAcrh64 branch target pass"),
                         cl::init(true));

llvm/lib/Target/AArch64/SVEIntrinsicOpts.cpp

 #include "llvm/IR/LLVMContext.h"
 #include "llvm/IR/PatternMatch.h"
 #include "llvm/InitializePasses.h"
 #include "llvm/Support/Debug.h"
 
 using namespace llvm;
 using namespace llvm::PatternMatch;
 
-#define DEBUG_TYPE "sve-intrinsic-opts"
+#define DEBUG_TYPE "aarch64-sve-intrinsic-opts"
 
 namespace llvm {
 void initializeSVEIntrinsicOptsPass(PassRegistry &);
 }
 
 namespace {
 struct SVEIntrinsicOpts : public ModulePass {
   static char ID; // Pass identification, replacement for typeid

llvm/lib/Target/ARM/MVEGatherScatterLowering.cpp

 #include "llvm/Pass.h"
 #include "llvm/Support/Casting.h"
 #include "llvm/Transforms/Utils/Local.h"
 #include <algorithm>
 #include <cassert>
 
 using namespace llvm;
 
-#define DEBUG_TYPE "mve-gather-scatter-lowering"
+#define DEBUG_TYPE "arm-mve-gather-scatter-lowering"
 
 cl::opt<bool> EnableMaskedGatherScatters(
     "enable-arm-maskedgatscat", cl::Hidden, cl::init(false),
     cl::desc("Enable the generation of masked gathers and scatters"));
 
 namespace {
 
 class MVEGatherScatterLowering : public FunctionPass {

llvm/test/CodeGen/AArch64/falkor-hwpf-fix.mir

-# RUN: llc -mtriple=aarch64-linux-gnu -mcpu=falkor -run-pass falkor-hwpf-fix-late -o - %s | FileCheck %s
+# RUN: llc -mtriple=aarch64-linux-gnu -mcpu=falkor -run-pass aarch64-falkor-hwpf-fix-late -o - %s | FileCheck %s
 ---
 # Verify that the tag collision between the loads is resolved for various load opcodes.
 
 # CHECK-LABEL: name: hwpf1
 # CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 0
 # CHECK: LDRWui $[[BASE]], 0
 # CHECK: LDRWui $x1, 1
 name:            hwpf1

llvm/test/CodeGen/AArch64/falkor-hwpf.ll

-; RUN: opt < %s -S -falkor-hwpf-fix -mtriple aarch64 -mcpu=falkor | FileCheck %s
-; RUN: opt < %s -S -falkor-hwpf-fix -mtriple aarch64 -mcpu=cortex-a57 | FileCheck %s --check-prefix=NOHWPF
+; RUN: opt < %s -S -aarch64-falkor-hwpf-fix -mtriple aarch64 -mcpu=falkor | FileCheck %s
+; RUN: opt < %s -S -aarch64-falkor-hwpf-fix -mtriple aarch64 -mcpu=cortex-a57 | FileCheck %s --check-prefix=NOHWPF
 
 ; Check that strided access metadata is added to loads in inner loops when compiling for Falkor.
 
 ; CHECK-LABEL: @hwpf1(
 ; CHECK: load i32, i32* %gep, align 4, !falkor.strided.access !0
 ; CHECK: load i32, i32* %gep2, align 4, !falkor.strided.access !0
 
 ; NOHWPF-LABEL: @hwpf1(

llvm/test/CodeGen/AArch64/stack-tagging-dbg.ll

-; RUN: opt < %s -stack-tagging -S -o - | FileCheck %s
+; RUN: opt < %s -aarch64-stack-tagging -S -o - | FileCheck %s
 
 target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
 target triple = "aarch64--linux-android"
 
 declare void @use32(i32*)
 declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone speculatable
 
 ; Debug intrinsics use the new alloca directly, not through a GEP or a tagp.

llvm/test/CodeGen/AArch64/stack-tagging-ex-1.ll

-; RUN: opt -S -stack-tagging %s -o - | FileCheck %s
+; RUN: opt -S -aarch64-stack-tagging %s -o - | FileCheck %s
 
 target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
 target triple = "aarch64-arm-unknown-eabi"
 
 define  void @f() local_unnamed_addr #0 personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
 start:
 ; CHECK-LABEL: start:
   %a = alloca i8, i32 48, align 8

llvm/test/CodeGen/AArch64/stack-tagging-ex-2.ll

 ;   try {
 ;     foo();
 ;   } catch (int exc) {
 ;   }
 
 ;   return 0;
 ; }
 
-; RUN: opt -S -stack-tagging %s -o - | FileCheck %s
+; RUN: opt -S -aarch64-stack-tagging %s -o - | FileCheck %s
 
 target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
 target triple = "aarch64-unknown-unknown-eabi"
 
 @_ZTIi = external dso_local constant i8*
 
 ; Function Attrs: noreturn sanitize_memtag
 define dso_local void @_Z3barv() local_unnamed_addr #0 {

llvm/test/CodeGen/AArch64/stack-tagging-initializer-merge.ll

-; RUN: opt < %s -stack-tagging -S -o - | FileCheck %s
+; RUN: opt < %s -aarch64-stack-tagging -S -o - | FileCheck %s
 
 target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
 target triple = "aarch64--linux-android"
 
 declare void @use(i8*)
 declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture)
 declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture)
 declare void @llvm.memset.p0i8.i64(i8* nocapture writeonly, i8, i64, i1 immarg)

llvm/test/CodeGen/AArch64/stack-tagging-untag-placement.ll

-;; RUN:  opt -S -stack-tagging %s -o - | FileCheck %s
+;; RUN:  opt -S -aarch64-stack-tagging %s -o - | FileCheck %s
 target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
 target triple = "aarch64-arm-unknown-eabi"
 
 define void @f() local_unnamed_addr #0  {
 S0:
 ; CHECK-LABEL: S0:
 ; CHECK: %basetag = call i8* @llvm.aarch64.irg.sp(i64 0)
   %v = alloca i8, i32 48, align 8

llvm/test/CodeGen/AArch64/stack-tagging.ll

-; RUN: opt < %s -stack-tagging -S -o - | FileCheck %s --check-prefixes=CHECK,SSI
-; RUN: opt < %s -stack-tagging -stack-tagging-use-stack-safety=0 -S -o - | FileCheck %s --check-prefixes=CHECK,NOSSI
+; RUN: opt < %s -aarch64-stack-tagging -S -o - | FileCheck %s --check-prefixes=CHECK,SSI
+; RUN: opt < %s -aarch64-stack-tagging -stack-tagging-use-stack-safety=0 -S -o - | FileCheck %s --check-prefixes=CHECK,NOSSI
 
 target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
 target triple = "aarch64--linux-android"
 
 declare void @use8(i8*)
 declare void @use32(i32*)
 declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture)
 declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture)

 ; CHECK: store i32
 ; CHECK: call void @noUse32(i32*
 ; CHECK: call void @llvm.aarch64.settag(
 ; CHECK: call void @llvm.aarch64.settag(
 ; NOSSI: call void @llvm.aarch64.settag(
 ; CHECK: ret void
 
 !0 = !{}
 No newline at end of file

llvm/test/CodeGen/AArch64/sve-intrinsic-opts-ptest.ll

-; RUN: opt -S -sve-intrinsic-opts -mtriple=aarch64-linux-gnu -mattr=+sve < %s 2>%t | FileCheck --check-prefix OPT %s
+; RUN: opt -S -aarch64-sve-intrinsic-opts -mtriple=aarch64-linux-gnu -mattr=+sve < %s 2>%t | FileCheck --check-prefix OPT %s
 ; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
 
 ; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
 ; WARN-NOT: warning
 
 define i1 @ptest_any1(<vscale x 2 x i1> %a) {
 ; OPT-LABEL: ptest_any1
 ; OPT: %mask = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 0)

llvm/test/CodeGen/AArch64/sve-intrinsic-opts-reinterpret.ll

-; RUN: opt -S -sve-intrinsic-opts -mtriple=aarch64-linux-gnu -mattr=+sve < %s 2>%t | FileCheck --check-prefix OPT %s
+; RUN: opt -S -aarch64-sve-intrinsic-opts -mtriple=aarch64-linux-gnu -mattr=+sve < %s 2>%t | FileCheck --check-prefix OPT %s
 ; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
 
 ; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
 ; WARN-NOT: warning
 
 define <vscale x 8 x i1> @reinterpret_test_h(<vscale x 8 x i1> %a) {
 ; OPT-LABEL: @reinterpret_test_h(
 ; OPT-NOT: convert

llvm/test/CodeGen/Thumb2/mve-gather-optimisation-deep.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 
 
-; RUN: opt --mve-gather-scatter-lowering -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -enable-arm-maskedgatscat %s -S -o 2>/dev/null - | FileCheck %s
+; RUN: opt --arm-mve-gather-scatter-lowering -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -enable-arm-maskedgatscat %s -S -o 2>/dev/null - | FileCheck %s
 
 define arm_aapcs_vfpcc void @push_out_add_sub_block(i32* noalias nocapture readonly %data, i32* noalias nocapture %dst, i32 %n.vec) {
 ; CHECK-LABEL: @push_out_add_sub_block(
 ; CHECK-NEXT:  vector.ph:
 ; CHECK-NEXT:    [[IND_END:%.*]] = shl i32 [[N_VEC:%.*]], 1
 ; CHECK-NEXT:    [[PUSHEDOUTADD:%.*]] = add <4 x i32> <i32 0, i32 2, i32 4, i32 6>, <i32 6, i32 6, i32 6, i32 6>
 ; CHECK-NEXT:    br label [[VECTOR_BODY:%.*]]
 ; CHECK:       vector.body: