[XCOFF][AIX] Support relocation generation for large code model

[jasonliu]

Summary

Support TOCU and TOCL relocation type for object file generation.

[jasonliu]

llvm/test/CodeGen/PowerPC/aix-xcoff-reloc-large.ll

75

Notice when D85455 lands, this would be a[TE] instead of a[TC].
Depending on which patch lands first, and I will rebase the other dependant patch (as it's a simple rebasing and shouldn't affect the review too much).

[jasonliu]

Rebase on lastest master to resolve potential merge conflict.

[DiggerLin]

llvm/lib/MC/XCOFFObjectWriter.cpp

432

I just wonder why there is no Type == XCOFF::RelocationType::R_TOCU ? we do not need to applyFixup for the instruction ?
addis 3, L..C0@u(2) ?

434

I am not sure whether I understand is correct or not ?
FixedValue of intructions
addis 3, L..C0@u(2) . FixedValue should get the high 16bits of SectionMap[SymASec]->Address - TOCCsects.front().Address;

lwz 3, L..C0@l(3) FixedValue should get the low 16bits of SectionMap[SymASec]->Address - TOCCsects.front().Address;

if I understand correct , the code need to change.

[jasonliu]

llvm/lib/MC/XCOFFObjectWriter.cpp

434

Could you give an example that would generated non-0 FixedValue in TOCU position?
The example (the test case I have below) I tried before, TOCU position always have 0 as its FixedValue with system assembler generated object.

[DiggerLin]

llvm/lib/MC/XCOFFObjectWriter.cpp

434

1ae98: 3c 62 00 01                   addis 3, 2, 1
                        0001ae9a:  R_TOCU       (idx: 36364) a10995[TE]
   1ae9c: 80 63 8d f8                   lwz 3, -29192(3)
                        0001ae9e:  R_TOCL       (idx: 36364) a10995[TE]
   1aea0: 90 83 00 00                   stw 4, 0(3)
   1aea4: 3c 62 00 01                   addis 3, 2, 1
                        0001aea6:  R_TOCU       (idx: 36366) a10996[TE]
   1aea8: 80 63 8d fc                   lwz 3, -29188(3)
                        0001aeaa:  R_TOCL       (idx: 36366) a10996[TE]
   1aeac: 90 83 00 00                   stw 4, 0(3)
   1aeb0: 3c 62 00 01                   addis 3, 2, 1

[jasonliu]

llvm/lib/MC/XCOFFObjectWriter.cpp

434

It seems the system as would generate a non-0 FixedValue for you when your TOC region is larger than 64KB.
But xlclang (which do not use system as to generate object) would always generate 0 for the TOCU region, and linker would know how to change the fix-up '0' to the proper value that points to the correct TOC entry.

[jasonliu]

Report fatal error when we know the initial 64kb TOC region is not enough to contain all the TOC entries.

[jasonliu]

llvm/lib/MC/XCOFFObjectWriter.cpp

434

Some update on this:
I talked with people from AIX OS team, and it seems indeed what we put in the TOCU's fix-up region does not matter for the linker.
But aside from that, I think our current logic for TOCL region might not work well when we overflow the initial TOC region, because we might need to wrap around the value in that case. For example, we would need to put 0 in TOCL region when it's the first TOC entry in the second TOC region.
And since we are not able to produce that case yet (we have a report_fatal_error somewhere else that would get triggered before this one because we haven't figured out a plan on how to deal with "minus" offset TOC entries in small code model mode.), I will report a fatal error here as well to remind us when we run into this issue in the future.

[DiggerLin]

LGTM

llvm/test/CodeGen/PowerPC/aix-xcoff-reloc-large.ll

2

minor: do we need -verify-machineinstrs here ?

[jasonliu]

llvm/test/CodeGen/PowerPC/aix-xcoff-reloc-large.ll

2

I think it's good to always verify if the machine instruction generated during the obj gen process are valid.
It doesn't really hurt to add it in.

llvm/lib/MC/XCOFFObjectWriter.cpp

CsectGroup &XCOFFObjectWriter::getCsectGroup(const MCSectionXCOFF *MCSec) {
   case XCOFF::XMC_TC0:
     assert(XCOFF::XTY_SD == MCSec->getCSectType() &&
            "Only an initialized csect can contain TOC-base.");
     assert(TOCCsects.empty() &&
            "We should have only one TOC-base, and it should be the first csect "
            "in this CsectGroup.");
     return TOCCsects;
   case XCOFF::XMC_TC:
+  case XCOFF::XMC_TE:
     assert(XCOFF::XTY_SD == MCSec->getCSectType() &&
            "Only an initialized csect can contain TC entry.");
     assert(!TOCCsects.empty() &&
            "We should at least have a TOC-base in this CsectGroup.");
     return TOCCsects;
   default:
     report_fatal_error("Unhandled mapping of csect to section.");
   }
void XCOFFObjectWriter::recordRelocation(MCAssembler &Asm,
   assert(SectionMap.find(SymASec) != SectionMap.end() &&
          "Expected containing csect to exist in map.");
 
   const uint32_t Index = getIndex(SymA, SymASec);
   if (Type == XCOFF::RelocationType::R_POS)
     // The FixedValue should be symbol's virtual address in this object file
     // plus any constant value that we might get.
     FixedValue = getVirtualAddress(SymA, SymASec) + Target.getConstant();
-  else if (Type == XCOFF::RelocationType::R_TOC)
+  else if (Type == XCOFF::RelocationType::R_TOC ||
+           Type == XCOFF::RelocationType::R_TOCL)
     // The FixedValue should be the TC entry offset from TOC-base.
     FixedValue = SectionMap[SymASec]->Address - TOCCsects.front().Address;
 
   assert(
       (TargetObjectWriter->is64Bit() ||
        Fixup.getOffset() <= UINT32_MAX - Layout.getFragmentOffset(Fragment)) &&
       "Fragment offset + fixup offset is overflowed in 32-bit mode.");
   uint32_t FixupOffsetInCsect =
       Layout.getFragmentOffset(Fragment) + Fixup.getOffset();
 

llvm/lib/Target/PowerPC/MCTargetDesc/PPCXCOFFObjectWriter.cpp

std::pair<uint8_t, uint8_t> PPCXCOFFObjectWriter::getRelocTypeAndSignSize(
 
   // The magic number we use in SignAndSize has a strong relationship with
   // the corresponding MCFixupKind. In most cases, it's the MCFixupKind
   // number - 1, because SignAndSize encodes the bit length being
   // relocated minus 1.
   switch ((unsigned)Fixup.getKind()) {
   default:
     report_fatal_error("Unimplemented fixup kind.");
-  case PPC::fixup_ppc_half16:
+  case PPC::fixup_ppc_half16: {
+    const uint8_t SignAndSizeForHalf16 = EncodedSignednessIndicator | 15;
     switch (Modifier) {
     default:
       report_fatal_error("Unsupported modifier for half16 fixup.");
     case MCSymbolRefExpr::VK_None:
-      return {XCOFF::RelocationType::R_TOC, EncodedSignednessIndicator | 15};
+      return {XCOFF::RelocationType::R_TOC, SignAndSizeForHalf16};
+    case MCSymbolRefExpr::VK_PPC_U:
+      return {XCOFF::RelocationType::R_TOCU, SignAndSizeForHalf16};
+    case MCSymbolRefExpr::VK_PPC_L:
+      return {XCOFF::RelocationType::R_TOCL, SignAndSizeForHalf16};
     }
-    break;
+  } break;
   case PPC::fixup_ppc_br24:
     // Branches are 4 byte aligned, so the 24 bits we encode in
     // the instruction actually represents a 26 bit offset.
     return {XCOFF::RelocationType::R_RBR, EncodedSignednessIndicator | 25};
   case FK_Data_4:
     return {XCOFF::RelocationType::R_POS, EncodedSignednessIndicator | 31};
   }
 }

llvm/test/CodeGen/PowerPC/aix-xcoff-reloc-large.ll

+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff \
+; RUN:     -filetype=obj -code-model=large -o %t.o < %s
+; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck --check-prefixes=RELOC %s
+; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck --check-prefix=DIS %s
+
+@a = global i32 2, align 4
+@b = global i32 10, align 4
+@c = global i32 11, align 4
+
+define i32 @foo() {
+entry:
+  %0 = load i32, i32* @a, align 4
+  %1 = load i32, i32* @b, align 4
+  %add = add nsw i32 %0, %1
+  %2 = load i32, i32* @c, align 4
+  %add1 = add nsw i32 %add, %2
+  ret i32 %add1
+}
+
+; RELOC:        Section (index: {{[0-9]+}}) .text {
+; RELOC-NEXT:   Relocation {
+; RELOC-NEXT:     Virtual Address: 0x2
+; RELOC-NEXT:     Symbol: a ([[#INDX:]])
+; RELOC-NEXT:     IsSigned: No
+; RELOC-NEXT:     FixupBitValue: 0
+; RELOC-NEXT:     Length: 16
+; RELOC-NEXT:     Type: R_TOCU (0x30)
+; RELOC-NEXT:   }
+; RELOC-NEXT:   Relocation {
+; RELOC-NEXT:     Virtual Address: 0x6
+; RELOC-NEXT:     Symbol: a ([[#INDX]])
+; RELOC-NEXT:     IsSigned: No
+; RELOC-NEXT:     FixupBitValue: 0
+; RELOC-NEXT:     Length: 16
+; RELOC-NEXT:     Type: R_TOCL (0x31)
+; RELOC-NEXT:   }
+; RELOC-NEXT:   Relocation {
+; RELOC-NEXT:     Virtual Address: 0xE
+; RELOC-NEXT:     Symbol: b ([[#INDX+2]])
+; RELOC-NEXT:     IsSigned: No
+; RELOC-NEXT:     FixupBitValue: 0
+; RELOC-NEXT:     Length: 16
+; RELOC-NEXT:     Type: R_TOCU (0x30)
+; RELOC-NEXT:   }
+; RELOC-NEXT:   Relocation {
+; RELOC-NEXT:     Virtual Address: 0x12
+; RELOC-NEXT:     Symbol: b ([[#INDX+2]])
+; RELOC-NEXT:     IsSigned: No
+; RELOC-NEXT:     FixupBitValue: 0
+; RELOC-NEXT:     Length: 16
+; RELOC-NEXT:     Type: R_TOCL (0x31)
+; RELOC-NEXT:   }
+; RELOC-NEXT:   Relocation {
+; RELOC-NEXT:     Virtual Address: 0x1A
+; RELOC-NEXT:     Symbol: c ([[#INDX+4]])
+; RELOC-NEXT:     IsSigned: No
+; RELOC-NEXT:     FixupBitValue: 0
+; RELOC-NEXT:     Length: 16
+; RELOC-NEXT:     Type: R_TOCU (0x30)
+; RELOC-NEXT:   }
+; RELOC-NEXT:   Relocation {
+; RELOC-NEXT:     Virtual Address: 0x1E
+; RELOC-NEXT:     Symbol: c ([[#INDX+4]])
+; RELOC-NEXT:     IsSigned: No
+; RELOC-NEXT:     FixupBitValue: 0
+; RELOC-NEXT:     Length: 16
+; RELOC-NEXT:     Type: R_TOCL (0x31)
+; RELOC-NEXT:   }
+
+; DIS:        Disassembly of section .text:
+; DIS-EMPTY:   
+; DIS-NEXT:   00000000 (idx: {{[0-9]+}}) .foo:
+; DIS-NEXT:          0: 3c 62 00 00   addis 3, 2, 0
+; DIS-NEXT:                           00000002:  R_TOCU       (idx: [[#INDX:]]) a[TE]
+; DIS-NEXT:          4: 80 63 00 00   lwz 3, 0(3)
+; DIS-NEXT:                           00000006:  R_TOCL       (idx: [[#INDX]]) a[TE]
+; DIS-NEXT:          8: 80 63 00 00   lwz 3, 0(3)
+; DIS-NEXT:          c: 3c 82 00 00   addis 4, 2, 0
+; DIS-NEXT:                           0000000e:  R_TOCU       (idx: [[#INDX+2]]) b[TE]
+; DIS-NEXT:         10: 80 84 00 04   lwz 4, 4(4)
+; DIS-NEXT:                           00000012:  R_TOCL       (idx: [[#INDX+2]]) b[TE]
+; DIS-NEXT:         14: 80 84 00 00   lwz 4, 0(4)
+; DIS-NEXT:         18: 3c a2 00 00   addis 5, 2, 0
+; DIS-NEXT:                           0000001a:  R_TOCU       (idx: [[#INDX+4]]) c[TE]
+; DIS-NEXT:         1c: 80 a5 00 08   lwz 5, 8(5)
+; DIS-NEXT:                           0000001e:  R_TOCL       (idx: [[#INDX+4]]) c[TE]
+; DIS-NEXT:         20: 7c 63 22 14   add 3, 3, 4
+; DIS-NEXT:         24: 80 a5 00 00   lwz 5, 0(5)
+; DIS-NEXT:         28: 7c 63 2a 14   add 3, 3, 5
+; DIS-NEXT:         2c: 4e 80 00 20   blr