[X86] Change the tuning settings for pentium4 to be more modern since its the default 32-bit cpu in clang

[craig.topper]

Summary

Alternative to D83897. I believe the big change here is that I removed slow unaligned memory 16

Down side that it may adversely effect tuning if someone explicitly targets -march=pentium4 and expects pentium4 tuned code. Of course pentium4 is so old our default behavior with the previous settings may not have been the best either.

[echristo]

LGTM.

[MaskRay]

llvm/lib/Target/X86/X86.td

1080

Typo?

[craig.topper]

I'll probably wait a day to see if @RKSimon or @spatel have any opinion

llvm/lib/Target/X86/X86.td

1080

thanks. I'll fix it before I commit.

[RKSimon]

LGTM - no objections, I don't think we have much that specifically targets optimal codegen on p4 - a few of the TTI costs and thats about it.

llvm/lib/Target/X86/X86.td

1078

Remove this?

[spatel]

I don't object, but this is less sustainable than adding a generic 32-bit model to match the generic 64-bit model (the alternate D83897 patch IIUC).

Maybe out-of-scope for this patch, but there's a bigger problem in that (AFAIK), we have no plan for updating the generic tuning. Ie, the 64-bit generic model was created 6 years ago and grows less relevant daily:

// We currently use the Sandy Bridge model as the default scheduling model as
// we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which
// covers a huge swath of x86 processors.

Should we create some metrics based on time or popularity that guide us on updating that? For example, are we stuck assuming SSE2-only for the generic model forever, or can we decide that 12+ years past the introduction of SSE4.1 lets us assume that is available/preferred?

[craig.topper]

In D83913#2155628, @spatel wrote:

I don't object, but this is less sustainable than adding a generic 32-bit model to match the generic 64-bit model (the alternate D83897 patch IIUC).

The "x86-64" CPU has existed for longer than 6 years. It was originally created to be the common subset between "nocona" and "k8" to be a good default CPU for any 64-bit system. It's missing cmpxchg16b for example. It picked up the generic tuning 6 years ago. But it should really have tuning for something closer to nocona/k8. If we had true mtune support, -mtune=x86-64 would tune for k8/nocona. At I think that's how it works in gcc.

Maybe out-of-scope for this patch, but there's a bigger problem in that (AFAIK), we have no plan for updating the generic tuning. Ie, the 64-bit generic model was created 6 years ago and grows less relevant daily:

// We currently use the Sandy Bridge model as the default scheduling model as
// we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which
// covers a huge swath of x86 processors.

Should we create some metrics based on time or popularity that guide us on updating that? For example, are we stuck assuming SSE2-only for the generic model forever, or can we decide that 12+ years past the introduction of SSE4.1 lets us assume that is available/preferred?

llvm/lib/Target/X86/X86.td

 // changes slightly.
 
 def : ProcessorModel<"pentium-m", GenericPostRAModel,
                      [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
                       FeatureMMX, FeatureSSE2, FeatureFXSR, FeatureNOPL,
                       FeatureCMOV, FeatureInsertVZEROUPPER]>;
 
 foreach P = ["pentium4", "pentium4m"] in {
+//  def : ProcessorModel<P, GenericPostRAModel,
+//                       [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
+//                        FeatureMMX, FeatureSSE2, FeatureFXSR, FeatureNOPL,
+//                        FeatureCMOV, FeatureInsertVZEROUPPER]>;
+
+  // Since 'pentium4' is the default 32-bit CPU on Linux and Windows,
+  // give it more modern tunings.
+  // FIXME: This wouldn't be needed if we supported mtune.
   def : ProcessorModel<P, GenericPostRAModel,
-                       [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
+                       [FeatureX87, FeatureCMPXCHG8B,
                         FeatureMMX, FeatureSSE2, FeatureFXSR, FeatureNOPL,
-                        FeatureCMOV, FeatureInsertVZEROUPPER]>;
+                        FeatureCMOV, FeatureInsertVZEROUPPER,
+                        FeatureSlow3OpsLEA, FeatureSlowDivide64,
+                        FeatureSlowIncDec, FeatureMacroFusion]>;
 }
 
 // Intel Quark.
 def : Proc<"lakemont",        [FeatureInsertVZEROUPPER]>;
 
 // Intel Core Duo.
 def : ProcessorModel<"yonah", SandyBridgeModel,
                      [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,

llvm/test/CodeGen/X86/cfguard-x86-vectorcall.ll

entry:
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 %3, i8* align 8 %4, i32 32, i1 false)
   %5 = load %struct.HVA, %struct.HVA* %2, align 8
   call x86_vectorcallcc void %0(%struct.HVA inreg %5)
   ret void
 
   ; X32-LABEL: func_cf_vector_x86
   ; X32:       movl 12(%ebp), %eax
   ; X32:       movl 8(%ebp), %ecx
-  ; X32:       movsd 24(%eax), %xmm4         # xmm4 = mem[0],zero
-  ; X32:       movsd %xmm4, 24(%esp)
-  ; X32:       movsd 16(%eax), %xmm5         # xmm5 = mem[0],zero
-  ; X32:       movsd %xmm5, 16(%esp)
-  ; X32:       movsd (%eax), %xmm6           # xmm6 = mem[0],zero
-  ; X32:       movsd 8(%eax), %xmm7          # xmm7 = mem[0],zero
-  ; X32:       movsd %xmm7, 8(%esp)
-  ; X32:       movsd %xmm6, (%esp)
+  ; X32:       movups (%eax), %xmm0
+  ; X32:       movups 16(%eax), %xmm1
+  ; X32:       movaps %xmm0, (%esp)
+  ; X32:       movaps %xmm1, 16(%esp)
+  ; X32:       movsd  (%esp), %xmm4
+  ; X32:       movsd  8(%esp), %xmm5
+  ; X32:       movsd  16(%esp), %xmm6
+  ; X32:       movsd  24(%esp), %xmm7
   ; X32:       calll *___guard_check_icall_fptr
-  ; X32:       movaps %xmm6, %xmm0
-  ; X32:       movaps %xmm7, %xmm1
-  ; X32:       movaps %xmm5, %xmm2
-  ; X32:       movaps %xmm4, %xmm3
+  ; X32:       movaps %xmm4, %xmm0
+  ; X32:       movaps %xmm5, %xmm1
+  ; X32:       movaps %xmm6, %xmm2
+  ; X32:       movaps %xmm7, %xmm3
   ; X32:       calll  *%ecx
 }
 attributes #0 = { "target-cpu"="pentium4" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" }
 
 %struct.HVA = type { double, double, double, double }
 
 declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture writeonly, i8* nocapture readonly, i32, i1 immarg) #1
 attributes #1 = { argmemonly nounwind willreturn }
 
 
 !llvm.module.flags = !{!0}
 !0 = !{i32 2, !"cfguard", i32 2}

llvm/test/CodeGen/X86/slow-unaligned-mem.ll

 ; Intel chips with slow unaligned memory accesses
 
 ; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=pentium3      2>&1 | FileCheck %s --check-prefix=SLOW
 ; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=pentium3m     2>&1 | FileCheck %s --check-prefix=SLOW
 ; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=pentium-m     2>&1 | FileCheck %s --check-prefix=SLOW
-; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=pentium4      2>&1 | FileCheck %s --check-prefix=SLOW
-; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=pentium4m     2>&1 | FileCheck %s --check-prefix=SLOW
 ; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=yonah         2>&1 | FileCheck %s --check-prefix=SLOW
 ; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=prescott      2>&1 | FileCheck %s --check-prefix=SLOW
 ; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=nocona        2>&1 | FileCheck %s --check-prefix=SLOW
 ; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=core2         2>&1 | FileCheck %s --check-prefix=SLOW
 ; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=penryn        2>&1 | FileCheck %s --check-prefix=SLOW
 ; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=bonnell       2>&1 | FileCheck %s --check-prefix=SLOW
 
 ; Intel chips with fast unaligned memory accesses
 
+; Marked fast because this is the default 32-bit mode CPU in clang.
+; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=pentium4      2>&1 | FileCheck %s --check-prefix=FAST
+; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=pentium4m     2>&1 | FileCheck %s --check-prefix=FAST
+
 ; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=silvermont     2>&1 | FileCheck %s --check-prefix=FAST
 ; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=nehalem        2>&1 | FileCheck %s --check-prefix=FAST
 ; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=westmere       2>&1 | FileCheck %s --check-prefix=FAST
 ; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=sandybridge    2>&1 | FileCheck %s --check-prefix=FAST
 ; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=ivybridge      2>&1 | FileCheck %s --check-prefix=FAST
 ; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=haswell        2>&1 | FileCheck %s --check-prefix=FAST
 ; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=broadwell      2>&1 | FileCheck %s --check-prefix=FAST
 ; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=knl            2>&1 | FileCheck %s --check-prefix=FAST

llvm/test/DebugInfo/COFF/fpo-shrink-wrap.ll

 ; ASM:         retl    $8
 ; ASM: Ltmp10:
 ; ASM:         .cv_fpo_endproc
 
 ; Note how RvaStart advances 7 bytes to skip the shrink-wrapped portion.
 ; OBJ: SubSectionType: FrameData (0xF5)
 ; OBJ:    FrameData {
 ; OBJ:      RvaStart: 0x0
-; OBJ:      CodeSize: 0x34
+; OBJ:      CodeSize: 0x36
 ; OBJ:      PrologSize: 0x9
 ; OBJ:      FrameFunc [
 ; OBJ-NEXT:   $T0 .raSearch =
 ; OBJ-NEXT:   $eip $T0 ^ =
 ; OBJ-NEXT:   $esp $T0 4 + =
 ; OBJ-NEXT: ]
 ; OBJ:    }
 ; OBJ:    FrameData {
 ; OBJ:      RvaStart: 0x7
-; OBJ:      CodeSize: 0x2D
+; OBJ:      CodeSize: 0x2F
 ; OBJ:      PrologSize: 0x2
 ; OBJ:      FrameFunc [
 ; OBJ-NEXT:   $T0 .raSearch =
 ; OBJ-NEXT:   $eip $T0 ^ =
 ; OBJ-NEXT:   $esp $T0 4 + =
 ; OBJ-NEXT:   $ebx $T0 4 - ^ =
 ; OBJ-NEXT: ]
 ; OBJ:    }
 ; OBJ:    FrameData {
 ; OBJ:      RvaStart: 0x8
-; OBJ:      CodeSize: 0x2C
+; OBJ:      CodeSize: 0x2E
 ; OBJ:      PrologSize: 0x1
 ; OBJ:      FrameFunc [
 ; OBJ-NEXT:   $T0 .raSearch =
 ; OBJ-NEXT:   $eip $T0 ^ =
 ; OBJ-NEXT:   $esp $T0 4 + =
 ; OBJ-NEXT:   $ebx $T0 4 - ^ =
 ; OBJ-NEXT:   $edi $T0 8 - ^ =
 ; OBJ-NEXT: ]
 ; OBJ:    }
 ; OBJ:    FrameData {
 ; OBJ:      RvaStart: 0x9
-; OBJ:      CodeSize: 0x2B
+; OBJ:      CodeSize: 0x2D
 ; OBJ:      PrologSize: 0x0
 ; OBJ:      FrameFunc [
 ; OBJ-NEXT:   $T0 .raSearch =
 ; OBJ-NEXT:   $eip $T0 ^ =
 ; OBJ-NEXT:   $esp $T0 4 + =
 ; OBJ-NEXT:   $ebx $T0 4 - ^ =
 ; OBJ-NEXT:   $edi $T0 8 - ^ =
 ; OBJ-NEXT:   $esi $T0 12 - ^ =

llvm/test/DebugInfo/COFF/types-array.ll

 ; CHECK:   Section: .debug$S (5)
 ; CHECK:   Magic: 0x4
 ; CHECK:   Subsection [
 ; CHECK:     SubSectionType: Symbols (0xF1)
 ; CHECK:     {{.*}}Proc{{.*}}Sym {
 ; CHECK:       PtrParent: 0x0
 ; CHECK:       PtrEnd: 0x0
 ; CHECK:       PtrNext: 0x0
-; CHECK:       CodeSize: 0x39
+; CHECK:       CodeSize: 0x2A
 ; CHECK:       DbgStart: 0x0
 ; CHECK:       DbgEnd: 0x0
 ; CHECK:       FunctionType: f (0x1002)
 ; CHECK:       CodeOffset: ?f@@YAXXZ+0x0
 ; CHECK:       Segment: 0x0
 ; CHECK:       Flags [ (0x0)
 ; CHECK:       ]
 ; CHECK:       DisplayName: f
 ; CHECK:       LinkageName: ?f@@YAXXZ
 ; CHECK:     }
 ; CHECK:     LocalSym {
 ; CHECK:       Type: 0x1003
 ; CHECK:       Flags [ (0x0)
 ; CHECK:       ]
 ; CHECK:       VarName: a
 ; CHECK:     }
 ; CHECK:     DefRangeFramePointerRelSym {
 ; CHECK:       Offset: -20
 ; CHECK:       LocalVariableAddrRange {
 ; CHECK:         OffsetStart: .text+0x6
 ; CHECK:         ISectStart: 0x0
-; CHECK:         Range: 0x33
+; CHECK:         Range: 0x24
 ; CHECK:       }
 ; CHECK:     }
 ; CHECK:     ProcEnd {
 ; CHECK:     }
 ; CHECK:   ]
 
 ; ModuleID = 't.cpp'
 source_filename = "t.cpp"