[X86] Change the scheduler model for 'pentium4' to SandyBridgeModel.

[craig.topper]

Summary

I meant to do this in D83913, but missed it while updating the
feature list.

Interestingly I think this is disabling the postRA scheduler. But
it does match our default 64-bit behavior.

[echristo]

Appears so, but ok.

llvm/lib/Target/X86/X86.td

 //  def : ProcessorModel<P, GenericPostRAModel,
 //                       [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
 //                        FeatureMMX, FeatureSSE2, FeatureFXSR, FeatureNOPL,
 //                        FeatureCMOV, FeatureInsertVZEROUPPER]>;
 
   // Since 'pentium4' is the default 32-bit CPU on Linux and Windows,
   // give it more modern tunings.
   // FIXME: This wouldn't be needed if we supported mtune.
-  def : ProcessorModel<P, GenericPostRAModel,
+  def : ProcessorModel<P, SandyBridgeModel,
                        [FeatureX87, FeatureCMPXCHG8B,
                         FeatureMMX, FeatureSSE2, FeatureFXSR, FeatureNOPL,
                         FeatureCMOV, FeatureInsertVZEROUPPER,
                         FeatureSlow3OpsLEA, FeatureSlowDivide64,
                         FeatureSlowIncDec, FeatureMacroFusion]>;
 }
 
 // Intel Quark.

llvm/test/CodeGen/X86/cfguard-x86-vectorcall.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --no_x86_scrub_rip
 ; RUN: llc < %s -mtriple=i686-pc-windows-msvc | FileCheck %s -check-prefix=X32
 ; Control Flow Guard is currently only available on Windows
 
 
 ; Test that Control Flow Guard checks are correctly added for x86 vector calls.
 define void @func_cf_vector_x86(void (%struct.HVA)* %0, %struct.HVA* %1) #0 {
+; X32-LABEL: func_cf_vector_x86:
+; X32:       # %bb.0: # %entry
+; X32-NEXT:    pushl %ebp
+; X32-NEXT:    movl %esp, %ebp
+; X32-NEXT:    andl $-16, %esp
+; X32-NEXT:    subl $48, %esp
+; X32-NEXT:    movl 8(%ebp), %ecx
+; X32-NEXT:    movl 12(%ebp), %eax
+; X32-NEXT:    movups (%eax), %xmm0
+; X32-NEXT:    movups 16(%eax), %xmm1
+; X32-NEXT:    movaps %xmm0, (%esp)
+; X32-NEXT:    movaps %xmm1, 16(%esp)
+; X32-NEXT:    movsd (%esp), %xmm4
+; X32-NEXT:    movsd 8(%esp), %xmm5
+; X32-NEXT:    movsd 16(%esp), %xmm6
+; X32-NEXT:    movsd 24(%esp), %xmm7
+; X32-NEXT:    calll *___guard_check_icall_fptr
+; X32-NEXT:    movaps %xmm4, %xmm0
+; X32-NEXT:    movaps %xmm5, %xmm1
+; X32-NEXT:    movaps %xmm6, %xmm2
+; X32-NEXT:    movaps %xmm7, %xmm3
+; X32-NEXT:    calll *%ecx
+; X32-NEXT:    movl %ebp, %esp
+; X32-NEXT:    popl %ebp
+; X32-NEXT:    retl
 entry:
   %2 = alloca %struct.HVA, align 8
   %3 = bitcast %struct.HVA* %2 to i8*
   %4 = bitcast %struct.HVA* %1 to i8*
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 8 %3, i8* align 8 %4, i32 32, i1 false)
   %5 = load %struct.HVA, %struct.HVA* %2, align 8
   call x86_vectorcallcc void %0(%struct.HVA inreg %5)
   ret void
 
-  ; X32-LABEL: func_cf_vector_x86
-  ; X32:       movl 12(%ebp), %eax
-  ; X32:       movl 8(%ebp), %ecx
-  ; X32:       movups (%eax), %xmm0
-  ; X32:       movups 16(%eax), %xmm1
-  ; X32:       movaps %xmm0, (%esp)
-  ; X32:       movaps %xmm1, 16(%esp)
-  ; X32:       movsd  (%esp), %xmm4
-  ; X32:       movsd  8(%esp), %xmm5
-  ; X32:       movsd  16(%esp), %xmm6
-  ; X32:       movsd  24(%esp), %xmm7
-  ; X32:       calll *___guard_check_icall_fptr
-  ; X32:       movaps %xmm4, %xmm0
-  ; X32:       movaps %xmm5, %xmm1
-  ; X32:       movaps %xmm6, %xmm2
-  ; X32:       movaps %xmm7, %xmm3
-  ; X32:       calll  *%ecx
 }
 attributes #0 = { "target-cpu"="pentium4" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" }
 
 %struct.HVA = type { double, double, double, double }
 
 declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture writeonly, i8* nocapture readonly, i32, i1 immarg) #1
 attributes #1 = { argmemonly nounwind willreturn }
 
 
 !llvm.module.flags = !{!0}
 !0 = !{i32 2, !"cfguard", i32 2}

llvm/test/CodeGen/X86/cmov-fp.ll

; NOCMOV-NEXT:    retl
   %cmp = icmp sle i32 %a, %b
   %sel = select i1 %cmp, float 99.0, float %x
   ret float %sel
 }
 
 define x86_fp80 @test17(i32 %a, i32 %b, x86_fp80 %x) nounwind {
 ; SSE-LABEL: test17:
 ; SSE:       # %bb.0:
-; SSE-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; SSE-NEXT:    fldt {{[0-9]+}}(%esp)
+; SSE-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; SSE-NEXT:    cmpl {{[0-9]+}}(%esp), %eax
 ; SSE-NEXT:    flds {{\.LCPI.*}}
 ; SSE-NEXT:    fxch %st(1)
-; SSE-NEXT:    cmpl {{[0-9]+}}(%esp), %eax
 ; SSE-NEXT:    fcmovnbe %st(1), %st
 ; SSE-NEXT:    fstp %st(1)
 ; SSE-NEXT:    retl
 ;
 ; NOSSE2-LABEL: test17:
 ; NOSSE2:       # %bb.0:
 ; NOSSE2-NEXT:    fldt {{[0-9]+}}(%esp)
 ; NOSSE2-NEXT:    movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT:    retl
   %cmp = icmp ugt i32 %a, %b
   %sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x
   ret x86_fp80 %sel
 }
 
 define x86_fp80 @test18(i32 %a, i32 %b, x86_fp80 %x) nounwind {
 ; SSE-LABEL: test18:
 ; SSE:       # %bb.0:
-; SSE-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; SSE-NEXT:    fldt {{[0-9]+}}(%esp)
+; SSE-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; SSE-NEXT:    cmpl {{[0-9]+}}(%esp), %eax
 ; SSE-NEXT:    flds {{\.LCPI.*}}
 ; SSE-NEXT:    fxch %st(1)
-; SSE-NEXT:    cmpl {{[0-9]+}}(%esp), %eax
 ; SSE-NEXT:    fcmovnb %st(1), %st
 ; SSE-NEXT:    fstp %st(1)
 ; SSE-NEXT:    retl
 ;
 ; NOSSE2-LABEL: test18:
 ; NOSSE2:       # %bb.0:
 ; NOSSE2-NEXT:    fldt {{[0-9]+}}(%esp)
 ; NOSSE2-NEXT:    movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT:    retl
   %cmp = icmp uge i32 %a, %b
   %sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x
   ret x86_fp80 %sel
 }
 
 define x86_fp80 @test19(i32 %a, i32 %b, x86_fp80 %x) nounwind {
 ; SSE-LABEL: test19:
 ; SSE:       # %bb.0:
-; SSE-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; SSE-NEXT:    fldt {{[0-9]+}}(%esp)
+; SSE-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; SSE-NEXT:    cmpl {{[0-9]+}}(%esp), %eax
 ; SSE-NEXT:    flds {{\.LCPI.*}}
 ; SSE-NEXT:    fxch %st(1)
-; SSE-NEXT:    cmpl {{[0-9]+}}(%esp), %eax
 ; SSE-NEXT:    fcmovb %st(1), %st
 ; SSE-NEXT:    fstp %st(1)
 ; SSE-NEXT:    retl
 ;
 ; NOSSE2-LABEL: test19:
 ; NOSSE2:       # %bb.0:
 ; NOSSE2-NEXT:    fldt {{[0-9]+}}(%esp)
 ; NOSSE2-NEXT:    movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT:    retl
   %cmp = icmp ult i32 %a, %b
   %sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x
   ret x86_fp80 %sel
 }
 
 define x86_fp80 @test20(i32 %a, i32 %b, x86_fp80 %x) nounwind {
 ; SSE-LABEL: test20:
 ; SSE:       # %bb.0:
-; SSE-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; SSE-NEXT:    fldt {{[0-9]+}}(%esp)
+; SSE-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; SSE-NEXT:    cmpl {{[0-9]+}}(%esp), %eax
 ; SSE-NEXT:    flds {{\.LCPI.*}}
 ; SSE-NEXT:    fxch %st(1)
-; SSE-NEXT:    cmpl {{[0-9]+}}(%esp), %eax
 ; SSE-NEXT:    fcmovbe %st(1), %st
 ; SSE-NEXT:    fstp %st(1)
 ; SSE-NEXT:    retl
 ;
 ; NOSSE2-LABEL: test20:
 ; NOSSE2:       # %bb.0:
 ; NOSSE2-NEXT:    fldt {{[0-9]+}}(%esp)
 ; NOSSE2-NEXT:    movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT:    retl
   %cmp = icmp ule i32 %a, %b
   %sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x
   ret x86_fp80 %sel
 }
 
 define x86_fp80 @test21(i32 %a, i32 %b, x86_fp80 %x) nounwind {
 ; SSE-LABEL: test21:
 ; SSE:       # %bb.0:
-; SSE-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; SSE-NEXT:    fldt {{[0-9]+}}(%esp)
-; SSE-NEXT:    flds {{\.LCPI.*}}
-; SSE-NEXT:    fxch %st(1)
+; SSE-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; SSE-NEXT:    cmpl {{[0-9]+}}(%esp), %eax
 ; SSE-NEXT:    setg %al
 ; SSE-NEXT:    testb %al, %al
+; SSE-NEXT:    flds {{\.LCPI.*}}
+; SSE-NEXT:    fxch %st(1)
 ; SSE-NEXT:    fcmovne %st(1), %st
 ; SSE-NEXT:    fstp %st(1)
 ; SSE-NEXT:    retl
 ;
 ; NOSSE2-LABEL: test21:
 ; NOSSE2:       # %bb.0:
 ; NOSSE2-NEXT:    fldt {{[0-9]+}}(%esp)
 ; NOSSE2-NEXT:    movl {{[0-9]+}}(%esp), %eax
; We don't emit a branch for fp80, why?
   %cmp = icmp sgt i32 %a, %b
   %sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x
   ret x86_fp80 %sel
 }
 
 define x86_fp80 @test22(i32 %a, i32 %b, x86_fp80 %x) nounwind {
 ; SSE-LABEL: test22:
 ; SSE:       # %bb.0:
-; SSE-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; SSE-NEXT:    fldt {{[0-9]+}}(%esp)
-; SSE-NEXT:    flds {{\.LCPI.*}}
-; SSE-NEXT:    fxch %st(1)
+; SSE-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; SSE-NEXT:    cmpl {{[0-9]+}}(%esp), %eax
 ; SSE-NEXT:    setge %al
 ; SSE-NEXT:    testb %al, %al
+; SSE-NEXT:    flds {{\.LCPI.*}}
+; SSE-NEXT:    fxch %st(1)
 ; SSE-NEXT:    fcmovne %st(1), %st
 ; SSE-NEXT:    fstp %st(1)
 ; SSE-NEXT:    retl
 ;
 ; NOSSE2-LABEL: test22:
 ; NOSSE2:       # %bb.0:
 ; NOSSE2-NEXT:    fldt {{[0-9]+}}(%esp)
 ; NOSSE2-NEXT:    movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT:    retl
   %cmp = icmp sge i32 %a, %b
   %sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x
   ret x86_fp80 %sel
 }
 
 define x86_fp80 @test23(i32 %a, i32 %b, x86_fp80 %x) nounwind {
 ; SSE-LABEL: test23:
 ; SSE:       # %bb.0:
-; SSE-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; SSE-NEXT:    fldt {{[0-9]+}}(%esp)
-; SSE-NEXT:    flds {{\.LCPI.*}}
-; SSE-NEXT:    fxch %st(1)
+; SSE-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; SSE-NEXT:    cmpl {{[0-9]+}}(%esp), %eax
 ; SSE-NEXT:    setl %al
 ; SSE-NEXT:    testb %al, %al
+; SSE-NEXT:    flds {{\.LCPI.*}}
+; SSE-NEXT:    fxch %st(1)
 ; SSE-NEXT:    fcmovne %st(1), %st
 ; SSE-NEXT:    fstp %st(1)
 ; SSE-NEXT:    retl
 ;
 ; NOSSE2-LABEL: test23:
 ; NOSSE2:       # %bb.0:
 ; NOSSE2-NEXT:    fldt {{[0-9]+}}(%esp)
 ; NOSSE2-NEXT:    movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT:    retl
   %cmp = icmp slt i32 %a, %b
   %sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x
   ret x86_fp80 %sel
 }
 
 define x86_fp80 @test24(i32 %a, i32 %b, x86_fp80 %x) nounwind {
 ; SSE-LABEL: test24:
 ; SSE:       # %bb.0:
-; SSE-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; SSE-NEXT:    fldt {{[0-9]+}}(%esp)
-; SSE-NEXT:    flds {{\.LCPI.*}}
-; SSE-NEXT:    fxch %st(1)
+; SSE-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; SSE-NEXT:    cmpl {{[0-9]+}}(%esp), %eax
 ; SSE-NEXT:    setle %al
 ; SSE-NEXT:    testb %al, %al
+; SSE-NEXT:    flds {{\.LCPI.*}}
+; SSE-NEXT:    fxch %st(1)
 ; SSE-NEXT:    fcmovne %st(1), %st
 ; SSE-NEXT:    fstp %st(1)
 ; SSE-NEXT:    retl
 ;
 ; NOSSE2-LABEL: test24:
 ; NOSSE2:       # %bb.0:
 ; NOSSE2-NEXT:    fldt {{[0-9]+}}(%esp)
 ; NOSSE2-NEXT:    movl {{[0-9]+}}(%esp), %eax

llvm/test/CodeGen/X86/post-ra-sched.ll

-; RUN: llc < %s -mtriple=i386 -mcpu=pentium4 | FileCheck %s
-; RUN: llc < %s -mtriple=i386 -mcpu=pentium4m | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i386 -mcpu=pentium4 | FileCheck %s --check-prefix=PENTIUM4
+; RUN: llc < %s -mtriple=i386 -mcpu=pentium4m | FileCheck %s --check-prefix=PENTIUM4
 ; RUN: llc < %s -mtriple=i386 -mcpu=pentium-m | FileCheck %s
 ; RUN: llc < %s -mtriple=i386 -mcpu=prescott | FileCheck %s
 ; RUN: llc < %s -mtriple=i386 -mcpu=nocona | FileCheck %s
 ;
 ; Verify that scheduling puts some distance between a load feeding into
 ; the address of another load, and that second load.  This currently
 ; happens during the post-RA-scheduler, which should be enabled by
 ; default with the above specified cpus.
 
+; Pentium4 is the default 32-bit CPU on Linux and currently has the postRA
+; scheduler disabled. Leaving the command lines in place in case we change that.
+
 @ptrs = external global [0 x i32*], align 4
 @idxa = common global i32 0, align 4
 @idxb = common global i32 0, align 4
 @res = common global i32 0, align 4
 
 define void @addindirect() {
+; PENTIUM4-LABEL: addindirect:
+; PENTIUM4:       # %bb.0: # %entry
+; PENTIUM4-NEXT:    movl idxa, %eax
+; PENTIUM4-NEXT:    movl ptrs(,%eax,4), %eax
+; PENTIUM4-NEXT:    movl idxb, %ecx
+; PENTIUM4-NEXT:    movl ptrs(,%ecx,4), %ecx
+; PENTIUM4-NEXT:    movl (%ecx), %ecx
+; PENTIUM4-NEXT:    addl (%eax), %ecx
+; PENTIUM4-NEXT:    movl %ecx, res
+; PENTIUM4-NEXT:    retl
+;
 ; CHECK-LABEL: addindirect:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    movl idxb, %ecx
 ; CHECK-NEXT:    movl idxa, %eax
 ; CHECK-NEXT:    movl ptrs(,%ecx,4), %ecx
 ; CHECK-NEXT:    movl ptrs(,%eax,4), %eax
 ; CHECK-NEXT:    movl (%ecx), %ecx
 ; CHECK-NEXT:    addl (%eax), %ecx

llvm/test/CodeGen/X86/pr34088.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=i686-unknown -mcpu=pentium4 | FileCheck %s
 
 %struct.Foo = type { i32, %struct.Bar }
 %struct.Bar = type { i32, %struct.Buffer, i32 }
 %struct.Buffer = type { i8*, i32 }
 
 ; This test checks that the load of store %2 is not dropped.
-; 
+;
 define i32 @pr34088() local_unnamed_addr {
 ; CHECK-LABEL: pr34088:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    pushl %ebp
 ; CHECK-NEXT:    .cfi_def_cfa_offset 8
 ; CHECK-NEXT:    .cfi_offset %ebp, -8
 ; CHECK-NEXT:    movl %esp, %ebp
 ; CHECK-NEXT:    .cfi_def_cfa_register %ebp
 ; CHECK-NEXT:    andl $-16, %esp
 ; CHECK-NEXT:    subl $32, %esp
 ; CHECK-NEXT:    xorps %xmm0, %xmm0
-; CHECK-NEXT:    movaps {{.*#+}} xmm1 = [205,205,205,205,205,205,205,205,205,205,205,205,205,205,205,205]
-; CHECK-NEXT:    xorl %eax, %eax
 ; CHECK-NEXT:    movaps %xmm0, (%esp)
 ; CHECK-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
-; CHECK-NEXT:    movl $-842150451, {{[0-9]+}}(%esp) # imm = 0xCDCDCDCD
+; CHECK-NEXT:    movaps {{.*#+}} xmm1 = [205,205,205,205,205,205,205,205,205,205,205,205,205,205,205,205]
 ; CHECK-NEXT:    movaps %xmm1, (%esp)
+; CHECK-NEXT:    movl $-842150451, {{[0-9]+}}(%esp) # imm = 0xCDCDCDCD
 ; CHECK-NEXT:    movsd %xmm0, {{[0-9]+}}(%esp)
+; CHECK-NEXT:    xorl %eax, %eax
 ; CHECK-NEXT:    movl %ebp, %esp
 ; CHECK-NEXT:    popl %ebp
 ; CHECK-NEXT:    .cfi_def_cfa %esp, 4
 ; CHECK-NEXT:    retl
 entry:
   %foo = alloca %struct.Foo, align 4
   %0 = bitcast %struct.Foo* %foo to i8*
   call void @llvm.memset.p0i8.i32(i8* align 4 nonnull %0, i8 0, i32 20, i1 false)

llvm/test/CodeGen/X86/pr40539.ll

 @fpi = external global float, align 4
 
 define zeroext i1 @_Z8test_cosv() {
 ; CHECK-LABEL: _Z8test_cosv:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    subl $8, %esp
 ; CHECK-NEXT:    .cfi_def_cfa_offset 12
 ; CHECK-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; CHECK-NEXT:    movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
 ; CHECK-NEXT:    divss {{\.LCPI.*}}, %xmm0
 ; CHECK-NEXT:    movss %xmm0, {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    flds {{[0-9]+}}(%esp)
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    fcos
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    fstps (%esp)
 ; CHECK-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-NEXT:    movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
 ; CHECK-NEXT:    ucomiss %xmm0, %xmm1
 ; CHECK-NEXT:    setae %cl
 ; CHECK-NEXT:    ucomiss {{\.LCPI.*}}, %xmm0
 ; CHECK-NEXT:    setae %al
 ; CHECK-NEXT:    andb %cl, %al
 ; CHECK-NEXT:    addl $8, %esp
 ; CHECK-NEXT:    .cfi_def_cfa_offset 4
 ; CHECK-NEXT:    retl

llvm/test/DebugInfo/COFF/fpo-stack-protect.ll

 
 ; CHECK: _ssp:                                   # @ssp
 ; CHECK:         .cv_fpo_proc    _ssp 4
 ; CHECK:         pushl   %esi
 ; CHECK:         .cv_fpo_pushreg %esi
 ; CHECK:         subl    $20, %esp
 ; CHECK:         .cv_fpo_stackalloc      20
 ; CHECK:         .cv_fpo_endprologue
+; CHECK:         movl    28(%esp), %esi
 ; CHECK:         ___security_cookie
 
-; CHECK:         movl    28(%esp), %esi
 ; CHECK:         movl    %esi, {{[0-9]*}}(%esp)
 ; CHECK:         movl    %esi, {{[0-9]*}}(%esp)
 ; CHECK:         movl    %esi, {{[0-9]*}}(%esp)
 ; CHECK:         movl    %esi, {{[0-9]*}}(%esp)
 
 ; CHECK:         calll   _escape
 ; CHECK:         calll   @__security_check_cookie@4
 
 ; CHECK:         movl    %esi, %eax
 ; CHECK:         addl    $20, %esp
 ; CHECK:         popl    %esi
 ; CHECK:         retl
-; CHECK: Ltmp3:
+; CHECK: Ltmp2:
 ; CHECK:         .cv_fpo_endproc
 
 ; ModuleID = 't.c'
 source_filename = "t.c"
 target datalayout = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"
 target triple = "i386-pc-windows-msvc19.11.25508"
 
 ; Function Attrs: nounwind sspstrong