[AMDGPU] Add missing test prefixes

[foad]

This can't be committed as-is because some of the checks fail. @rampitec how should they be fixed? Should I just update the checks, or do we need to fix some real bugs?

llvm/test/CodeGen/AMDGPU/perfhint.ll

33

This check fails.

87

This check fails. Perhaps D47740 never worked?

[rampitec]

llvm/test/CodeGen/AMDGPU/perfhint.ll

33

This one is memory bound, there are practically only memory operations here. I think it needs some ALU in between to catch large stride only as intended.

87

Looks like it did not :(

Anyway, this case is not memory bound even though it is indirect. This is because we have a single load followed by multiple stores, that was the point of the check.

[foad]

I've committed the easy bits as 2dc3d1b3136522e7c8e92d742d8ecc3405b9b4bb.

llvm/test/CodeGen/AMDGPU/perfhint.ll

33

OK, fixed in f05bce86af32d7b5cf1ab28b3abf6ee473bf3ef1.

[foad]

llvm/test/CodeGen/AMDGPU/perfhint.ll

87

The problem is that after AMDGPULowerKernelArguments, the load from %arg looks like this:

%arg.load = load float addrspace(1)*, float addrspace(1)* addrspace(4)* %arg.kernarg.offset.cast, align 4, !invariant.load !0
%load = load float, float addrspace(1)* %arg.load, align 8

which is indirect. Any ideas?

[rampitec]

llvm/test/CodeGen/AMDGPU/perfhint.ll

33

Thank you!

87

A-ha! The representation changed, but we did not catch it because of the broken test.

The first load is from constant, so it is uniform. I suppose we can ignore constant address space for this purpose. It creates much less memory traffic.

[foad]

All changes have been committed or split out into another review.

llvm/test/CodeGen/AMDGPU/perfhint.ll

87

I've done this in D84301.

llvm/test/CodeGen/AMDGPU/perfhint.ll

 ; RUN: llc -march=amdgcn < %s | FileCheck -check-prefix=GCN %s
 
 ; GCN-LABEL: {{^}}test_membound:
-; MemoryBound: 1
-; WaveLimiterHint : 1
+; GCN: MemoryBound: 1
+; GCN: WaveLimiterHint : 1
 define amdgpu_kernel void @test_membound(<4 x i32> addrspace(1)* nocapture readonly %arg, <4 x i32> addrspace(1)* nocapture %arg1) {
 bb:
   %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
   %tmp2 = zext i32 %tmp to i64
   %tmp3 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 %tmp2
   %tmp4 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp3, align 16
   %tmp5 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 %tmp2
   store <4 x i32> %tmp4, <4 x i32> addrspace(1)* %tmp5, align 16
bb:
   %tmp15 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 %tmp14
   %tmp16 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp15, align 16
   %tmp17 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 %tmp14
   store <4 x i32> %tmp16, <4 x i32> addrspace(1)* %tmp17, align 16
   ret void
 }
 
 ; GCN-LABEL: {{^}}test_large_stride:
-; MemoryBound: 0
-; WaveLimiterHint : 1
+; GCN: MemoryBound: 0
+; GCN: WaveLimiterHint : 1
 define amdgpu_kernel void @test_large_stride(i32 addrspace(1)* nocapture %arg) {
 bb:
   %tmp = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 4096
   %tmp1 = load i32, i32 addrspace(1)* %tmp, align 4
   %tmp2 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 1
   store i32 %tmp1, i32 addrspace(1)* %tmp2, align 4
   %tmp3 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 8192
   %tmp4 = load i32, i32 addrspace(1)* %tmp3, align 4
   %tmp5 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 2
   store i32 %tmp4, i32 addrspace(1)* %tmp5, align 4
   %tmp6 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 12288
   %tmp7 = load i32, i32 addrspace(1)* %tmp6, align 4
   %tmp8 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 3
   store i32 %tmp7, i32 addrspace(1)* %tmp8, align 4
   ret void
 }
 
 ; GCN-LABEL: {{^}}test_indirect:
-; MemoryBound: 0
-; WaveLimiterHint : 1
+; GCN: MemoryBound: 0
+; GCN: WaveLimiterHint : 1
 define amdgpu_kernel void @test_indirect(i32 addrspace(1)* nocapture %arg) {
 bb:
   %tmp = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 1
   %tmp1 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 2
   %tmp2 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 3
   %tmp3 = bitcast i32 addrspace(1)* %arg to <4 x i32> addrspace(1)*
   %tmp4 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp3, align 4
   %tmp5 = extractelement <4 x i32> %tmp4, i32 0
bb:
   %tmp18 = sext i32 %tmp17 to i64
   %tmp19 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %tmp18
   %tmp20 = load i32, i32 addrspace(1)* %tmp19, align 4
   store i32 %tmp20, i32 addrspace(1)* %tmp2, align 4
   ret void
 }
 
 ; GCN-LABEL: {{^}}test_indirect_through_phi:
-; MemoryBound: 0
-; WaveLimiterHint : 0
+; GCN: MemoryBound: 0
+; GCN: WaveLimiterHint : 0
 define amdgpu_kernel void @test_indirect_through_phi(float addrspace(1)* %arg) {
 bb:
   %load = load float, float addrspace(1)* %arg, align 8
   %load.f = bitcast float %load to i32
   %n = tail call i32 @llvm.amdgcn.workitem.id.x()
   br label %bb1
 
 bb1:                                              ; preds = %bb1, %bb