[PowerPC][Power10] Fix VINS* (vector insert byte/half/word) instructions to have i32 arguments.

[amyk]

Summary

Previously, the vins* intrinsic was incorrectly defined to have its second and third argument arguments as an i64.
This patch fixes the second and third argument of the vins* instruction and intrinsic to have i32s instead.

For example, vinsw is now defined as:

<4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32>, i32, i32)

Instead of:

<4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32>, i64, i32)

[lei]

LGTM

[rzurob]

We should update vins[bhw][lr] too. They have the same problem.

llvm/include/llvm/IR/IntrinsicsPowerPC.td

523

The same problem also occurs in vins[bhw][lr]

[amyk]

llvm/include/llvm/IR/IntrinsicsPowerPC.td

523

Ah, I missed that. Thank you for bringing that to my attention. I'll look into it.

[amyk]

Updated revision to fix vector insert byte/half/word versions to have an i32 argument.

[bsaleil]

LGTM

[nemanjai]

LGTM aside from a minor nit regarding the description.

clang/include/clang/Basic/BuiltinsPPC.def

324 ↗

(On Diff #277153)

The description of this review mentions the second argument but you are changing the second and third argument. Please fix the description.

[nemanjai]

@rzurob This cannot proceed without your approval since you requested changes.

[rzurob]

LGTM. Thanks!

llvm/include/llvm/IR/IntrinsicsPowerPC.td

def int_ppc_altivec_vinshvrx : GCCBuiltin<"__builtin_altivec_vinshvrx">,
                         [llvm_v8i16_ty, llvm_i64_ty, llvm_v8i16_ty],
                         [IntrNoMem]>;
   def int_ppc_altivec_vinswvlx : GCCBuiltin<"__builtin_altivec_vinswvlx">,
               Intrinsic<[llvm_v4i32_ty],
                         [llvm_v4i32_ty, llvm_i64_ty, llvm_v4i32_ty],
                         [IntrNoMem]>;
   def int_ppc_altivec_vinswvrx : GCCBuiltin<"__builtin_altivec_vinswvrx">,
               Intrinsic<[llvm_v4i32_ty],
                         [llvm_v4i32_ty, llvm_i64_ty, llvm_v4i32_ty],
                         [IntrNoMem]>;
   // P10 Vector Insert with immediate.
   def int_ppc_altivec_vinsw :
               Intrinsic<[llvm_v4i32_ty],
-                        [llvm_v4i32_ty, llvm_i64_ty, llvm_i32_ty],
+                        [llvm_v4i32_ty, llvm_i32_ty, llvm_i32_ty],
                         [IntrNoMem, ImmArg<ArgIndex<2>>]>;
   def int_ppc_altivec_vinsd :
               Intrinsic<[llvm_v2i64_ty],
                         [llvm_v2i64_ty, llvm_i64_ty, llvm_i32_ty],
                         [IntrNoMem, ImmArg<ArgIndex<2>>]>;
 }
 
 // Vector average.

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

class VXForm_RD5_N3_VB5<bits<11> xo, dag OOL, dag IOL, string asmstr,
   let Inst{6-10}  = RD;
   let Inst{11-12} = 0;
   let Inst{13-15} = N;
   let Inst{16-20} = VB;
   let Inst{21-31} = xo;
 }
 
 
-// VX-Form: [PO VRT / UIM RB XO].
-// We use VXForm_1 to implement it, that is, we use "VRA" (5 bit) to represent
-// "/ UIM" (unused bit followed by a 4-bit immediate)
-// Destructive (insert) forms are suffixed with _ins.
-class VXForm_VRT5_UIM5_RB5_ins<bits<11> xo, string opc, list<dag> pattern>
-  : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vDi, u4imm:$UIM, g8rc:$rB),
-             !strconcat(opc, " $vD, $rB, $UIM"), IIC_VecGeneral, pattern>,
-             RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
-
 // VX-Form: [PO VRT RA VRB XO].
 // Destructive (insert) forms are suffixed with _ins.
 class VXForm_VTB5_RA5_ins<bits<11> xo, string opc, list<dag> pattern>
   : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vDi, g8rc:$rA, vrrc:$vB),
              !strconcat(opc, " $vD, $rA, $vB"), IIC_VecGeneral, pattern>,
              RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
 
 // VX-Form: [PO VRT RA RB XO].
let Predicates = [IsISA3_1] in {
   def VSRDBI : VNForm_VTAB5_SD3<22, 1, (outs vrrc:$VRT),
                                 (ins vrrc:$VRA, vrrc:$VRB, u3imm:$SH),
                                 "vsrdbi $VRT, $VRA, $VRB, $SH",
                                 IIC_VecGeneral,
                                 [(set v16i8:$VRT,
                                       (int_ppc_altivec_vsrdbi v16i8:$VRA,
                                                               v16i8:$VRB, 
                                                               i32:$SH))]>;
-  def VINSW : 
-    VXForm_VRT5_UIM5_RB5_ins<207, "vinsw",
-                             [(set v4i32:$vD,
-                                   (int_ppc_altivec_vinsw v4i32:$vDi, i64:$rB,
-                                                          timm:$UIM))]>;
+  def VINSW :
+    VXForm_1<207, (outs vrrc:$vD), (ins vrrc:$vDi, u4imm:$UIM, gprc:$rB),
+             "vinsw $vD, $rB, $UIM", IIC_VecGeneral,
+                   (int_ppc_altivec_vinsw v4i32:$vDi, i32:$rB, timm:$UIM))]>,
+             RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
   def VINSD :
-    VXForm_VRT5_UIM5_RB5_ins<463, "vinsd",
-                             [(set v2i64:$vD,
-                                   (int_ppc_altivec_vinsd v2i64:$vDi, i64:$rB,
-                                                          timm:$UIM))]>;
+    VXForm_1<463, (outs vrrc:$vD), (ins vrrc:$vDi, u4imm:$UIM, g8rc:$rB),
+             "vinsd $vD, $rB, $UIM", IIC_VecGeneral,
+                   (int_ppc_altivec_vinsd v2i64:$vDi, i64:$rB, timm:$UIM))]>,
+             RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
   def VINSBVLX :
     VXForm_VTB5_RA5_ins<15, "vinsbvlx",
                         [(set v16i8:$vD,
                               (int_ppc_altivec_vinsbvlx v16i8:$vDi, i64:$rA,
                                                         v16i8:$vB))]>;
   def VINSBVRX :
     VXForm_VTB5_RA5_ins<271, "vinsbvrx",
                         [(set v16i8:$vD,

llvm/test/CodeGen/PowerPC/builtins-ppc-p10permute.ll

 ; CHECK-NEXT:    vinswvrx v2, r5, v3
 ; CHECK-NEXT:    blr
 entry:
   %0 = tail call <4 x i32> @llvm.ppc.altivec.vinswvrx(<4 x i32> %a, i64 %b, <4 x i32> %c)
   ret <4 x i32> %0
 }
 declare <4 x i32> @llvm.ppc.altivec.vinswvrx(<4 x i32>, i64, <4 x i32>)
 
-define <4 x i32> @testVINSW(<4 x i32> %a, i64 %b) {
+define <4 x i32> @testVINSW(<4 x i32> %a, i32 %b) {
 ; CHECK-LABEL: testVINSW:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vinsw v2, r5, 1
 ; CHECK-NEXT:    blr
 entry:
-  %0 = tail call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> %a, i64 %b, i32 1)
+  %0 = tail call <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32> %a, i32 %b, i32 1)
   ret <4 x i32> %0
 }
-declare <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32>, i64, i32 immarg)
+declare <4 x i32> @llvm.ppc.altivec.vinsw(<4 x i32>, i32, i32 immarg)
 
 define <2 x i64> @testVINSD(<2 x i64> %a, i64 %b) {
 ; CHECK-LABEL: testVINSD:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vinsd v2, r5, 1
 ; CHECK-NEXT:    blr
 entry:
   %0 = tail call <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64> %a, i64 %b, i32 1)
   ret <2 x i64> %0
 }
 declare <2 x i64> @llvm.ppc.altivec.vinsd(<2 x i64>, i64, i32 immarg)