[PowerPC] Enable default support of quad precision operations

[lei]

Summary

Remove option guarding support of quad precision operations.

[qiucf]

llvm/test/CodeGen/PowerPC/builtins-ppc-p9-f128.ll

58

Misindent?

[steven.zhang]

LGTM as long as you fix that unintend change of that line of the test.

[nemanjai]

llvm/test/CodeGen/PowerPC/float-load-store-pair.ll

71

This missing store is a bit of a concern.

[nemanjai]

LGTM. Thank you.

llvm/test/CodeGen/PowerPC/float-load-store-pair.ll

71

Oh NVM. That is a store to pass the f128 on the stack which we don't need to do according to the ABI.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
 
 static cl::opt<bool> DisableSCO("disable-ppc-sco",
 cl::desc("disable sibling call optimization on ppc"), cl::Hidden);
 
 static cl::opt<bool> DisableInnermostLoopAlign32("disable-ppc-innermost-loop-align32",
 cl::desc("don't always align innermost loop to 32 bytes on ppc"), cl::Hidden);
 
-static cl::opt<bool> EnableQuadPrecision("enable-ppc-quad-precision",
-cl::desc("enable quad precision float support on ppc"), cl::Hidden);
-
 static cl::opt<bool> UseAbsoluteJumpTables("ppc-use-absolute-jumptables",
 cl::desc("use absolute jump tables on ppc"), cl::Hidden);
 
 STATISTIC(NumTailCalls, "Number of tail calls");
 STATISTIC(NumSiblingCalls, "Number of sibling calls");
 STATISTIC(ShufflesHandledWithVPERM, "Number of shuffles lowered to a VPERM");
 STATISTIC(NumDynamicAllocaProbed, "Number of dynamic stack allocation probed");
 
if (Subtarget.hasP9Vector()) {
 
       // 128 bit shifts can be accomplished via 3 instructions for SHL and
       // SRL, but not for SRA because of the instructions available:
       // VS{RL} and VS{RL}O.
       setOperationAction(ISD::SHL, MVT::v1i128, Legal);
       setOperationAction(ISD::SRL, MVT::v1i128, Legal);
       setOperationAction(ISD::SRA, MVT::v1i128, Expand);
 
-      if (EnableQuadPrecision) {
-        addRegisterClass(MVT::f128, &PPC::VRRCRegClass);
-        setOperationAction(ISD::FADD, MVT::f128, Legal);
-        setOperationAction(ISD::FSUB, MVT::f128, Legal);
-        setOperationAction(ISD::FDIV, MVT::f128, Legal);
-        setOperationAction(ISD::FMUL, MVT::f128, Legal);
-        setOperationAction(ISD::FP_EXTEND, MVT::f128, Legal);
-        // No extending loads to f128 on PPC.
-        for (MVT FPT : MVT::fp_valuetypes())
-          setLoadExtAction(ISD::EXTLOAD, MVT::f128, FPT, Expand);
-        setOperationAction(ISD::FMA, MVT::f128, Legal);
-        setCondCodeAction(ISD::SETULT, MVT::f128, Expand);
-        setCondCodeAction(ISD::SETUGT, MVT::f128, Expand);
-        setCondCodeAction(ISD::SETUEQ, MVT::f128, Expand);
-        setCondCodeAction(ISD::SETOGE, MVT::f128, Expand);
-        setCondCodeAction(ISD::SETOLE, MVT::f128, Expand);
-        setCondCodeAction(ISD::SETONE, MVT::f128, Expand);
 
-        setOperationAction(ISD::FTRUNC, MVT::f128, Legal);
-        setOperationAction(ISD::FRINT, MVT::f128, Legal);
-        setOperationAction(ISD::FFLOOR, MVT::f128, Legal);
-        setOperationAction(ISD::FCEIL, MVT::f128, Legal);
-        setOperationAction(ISD::FNEARBYINT, MVT::f128, Legal);
-        setOperationAction(ISD::FROUND, MVT::f128, Legal);
 
-        setOperationAction(ISD::SELECT, MVT::f128, Expand);
-        setOperationAction(ISD::FP_ROUND, MVT::f64, Legal);
-        setOperationAction(ISD::FP_ROUND, MVT::f32, Legal);
-        setTruncStoreAction(MVT::f128, MVT::f64, Expand);
-        setTruncStoreAction(MVT::f128, MVT::f32, Expand);
-        setOperationAction(ISD::BITCAST, MVT::i128, Custom);
-        // No implementation for these ops for PowerPC.
-        setOperationAction(ISD::FSIN , MVT::f128, Expand);
-        setOperationAction(ISD::FCOS , MVT::f128, Expand);
-        setOperationAction(ISD::FPOW, MVT::f128, Expand);
-        setOperationAction(ISD::FPOWI, MVT::f128, Expand);
-        setOperationAction(ISD::FREM, MVT::f128, Expand);
+      setOperationAction(ISD::FSIN, MVT::f128, Expand);
+      setOperationAction(ISD::FCOS, MVT::f128, Expand);
 
-        // Handle constrained floating-point operations of fp128
-        setOperationAction(ISD::STRICT_FADD, MVT::f128, Legal);
-        setOperationAction(ISD::STRICT_FSUB, MVT::f128, Legal);
-        setOperationAction(ISD::STRICT_FMUL, MVT::f128, Legal);
-        setOperationAction(ISD::STRICT_FDIV, MVT::f128, Legal);
-        setOperationAction(ISD::STRICT_FMA, MVT::f128, Legal);
-        setOperationAction(ISD::STRICT_FSQRT, MVT::f128, Legal);
-        setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f128, Legal);
-        setOperationAction(ISD::STRICT_FP_ROUND, MVT::f64, Legal);
-        setOperationAction(ISD::STRICT_FP_ROUND, MVT::f32, Legal);
-        setOperationAction(ISD::STRICT_FRINT, MVT::f128, Legal);
-        setOperationAction(ISD::STRICT_FNEARBYINT, MVT::f128, Legal);
-        setOperationAction(ISD::STRICT_FFLOOR, MVT::f128, Legal);
-        setOperationAction(ISD::STRICT_FCEIL,  MVT::f128, Legal);
-        setOperationAction(ISD::STRICT_FTRUNC, MVT::f128, Legal);
-        setOperationAction(ISD::STRICT_FROUND, MVT::f128, Legal);
-      }
+      setOperationAction(ISD::STRICT_FCEIL, MVT::f128, Legal);
       setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
       setOperationAction(ISD::BSWAP, MVT::v8i16, Legal);
       setOperationAction(ISD::BSWAP, MVT::v4i32, Legal);
       setOperationAction(ISD::BSWAP, MVT::v2i64, Legal);
       setOperationAction(ISD::BSWAP, MVT::v1i128, Legal);
     }
 
     if (Subtarget.hasP9Altivec()) {
if (TM.Options.UnsafeFPMath) {
     setTargetDAGCombine(ISD::FSQRT);
   }
 
   if (Subtarget.hasP9Altivec()) {
     setTargetDAGCombine(ISD::ABS);
     setTargetDAGCombine(ISD::VSELECT);
   }
 
-  if (EnableQuadPrecision) {
-    setLibcallName(RTLIB::LOG_F128, "logf128");
-    setLibcallName(RTLIB::LOG2_F128, "log2f128");
-    setLibcallName(RTLIB::LOG10_F128, "log10f128");
-    setLibcallName(RTLIB::EXP_F128, "expf128");
-    setLibcallName(RTLIB::EXP2_F128, "exp2f128");
-    setLibcallName(RTLIB::SIN_F128, "sinf128");
-    setLibcallName(RTLIB::COS_F128, "cosf128");
-    setLibcallName(RTLIB::POW_F128, "powf128");
-    setLibcallName(RTLIB::FMIN_F128, "fminf128");
-    setLibcallName(RTLIB::FMAX_F128, "fmaxf128");
-    setLibcallName(RTLIB::POWI_F128, "__powikf2");
-    setLibcallName(RTLIB::REM_F128, "fmodf128");
-  }
 
   // With 32 condition bits, we don't need to sink (and duplicate) compares
   // aggressively in CodeGenPrep.
   if (Subtarget.useCRBits()) {
     setHasMultipleConditionRegisters();
     setJumpIsExpensive();
   }
 
SDValue PPCTargetLowering::LowerFP_TO_INTDirectMove(SDValue Op,
   }
   return Tmp;
 }
 
 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
                                           const SDLoc &dl) const {
 
   // FP to INT conversions are legal for f128.
-  if (EnableQuadPrecision && (Op->getOperand(0).getValueType() == MVT::f128))
+  if (Op->getOperand(0).getValueType() == MVT::f128)
     return Op;
 
   // Expand ppcf128 to i32 by hand for the benefit of llvm-gcc bootstrap on
   // PPC (the libcall is not available).
   if (Op.getOperand(0).getValueType() == MVT::ppcf128) {
     if (Op.getValueType() == MVT::i32) {
       if (Op.getOpcode() == ISD::FP_TO_SINT) {
         SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
 
   EVT InVT = Op.getOperand(0).getValueType();
   EVT OutVT = Op.getValueType();
   if (OutVT.isVector() && OutVT.isFloatingPoint() &&
       isOperationCustom(Op.getOpcode(), InVT))
     return LowerINT_TO_FPVector(Op, DAG, dl);
 
   // Conversions to f128 are legal.
-  if (EnableQuadPrecision && (Op.getValueType() == MVT::f128))
+  if (Op.getValueType() == MVT::f128)
     return Op;
 
   if (Subtarget.hasQPX() && Op.getOperand(0).getValueType() == MVT::v4i1) {
     if (Op.getValueType() != MVT::v4f32 && Op.getValueType() != MVT::v4f64)
       return SDValue();
 
     SDValue Value = Op.getOperand(0);
     // The values are now known to be -1 (false) or 1 (true). To convert this

 }
 
 // Lower BITCAST(f128, (build_pair i64, i64)) to BUILD_FP128.
 SDValue PPCTargetLowering::LowerBITCAST(SDValue Op, SelectionDAG &DAG) const {
 
   SDLoc dl(Op);
   SDValue Op0 = Op->getOperand(0);
 
-  if (!EnableQuadPrecision ||
-      (Op.getValueType() != MVT::f128 ) ||
+  if ((Op.getValueType() != MVT::f128) ||
       (Op0.getOpcode() != ISD::BUILD_PAIR) ||
-      (Op0.getOperand(0).getValueType() !=  MVT::i64) ||
+      (Op0.getOperand(0).getValueType() != MVT::i64) ||
       (Op0.getOperand(1).getValueType() != MVT::i64))
     return SDValue();
 
   return DAG.getNode(PPCISD::BUILD_FP128, dl, MVT::f128, Op0.getOperand(0),
                      Op0.getOperand(1));
 }
 
 static const SDValue *getNormalLoadInput(const SDValue &Op) {

 
 bool PPCTargetLowering::isFMAFasterThanFMulAndFAdd(const Function &F,
                                                    Type *Ty) const {
   switch (Ty->getScalarType()->getTypeID()) {
   case Type::FloatTyID:
   case Type::DoubleTyID:
     return true;
   case Type::FP128TyID:
-    return EnableQuadPrecision && Subtarget.hasP9Vector();
+    return Subtarget.hasP9Vector();
   default:
     return false;
   }
 }
 
 // Currently this is a copy from AArch64TargetLowering::isProfitableToHoist.
 // FIXME: add more patterns which are profitable to hoist.
 bool PPCTargetLowering::isProfitableToHoist(Instruction *I) const {

llvm/test/CodeGen/PowerPC/builtins-ppc-p9-f128.ll

-; RUN: llc -verify-machineinstrs -mcpu=pwr9 -enable-ppc-quad-precision \
-; RUN:   -mtriple=powerpc64le-unknown-unknown -ppc-vsr-nums-as-vr \
-; RUN:   -ppc-asm-full-reg-names < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s
 
 @A = common global fp128 0xL00000000000000000000000000000000, align 16
 @B = common global fp128 0xL00000000000000000000000000000000, align 16
 @C = common global fp128 0xL00000000000000000000000000000000, align 16
 @D = common global fp128 0xL00000000000000000000000000000000, align 16
 
 define fp128 @testSqrtOdd(fp128 %a) {
 entry:

 ; CHECK: xsaddqpo v2, v2, v3
 ; CHECK: blr
 }
 
 declare fp128 @llvm.ppc.addf128.round.to.odd(fp128, fp128)
 
 define fp128 @testSubOdd(fp128 %a, fp128 %b) {
 entry:
   %0 = call fp128 @llvm.ppc.subf128.round.to.odd(fp128 %a, fp128 %b)
   ret fp128 %0
 ; CHECK-LABEL: testSubOdd
 ; CHECK: xssubqpo v2, v2, v3
 ; CHECK: blr
 }
 
 ; Function Attrs: nounwind readnone
 declare fp128 @llvm.ppc.subf128.round.to.odd(fp128, fp128)

llvm/test/CodeGen/PowerPC/constant-pool.ll

 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
-; RUN:   -mcpu=future -enable-ppc-quad-precision -ppc-asm-full-reg-names \
-; RUN:   < %s | FileCheck %s
+; RUN:   -mcpu=future -ppc-asm-full-reg-names < %s | FileCheck %s
 
  define float @FloatConstantPool() {
 ; CHECK-LABEL: FloatConstantPool:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    plfs f1, .LCPI0_0@PCREL(0), 1
 entry:
   ret float 0x380FFFF840000000
 }

llvm/test/CodeGen/PowerPC/f128-aggregates.ll

 ; RUN: llc -relocation-model=pic -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
-; RUN:   -enable-ppc-quad-precision -verify-machineinstrs \
-; RUN:   -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s
+; RUN:   -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s \
+; RUN:   | FileCheck %s
 ; RUN: llc -relocation-model=pic -mcpu=pwr9 -mtriple=powerpc64-unknown-unknown \
-; RUN:   -enable-ppc-quad-precision -verify-machineinstrs \
-; RUN:   -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s \
+; RUN:   -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s \
 ; RUN:   | FileCheck -check-prefix=CHECK-BE %s
 
 ; Testing homogeneous aggregates.
 
 %struct.With9fp128params = type { fp128, fp128, fp128, fp128, fp128, fp128,
                                   fp128, fp128, fp128 }
 
 @a1 = local_unnamed_addr global [3 x fp128] zeroinitializer, align 16

llvm/test/CodeGen/PowerPC/f128-arith.ll

-; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
-; RUN:   -enable-ppc-quad-precision -verify-machineinstrs \
+; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown -verify-machineinstrs \
 ; RUN:   -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s
 
 ; Function Attrs: norecurse nounwind
 define void @qpAdd(fp128* nocapture readonly %a, fp128* nocapture %res) {
 entry:
   %0 = load fp128, fp128* %a, align 16
   %add = fadd fp128 %0, %0
   store fp128 %add, fp128* %res, align 16

llvm/test/CodeGen/PowerPC/f128-bitcast.ll

-; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
-; RUN:   -enable-ppc-quad-precision -verify-machineinstrs \
+; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown -verify-machineinstrs \
 ; RUN:   -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s
-; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-unknown-unknown \
-; RUN:   -enable-ppc-quad-precision -verify-machineinstrs \
-; RUN:   -ppc-asm-full-reg-names \
-; RUN:   -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-BE
+; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-unknown-unknown -verify-machineinstrs \
+; RUN:   -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
+; RUN:   FileCheck %s --check-prefix=CHECK-BE
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @getPart1(fp128 %in) local_unnamed_addr {
 entry:
   %0 = bitcast fp128 %in to i128
   %a.sroa.0.0.extract.trunc = trunc i128 %0 to i64
   ret i64 %a.sroa.0.0.extract.trunc
 ; CHECK-LABEL: getPart1

llvm/test/CodeGen/PowerPC/f128-compare.ll

-; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
-; RUN:   -enable-ppc-quad-precision -verify-machineinstrs \
+; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown -verify-machineinstrs \
 ; RUN:   -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s
 
 @a_qp = common global fp128 0xL00000000000000000000000000000000, align 16
 @b_qp = common global fp128 0xL00000000000000000000000000000000, align 16
 
 ; Function Attrs: noinline nounwind optnone
 define signext i32 @greater_qp() {
 entry:

llvm/test/CodeGen/PowerPC/f128-conv.ll

 ; RUN: llc -relocation-model=pic -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
-; RUN:   -enable-ppc-quad-precision -ppc-vsr-nums-as-vr \
-; RUN:   -verify-machineinstrs -ppc-asm-full-reg-names < %s | FileCheck %s
+; RUN:   -ppc-vsr-nums-as-vr -verify-machineinstrs -ppc-asm-full-reg-names < %s \
+; RUN:   | FileCheck %s
 
 @mem = global [5 x i64] [i64 56, i64 63, i64 3, i64 5, i64 6], align 8
 @umem = global [5 x i64] [i64 560, i64 100, i64 34, i64 2, i64 5], align 8
 @swMem = global [5 x i32] [i32 5, i32 2, i32 3, i32 4, i32 0], align 4
 @uwMem = global [5 x i32] [i32 5, i32 2, i32 3, i32 4, i32 0], align 4
 @uhwMem = local_unnamed_addr global [5 x i16] [i16 5, i16 2, i16 3, i16 4, i16 0], align 2
 @ubMem = local_unnamed_addr global [5 x i8] c"\05\02\03\04\00", align 1
 

llvm/test/CodeGen/PowerPC/f128-fma.ll

 ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
-; RUN:   -enable-ppc-quad-precision -ppc-vsr-nums-as-vr \
-; RUN:   -ppc-asm-full-reg-names < %s | FileCheck %s
+; RUN:   -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s
 
 define void @qpFmadd(fp128* nocapture readonly %a, fp128* nocapture %b,
                    fp128* nocapture readonly %c, fp128* nocapture %res) {
 entry:
   %0 = load fp128, fp128* %a, align 16
   %1 = load fp128, fp128* %b, align 16
   %2 = load fp128, fp128* %c, align 16
   %madd = tail call fp128 @llvm.fmuladd.f128(fp128 %0, fp128 %1, fp128 %2)

llvm/test/CodeGen/PowerPC/f128-passByValue.ll

-; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
-; RUN:   -enable-ppc-quad-precision -ppc-vsr-nums-as-vr \
+; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown -ppc-vsr-nums-as-vr \
 ; RUN:   -verify-machineinstrs -ppc-asm-full-reg-names < %s | FileCheck %s
 
 ; Function Attrs: norecurse nounwind readnone
 define fp128 @loadConstant() {
 ; CHECK-LABEL: loadConstant:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis r[[REG0:[0-9]+]], r2, .LCPI0_0@toc@ha
 ; CHECK-NEXT:    addi r[[REG0]], r[[REG0]], .LCPI0_0@toc@l

llvm/test/CodeGen/PowerPC/f128-rounding.ll

-; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
-; RUN:   -enable-ppc-quad-precision -verify-machineinstrs \
+; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown -verify-machineinstrs \
 ; RUN:   -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s
 
 
 define void @qp_trunc(fp128* nocapture readonly %a, fp128* nocapture %res) {
 entry:
   %0 = load fp128, fp128* %a, align 16
   %1 = tail call fp128 @llvm.trunc.f128(fp128 %0)
   store fp128 %1, fp128* %res, align 16

llvm/test/CodeGen/PowerPC/f128-truncateNconv.ll

 ; RUN: llc -relocation-model=pic -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
-; RUN:   -verify-machineinstrs -enable-ppc-quad-precision \
-; RUN:   -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s
+; RUN:   -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s \
+; RUN:   | FileCheck %s
 
 @f128Array = global [4 x fp128] [fp128 0xL00000000000000004004C00000000000,
                                  fp128 0xLF000000000000000400808AB851EB851,
                                  fp128 0xL5000000000000000400E0C26324C8366,
                                  fp128 0xL8000000000000000400A24E2E147AE14],
                                 align 16
 
 ; Function Attrs: norecurse nounwind readonly

llvm/test/CodeGen/PowerPC/f128-vecExtractNconv.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown -ppc-vsr-nums-as-vr \
 ; RUN:   -relocation-model=pic -ppc-asm-full-reg-names -verify-machineinstrs \
-; RUN:   -enable-ppc-quad-precision < %s | FileCheck %s
+; RUN:   < %s | FileCheck %s
 ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-unknown-unknown -ppc-vsr-nums-as-vr \
 ; RUN:   -ppc-asm-full-reg-names -verify-machineinstrs \
-; RUN:   -enable-ppc-quad-precision < %s | FileCheck %s -check-prefix=CHECK-BE
+; RUN:   < %s | FileCheck %s -check-prefix=CHECK-BE
 
 ; Vector extract DWord and convert to quad precision.
 
 @sdwVecMem = global <2 x i64> <i64 88, i64 99>, align 16
 @udwVecMem = global <2 x i64> <i64 88, i64 99>, align 16
 
 ; Function Attrs: norecurse nounwind
 define void @sdwVecConv2qp(fp128* nocapture %a, <2 x i64> %b) {

llvm/test/CodeGen/PowerPC/float-load-store-pair.ll

 ; CHECK-NEXT:    lfd 7, a7@toc@l(3)
 ; CHECK-NEXT:    addis 3, 2, a8@toc@ha
 ; CHECK-NEXT:    lfd 8, a8@toc@l(3)
 ; CHECK-NEXT:    addis 3, 2, a9@toc@ha
 ; CHECK-NEXT:    lfd 9, a9@toc@l(3)
 ; CHECK-NEXT:    addis 3, 2, a10@toc@ha
 ; CHECK-NEXT:    lfd 10, a10@toc@l(3)
 ; CHECK-NEXT:    addis 3, 2, a11@toc@ha
-; CHECK-NEXT:    addis 6, 2, a17@toc@ha
+; CHECK-NEXT:    lfd 11, a11@toc@l(3)
+; CHECK-NEXT:    addis 3, 2, a12@toc@ha
 ; CHECK-NEXT:    addis 5, 2, a16@toc@ha
+; CHECK-NEXT:    addis 6, 2, a17@toc@ha
 ; CHECK-NEXT:    addi 6, 6, a17@toc@l
-; CHECK-NEXT:    addi 5, 5, a16@toc@l
 ; CHECK-NEXT:    lxvx 34, 0, 6
+; CHECK-NEXT:    lfd 12, a12@toc@l(3)
+; CHECK-NEXT:    addis 3, 2, a13@toc@ha
+; CHECK-NEXT:    addi 5, 5, a16@toc@l
 ; CHECK-NEXT:    addis 4, 2, a15@toc@ha
 ; CHECK-NEXT:    lxvx 0, 0, 5
 ; CHECK-NEXT:    ld 4, a15@toc@l(4)
-; CHECK-NEXT:    li 5, 168
-; CHECK-NEXT:    lfd 11, a11@toc@l(3)
-; CHECK-NEXT:    addis 3, 2, a12@toc@ha
-; CHECK-NEXT:    lfd 12, a12@toc@l(3)
-; CHECK-NEXT:    addis 3, 2, a13@toc@ha
+; CHECK-NEXT:    li 5, 152
 ; CHECK-NEXT:    lfd 13, a13@toc@l(3)
 ; CHECK-NEXT:    addis 3, 2, a14@toc@ha
 ; CHECK-NEXT:    ld 3, a14@toc@l(3)
-; CHECK-NEXT:    stxvx 34, 1, 5
-; CHECK-NEXT:    li 5, 152
 ; CHECK-NEXT:    stxvx 0, 1, 5
 ; CHECK-NEXT:    std 4, 144(1)
 ; CHECK-NEXT:    std 3, 136(1)
 ; CHECK-NEXT:    bl _Z3fooddddddddddddddd
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    addi 1, 1, 192
 ; CHECK-NEXT:    ld 0, 16(1)

llvm/test/CodeGen/PowerPC/fp-strict-f128.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s -mtriple=powerpc64le-unknown-linux -mcpu=pwr9 -enable-ppc-quad-precision=true | FileCheck %s
+; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
+; RUN:   < %s -mtriple=powerpc64le-unknown-linux -mcpu=pwr9 | FileCheck %s
 
 declare fp128 @llvm.experimental.constrained.fadd.f128(fp128, fp128, metadata, metadata)
 declare fp128 @llvm.experimental.constrained.fsub.f128(fp128, fp128, metadata, metadata)
 declare fp128 @llvm.experimental.constrained.fmul.f128(fp128, fp128, metadata, metadata)
 declare fp128 @llvm.experimental.constrained.fdiv.f128(fp128, fp128, metadata, metadata)
 
 declare fp128 @llvm.experimental.constrained.fma.f128(fp128, fp128, fp128, metadata, metadata)
 declare fp128 @llvm.experimental.constrained.sqrt.f128(fp128, metadata, metadata)

llvm/test/CodeGen/PowerPC/global-address-non-got-indirect-access.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
-; RUN:   -mcpu=future -enable-ppc-quad-precision -ppc-asm-full-reg-names \
-; RUN:   -ppc-vsr-nums-as-vr < %s | FileCheck %s
+; RUN:   -mcpu=future -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s \
+; RUN:   | FileCheck %s
 
  @_ZL13StaticBoolVar = internal unnamed_addr global i8 0, align 1
 @_ZL19StaticSignedCharVar = internal unnamed_addr global i8 0, align 1
 @_ZL21StaticUnsignedCharVar = internal unnamed_addr global i8 0, align 1
 @_ZL20StaticSignedShortVar = internal unnamed_addr global i16 0, align 2
 @_ZL22StaticUnsignedShortVar = internal unnamed_addr global i16 0, align 2
 @_ZL18StaticSignedIntVar = internal unnamed_addr global i32 0, align 4
 @_ZL20StaticUnsignedIntVar = internal unnamed_addr global i32 0, align 4

llvm/test/CodeGen/PowerPC/pcrel-got-indirect.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
-; RUN:   -mcpu=future -enable-ppc-quad-precision -ppc-asm-full-reg-names \
-; RUN:   -ppc-vsr-nums-as-vr < %s | FileCheck %s
+; RUN:   -mcpu=future -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s \
+; RUN:   | FileCheck %s
 
 %struct.Struct = type { i8, i16, i32 }
 
 @valChar = external local_unnamed_addr global i8, align 1
 @valShort = external local_unnamed_addr global i16, align 2
 @valInt = external global i32, align 4
 @valUnsigned = external local_unnamed_addr global i32, align 4
 @valLong = external local_unnamed_addr global i64, align 8

llvm/test/CodeGen/PowerPC/ppc64-P9-setb.ll

 ; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
-; RUN:   -enable-ppc-quad-precision -ppc-asm-full-reg-names < %s | FileCheck %s
+; RUN:   -ppc-asm-full-reg-names < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown \
 ; RUN:   -ppc-asm-full-reg-names < %s | FileCheck %s -check-prefix=CHECK-PWR8    \
 ; RUN:   -implicit-check-not "\<setb\>"
 
 ; Test different patterns with type i64
 
 ; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setne)), setlt
 define i64 @setb1(i64 %a, i64 %b) {

llvm/test/CodeGen/PowerPC/recipest.ll

 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    addi 1, 1, 32
 ; CHECK-P8-NEXT:    ld 0, 16(1)
 ; CHECK-P8-NEXT:    mtlr 0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: hoo5_fmf:
 ; CHECK-P9:       # %bb.0:
-; CHECK-P9-NEXT:    mflr 0
-; CHECK-P9-NEXT:    std 0, 16(1)
-; CHECK-P9-NEXT:    stdu 1, -32(1)
-; CHECK-P9-NEXT:    bl sqrtl
-; CHECK-P9-NEXT:    nop
-; CHECK-P9-NEXT:    addi 1, 1, 32
-; CHECK-P9-NEXT:    ld 0, 16(1)
-; CHECK-P9-NEXT:    mtlr 0
+; CHECK-P9-NEXT:    xssqrtqp 2, 2
 ; CHECK-P9-NEXT:    blr
   %r = call reassoc ninf afn fp128 @llvm.sqrt.f128(fp128 %a)
   ret fp128 %r
 }
 
 define fp128 @hoo5_safe(fp128 %a) #1 {
 ; CHECK-P7-LABEL: hoo5_safe:
 ; CHECK-P7:       # %bb.0:

 ; CHECK-P8-NEXT:    nop
 ; CHECK-P8-NEXT:    addi 1, 1, 32
 ; CHECK-P8-NEXT:    ld 0, 16(1)
 ; CHECK-P8-NEXT:    mtlr 0
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P9-LABEL: hoo5_safe:
 ; CHECK-P9:       # %bb.0:
-; CHECK-P9-NEXT:    mflr 0
-; CHECK-P9-NEXT:    std 0, 16(1)
-; CHECK-P9-NEXT:    stdu 1, -32(1)
-; CHECK-P9-NEXT:    bl sqrtl
-; CHECK-P9-NEXT:    nop
-; CHECK-P9-NEXT:    addi 1, 1, 32
-; CHECK-P9-NEXT:    ld 0, 16(1)
-; CHECK-P9-NEXT:    mtlr 0
+; CHECK-P9-NEXT:    xssqrtqp 2, 2
 ; CHECK-P9-NEXT:    blr
   %r = call fp128 @llvm.sqrt.f128(fp128 %a)
   ret fp128 %r
 }
 
 attributes #0 = { nounwind "reciprocal-estimates"="sqrtf:0,sqrtd:0" }
 attributes #1 = { nounwind "denormal-fp-math"="preserve-sign,preserve-sign" }