[PowerPC] Implement Move to VSR Mask builtins in LLVM/Clang

[amyk]

Summary

This patch implements the vec_gen[b|h|w|d|q]m function prototypes in altivec.h in order
to utilize the move to VSR with mask instructions introduced in Power10.

Depends on D82675.

[amyk]

I will need to update this patch to remove the instruction definition and MC tests.

[amyk]

Rebased patch, and removed MC tests from the original patch.

[amyk]

Ping.

[amyk]

Ping.

[steven.zhang]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

10054 ↗

(On Diff #283113)

Can we handle this inside the .td ? i.e. change the definition of the instr as:

def MTVSRBMI : DXForm<4, 10, (outs vrrc:$vD), (ins u8imm64:$D),
                      "mtvsrbmi $vD, $D", IIC_VecGeneral,
                      [(set v16i8:$vD,
                            (int_ppc_altivec_mtvsrbm imm:$D))]>;

And add the missing u8imm64 as what we did for u16imm64 ?

[amyk]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

10054 ↗

(On Diff #283113)

I actually made a mistake when I was implementing this patch. The immediate should fit within 16-bits and not 8-bits. Sorry about that. I will update the patch to remove this handling as it is unnecessary and not correct.

[amyk]

• Rebased patch.
• Update patch to remove unnecessary immediate handling.

[steven.zhang]

LGTM.

clang/include/clang/Basic/BuiltinsPPC.def

 BUILTIN(__builtin_altivec_vexpandqm, "V1ULLLiV1ULLLi", "")
 
 // P10 Vector Count with Mask built-ins.
 BUILTIN(__builtin_altivec_vcntmbb, "ULLiV16UcUi", "")
 BUILTIN(__builtin_altivec_vcntmbh, "ULLiV8UsUi", "")
 BUILTIN(__builtin_altivec_vcntmbw, "ULLiV4UiUi", "")
 BUILTIN(__builtin_altivec_vcntmbd, "ULLiV2ULLiUi", "")
 
+// P10 Move to VSR with Mask built-ins.
+BUILTIN(__builtin_altivec_mtvsrbm, "V16UcULLi", "")
+BUILTIN(__builtin_altivec_mtvsrhm, "V8UsULLi", "")
+BUILTIN(__builtin_altivec_mtvsrwm, "V4UiULLi", "")
+BUILTIN(__builtin_altivec_mtvsrdm, "V2ULLiULLi", "")
+BUILTIN(__builtin_altivec_mtvsrqm, "V1ULLLiULLi", "")
+
 // P10 Vector Parallel Bits built-ins.
 BUILTIN(__builtin_altivec_vpdepd, "V2ULLiV2ULLiV2ULLi", "")
 BUILTIN(__builtin_altivec_vpextd, "V2ULLiV2ULLiV2ULLi", "")
 
 // P10 Vector Centrifuge built-in.
 BUILTIN(__builtin_altivec_vcfuged, "V2ULLiV2ULLiV2ULLi", "")
 
 // P10 Vector Gather Every N-th Bit built-in.

clang/lib/Headers/altivec.h

_Generic((__a), vector unsigned char                                         \
            : __builtin_altivec_vcntmbb((__a), (unsigned int)(__mp)),           \
              vector unsigned short                                             \
            : __builtin_altivec_vcntmbh((__a), (unsigned int)(__mp)),           \
              vector unsigned int                                               \
            : __builtin_altivec_vcntmbw((__a), (unsigned int)(__mp)),           \
              vector unsigned long long                                         \
            : __builtin_altivec_vcntmbd((__a), (unsigned int)(__mp)))
 
+/* vec_gen[b|h|w|d|q]m */
+
+static __inline__ vector unsigned char __ATTRS_o_ai
+vec_genbm(unsigned long long __bm) {
+  return __builtin_altivec_mtvsrbm(__bm);
+}
+
+static __inline__ vector unsigned short __ATTRS_o_ai
+vec_genhm(unsigned long long __bm) {
+  return __builtin_altivec_mtvsrhm(__bm);
+}
+
+static __inline__ vector unsigned int __ATTRS_o_ai
+vec_genwm(unsigned long long __bm) {
+  return __builtin_altivec_mtvsrwm(__bm);
+}
+
+static __inline__ vector unsigned long long __ATTRS_o_ai
+vec_gendm(unsigned long long __bm) {
+  return __builtin_altivec_mtvsrdm(__bm);
+}
+
+static __inline__ vector unsigned __int128 __ATTRS_o_ai
+vec_genqm(unsigned long long __bm) {
+  return __builtin_altivec_mtvsrqm(__bm);
+}
+
 /* vec_pdep */
 
 static __inline__ vector unsigned long long __ATTRS_o_ai
 vec_pdep(vector unsigned long long __a, vector unsigned long long __b) {
   return __builtin_altivec_vpdepd(__a, __b);
 }
 
 /* vec_pext */

clang/test/CodeGen/builtins-ppc-p10vector.c

 }
 
 unsigned long long test_vec_cntm_ull(void) {
   // CHECK: @llvm.ppc.altivec.vcntmbd(<2 x i64> %{{.+}}, i32
   // CHECK-NEXT: ret i64
   return vec_cntm(vulla, 0);
 }
 
+vector unsigned char test_vec_genbm(void) {
+  // CHECK: @llvm.ppc.altivec.mtvsrbm(i64 %{{.+}})
+  // CHECK-NEXT: ret <16 x i8>
+  return vec_genbm(ulla);
+}
+
+vector unsigned char test_vec_genbm_imm(void) {
+  // CHECK: store i64 1
+  // CHECK: @llvm.ppc.altivec.mtvsrbm(i64 %{{.+}})
+  // CHECK-NEXT: ret <16 x i8>
+  return vec_genbm(1);
+}
+
+vector unsigned char test_vec_genbm_imm2(void) {
+  // CHECK: store i64 255
+  // CHECK: @llvm.ppc.altivec.mtvsrbm(i64 %{{.+}})
+  // CHECK-NEXT: ret <16 x i8>
+  return vec_genbm(255);
+}
+
+vector unsigned char test_vec_genbm_imm3(void) {
+  // CHECK: store i64 65535
+  // CHECK: @llvm.ppc.altivec.mtvsrbm(i64 %{{.+}})
+  // CHECK-NEXT: ret <16 x i8>
+  return vec_genbm(65535);
+}
+
+vector unsigned char test_vec_genbm_imm4(void) {
+  // CHECK: store i64 65536
+  // CHECK: @llvm.ppc.altivec.mtvsrbm(i64 %{{.+}})
+  // CHECK-NEXT: ret <16 x i8>
+  return vec_genbm(65536);
+}
+
+vector unsigned char test_vec_genbm_imm5(void) {
+  // CHECK: store i64 65546
+  // CHECK: @llvm.ppc.altivec.mtvsrbm(i64 %{{.+}})
+  // CHECK-NEXT: ret <16 x i8>
+  return vec_genbm(65546);
+}
+
+vector unsigned short test_vec_genhm(void) {
+  // CHECK: @llvm.ppc.altivec.mtvsrhm(i64 %{{.+}})
+  // CHECK-NEXT: ret <8 x i16>
+  return vec_genhm(ulla);
+}
+
+vector unsigned int test_vec_genwm(void) {
+  // CHECK: @llvm.ppc.altivec.mtvsrwm(i64 %{{.+}})
+  // CHECK-NEXT: ret <4 x i32>
+  return vec_genwm(ulla);
+}
+
+vector unsigned long long test_vec_gendm(void) {
+  // CHECK: @llvm.ppc.altivec.mtvsrdm(i64 %{{.+}})
+  // CHECK-NEXT: ret <2 x i64>
+  return vec_gendm(ulla);
+}
+
+vector unsigned __int128 test_vec_genqm(void) {
+  // CHECK: @llvm.ppc.altivec.mtvsrqm(i64 %{{.+}})
+  // CHECK-NEXT: ret <1 x i128>
+  return vec_genqm(ulla);
+}
+
 unsigned long long test_vgnb_1(void) {
   // CHECK: @llvm.ppc.altivec.vgnb(<1 x i128> %{{.+}}, i32 2)
   // CHECK-NEXT: ret i64
   return vec_gnb(vui128a, 2);
 }
 
 unsigned long long test_vgnb_2(void) {
   // CHECK: @llvm.ppc.altivec.vgnb(<1 x i128> %{{.+}}, i32 7)

llvm/include/llvm/IR/IntrinsicsPowerPC.td

def int_ppc_altivec_vcntmbh : GCCBuiltin<"__builtin_altivec_vcntmbh">,
                         [IntrNoMem, ImmArg<ArgIndex<1>>]>;
   def int_ppc_altivec_vcntmbw : GCCBuiltin<"__builtin_altivec_vcntmbw">,
               Intrinsic<[llvm_i64_ty], [llvm_v4i32_ty, llvm_i32_ty],
                         [IntrNoMem, ImmArg<ArgIndex<1>>]>;
   def int_ppc_altivec_vcntmbd : GCCBuiltin<"__builtin_altivec_vcntmbd">,
               Intrinsic<[llvm_i64_ty], [llvm_v2i64_ty, llvm_i32_ty],
                         [IntrNoMem, ImmArg<ArgIndex<1>>]>;
 
+  // P10 Move to VSR with Mask Intrinsics.
+  def int_ppc_altivec_mtvsrbm : GCCBuiltin<"__builtin_altivec_mtvsrbm">,
+              Intrinsic<[llvm_v16i8_ty], [llvm_i64_ty], [IntrNoMem]>;
+  def int_ppc_altivec_mtvsrhm : GCCBuiltin<"__builtin_altivec_mtvsrhm">,
+              Intrinsic<[llvm_v8i16_ty], [llvm_i64_ty], [IntrNoMem]>;
+  def int_ppc_altivec_mtvsrwm : GCCBuiltin<"__builtin_altivec_mtvsrwm">,
+              Intrinsic<[llvm_v4i32_ty], [llvm_i64_ty], [IntrNoMem]>;
+  def int_ppc_altivec_mtvsrdm : GCCBuiltin<"__builtin_altivec_mtvsrdm">,
+              Intrinsic<[llvm_v2i64_ty], [llvm_i64_ty], [IntrNoMem]>;
+  def int_ppc_altivec_mtvsrqm : GCCBuiltin<"__builtin_altivec_mtvsrqm">,
+              Intrinsic<[llvm_v1i128_ty], [llvm_i64_ty], [IntrNoMem]>;
+
   // P10 Vector Parallel Bits Deposit/Extract Doubleword Builtins.
   def int_ppc_altivec_vpdepd : GCCBuiltin<"__builtin_altivec_vpdepd">,
               Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
                         [IntrNoMem]>;
   def int_ppc_altivec_vpextd : GCCBuiltin<"__builtin_altivec_vpextd">,
               Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
                         [IntrNoMem]>;
 

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

def VEXPANDDM : VXForm_RD5_XO5_RS5<1602, 3, (outs vrrc:$vD), (ins vrrc:$vB),
                                      [(set v2i64:$vD, (int_ppc_altivec_vexpanddm
                                            v2i64:$vB))]>;
   def VEXPANDQM : VXForm_RD5_XO5_RS5<1602, 4, (outs vrrc:$vD), (ins vrrc:$vB),
                                      "vexpandqm $vD, $vB", IIC_VecGeneral,
                                      [(set v1i128:$vD, (int_ppc_altivec_vexpandqm
                                            v1i128:$vB))]>;
   def MTVSRBM : VXForm_RD5_XO5_RS5<1602, 16, (outs vrrc:$vD), (ins g8rc:$rB),
                                    "mtvsrbm $vD, $rB", IIC_VecGeneral,
-                                   []>;
+                                   [(set v16i8:$vD,
+                                         (int_ppc_altivec_mtvsrbm i64:$rB))]>;
   def MTVSRHM : VXForm_RD5_XO5_RS5<1602, 17, (outs vrrc:$vD), (ins g8rc:$rB),
                                    "mtvsrhm $vD, $rB", IIC_VecGeneral,
-                                   []>;
+                                   [(set v8i16:$vD,
+                                         (int_ppc_altivec_mtvsrhm i64:$rB))]>;
   def MTVSRWM : VXForm_RD5_XO5_RS5<1602, 18, (outs vrrc:$vD), (ins g8rc:$rB),
                                    "mtvsrwm $vD, $rB", IIC_VecGeneral,
-                                   []>;
+                                   [(set v4i32:$vD,
+                                         (int_ppc_altivec_mtvsrwm i64:$rB))]>;
   def MTVSRDM : VXForm_RD5_XO5_RS5<1602, 19, (outs vrrc:$vD), (ins g8rc:$rB),
                                    "mtvsrdm $vD, $rB", IIC_VecGeneral,
-                                   []>;
+                                   [(set v2i64:$vD,
+                                         (int_ppc_altivec_mtvsrdm i64:$rB))]>;
   def MTVSRQM : VXForm_RD5_XO5_RS5<1602, 20, (outs vrrc:$vD), (ins g8rc:$rB),
                                    "mtvsrqm $vD, $rB", IIC_VecGeneral,
-                                   []>;
+                                   [(set v1i128:$vD,
+                                         (int_ppc_altivec_mtvsrqm i64:$rB))]>;
   def MTVSRBMI : DXForm<4, 10, (outs vrrc:$vD), (ins u16imm64:$D),
                         "mtvsrbmi $vD, $D", IIC_VecGeneral,
-                        []>;
+                        [(set v16i8:$vD,
+                              (int_ppc_altivec_mtvsrbm imm:$D))]>;
   def VCNTMBB : VXForm_RD5_MP_VB5<1602, 12, (outs g8rc:$rD),
                                   (ins vrrc:$vB, u1imm:$MP),
                                   "vcntmbb $rD, $vB, $MP", IIC_VecGeneral,
                                   [(set i64:$rD, (int_ppc_altivec_vcntmbb
                                         v16i8:$vB, timm:$MP))]>;
   def VCNTMBH : VXForm_RD5_MP_VB5<1602, 13, (outs g8rc:$rD),
                                   (ins vrrc:$vB, u1imm:$MP),
                                   "vcntmbh $rD, $vB, $MP", IIC_VecGeneral,

llvm/test/CodeGen/PowerPC/p10-vector-mask-ops.ll

 ; CHECK-LABEL: test_vcntmbd:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vcntmbd r3, v2, 0
 ; CHECK-NEXT:    blr
 entry:
   %cnt = tail call i64 @llvm.ppc.altivec.vcntmbd(<2 x i64> %a, i32 0)
   ret i64 %cnt
 }
+
+declare <16 x i8> @llvm.ppc.altivec.mtvsrbm(i64)
+declare <8 x i16> @llvm.ppc.altivec.mtvsrhm(i64)
+declare <4 x i32> @llvm.ppc.altivec.mtvsrwm(i64)
+declare <2 x i64> @llvm.ppc.altivec.mtvsrdm(i64)
+declare <1 x i128> @llvm.ppc.altivec.mtvsrqm(i64)
+
+define <16 x i8>  @test_mtvsrbm(i64 %a) {
+; CHECK-LABEL: test_mtvsrbm:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mtvsrbm v2, r3
+; CHECK-NEXT:    blr
+entry:
+  %mv = tail call <16 x i8> @llvm.ppc.altivec.mtvsrbm(i64 %a)
+  ret <16 x i8> %mv
+}
+
+define <16 x i8>  @test_mtvsrbmi() {
+; CHECK-LABEL: test_mtvsrbmi:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mtvsrbmi v2, 1
+; CHECK-NEXT:    blr
+entry:
+  %mv = tail call <16 x i8> @llvm.ppc.altivec.mtvsrbm(i64 1)
+  ret <16 x i8> %mv
+}
+
+define <16 x i8>  @test_mtvsrbmi2() {
+; CHECK-LABEL: test_mtvsrbmi2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mtvsrbmi v2, 255
+; CHECK-NEXT:    blr
+entry:
+  %mv = tail call <16 x i8> @llvm.ppc.altivec.mtvsrbm(i64 255)
+  ret <16 x i8> %mv
+}
+
+define <16 x i8>  @test_mtvsrbmi3() {
+; CHECK-LABEL: test_mtvsrbmi3:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mtvsrbmi v2, 65535
+; CHECK-NEXT:    blr
+entry:
+  %mv = tail call <16 x i8> @llvm.ppc.altivec.mtvsrbm(i64 65535)
+  ret <16 x i8> %mv
+}
+
+define <16 x i8>  @test_mtvsrbmi4() {
+; CHECK-LABEL: test_mtvsrbmi4:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mtvsrbmi v2, 0
+; CHECK-NEXT:    blr
+entry:
+  %mv = tail call <16 x i8> @llvm.ppc.altivec.mtvsrbm(i64 65536)
+  ret <16 x i8> %mv
+}
+
+define <16 x i8>  @test_mtvsrbmi5() {
+; CHECK-LABEL: test_mtvsrbmi5:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mtvsrbmi v2, 10
+; CHECK-NEXT:    blr
+entry:
+  %mv = tail call <16 x i8> @llvm.ppc.altivec.mtvsrbm(i64 65546)
+  ret <16 x i8> %mv
+}
+
+define <8 x i16> @test_mtvsrhm(i64 %a) {
+; CHECK-LABEL: test_mtvsrhm:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mtvsrhm v2, r3
+; CHECK-NEXT:    blr
+entry:
+  %mv = tail call <8 x i16> @llvm.ppc.altivec.mtvsrhm(i64 %a)
+  ret <8 x i16> %mv
+}
+
+define <4 x i32> @test_mtvsrwm(i64 %a) {
+; CHECK-LABEL: test_mtvsrwm:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mtvsrwm v2, r3
+; CHECK-NEXT:    blr
+entry:
+  %mv = tail call <4 x i32> @llvm.ppc.altivec.mtvsrwm(i64 %a)
+  ret <4 x i32> %mv
+}
+
+define <2 x i64> @test_mtvsrdm(i64 %a) {
+; CHECK-LABEL: test_mtvsrdm:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mtvsrdm v2, r3
+; CHECK-NEXT:    blr
+entry:
+  %mv = tail call <2 x i64> @llvm.ppc.altivec.mtvsrdm(i64 %a)
+  ret <2 x i64> %mv
+}
+
+define <1 x i128> @test_mtvsrqm(i64 %a) {
+; CHECK-LABEL: test_mtvsrqm:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mtvsrqm v2, r3
+; CHECK-NEXT:    blr
+entry:
+  %mv = tail call <1 x i128> @llvm.ppc.altivec.mtvsrqm(i64 %a)
+  ret <1 x i128> %mv
+}