[NFC][PPC][AIX] Add stack frame layout diagram to PPCISelLowering.cpp

[ZarkoCA]

Summary

This NFC patch adds a diagram of the AIX ABI stack frame layout.

Based on https://www.ibm.com/support/knowledgecenter/en/ssw_aix_72/assembler/idalangref_runtime_process.html

[sfertile]

Looks good Zarko. I think we should either flip this over to show the stack growing down, or keep it as is but add High Memory at the bottom and Low memory at the top to show the stack grows downwards.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

7204

Can we add something over on the right hand side to show which of these make up the linkage area? Something like:

--|
  |
  |
  |
  | Linkage Area
  |
  |
  |
  |
 --

7207

Minor nit: Conditional --> Condition

7235

minor nit: +---> should be +--- . The first makes it look like the backchains point to each other as opposed to each backchain pointing ot the previous backchain.

[ZarkoCA]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

7204

Good suggestion, we should definitely have that.

[ZarkoCA]

Addressed Sean's comments:

Fixed typos and labelled linkage area in the stack frame.

[ZarkoCA]

Added High/Low Memory labels to diagram.

[sfertile]

LGTM.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

if (PPC::G8RCRegClass.contains(Reg)) {
     assert(Reg >= PPC::X3 && Reg <= PPC::X10 &&
            "Reg must be a valid argument register!");
     return LASize + 8 * (Reg - PPC::X3);
   }
 
   llvm_unreachable("Only general purpose registers expected.");
 }
 
+//   AIX ABI Stack Frame Layout:
+//
+//   Low Memory +--------------------------------------------+
+//   SP   +---> | Back chain                                 | ---+
+//        |     +--------------------------------------------+    |   
+//        |     | Saved Condition Register                   |    |
+//        |     +--------------------------------------------+    |
+//        |     | Saved Linkage Register                     |    |
+//        |     +--------------------------------------------+    | Linkage Area
+//        |     | Reserved for compilers                     |    |
+//        |     +--------------------------------------------+    |
+//        |     | Reserved for binders                       |    |
+//        |     +--------------------------------------------+    |
+//        |     | Saved TOC pointer                          | ---+
+//        |     +--------------------------------------------+
+//        |     | Parameter save area                        |
+//        |     +--------------------------------------------+
+//        |     | Alloca space                               |
+//        |     +--------------------------------------------+
+//        |     | Local variable space                       |
+//        |     +--------------------------------------------+
+//        |     | Float/int conversion temporary             |
+//        |     +--------------------------------------------+
+//        |     | Save area for AltiVec registers            |
+//        |     +--------------------------------------------+
+//        |     | AltiVec alignment padding                  |
+//        |     +--------------------------------------------+
+//        |     | Save area for VRSAVE register              |
+//        |     +--------------------------------------------+
+//        |     | Save area for General Purpose registers    |
+//        |     +--------------------------------------------+
+//        |     | Save area for Floating Point registers     |
+//        |     +--------------------------------------------+
+//        +---- | Back chain                                 |
+// High Memory  +--------------------------------------------+
+//
+//  Specifications:
+//  AIX 7.2 Assembler Language Reference
+//  Subroutine linkage convention
+
 SDValue PPCTargetLowering::LowerFormalArguments_AIX(
     SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
     const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
     SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
 
   assert((CallConv == CallingConv::C || CallConv == CallingConv::Cold ||
           CallConv == CallingConv::Fast) &&
          "Unexpected calling convention!");

 
 SDValue PPCTargetLowering::LowerCall_AIX(
     SDValue Chain, SDValue Callee, CallFlags CFlags,
     const SmallVectorImpl<ISD::OutputArg> &Outs,
     const SmallVectorImpl<SDValue> &OutVals,
     const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
     SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
     const CallBase *CB) const {
+  // See PPCTargetLowering::LowerFormalArguments_AIX() for a description of the
+  // AIX ABI stack frame layout.
 
   assert((CFlags.CallConv == CallingConv::C ||
           CFlags.CallConv == CallingConv::Cold ||
           CFlags.CallConv == CallingConv::Fast) &&
          "Unexpected calling convention!");
 
   if (CFlags.IsPatchPoint)
     report_fatal_error("This call type is unimplemented on AIX.");