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Differential D81819

[PowerPC] Add InstAlias for those Rotate Instructions
Needs ReviewPublic

Authored by Esme on Jun 14 2020, 8:36 PM.

Details

Reviewers
efriedma
hfinkel
nemanjai
ZhangKang
Group Reviewers
Restricted Project
Summary

For some simple InstAlias, we can implement it in td files. But for some complex InstAlias,
td can't implement it, we should implement those complex InstAlias it in PPCInstrPrinter.cpp.
For example:

asm
sldi ra,rs,n (n < 64)    <=====>     rldicr ra,rs,n,63-n

This patch will implement some complex InstAlias in PPCInstrPrinter.cpp for below instructions:

RLDIMI: insrdi
RLWIMI: inslwi, insrwi
RLWINM: slwi srwi clrrwi clrlslwi extlwi extrwi
RLDIC: clrlsldi
RLDIC: srdi extrdi
RLDICR: sldi clrrdi extldi

Diff Detail

Revision Contents

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Diff 270655

llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp

Show First 20 Lines • Show All 86 Lines • ▼ Show 20 Lines if (TT.isOSAIX() &&
O << ", "; O << ", ";
printOperand(MI, 2, O); printOperand(MI, 2, O);
O << "("; O << "(";
printOperand(MI, 1, O); printOperand(MI, 1, O);
O << ")"; O << ")";
return; return;
} }
// Check for slwi/srwi mnemonics. // Check for RLDIMI mnemonics.
if (MI->getOpcode() == PPC::RLWINM) { if (MI->getOpcode() == PPC::RLDIMI || MI->getOpcode() == PPC::RLDIMI_rec) {
unsigned char SH = MI->getOperand(3).getImm();
unsigned char MB = MI->getOperand(4).getImm();
if (MB + SH < 64) {
// Check for insrdi
if (MI->getOpcode() == PPC::RLDIMI)
O << "\tinsrdi ";
else
O << "\tinsrdi. ";
SH = 64 - MB - SH;
// Op0 is same with Op1, but Op1 is input, Op0 is output.
printOperand(MI, 0, O);
O << ", ";
printOperand(MI, 2, O);
O << ", " << (unsigned int)SH;
O << ", " << (unsigned int)MB;
printAnnotation(O, Annot);
return;
}
}
// Check for RLWIMI mnemonics.
if (MI->getOpcode() == PPC::RLWIMI || MI->getOpcode() == PPC::RLWIMI_rec ||
MI->getOpcode() == PPC::RLWIMI8 || MI->getOpcode() == PPC::RLWIMI8_rec) {
unsigned char SH = MI->getOperand(3).getImm();
unsigned char MB = MI->getOperand(4).getImm();
unsigned char ME = MI->getOperand(5).getImm();
int Op2 = -1;
if (SH && SH < 32 && MB == (32 - SH) && (ME + SH) > 31) {
// Check for inslwi
if (MI->getOpcode() == PPC::RLWIMI || MI->getOpcode() == PPC::RLWIMI8)
O << "\tinslwi ";
else
O << "\tinslwi. ";
Op2 = ME + SH - 31;
} else if (SH <= 31 && ME == (31 - SH) && (MB + SH) < 32) {
// Check for insrwi
if (MI->getOpcode() == PPC::RLWIMI || MI->getOpcode() == PPC::RLWIMI8)
O << "\tinsrwi ";
else
O << "\tinsrwi. ";
Op2 = 32 - MB - SH;
}
if (Op2 > -1) {
// Op0 is same with Op1, but Op1 is input, Op0 is output.
printOperand(MI, 0, O);
O << ", ";
printOperand(MI, 2, O);
O << ", " << (unsigned int)Op2;
O << ", " << (unsigned int)MB;
printAnnotation(O, Annot);
return;
}
}
// Check for RLWINM mnemonics.
if (MI->getOpcode() == PPC::RLWINM || MI->getOpcode() == PPC::RLWINM_rec ||
MI->getOpcode() == PPC::RLWINM8 || MI->getOpcode() == PPC::RLWINM8_rec) {
unsigned char SH = MI->getOperand(2).getImm(); unsigned char SH = MI->getOperand(2).getImm();
unsigned char MB = MI->getOperand(3).getImm(); unsigned char MB = MI->getOperand(3).getImm();
unsigned char ME = MI->getOperand(4).getImm(); unsigned char ME = MI->getOperand(4).getImm();
bool useSubstituteMnemonic = false; int Op2 = -1, Op3 = -1;
if (SH <= 31 && MB == 0 && ME == (31-SH)) {
O << "\tslwi "; useSubstituteMnemonic = true; if (SH < 32 && MB == 0 && ME == (31 - SH)) {
} // Check for slwi
if (SH <= 31 && MB == (32-SH) && ME == 31) { if (MI->getOpcode() == PPC::RLWINM || MI->getOpcode() == PPC::RLWINM8)
O << "\tsrwi "; useSubstituteMnemonic = true; O << "\tslwi ";
SH = 32-SH; else
O << "\tslwi. ";
Op2 = SH;
} else if (SH && SH < 32 && MB == (32 - SH) && ME == 31) {
// Check for srwi
if (MI->getOpcode() == PPC::RLWINM || MI->getOpcode() == PPC::RLWINM8)
O << "\tsrwi ";
else
O << "\tsrwi. ";
Op2 = 32 - SH;
} else if (SH == 0 && MB == 0 && ME < 32) {
// Check for clrrwi
if (MI->getOpcode() == PPC::RLWINM || MI->getOpcode() == PPC::RLWINM8)
O << "\tclrrwi ";
else
O << "\tclrrwi. ";
Op2 = 31 - ME;
} else if (SH && SH < 32 && (SH + ME) == 31 && (SH + MB) < 32) {
// Check for clrlslwi
if (MI->getOpcode() == PPC::RLWINM || MI->getOpcode() == PPC::RLWINM8)
O << "\tclrlslwi ";
else
O << "\tclrlslwi. ";
Op2 = SH + MB;
Op3 = SH;
} else if (SH < 32 && MB == 0 && ME < 31) {
// Check for extlwi
if (MI->getOpcode() == PPC::RLWINM || MI->getOpcode() == PPC::RLWINM8)
O << "\textlwi ";
else
O << "\textlwi. ";
Op2 = ME + 1;
Op3 = SH;
} else if (SH < 32 && MB < 32 && ME == 31 && (SH + MB) > 33) {
// Check for extrwi
if (MI->getOpcode() == PPC::RLWINM || MI->getOpcode() == PPC::RLWINM8)
O << "\textrwi ";
else
O << "\textrwi. ";
Op2 = 32 - MB;
Op3 = SH + MB - 32;
} }
if (useSubstituteMnemonic) {
if (Op2 > -1) {
printOperand(MI, 0, O); printOperand(MI, 0, O);
O << ", "; O << ", ";
printOperand(MI, 1, O); printOperand(MI, 1, O);
O << ", " << (unsigned int)Op2;
if (Op3 > -1)
O << ", " << (unsigned int)Op3;
printAnnotation(O, Annot);
return;
}
}
// Check for RLDIC mnemonics.
if (MI->getOpcode() == PPC::RLDIC || MI->getOpcode() == PPC::RLDIC_rec) {
unsigned char SH = MI->getOperand(2).getImm();
unsigned char MB = MI->getOperand(3).getImm();
if (SH + MB < 64) {
// Check for clrlsldi
if (MI->getOpcode() == PPC::RLDIC)
O << "\tclrlsldi ";
else
O << "\tclrlsldi. ";
printOperand(MI, 0, O);
O << ", ";
printOperand(MI, 1, O);
O << ", " << (unsigned int)(SH + MB);
O << ", " << (unsigned int)SH; O << ", " << (unsigned int)SH;
printAnnotation(O, Annot);
return;
}
}
// Check for RLDICL mnemonics.
if (MI->getOpcode() == PPC::RLDICL ||
MI->getOpcode() == PPC::RLDICL_rec ||
MI->getOpcode() == PPC::RLDICL_32 ||
MI->getOpcode() == PPC::RLDICL_32_rec ||
MI->getOpcode() == PPC::RLDICL_32_64) {
unsigned char SH = MI->getOperand(2).getImm();
unsigned char MB = MI->getOperand(3).getImm();
int Op2 = -1, Op3 = -1;
if (SH && SH < 64 && SH == (64 - MB)) {
// Check for srdi
if (MI->getOpcode() == PPC::RLDICL ||
MI->getOpcode() == PPC::RLDICL_32 ||
MI->getOpcode() == PPC::RLDICL_32_64)
O << "\tsrdi ";
else
O << "\tsrdi. ";
Op2 = 64 - SH;
} else if (SH && SH < 64 && (SH + MB) > 63 && MB < 64) {
// Check for extrdi
if (MI->getOpcode() == PPC::RLDICL ||
MI->getOpcode() == PPC::RLDICL_32 ||
MI->getOpcode() == PPC::RLDICL_32_64)
O << "\textrdi ";
else
O << "\textrdi. ";
Op2 = 64 - MB;
Op3 = SH + MB - 64;
}
if (Op2 > -1) {
printOperand(MI, 0, O);
O << ", ";
printOperand(MI, 1, O);
O << ", " << (unsigned int)Op2;
if (Op3 > -1)
O << ", " << (unsigned int)Op3;
printAnnotation(O, Annot); printAnnotation(O, Annot);
return; return;
} }
} }
// Check for RLDICR mnemonics.
if (MI->getOpcode() == PPC::RLDICR || if (MI->getOpcode() == PPC::RLDICR ||
MI->getOpcode() == PPC::RLDICR_32) { MI->getOpcode() == PPC::RLDICR_32 ||
MI->getOpcode() == PPC::RLDICR_rec) {
unsigned char SH = MI->getOperand(2).getImm(); unsigned char SH = MI->getOperand(2).getImm();
unsigned char ME = MI->getOperand(3).getImm(); unsigned char ME = MI->getOperand(3).getImm();
// rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH int Op2 = -1, Op3 = -1;
if (63-SH == ME) { if (63 - SH == ME) {
// Check for sldi
if (MI->getOpcode() == PPC::RLDICR || MI->getOpcode() == PPC::RLDICR_32)
O << "\tsldi "; O << "\tsldi ";
else
O << "\tsldi. ";
Op2 = SH;
} else if (SH == 0 && ME < 64) {
// Check for clrrdi
if (MI->getOpcode() == PPC::RLDICR || MI->getOpcode() == PPC::RLDICR_32)
O << "\tclrrdi ";
else
O << "\tclrrdi. ";
Op2 = 63 - ME;
} else if (SH < 64 && ME < 63) {
// Check for extldi
if (MI->getOpcode() == PPC::RLDICR || MI->getOpcode() == PPC::RLDICR_32)
O << "\textldi ";
else
O << "\textldi. ";
Op2 = ME + 1;
Op3 = SH;
}
if (Op2 > -1) {
printOperand(MI, 0, O); printOperand(MI, 0, O);
O << ", "; O << ", ";
printOperand(MI, 1, O); printOperand(MI, 1, O);
O << ", " << (unsigned int)SH; O << ", " << (unsigned int)Op2;
if (Op3 > -1)
O << ", " << (unsigned int)Op3;
printAnnotation(O, Annot); printAnnotation(O, Annot);
return; return;
} }
} }
// dcbt[st] is printed manually here because: // dcbt[st] is printed manually here because:
// 1. The assembly syntax is different between embedded and server targets // 1. The assembly syntax is different between embedded and server targets
// 2. We must print the short mnemonics for TH == 0 because the // 2. We must print the short mnemonics for TH == 0 because the
▲ Show 20 Lines • Show All 466 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/2006-11-10-DAGCombineMiscompile.ll

; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | grep rlwimi ; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | grep insrwi
define void @test(i16 %div.0.i.i.i.i, i32 %L_num.0.i.i.i.i, i32 %tmp1.i.i206.i.i, i16* %P) { define void @test(i16 %div.0.i.i.i.i, i32 %L_num.0.i.i.i.i, i32 %tmp1.i.i206.i.i, i16* %P) {
%X = shl i16 %div.0.i.i.i.i, 1 ; <i16> [#uses=1] %X = shl i16 %div.0.i.i.i.i, 1 ; <i16> [#uses=1]
%tmp28.i.i.i.i = shl i32 %L_num.0.i.i.i.i, 1 ; <i32> [#uses=1] %tmp28.i.i.i.i = shl i32 %L_num.0.i.i.i.i, 1 ; <i32> [#uses=1]
%tmp31.i.i.i.i = icmp slt i32 %tmp28.i.i.i.i, %tmp1.i.i206.i.i ; <i1> [#uses=1] %tmp31.i.i.i.i = icmp slt i32 %tmp28.i.i.i.i, %tmp1.i.i206.i.i ; <i1> [#uses=1]
%tmp31.i.i.i.i.upgrd.1 = zext i1 %tmp31.i.i.i.i to i16 ; <i16> [#uses=1] %tmp31.i.i.i.i.upgrd.1 = zext i1 %tmp31.i.i.i.i to i16 ; <i16> [#uses=1]
%tmp371.i.i.i.i1 = or i16 %tmp31.i.i.i.i.upgrd.1, %X ; <i16> [#uses=1] %tmp371.i.i.i.i1 = or i16 %tmp31.i.i.i.i.upgrd.1, %X ; <i16> [#uses=1]
%div.0.be.i.i.i.i = xor i16 %tmp371.i.i.i.i1, 1 ; <i16> [#uses=1] %div.0.be.i.i.i.i = xor i16 %tmp371.i.i.i.i1, 1 ; <i16> [#uses=1]
store i16 %div.0.be.i.i.i.i, i16* %P store i16 %div.0.be.i.i.i.i, i16* %P
ret void ret void
} }

llvm/test/CodeGen/PowerPC/CompareEliminationSpillIssue.ll

Show All 30 Linesentry:
%cmp = icmp sle i32 %add, %c %cmp = icmp sle i32 %add, %c
%conv1 = zext i1 %cmp to i32 %conv1 = zext i1 %cmp to i32
ret i32 %conv1 ret i32 %conv1
; CHECK-LABEL: test ; CHECK-LABEL: test
; CHECK: sub r3, ; CHECK: sub r3,
; CHECK: extsw r3, ; CHECK: extsw r3,
; CHECK: bl call ; CHECK: bl call
; CHECK: sub r3, ; CHECK: sub r3,
; CHECK: rldicl r3, r3, 1, 63 ; CHECK: srdi r3, r3, 63
; CHECK: std r3, [[OFF:[0-9]+]](r1) ; CHECK: std r3, [[OFF:[0-9]+]](r1)
; CHECK: #APP ; CHECK: #APP
; CHECK: ld r3, [[OFF]](r1) ; CHECK: ld r3, [[OFF]](r1)
; CHECK: xori r3, r3, 1 ; CHECK: xori r3, r3, 1
; CHECK: blr ; CHECK: blr
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
Show All 9 Lines

llvm/test/CodeGen/PowerPC/Frames-dyn-alloca.ll

Show All 23 Lines
} }
; PPC32-LINUX-LABEL: f1 ; PPC32-LINUX-LABEL: f1
; PPC32-LINUX: stwu 1, -32(1) ; PPC32-LINUX: stwu 1, -32(1)
; PPC32-LINUX-NEXT: slwi 3, 3, 2 ; PPC32-LINUX-NEXT: slwi 3, 3, 2
; PPC32-LINUX-NEXT: addi 3, 3, 15 ; PPC32-LINUX-NEXT: addi 3, 3, 15
; PPC32-LINUX-NEXT: stw 31, 28(1) ; PPC32-LINUX-NEXT: stw 31, 28(1)
; PPC32-LINUX-NEXT: mr 31, 1 ; PPC32-LINUX-NEXT: mr 31, 1
; PPC32-LINUX-NEXT: rlwinm 3, 3, 0, 0, 27 ; PPC32-LINUX-NEXT: clrrwi 3, 3, 4
; PPC32-LINUX-NEXT: neg 3, 3 ; PPC32-LINUX-NEXT: neg 3, 3
; PPC32-LINUX-NEXT: addi 4, 31, 32 ; PPC32-LINUX-NEXT: addi 4, 31, 32
; PPC32-LINUX-NEXT: stwux 4, 1, 3 ; PPC32-LINUX-NEXT: stwux 4, 1, 3
; PPC32-LINUX-NEXT: lwz 31, 0(1) ; PPC32-LINUX-NEXT: lwz 31, 0(1)
; PPC32-LINUX-NEXT: addi 3, 1, 16 ; PPC32-LINUX-NEXT: addi 3, 1, 16
; PPC32-LINUX-NEXT: lwz 0, -4(31) ; PPC32-LINUX-NEXT: lwz 0, -4(31)
; PPC32-LINUX-NEXT: mr 1, 31 ; PPC32-LINUX-NEXT: mr 1, 31
; PPC32-LINUX-NEXT: mr 31, 0 ; PPC32-LINUX-NEXT: mr 31, 0
; PPC32-LINUX-NEXT: blr ; PPC32-LINUX-NEXT: blr
; PPC64-LINUX-LABEL: f1 ; PPC64-LINUX-LABEL: f1
; PPC64-LINUX: std 31, -8(1) ; PPC64-LINUX: std 31, -8(1)
; PPC64-LINUX-NEXT: stdu 1, -64(1) ; PPC64-LINUX-NEXT: stdu 1, -64(1)
; PPC64-LINUX-NEXT: rldic 3, 3, 2, 30 ; PPC64-LINUX-NEXT: clrlsldi 3, 3, 32, 2
; PPC64-LINUX-NEXT: mr 31, 1 ; PPC64-LINUX-NEXT: mr 31, 1
; PPC64-LINUX-NEXT: addi 3, 3, 15 ; PPC64-LINUX-NEXT: addi 3, 3, 15
; PPC64-LINUX-NEXT: rldicl 3, 3, 60, 4 ; PPC64-LINUX-NEXT: srdi 3, 3, 4
; PPC64-LINUX-NEXT: addi 4, 31, 64 ; PPC64-LINUX-NEXT: addi 4, 31, 64
; PPC64-LINUX-NEXT: rldicl 3, 3, 4, 29 ; PPC64-LINUX-NEXT: rldicl 3, 3, 4, 29
; PPC64-LINUX-NEXT: neg 3, 3 ; PPC64-LINUX-NEXT: neg 3, 3
; PPC64-LINUX-NEXT: stdux 4, 1, 3 ; PPC64-LINUX-NEXT: stdux 4, 1, 3
; The linkage area is always put on the top of the stack. ; The linkage area is always put on the top of the stack.
; PPC64-LINUX-NEXT: addi 3, 1, 48 ; PPC64-LINUX-NEXT: addi 3, 1, 48
; PPC64-LINUX-NEXT: ld 1, 0(1) ; PPC64-LINUX-NEXT: ld 1, 0(1)
; PPC64-LINUX-NEXT: ld 31, -8(1) ; PPC64-LINUX-NEXT: ld 31, -8(1)
; PPC64-LINUX-NEXT: blr ; PPC64-LINUX-NEXT: blr
; PPC32-AIX-LABEL: f1 ; PPC32-AIX-LABEL: f1
; PPC32-AIX: stw 31, -4(1) ; PPC32-AIX: stw 31, -4(1)
; PPC32-AIX-NEXT: stwu 1, -48(1) ; PPC32-AIX-NEXT: stwu 1, -48(1)
; PPC32-AIX-NEXT: slwi 3, 3, 2 ; PPC32-AIX-NEXT: slwi 3, 3, 2
; PPC32-AIX-NEXT: mr 31, 1 ; PPC32-AIX-NEXT: mr 31, 1
; PPC32-AIX-NEXT: addi 3, 3, 15 ; PPC32-AIX-NEXT: addi 3, 3, 15
; PPC32-AIX-NEXT: addi 4, 31, 48 ; PPC32-AIX-NEXT: addi 4, 31, 48
; PPC32-AIX-NEXT: rlwinm 3, 3, 0, 0, 27 ; PPC32-AIX-NEXT: clrrwi 3, 3, 4
; PPC32-AIX-NEXT: neg 3, 3 ; PPC32-AIX-NEXT: neg 3, 3
; PPC32-AIX-NEXT: stwux 4, 1, 3 ; PPC32-AIX-NEXT: stwux 4, 1, 3
; The linkage area is always put on the top of the stack. ; The linkage area is always put on the top of the stack.
; PPC32-AIX-NEXT: addi 3, 1, 32 ; PPC32-AIX-NEXT: addi 3, 1, 32
; PPC32-AIX-NEXT: lwz 1, 0(1) ; PPC32-AIX-NEXT: lwz 1, 0(1)
; PPC32-AIX-NEXT: lwz 31, -4(1) ; PPC32-AIX-NEXT: lwz 31, -4(1)
; PPC32-AIX-NEXT: blr ; PPC32-AIX-NEXT: blr
; PPC64-AIX-LABEL: f1 ; PPC64-AIX-LABEL: f1
; PPC64-AIX: std 31, -8(1) ; PPC64-AIX: std 31, -8(1)
; PPC64-AIX-NEXT: stdu 1, -64(1) ; PPC64-AIX-NEXT: stdu 1, -64(1)
; PPC64-AIX-NEXT: rldic 3, 3, 2, 30 ; PPC64-AIX-NEXT: clrlsldi 3, 3, 32, 2
; PPC64-AIX-NEXT: mr 31, 1 ; PPC64-AIX-NEXT: mr 31, 1
; PPC64-AIX-NEXT: addi 3, 3, 15 ; PPC64-AIX-NEXT: addi 3, 3, 15
; PPC64-AIX-NEXT: addi 4, 31, 64 ; PPC64-AIX-NEXT: addi 4, 31, 64
; PPC64-AIX-NEXT: rldicl 3, 3, 60, 4 ; PPC64-AIX-NEXT: srdi 3, 3, 4
; PPC64-AIX-NEXT: rldicl 3, 3, 4, 29 ; PPC64-AIX-NEXT: rldicl 3, 3, 4, 29
; PPC64-AIX-NEXT: neg 3, 3 ; PPC64-AIX-NEXT: neg 3, 3
; PPC64-AIX-NEXT: stdux 4, 1, 3 ; PPC64-AIX-NEXT: stdux 4, 1, 3
; The linkage area is always put on the top of the stack. ; The linkage area is always put on the top of the stack.
; PPC64-AIX-NEXT: addi 3, 1, 48 ; PPC64-AIX-NEXT: addi 3, 1, 48
; PPC64-AIX-NEXT: ld 1, 0(1) ; PPC64-AIX-NEXT: ld 1, 0(1)
; PPC64-AIX-NEXT: ld 31, -8(1) ; PPC64-AIX-NEXT: ld 31, -8(1)
; PPC64-AIX-NEXT: blr ; PPC64-AIX-NEXT: blr

llvm/test/CodeGen/PowerPC/PR35812-neg-cmpxchg.ll

Show First 20 Lines • Show All 77 Lines • ▼ Show 20 Lines
; CHECK-P7-NEXT: li 6, 234 ; CHECK-P7-NEXT: li 6, 234
; CHECK-P7-NEXT: ori 5, 5, 33059 ; CHECK-P7-NEXT: ori 5, 5, 33059
; CHECK-P7-NEXT: rlwinm 3, 4, 3, 27, 27 ; CHECK-P7-NEXT: rlwinm 3, 4, 3, 27, 27
; CHECK-P7-NEXT: ori 7, 7, 65535 ; CHECK-P7-NEXT: ori 7, 7, 65535
; CHECK-P7-NEXT: sync ; CHECK-P7-NEXT: sync
; CHECK-P7-NEXT: slw 6, 6, 3 ; CHECK-P7-NEXT: slw 6, 6, 3
; CHECK-P7-NEXT: slw 8, 5, 3 ; CHECK-P7-NEXT: slw 8, 5, 3
; CHECK-P7-NEXT: slw 5, 7, 3 ; CHECK-P7-NEXT: slw 5, 7, 3
; CHECK-P7-NEXT: rldicr 4, 4, 0, 61 ; CHECK-P7-NEXT: clrrdi 4, 4, 2
; CHECK-P7-NEXT: and 7, 6, 5 ; CHECK-P7-NEXT: and 7, 6, 5
; CHECK-P7-NEXT: and 8, 8, 5 ; CHECK-P7-NEXT: and 8, 8, 5
; CHECK-P7-NEXT: .LBB0_1: # %L.entry ; CHECK-P7-NEXT: .LBB0_1: # %L.entry
; CHECK-P7-NEXT: # ; CHECK-P7-NEXT: #
; CHECK-P7-NEXT: lwarx 9, 0, 4 ; CHECK-P7-NEXT: lwarx 9, 0, 4
; CHECK-P7-NEXT: and 6, 9, 5 ; CHECK-P7-NEXT: and 6, 9, 5
; CHECK-P7-NEXT: cmpw 6, 8 ; CHECK-P7-NEXT: cmpw 6, 8
; CHECK-P7-NEXT: bne 0, .LBB0_3 ; CHECK-P7-NEXT: bne 0, .LBB0_3
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llvm/test/CodeGen/PowerPC/absol-jump-table-enabled.ll

; NOTE: This test case generates a jump table on PowerPC big and little endian ; NOTE: This test case generates a jump table on PowerPC big and little endian
; NOTE: then verifies that the command line option to enable absolute jump ; NOTE: then verifies that the command line option to enable absolute jump
; NOTE: table works correctly. ; NOTE: table works correctly.
; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -o - \ ; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -o - \
; RUN: -ppc-use-absolute-jumptables -ppc-asm-full-reg-names \ ; RUN: -ppc-use-absolute-jumptables -ppc-asm-full-reg-names \
; RUN: -verify-machineinstrs %s | FileCheck %s -check-prefix=CHECK-LE ; RUN: -verify-machineinstrs %s | FileCheck %s -check-prefix=CHECK-LE
; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -o - \ ; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -o - \
; RUN: -ppc-use-absolute-jumptables -ppc-asm-full-reg-names \ ; RUN: -ppc-use-absolute-jumptables -ppc-asm-full-reg-names \
; RUN: -verify-machineinstrs %s | FileCheck %s -check-prefix=CHECK-BE ; RUN: -verify-machineinstrs %s | FileCheck %s -check-prefix=CHECK-BE
%struct.node = type { i8, %struct.node* } %struct.node = type { i8, %struct.node* }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define zeroext i32 @jumpTableTest(%struct.node* readonly %list) { define zeroext i32 @jumpTableTest(%struct.node* readonly %list) {
; CHECK-LE-LABEL: jumpTableTest: ; CHECK-LE-LABEL: jumpTableTest:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE: rldic r[[REG:[0-9]+]], r[[REG]], 3, 29 ; CHECK-LE: clrlsldi r[[REG:[0-9]+]], r[[REG]], 32, 3
; CHECK-LE: ldx r[[REG]], r[[REG]], r[[REG1:[0-9]+]] ; CHECK-LE: ldx r[[REG]], r[[REG]], r[[REG1:[0-9]+]]
; CHECK-LE: mtctr r[[REG]] ; CHECK-LE: mtctr r[[REG]]
; CHECK-LE: bctr ; CHECK-LE: bctr
; CHECK-LE: blr ; CHECK-LE: blr
; ;
; CHECK-BE-LABEL: jumpTableTest: ; CHECK-BE-LABEL: jumpTableTest:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE: rldic r[[REG:[0-9]+]], r[[REG]], 2, 30 ; CHECK-BE: clrlsldi r[[REG:[0-9]+]], r[[REG]], 32, 2
; CHECK-BE: lwax r[[REG]], r[[REG]], r[[REG1:[0-9]+]] ; CHECK-BE: lwax r[[REG]], r[[REG]], r[[REG1:[0-9]+]]
; CHECK-BE: mtctr r[[REG]] ; CHECK-BE: mtctr r[[REG]]
; CHECK-BE: bctr ; CHECK-BE: bctr
; CHECK-BE: blr ; CHECK-BE: blr
entry: entry:
%cmp36 = icmp eq %struct.node* %list, null %cmp36 = icmp eq %struct.node* %list, null
br i1 %cmp36, label %while.end, label %while.body br i1 %cmp36, label %while.end, label %while.body
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llvm/test/CodeGen/PowerPC/addegluecrash.ll

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; CHECK-NEXT: ld 5, 8(5) ; CHECK-NEXT: ld 5, 8(5)
; CHECK-NEXT: mulld 8, 5, 7 ; CHECK-NEXT: mulld 8, 5, 7
; CHECK-NEXT: mulhdu 5, 5, 7 ; CHECK-NEXT: mulhdu 5, 5, 7
; CHECK-NEXT: addc 6, 6, 8 ; CHECK-NEXT: addc 6, 6, 8
; CHECK-NEXT: addze 5, 5 ; CHECK-NEXT: addze 5, 5
; CHECK-NEXT: add 4, 5, 4 ; CHECK-NEXT: add 4, 5, 4
; CHECK-NEXT: cmpld 7, 4, 5 ; CHECK-NEXT: cmpld 7, 4, 5
; CHECK-NEXT: mfocrf 4, 1 ; CHECK-NEXT: mfocrf 4, 1
; CHECK-NEXT: rlwinm 4, 4, 29, 31, 31 ; CHECK-NEXT: extrwi 4, 4, 1, 28
; CHECK-NEXT: # implicit-def: $x5 ; CHECK-NEXT: # implicit-def: $x5
; CHECK-NEXT: mr 5, 4 ; CHECK-NEXT: mr 5, 4
; CHECK-NEXT: clrldi 4, 5, 32 ; CHECK-NEXT: clrldi 4, 5, 32
; CHECK-NEXT: std 4, 0(3) ; CHECK-NEXT: std 4, 0(3)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%1 = load i64, i64* %a, align 8 %1 = load i64, i64* %a, align 8
%conv = zext i64 %1 to i128 %conv = zext i64 %1 to i128
%2 = load i64, i64* %b, align 8 %2 = load i64, i64* %b, align 8
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llvm/test/CodeGen/PowerPC/addi-offset-fold.ll

Show All 22 Linesentry:
%bf.cast = and i32 %bf.lshr.tr, 127 %bf.cast = and i32 %bf.lshr.tr, 127
ret i32 %bf.cast ret i32 %bf.cast
; CHECK-LABEL: @foo ; CHECK-LABEL: @foo
; FIXME: We don't need to do these stores at all. ; FIXME: We don't need to do these stores at all.
; CHECK-DAG: std 3, -24(1) ; CHECK-DAG: std 3, -24(1)
; CHECK-DAG: stb 4, -16(1) ; CHECK-DAG: stb 4, -16(1)
; CHECK-DAG: lwz [[REG2:[0-9]+]], -20(1) ; CHECK-DAG: lwz [[REG2:[0-9]+]], -20(1)
; CHECK-DAG: rlwinm 3, [[REG2]], 1, 31, 31 ; CHECK-DAG: srwi 3, [[REG2]], 31
; CHECK: rlwimi 3, 4, 1, 25, 30 ; CHECK: insrwi 3, 4, 6, 25
; CHECK: blr ; CHECK: blr
} }
attributes #0 = { nounwind "frame-pointer"="all" "target-cpu"="ppc64le" } attributes #0 = { nounwind "frame-pointer"="all" "target-cpu"="ppc64le" }

llvm/test/CodeGen/PowerPC/addze.ll

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} }
define i64 @test2(i64 %X, i64 %Z) { define i64 @test2(i64 %X, i64 %Z) {
; CHECK-LABEL: test2: ; CHECK-LABEL: test2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li [[REG1:r[0-9]+]], -32768 ; CHECK-NEXT: li [[REG1:r[0-9]+]], -32768
; CHECK-NEXT: xor [[REG2:r[0-9]+]], [[REG2]], [[REG1]] ; CHECK-NEXT: xor [[REG2:r[0-9]+]], [[REG2]], [[REG1]]
; CHECK-NEXT: cntlzd [[REG2]], [[REG2]] ; CHECK-NEXT: cntlzd [[REG2]], [[REG2]]
; CHECK-NEXT: rldicl [[REG2]], [[REG2]], 58, 63 ; CHECK-NEXT: extrdi [[REG2]], [[REG2]], 1, 57
; CHECK-NEXT: add [[REG3:r[0-9]+]], [[REG2]], [[REG3]] ; CHECK-NEXT: add [[REG3:r[0-9]+]], [[REG2]], [[REG3]]
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%cmp = icmp eq i64 %Z, -32768 %cmp = icmp eq i64 %Z, -32768
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
%add = add nsw i64 %conv1, %X %add = add nsw i64 %conv1, %X
ret i64 %add ret i64 %add
} }
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define i64 @test4(i64 %X, i64 %Z) { define i64 @test4(i64 %X, i64 %Z) {
; CHECK-LABEL: test4: ; CHECK-LABEL: test4:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li [[REG1:r[0-9]+]], 0 ; CHECK-NEXT: li [[REG1:r[0-9]+]], 0
; CHECK-NEXT: ori [[REG1]], [[REG1]], 32769 ; CHECK-NEXT: ori [[REG1]], [[REG1]], 32769
; CHECK-NEXT: xor [[REG2:r[0-9]+]], [[REG2]], [[REG1]] ; CHECK-NEXT: xor [[REG2:r[0-9]+]], [[REG2]], [[REG1]]
; CHECK-NEXT: cntlzd [[REG2]], [[REG2]] ; CHECK-NEXT: cntlzd [[REG2]], [[REG2]]
; CHECK-NEXT: rldicl [[REG2]], [[REG2]], 58, 63 ; CHECK-NEXT: extrdi [[REG2]], [[REG2]], 1, 57
; CHECK-NEXT: add [[REG3:r[0-9]+]], [[REG2]], [[REG3]] ; CHECK-NEXT: add [[REG3:r[0-9]+]], [[REG2]], [[REG3]]
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%cmp = icmp eq i64 %Z, 32769 %cmp = icmp eq i64 %Z, 32769
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
%add = add nsw i64 %conv1, %X %add = add nsw i64 %conv1, %X
ret i64 %add ret i64 %add
} }
Show All 12 Lines; CHECK-NEXT: blr
ret i64 %add ret i64 %add
} }
define i64 @test6(i64 %X, i64 %Y, i64 %Z) { define i64 @test6(i64 %X, i64 %Y, i64 %Z) {
; CHECK-LABEL: test6: ; CHECK-LABEL: test6:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: xor [[REG2:r[0-9]+]], [[REG2]], [[REG1:r[0-9]+]] ; CHECK-NEXT: xor [[REG2:r[0-9]+]], [[REG2]], [[REG1:r[0-9]+]]
; CHECK-NEXT: cntlzd [[REG2]], [[REG2]] ; CHECK-NEXT: cntlzd [[REG2]], [[REG2]]
; CHECK-NEXT: rldicl [[REG2]], [[REG2]], 58, 63 ; CHECK-NEXT: extrdi [[REG2]], [[REG2]], 1, 57
; CHECK-NEXT: add [[REG3:r[0-9]+]], [[REG2]], [[REG3]] ; CHECK-NEXT: add [[REG3:r[0-9]+]], [[REG2]], [[REG3]]
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%cmp = icmp eq i64 %Y, %Z %cmp = icmp eq i64 %Y, %Z
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
%add = add nsw i64 %conv1, %X %add = add nsw i64 %conv1, %X
ret i64 %add ret i64 %add
} }

llvm/test/CodeGen/PowerPC/aix-cc-byval-mem.ll

Show First 20 Lines • Show All 370 Lines • ▼ Show 20 Lines
; ASM64BIT-NEXT: bl .memcpy ; ASM64BIT-NEXT: bl .memcpy
; ASM64BIT-DAG: ld [[REG2:[0-9]+]], L..C{{[0-9]+}}(2) ; ASM64BIT-DAG: ld [[REG2:[0-9]+]], L..C{{[0-9]+}}(2)
; ASM64BIT-DAG: ld 4, 0([[REG2]]) ; ASM64BIT-DAG: ld 4, 0([[REG2]])
; ASM64BIT-DAG: ld 5, 8([[REG2]]) ; ASM64BIT-DAG: ld 5, 8([[REG2]])
; ASM64BIT-DAG: ld 6, 16([[REG2]]) ; ASM64BIT-DAG: ld 6, 16([[REG2]])
; ASM64BIT-DAG: lwz [[REG3:[0-9]+]], 24([[REG2]]) ; ASM64BIT-DAG: lwz [[REG3:[0-9]+]], 24([[REG2]])
; ASM64BIT-DAG: lhz [[REG4:[0-9]+]], 28([[REG2]]) ; ASM64BIT-DAG: lhz [[REG4:[0-9]+]], 28([[REG2]])
; ASM64BIT-DAG: lbz 7, 30([[REG2]]) ; ASM64BIT-DAG: lbz 7, 30([[REG2]])
; ASM64BIT-DAG: rlwinm 7, 7, 8, 16, 23 ; ASM64BIT-DAG: clrlslwi 7, 7, 24, 8
; ASM64BIT-DAG: rlwimi 7, [[REG4]], 16, 0, 15 ; ASM64BIT-DAG: insrwi 7, [[REG4]], 16, 0
; ASM64BIT-DAG: rldimi 7, [[REG3]], 32, 0 ; ASM64BIT-DAG: insrdi 7, [[REG3]], 32, 0
; ASM64BIT-DAG: ld 8, 0([[REG1]]) ; ASM64BIT-DAG: ld 8, 0([[REG1]])
; ASM64BIT-DAG: ld 9, 8([[REG1]]) ; ASM64BIT-DAG: ld 9, 8([[REG1]])
; ASM64BIT-DAG: ld 10, 16([[REG1]]) ; ASM64BIT-DAG: ld 10, 16([[REG1]])
; ASM64BIT: bl .test_byval_mem4 ; ASM64BIT: bl .test_byval_mem4
; ASM64BIT: addi 1, 1, 368 ; ASM64BIT: addi 1, 1, 368
define void @test_byval_mem4(i32, %struct_S31* byval(%struct_S31) align 1, %struct_S256* byval(%struct_S256) align 1 %s) { define void @test_byval_mem4(i32, %struct_S31* byval(%struct_S31) align 1, %struct_S256* byval(%struct_S256) align 1 %s) {
entry: entry:
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llvm/test/CodeGen/PowerPC/aix-cc-byval.ll

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; ASM32-DAG: li 5, 3 ; ASM32-DAG: li 5, 3
; ASM32-DAG: li 6, 4 ; ASM32-DAG: li 6, 4
; ASM32-DAG: li 7, 5 ; ASM32-DAG: li 7, 5
; ASM32-DAG: li 8, 6 ; ASM32-DAG: li 8, 6
; ASM32-DAG: li 9, 7 ; ASM32-DAG: li 9, 7
; ASM32-DAG: lwz [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2) ; ASM32-DAG: lwz [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2)
; ASM32-DAG: lhz [[REG1:[0-9]+]], 0([[REGADDR]]) ; ASM32-DAG: lhz [[REG1:[0-9]+]], 0([[REGADDR]])
; ASM32-DAG: lbz [[REG2:[0-9]+]], 2([[REGADDR]]) ; ASM32-DAG: lbz [[REG2:[0-9]+]], 2([[REGADDR]])
; ASM32-DAG: rlwinm 10, [[REG2]], 8, 16, 23 ; ASM32-DAG: clrlslwi 10, [[REG2]], 24, 8
; ASM32-DAG: rlwimi 10, [[REG1]], 16, 0, 15 ; ASM32-DAG: insrwi 10, [[REG1]], 16, 0
; ASM32-DAG: li [[REG3:[0-9]+]], 42 ; ASM32-DAG: li [[REG3:[0-9]+]], 42
; ASM32-DAG: stw [[REG3]], 56(1) ; ASM32-DAG: stw [[REG3]], 56(1)
; ASM32-NEXT: bl .test_byval_3Byte ; ASM32-NEXT: bl .test_byval_3Byte
; ASM32-NEXT: nop ; ASM32-NEXT: nop
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
; 64BIT: ADJCALLSTACKDOWN 120, 0, implicit-def dead $r1, implicit $r1 ; 64BIT: ADJCALLSTACKDOWN 120, 0, implicit-def dead $r1, implicit $r1
; 64BIT-DAG: $x3 = LI8 1 ; 64BIT-DAG: $x3 = LI8 1
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; ASM64-DAG: li 5, 3 ; ASM64-DAG: li 5, 3
; ASM64-DAG: li 6, 4 ; ASM64-DAG: li 6, 4
; ASM64-DAG: li 7, 5 ; ASM64-DAG: li 7, 5
; ASM64-DAG: li 8, 6 ; ASM64-DAG: li 8, 6
; ASM64-DAG: li 9, 7 ; ASM64-DAG: li 9, 7
; ASM64-DAG: ld [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2) ; ASM64-DAG: ld [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2)
; ASM64-DAG: lhz [[REG1:[0-9]+]], 0([[REGADDR]]) ; ASM64-DAG: lhz [[REG1:[0-9]+]], 0([[REGADDR]])
; ASM64-DAG: lbz [[REG2:[0-9]+]], 2([[REGADDR]]) ; ASM64-DAG: lbz [[REG2:[0-9]+]], 2([[REGADDR]])
; ASM64-DAG: rldic 10, [[REG2]], 40, 16 ; ASM64-DAG: clrlsldi 10, 3, 56, 40
; ASM64-DAG: rldimi 10, [[REG1]], 48, 0 ; ASM64-DAG: insrdi 10, [[REG1]], 16, 0
; ASM64-DAG: li [[REG3:[0-9]+]], 42 ; ASM64-DAG: li [[REG3:[0-9]+]], 42
; ASM64-DAG: std [[REG3]], 112(1) ; ASM64-DAG: std [[REG3]], 112(1)
; ASM64-NEXT: bl .test_byval_3Byte ; ASM64-NEXT: bl .test_byval_3Byte
; ASM64-NEXT: nop ; ASM64-NEXT: nop
define zeroext i16 @test_byval_3Byte(i32, i32, i32, i32, i32, i32, i32, %struct.S3* byval(%struct.S3) align 1 %s, i32) { define zeroext i16 @test_byval_3Byte(i32, i32, i32, i32, i32, i32, i32, %struct.S3* byval(%struct.S3) align 1 %s, i32) {
entry: entry:
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; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_5Byte>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1 ; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_5Byte>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 ; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
; ASM64: stdu 1, -112(1) ; ASM64: stdu 1, -112(1)
; ASM64-NEXT: ld [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2) ; ASM64-NEXT: ld [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2)
; ASM64-DAG: lwz [[REG1:[0-9]+]], 0([[REGADDR]]) ; ASM64-DAG: lwz [[REG1:[0-9]+]], 0([[REGADDR]])
; ASM64-DAG: lbz [[REG2:[0-9]+]], 4([[REGADDR]]) ; ASM64-DAG: lbz [[REG2:[0-9]+]], 4([[REGADDR]])
; ASM64-DAG: rlwinm 3, [[REG2]], 24, 0, 7 ; ASM64-DAG: slwi 3, [[REG2]], 24
; ASM64-DAG: rldimi 3, [[REG1]], 32, 0 ; ASM64-DAG: insrdi 3, [[REG1]], 32, 0
; ASM64-NEXT: bl .test_byval_5Byte ; ASM64-NEXT: bl .test_byval_5Byte
; ASM64-NEXT: nop ; ASM64-NEXT: nop
%struct.S6 = type { [6 x i8] } %struct.S6 = type { [6 x i8] }
@gS6 = external global %struct.S6, align 1 @gS6 = external global %struct.S6, align 1
Show All 37 Lines
; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_6Byte>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1 ; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_6Byte>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 ; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
; ASM64: stdu 1, -112(1) ; ASM64: stdu 1, -112(1)
; ASM64-NEXT: ld [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2) ; ASM64-NEXT: ld [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2)
; ASM64-DAG: lwz [[REG1:[0-9]+]], 0([[REGADDR]]) ; ASM64-DAG: lwz [[REG1:[0-9]+]], 0([[REGADDR]])
; ASM64-DAG: lhz [[REG2:[0-9]+]], 4([[REGADDR]]) ; ASM64-DAG: lhz [[REG2:[0-9]+]], 4([[REGADDR]])
; ASM64-DAG: rlwinm 3, [[REG2]], 16, 0, 15 ; ASM64-DAG: slwi 3, [[REG2]], 16
; ASM64-DAG: rldimi 3, [[REG1]], 32, 0 ; ASM64-DAG: insrdi 3, [[REG1]], 32, 0
; ASM64-NEXT: bl .test_byval_6Byte ; ASM64-NEXT: bl .test_byval_6Byte
; ASM64-NEXT: nop ; ASM64-NEXT: nop
%struct.S7 = type { [7 x i8] } %struct.S7 = type { [7 x i8] }
@gS7 = external global %struct.S7, align 1 @gS7 = external global %struct.S7, align 1
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; CHECKASM-LABEL: .call_test_byval_7Byte: ; CHECKASM-LABEL: .call_test_byval_7Byte:
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
; ASM32: stwu 1, -64(1) ; ASM32: stwu 1, -64(1)
; ASM32-NEXT: lwz [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2) ; ASM32-NEXT: lwz [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2)
; ASM32-DAG: lwz 3, 0([[REGADDR]]) ; ASM32-DAG: lwz 3, 0([[REGADDR]])
; ASM32-DAG: lhz [[REG1:[0-9]+]], 4([[REGADDR]]) ; ASM32-DAG: lhz [[REG1:[0-9]+]], 4([[REGADDR]])
; ASM32-DAG: lbz [[REG2:[0-9]+]], 6([[REGADDR]]) ; ASM32-DAG: lbz [[REG2:[0-9]+]], 6([[REGADDR]])
; ASM32-DAG: rlwinm 4, [[REG2]], 8, 16, 23 ; ASM32-DAG: clrlslwi 4, [[REG2]], 24, 8
; ASM32-DAG: rlwimi 4, [[REG1]], 16, 0, 15 ; ASM32-DAG: insrwi 4, [[REG1]], 16, 0
; ASM32-NEXT: bl .test_byval_7Byte ; ASM32-NEXT: bl .test_byval_7Byte
; ASM32-NEXT: nop ; ASM32-NEXT: nop
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 ; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
; 64BIT-NEXT: renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS7, $x2 :: (load 8 from got) ; 64BIT-NEXT: renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS7, $x2 :: (load 8 from got)
; 64BIT-DAG: renamable $x[[REG1:[0-9]+]] = LWZ8 0, killed renamable $x[[REGADDR]] :: (load 4) ; 64BIT-DAG: renamable $x[[REG1:[0-9]+]] = LWZ8 0, killed renamable $x[[REGADDR]] :: (load 4)
; 64BIT-DAG: renamable $x[[REG2:[0-9]+]] = LHZ8 4, renamable $x[[REGADDR]] :: (load 2) ; 64BIT-DAG: renamable $x[[REG2:[0-9]+]] = LHZ8 4, renamable $x[[REGADDR]] :: (load 2)
; 64BIT-DAG: renamable $x[[REG3:[0-9]+]] = LBZ8 6, renamable $x[[REGADDR]] :: (load 1) ; 64BIT-DAG: renamable $x[[REG3:[0-9]+]] = LBZ8 6, renamable $x[[REGADDR]] :: (load 1)
; 64BIT-DAG: renamable $x3 = RLWINM8 killed renamable $x[[REG3]], 8, 16, 23 ; 64BIT-DAG: renamable $x3 = RLWINM8 killed renamable $x[[REG3]], 8, 16, 23
; 64BIT-DAG: renamable $x3 = RLWIMI8 killed renamable $x3, killed renamable $x[[REG2]], 16, 0, 15 ; 64BIT-DAG: renamable $x3 = RLWIMI8 killed renamable $x3, killed renamable $x[[REG2]], 16, 0, 15
; 64BIT-DAG: renamable $x3 = RLDIMI killed renamable $x3, killed renamable $x[[REG1]], 32, 0 ; 64BIT-DAG: renamable $x3 = RLDIMI killed renamable $x3, killed renamable $x[[REG1]], 32, 0
; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_7Byte>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1 ; 64BIT-NEXT: BL8_NOP <mcsymbol .test_byval_7Byte>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1 ; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
; ASM64: stdu 1, -112(1) ; ASM64: stdu 1, -112(1)
; ASM64-NEXT: ld [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2) ; ASM64-NEXT: ld [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2)
; ASM64-DAG: lwz [[REG1:[0-9]+]], 0([[REGADDR]]) ; ASM64-DAG: lwz [[REG1:[0-9]+]], 0([[REGADDR]])
; ASM64-DAG: lhz [[REG2:[0-9]+]], 4([[REGADDR]]) ; ASM64-DAG: lhz [[REG2:[0-9]+]], 4([[REGADDR]])
; ASM64-DAG: lbz [[REG3:[0-9]+]], 6([[REGADDR]]) ; ASM64-DAG: lbz [[REG3:[0-9]+]], 6([[REGADDR]])
; ASM64-DAG: rlwinm 3, [[REG3]], 8, 16, 23 ; ASM64-DAG: clrlslwi 3, [[REG3]], 24, 8
; ASM64-DAG: rlwimi 3, [[REG2]], 16, 0, 15 ; ASM64-DAG: insrwi 3, [[REG2]], 16, 0
; ASM64-DAG: rldimi 3, [[REG1]], 32, 0 ; ASM64-DAG: insrdi 3, [[REG1]], 32, 0
; ASM64-NEXT: bl .test_byval_7Byte ; ASM64-NEXT: bl .test_byval_7Byte
; ASM64-NEXT: nop ; ASM64-NEXT: nop
%struct.S8 = type { [8 x i8] } %struct.S8 = type { [8 x i8] }
@gS8 = external global %struct.S8, align 1 @gS8 = external global %struct.S8, align 1
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; ASM32-DAG: lwz 4, 4([[REGADDR]]) ; ASM32-DAG: lwz 4, 4([[REGADDR]])
; ASM32-DAG: lwz 5, 8([[REGADDR]]) ; ASM32-DAG: lwz 5, 8([[REGADDR]])
; ASM32-DAG: lwz 6, 12([[REGADDR]]) ; ASM32-DAG: lwz 6, 12([[REGADDR]])
; ASM32-DAG: lwz 7, 16([[REGADDR]]) ; ASM32-DAG: lwz 7, 16([[REGADDR]])
; ASM32-DAG: lwz 8, 20([[REGADDR]]) ; ASM32-DAG: lwz 8, 20([[REGADDR]])
; ASM32-DAG: lwz 9, 24([[REGADDR]]) ; ASM32-DAG: lwz 9, 24([[REGADDR]])
; ASM32-DAG: lbz 10, 30([[REGADDR]]) ; ASM32-DAG: lbz 10, 30([[REGADDR]])
; ASM32-DAG: lhz [[REG:[0-9]+]], 28([[REGADDR]]) ; ASM32-DAG: lhz [[REG:[0-9]+]], 28([[REGADDR]])
; ASM32-DAG: rlwinm 10, 10, 8, 16, 23 ; ASM32-DAG: clrlslwi 10, 10, 24, 8
; ASM32-DAG: rlwimi 10, [[REG]], 16, 0, 15 ; ASM32-DAG: insrwi 10, [[REG]], 16, 0
; ASM32-NEXT: bl .test_byval_31Byte ; ASM32-NEXT: bl .test_byval_31Byte
; ASM32-NEXT: nop ; ASM32-NEXT: nop
; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings. ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1 ; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
; 64BIT-NEXT: renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS31, $x2 :: (load 8 from got) ; 64BIT-NEXT: renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS31, $x2 :: (load 8 from got)
; 64BIT-DAG: renamable $x3 = LD 0, killed renamable $x[[REGADDR]] :: (load 8) ; 64BIT-DAG: renamable $x3 = LD 0, killed renamable $x[[REGADDR]] :: (load 8)
; 64BIT-DAG: renamable $x4 = LD 8, renamable $x[[REGADDR]] :: (load 8) ; 64BIT-DAG: renamable $x4 = LD 8, renamable $x[[REGADDR]] :: (load 8)
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; ASM64: stdu 1, -112(1) ; ASM64: stdu 1, -112(1)
; ASM64-NEXT: ld [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2) ; ASM64-NEXT: ld [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2)
; ASM64-DAG: ld 3, 0([[REGADDR]]) ; ASM64-DAG: ld 3, 0([[REGADDR]])
; ASM64-DAG: ld 4, 8([[REGADDR]]) ; ASM64-DAG: ld 4, 8([[REGADDR]])
; ASM64-DAG: ld 5, 16([[REGADDR]]) ; ASM64-DAG: ld 5, 16([[REGADDR]])
; ASM64-DAG: lwz [[REG1:[0-9]+]], 24([[REGADDR]]) ; ASM64-DAG: lwz [[REG1:[0-9]+]], 24([[REGADDR]])
; ASM64-DAG: lhz [[REG2:[0-9]+]], 28([[REGADDR]]) ; ASM64-DAG: lhz [[REG2:[0-9]+]], 28([[REGADDR]])
; ASM64-DAG: lbz [[REG3:[0-9]+]], 30([[REGADDR]]) ; ASM64-DAG: lbz [[REG3:[0-9]+]], 30([[REGADDR]])
; ASM64-DAG: rlwinm 6, [[REG3]], 8, 16, 23 ; ASM64-DAG: clrlslwi 6, [[REG3]], 24, 8
; ASM64-DAG: rlwimi 6, [[REG2]], 16, 0, 15 ; ASM64-DAG: insrwi 6, [[REG2]], 16, 0
; ASM64-DAG: rldimi 6, [[REG1]], 32, 0 ; ASM64-DAG: insrdi 6, [[REG1]], 32, 0
; ASM64-NEXT: bl .test_byval_31Byte ; ASM64-NEXT: bl .test_byval_31Byte
; ASM64-NEXT: nop ; ASM64-NEXT: nop
define double @test_byval_31Byte(%struct.S31* byval(%struct.S31) align 1 %s) { define double @test_byval_31Byte(%struct.S31* byval(%struct.S31) align 1 %s) {
entry: entry:
%gep = getelementptr inbounds %struct.S31, %struct.S31* %s, i32 0, i32 3 %gep = getelementptr inbounds %struct.S31, %struct.S31* %s, i32 0, i32 3
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llvm/test/CodeGen/PowerPC/aix-lower-jump-table.ll

Show First 20 Lines • Show All 131 Lines • ▼ Show 20 Lines
; 32LARGE-ASM: .vbyte 4, L..BB0_5-.LJTI0_0 ; 32LARGE-ASM: .vbyte 4, L..BB0_5-.LJTI0_0
; 64SMALL-ASM-LABEL: jump_table ; 64SMALL-ASM-LABEL: jump_table
; 64SMALL-ASM: .jump_table: ; 64SMALL-ASM: .jump_table:
; 64SMALL-ASM: addi 3, 3, -1 ; 64SMALL-ASM: addi 3, 3, -1
; 64SMALL-ASM: cmplwi 3, 3 ; 64SMALL-ASM: cmplwi 3, 3
; 64SMALL-ASM: bgt 0, L..BB0_6 ; 64SMALL-ASM: bgt 0, L..BB0_6
; 64SMALL-ASM: ld 4, L..C0(2) ; 64SMALL-ASM: ld 4, L..C0(2)
; 64SMALL-ASM: rldic 3, 3, 2, 30 ; 64SMALL-ASM: clrlsldi 3, 3, 32, 2
; 64SMALL-ASM: lwax 3, 3, 4 ; 64SMALL-ASM: lwax 3, 3, 4
; 64SMALL-ASM: add 3, 3, 4 ; 64SMALL-ASM: add 3, 3, 4
; 64SMALL-ASM: mtctr 3 ; 64SMALL-ASM: mtctr 3
; 64SMALL-ASM: bctr ; 64SMALL-ASM: bctr
; 64SMALL-ASM: L..BB0_2: ; 64SMALL-ASM: L..BB0_2:
; 64SMALL-ASM: L..BB0_3: ; 64SMALL-ASM: L..BB0_3:
; 64SMALL-ASM: L..BB0_4: ; 64SMALL-ASM: L..BB0_4:
; 64SMALL-ASM: L..BB0_5: ; 64SMALL-ASM: L..BB0_5:
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; 64SMALL-ASM: .vbyte 4, L..BB0_5-.LJTI0_0 ; 64SMALL-ASM: .vbyte 4, L..BB0_5-.LJTI0_0
; 64LARGE-ASM-LABEL: jump_table ; 64LARGE-ASM-LABEL: jump_table
; 64LARGE-ASM: .jump_table: ; 64LARGE-ASM: .jump_table:
; 64LARGE-ASM: addi 3, 3, -1 ; 64LARGE-ASM: addi 3, 3, -1
; 64LARGE-ASM: cmplwi 3, 3 ; 64LARGE-ASM: cmplwi 3, 3
; 64LARGE-ASM: bgt 0, L..BB0_6 ; 64LARGE-ASM: bgt 0, L..BB0_6
; 64LARGE-ASM: addis 4, L..C0@u(2) ; 64LARGE-ASM: addis 4, L..C0@u(2)
; 64LARGE-ASM: rldic 3, 3, 2, 30 ; 64LARGE-ASM: clrlsldi 3, 3, 32, 2
; 64LARGE-ASM: ld 4, L..C0@l(4) ; 64LARGE-ASM: ld 4, L..C0@l(4)
; 64LARGE-ASM: lwax 3, 3, 4 ; 64LARGE-ASM: lwax 3, 3, 4
; 64LARGE-ASM: add 3, 3, 4 ; 64LARGE-ASM: add 3, 3, 4
; 64LARGE-ASM: mtctr 3 ; 64LARGE-ASM: mtctr 3
; 64LARGE-ASM: bctr ; 64LARGE-ASM: bctr
; 64LARGE-ASM: L..BB0_2: ; 64LARGE-ASM: L..BB0_2:
; 64LARGE-ASM: L..BB0_3: ; 64LARGE-ASM: L..BB0_3:
; 64LARGE-ASM: L..BB0_4: ; 64LARGE-ASM: L..BB0_4:
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llvm/test/CodeGen/PowerPC/and-mask.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s ; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
; mask 0xFFFFFFFE ; mask 0xFFFFFFFE
define i32 @test1(i32 %a) { define i32 @test1(i32 %a) {
; CHECK-LABEL: test1: ; CHECK-LABEL: test1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: rlwinm 3, 3, 0, 0, 30 ; CHECK-NEXT: clrrwi 3, 3, 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%and = and i32 %a, -2 %and = and i32 %a, -2
ret i32 %and ret i32 %and
} }
; mask 0xFFFFFFFFFFFFFFF9 ; mask 0xFFFFFFFFFFFFFFF9
define i64 @test2(i64 %a) { define i64 @test2(i64 %a) {
; CHECK-LABEL: test2: ; CHECK-LABEL: test2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: rldicl 3, 3, 61, 2 ; CHECK-NEXT: rldicl 3, 3, 61, 2
; CHECK-NEXT: rotldi 3, 3, 3 ; CHECK-NEXT: rotldi 3, 3, 3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%and = and i64 %a, -7 %and = and i64 %a, -7
ret i64 %and ret i64 %and
} }
; mask: 0xFFFFFFC00000 ; mask: 0xFFFFFFC00000
define i64 @test3(i64 %a) { define i64 @test3(i64 %a) {
; CHECK-LABEL: test3: ; CHECK-LABEL: test3:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: rldicl 3, 3, 42, 22 ; CHECK-NEXT: srdi 3, 3, 22
; CHECK-NEXT: rldicl 3, 3, 22, 16 ; CHECK-NEXT: rldicl 3, 3, 22, 16
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%and = and i64 %a, 281474972516352 %and = and i64 %a, 281474972516352
ret i64 %and ret i64 %and
} }
; mask: 0xC000000FF ; mask: 0xC000000FF
define i64 @test4(i64 %a) { define i64 @test4(i64 %a) {
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llvm/test/CodeGen/PowerPC/andc.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-unknown | FileCheck %s ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-unknown | FileCheck %s
define i1 @and_cmp1(i32 %x, i32 %y) { define i1 @and_cmp1(i32 %x, i32 %y) {
; CHECK-LABEL: and_cmp1: ; CHECK-LABEL: and_cmp1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: andc 3, 4, 3 ; CHECK-NEXT: andc 3, 4, 3
; CHECK-NEXT: cntlzw 3, 3 ; CHECK-NEXT: cntlzw 3, 3
; CHECK-NEXT: rlwinm 3, 3, 27, 31, 31 ; CHECK-NEXT: extrwi 3, 3, 1, 26
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%and = and i32 %x, %y %and = and i32 %x, %y
%cmp = icmp eq i32 %and, %y %cmp = icmp eq i32 %and, %y
ret i1 %cmp ret i1 %cmp
} }
define i1 @and_cmp_const(i32 %x) { define i1 @and_cmp_const(i32 %x) {
; CHECK-LABEL: and_cmp_const: ; CHECK-LABEL: and_cmp_const:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li 4, 43 ; CHECK-NEXT: li 4, 43
; CHECK-NEXT: andc 3, 4, 3 ; CHECK-NEXT: andc 3, 4, 3
; CHECK-NEXT: cntlzw 3, 3 ; CHECK-NEXT: cntlzw 3, 3
; CHECK-NEXT: rlwinm 3, 3, 27, 31, 31 ; CHECK-NEXT: extrwi 3, 3, 1, 26
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%and = and i32 %x, 43 %and = and i32 %x, 43
%cmp = icmp eq i32 %and, 43 %cmp = icmp eq i32 %and, 43
ret i1 %cmp ret i1 %cmp
} }
define i1 @foo(i32 %i) { define i1 @foo(i32 %i) {
; CHECK-LABEL: foo: ; CHECK-LABEL: foo:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lis 4, 4660 ; CHECK-NEXT: lis 4, 4660
; CHECK-NEXT: ori 4, 4, 22136 ; CHECK-NEXT: ori 4, 4, 22136
; CHECK-NEXT: andc 3, 4, 3 ; CHECK-NEXT: andc 3, 4, 3
; CHECK-NEXT: cntlzw 3, 3 ; CHECK-NEXT: cntlzw 3, 3
; CHECK-NEXT: rlwinm 3, 3, 27, 31, 31 ; CHECK-NEXT: extrwi 3, 3, 1, 26
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%and = and i32 %i, 305419896 %and = and i32 %i, 305419896
%cmp = icmp eq i32 %and, 305419896 %cmp = icmp eq i32 %and, 305419896
ret i1 %cmp ret i1 %cmp
} }
define <4 x i32> @hidden_not_v4i32(<4 x i32> %x) { define <4 x i32> @hidden_not_v4i32(<4 x i32> %x) {
; CHECK-LABEL: hidden_not_v4i32: ; CHECK-LABEL: hidden_not_v4i32:
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llvm/test/CodeGen/PowerPC/anyext_srl.ll

Show All 12 Linesentry:
%cmp.i = icmp ne i32 %and.i, 0 %cmp.i = icmp ne i32 %and.i, 0
%arrayidx.i37 = bitcast %class.PB2* %s_b to i32* %arrayidx.i37 = bitcast %class.PB2* %s_b to i32*
%1 = load i32, i32* %arrayidx.i37, align 8, !tbaa !1 %1 = load i32, i32* %arrayidx.i37, align 8, !tbaa !1
%and.i4 = and i32 %1, 8 %and.i4 = and i32 %1, 8
%cmp.i5 = icmp ne i32 %and.i4, 0 %cmp.i5 = icmp ne i32 %and.i4, 0
%cmp = xor i1 %cmp.i, %cmp.i5 %cmp = xor i1 %cmp.i, %cmp.i5
ret i1 %cmp ret i1 %cmp
; CHECK-LABEL: @foo ; CHECK-LABEL: @foo
; CHECK: rldicl {{[0-9]+}}, {{[0-9]+}}, 61, 63 ; CHECK: extrdi {{[0-9]+}}, {{[0-9]+}}, 1, 60
} }
!1 = !{!2, !2, i64 0} !1 = !{!2, !2, i64 0}
!2 = !{!"int", !3, i64 0} !2 = !{!"int", !3, i64 0}
!3 = !{!"omnipotent char", !4, i64 0} !3 = !{!"omnipotent char", !4, i64 0}
!4 = !{!"Simple C++ TBAA"} !4 = !{!"Simple C++ TBAA"}

llvm/test/CodeGen/PowerPC/atomic-minmax.ll

Show First 20 Lines • Show All 228 Lines • ▼ Show 20 Lines
define void @ae16min(i16* nocapture dereferenceable(4) %minimum, i16 %val) #0 { define void @ae16min(i16* nocapture dereferenceable(4) %minimum, i16 %val) #0 {
entry: entry:
%0 = atomicrmw min i16* %minimum, i16 %val monotonic %0 = atomicrmw min i16* %minimum, i16 %val monotonic
ret void ret void
; CHECK-LABEL: @ae16min ; CHECK-LABEL: @ae16min
; CHECK-DAG: rlwinm [[SA1:[0-9]+]], 3, 3, 27, 27 ; CHECK-DAG: rlwinm [[SA1:[0-9]+]], 3, 3, 27, 27
; CHECK-DAG: li [[M1:[0-9]+]], 0 ; CHECK-DAG: li [[M1:[0-9]+]], 0
; CHECK-DAG: rldicr 3, 3, 0, 61 ; CHECK-DAG: clrrdi 3, 3, 2
; CHECK-DAG: xori [[SA:[0-9]+]], [[SA1]], 16 ; CHECK-DAG: xori [[SA:[0-9]+]], [[SA1]], 16
; CHECK-DAG: ori [[M2:[0-9]+]], [[M1]], 65535 ; CHECK-DAG: ori [[M2:[0-9]+]], [[M1]], 65535
; CHECK-DAG: slw [[SV:[0-9]+]], 4, [[SA]] ; CHECK-DAG: slw [[SV:[0-9]+]], 4, [[SA]]
; CHECK-DAG: slw [[M:[0-9]+]], [[M2]], [[SA]] ; CHECK-DAG: slw [[M:[0-9]+]], [[M2]], [[SA]]
; CHECK-DAG: and [[SMV:[0-9]+]], [[SV]], [[M]] ; CHECK-DAG: and [[SMV:[0-9]+]], [[SV]], [[M]]
; CHECK: lwarx [[OLDV:[0-9]+]], 0, 3 ; CHECK: lwarx [[OLDV:[0-9]+]], 0, 3
; CHECK: and [[MOLDV:[0-9]+]], [[OLDV]], [[M]] ; CHECK: and [[MOLDV:[0-9]+]], [[OLDV]], [[M]]
; CHECK: srw [[SMOLDV:[0-9]+]], [[MOLDV]], [[SA]] ; CHECK: srw [[SMOLDV:[0-9]+]], [[MOLDV]], [[SA]]
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define void @ae16max(i16* nocapture dereferenceable(4) %minimum, i16 %val) #0 { define void @ae16max(i16* nocapture dereferenceable(4) %minimum, i16 %val) #0 {
entry: entry:
%0 = atomicrmw max i16* %minimum, i16 %val monotonic %0 = atomicrmw max i16* %minimum, i16 %val monotonic
ret void ret void
; CHECK-LABEL: @ae16max ; CHECK-LABEL: @ae16max
; CHECK-DAG: rlwinm [[SA1:[0-9]+]], 3, 3, 27, 27 ; CHECK-DAG: rlwinm [[SA1:[0-9]+]], 3, 3, 27, 27
; CHECK-DAG: li [[M1:[0-9]+]], 0 ; CHECK-DAG: li [[M1:[0-9]+]], 0
; CHECK-DAG: rldicr 3, 3, 0, 61 ; CHECK-DAG: clrrdi 3, 3, 2
; CHECK-DAG: xori [[SA:[0-9]+]], [[SA1]], 16 ; CHECK-DAG: xori [[SA:[0-9]+]], [[SA1]], 16
; CHECK-DAG: ori [[M2:[0-9]+]], [[M1]], 65535 ; CHECK-DAG: ori [[M2:[0-9]+]], [[M1]], 65535
; CHECK-DAG: slw [[SV:[0-9]+]], 4, [[SA]] ; CHECK-DAG: slw [[SV:[0-9]+]], 4, [[SA]]
; CHECK-DAG: slw [[M:[0-9]+]], [[M2]], [[SA]] ; CHECK-DAG: slw [[M:[0-9]+]], [[M2]], [[SA]]
; CHECK-DAG: and [[SMV:[0-9]+]], [[SV]], [[M]] ; CHECK-DAG: and [[SMV:[0-9]+]], [[SV]], [[M]]
; CHECK: lwarx [[OLDV:[0-9]+]], 0, 3 ; CHECK: lwarx [[OLDV:[0-9]+]], 0, 3
; CHECK: and [[MOLDV:[0-9]+]], [[OLDV]], [[M]] ; CHECK: and [[MOLDV:[0-9]+]], [[OLDV]], [[M]]
; CHECK: srw [[SMOLDV:[0-9]+]], [[MOLDV]], [[SA]] ; CHECK: srw [[SMOLDV:[0-9]+]], [[MOLDV]], [[SA]]
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define void @ae16umin(i16* nocapture dereferenceable(4) %minimum, i16 %val) #0 { define void @ae16umin(i16* nocapture dereferenceable(4) %minimum, i16 %val) #0 {
entry: entry:
%0 = atomicrmw umin i16* %minimum, i16 %val monotonic %0 = atomicrmw umin i16* %minimum, i16 %val monotonic
ret void ret void
; CHECK-LABEL: @ae16umin ; CHECK-LABEL: @ae16umin
; CHECK-DAG: rlwinm [[SA1:[0-9]+]], 3, 3, 27, 27 ; CHECK-DAG: rlwinm [[SA1:[0-9]+]], 3, 3, 27, 27
; CHECK-DAG: li [[M1:[0-9]+]], 0 ; CHECK-DAG: li [[M1:[0-9]+]], 0
; CHECK-DAG: rldicr 3, 3, 0, 61 ; CHECK-DAG: clrrdi 3, 3, 2
; CHECK-DAG: xori [[SA:[0-9]+]], [[SA1]], 16 ; CHECK-DAG: xori [[SA:[0-9]+]], [[SA1]], 16
; CHECK-DAG: ori [[M2:[0-9]+]], [[M1]], 65535 ; CHECK-DAG: ori [[M2:[0-9]+]], [[M1]], 65535
; CHECK-DAG: slw [[SV:[0-9]+]], 4, [[SA]] ; CHECK-DAG: slw [[SV:[0-9]+]], 4, [[SA]]
; CHECK-DAG: slw [[M:[0-9]+]], [[M2]], [[SA]] ; CHECK-DAG: slw [[M:[0-9]+]], [[M2]], [[SA]]
; CHECK-DAG: and [[SMV:[0-9]+]], [[SV]], [[M]] ; CHECK-DAG: and [[SMV:[0-9]+]], [[SV]], [[M]]
; CHECK: lwarx [[OLDV:[0-9]+]], 0, 3 ; CHECK: lwarx [[OLDV:[0-9]+]], 0, 3
; CHECK: and [[MOLDV:[0-9]+]], [[OLDV]], [[M]] ; CHECK: and [[MOLDV:[0-9]+]], [[OLDV]], [[M]]
; CHECK: cmplw 4, [[MOLDV]] ; CHECK: cmplw 4, [[MOLDV]]
; CHECK: bgelr 0 ; CHECK: bgelr 0
; CHECK: andc [[NOLDV:[0-9]+]], [[OLDV]], [[M]] ; CHECK: andc [[NOLDV:[0-9]+]], [[OLDV]], [[M]]
; CHECK: or [[NEWV:[0-9]+]], [[SMV]], [[NOLDV]] ; CHECK: or [[NEWV:[0-9]+]], [[SMV]], [[NOLDV]]
; CHECK: stwcx. [[NEWV]], 0, 3 ; CHECK: stwcx. [[NEWV]], 0, 3
; CHECK: bne 0, ; CHECK: bne 0,
; CHECK: blr ; CHECK: blr
} }
define void @ae16umax(i16* nocapture dereferenceable(4) %minimum, i16 %val) #0 { define void @ae16umax(i16* nocapture dereferenceable(4) %minimum, i16 %val) #0 {
entry: entry:
%0 = atomicrmw umax i16* %minimum, i16 %val monotonic %0 = atomicrmw umax i16* %minimum, i16 %val monotonic
ret void ret void
; CHECK-LABEL: @ae16umax ; CHECK-LABEL: @ae16umax
; CHECK-DAG: rlwinm [[SA1:[0-9]+]], 3, 3, 27, 27 ; CHECK-DAG: rlwinm [[SA1:[0-9]+]], 3, 3, 27, 27
; CHECK-DAG: li [[M1:[0-9]+]], 0 ; CHECK-DAG: li [[M1:[0-9]+]], 0
; CHECK-DAG: rldicr 3, 3, 0, 61 ; CHECK-DAG: clrrdi 3, 3, 2
; CHECK-DAG: xori [[SA:[0-9]+]], [[SA1]], 16 ; CHECK-DAG: xori [[SA:[0-9]+]], [[SA1]], 16
; CHECK-DAG: ori [[M2:[0-9]+]], [[M1]], 65535 ; CHECK-DAG: ori [[M2:[0-9]+]], [[M1]], 65535
; CHECK-DAG: slw [[SV:[0-9]+]], 4, [[SA]] ; CHECK-DAG: slw [[SV:[0-9]+]], 4, [[SA]]
; CHECK-DAG: slw [[M:[0-9]+]], [[M2]], [[SA]] ; CHECK-DAG: slw [[M:[0-9]+]], [[M2]], [[SA]]
; CHECK-DAG: and [[SMV:[0-9]+]], [[SV]], [[M]] ; CHECK-DAG: and [[SMV:[0-9]+]], [[SV]], [[M]]
; CHECK: lwarx [[OLDV:[0-9]+]], 0, 3 ; CHECK: lwarx [[OLDV:[0-9]+]], 0, 3
; CHECK: and [[MOLDV:[0-9]+]], [[OLDV]], [[M]] ; CHECK: and [[MOLDV:[0-9]+]], [[OLDV]], [[M]]
; CHECK: cmplw 4, [[MOLDV]] ; CHECK: cmplw 4, [[MOLDV]]
; CHECK: blelr 0 ; CHECK: blelr 0
; CHECK: andc [[NOLDV:[0-9]+]], [[OLDV]], [[M]] ; CHECK: andc [[NOLDV:[0-9]+]], [[OLDV]], [[M]]
; CHECK: or [[NEWV:[0-9]+]], [[SMV]], [[NOLDV]] ; CHECK: or [[NEWV:[0-9]+]], [[SMV]], [[NOLDV]]
; CHECK: stwcx. [[NEWV]], 0, 3 ; CHECK: stwcx. [[NEWV]], 0, 3
; CHECK: bne 0, ; CHECK: bne 0,
; CHECK: blr ; CHECK: blr
} }
define void @ae8min(i8* nocapture dereferenceable(4) %minimum, i8 %val) #0 { define void @ae8min(i8* nocapture dereferenceable(4) %minimum, i8 %val) #0 {
entry: entry:
%0 = atomicrmw min i8* %minimum, i8 %val monotonic %0 = atomicrmw min i8* %minimum, i8 %val monotonic
ret void ret void
; CHECK-LABEL: @ae8min ; CHECK-LABEL: @ae8min
; CHECK-DAG: rlwinm [[SA1:[0-9]+]], 3, 3, 27, 28 ; CHECK-DAG: clrlslwi [[SA1:[0-9]+]], 3, 30, 3
; CHECK-DAG: li [[M1:[0-9]+]], 255 ; CHECK-DAG: li [[M1:[0-9]+]], 255
; CHECK-DAG: rldicr 3, 3, 0, 61 ; CHECK-DAG: clrrdi 3, 3, 2
; CHECK-DAG: xori [[SA:[0-9]+]], [[SA1]], 24 ; CHECK-DAG: xori [[SA:[0-9]+]], [[SA1]], 24
; CHECK-DAG: slw [[SV:[0-9]+]], 4, [[SA]] ; CHECK-DAG: slw [[SV:[0-9]+]], 4, [[SA]]
; CHECK-DAG: slw [[M:[0-9]+]], [[M1]], [[SA]] ; CHECK-DAG: slw [[M:[0-9]+]], [[M1]], [[SA]]
; CHECK-DAG: and [[SMV:[0-9]+]], [[SV]], [[M]] ; CHECK-DAG: and [[SMV:[0-9]+]], [[SV]], [[M]]
; CHECK: lwarx [[OLDV:[0-9]+]], 0, 3 ; CHECK: lwarx [[OLDV:[0-9]+]], 0, 3
; CHECK: and [[MOLDV:[0-9]+]], [[OLDV]], [[M]] ; CHECK: and [[MOLDV:[0-9]+]], [[OLDV]], [[M]]
; CHECK: srw [[SMOLDV:[0-9]+]], [[MOLDV]], [[SA]] ; CHECK: srw [[SMOLDV:[0-9]+]], [[MOLDV]], [[SA]]
; CHECK: extsb [[SESMOLDV:[0-9]+]], [[SMOLDV]] ; CHECK: extsb [[SESMOLDV:[0-9]+]], [[SMOLDV]]
; CHECK: cmpw 4, [[SESMOLDV]] ; CHECK: cmpw 4, [[SESMOLDV]]
; CHECK: bgelr 0 ; CHECK: bgelr 0
; CHECK: andc [[NOLDV:[0-9]+]], [[OLDV]], [[M]] ; CHECK: andc [[NOLDV:[0-9]+]], [[OLDV]], [[M]]
; CHECK: or [[NEWV:[0-9]+]], [[SMV]], [[NOLDV]] ; CHECK: or [[NEWV:[0-9]+]], [[SMV]], [[NOLDV]]
; CHECK: stwcx. [[NEWV]], 0, 3 ; CHECK: stwcx. [[NEWV]], 0, 3
; CHECK: bne 0, ; CHECK: bne 0,
; CHECK: blr ; CHECK: blr
} }
define void @ae8max(i8* nocapture dereferenceable(4) %minimum, i8 %val) #0 { define void @ae8max(i8* nocapture dereferenceable(4) %minimum, i8 %val) #0 {
entry: entry:
%0 = atomicrmw max i8* %minimum, i8 %val monotonic %0 = atomicrmw max i8* %minimum, i8 %val monotonic
ret void ret void
; CHECK-LABEL: @ae8max ; CHECK-LABEL: @ae8max
; CHECK-DAG: rlwinm [[SA1:[0-9]+]], 3, 3, 27, 28 ; CHECK-DAG: clrlslwi [[SA1:[0-9]+]], 3, 30, 3
; CHECK-DAG: li [[M1:[0-9]+]], 255 ; CHECK-DAG: li [[M1:[0-9]+]], 255
; CHECK-DAG: rldicr 3, 3, 0, 61 ; CHECK-DAG: clrrdi 3, 3, 2
; CHECK-DAG: xori [[SA:[0-9]+]], [[SA1]], 24 ; CHECK-DAG: xori [[SA:[0-9]+]], [[SA1]], 24
; CHECK-DAG: slw [[SV:[0-9]+]], 4, [[SA]] ; CHECK-DAG: slw [[SV:[0-9]+]], 4, [[SA]]
; CHECK-DAG: slw [[M:[0-9]+]], [[M1]], [[SA]] ; CHECK-DAG: slw [[M:[0-9]+]], [[M1]], [[SA]]
; CHECK-DAG: and [[SMV:[0-9]+]], [[SV]], [[M]] ; CHECK-DAG: and [[SMV:[0-9]+]], [[SV]], [[M]]
; CHECK: lwarx [[OLDV:[0-9]+]], 0, 3 ; CHECK: lwarx [[OLDV:[0-9]+]], 0, 3
; CHECK: and [[MOLDV:[0-9]+]], [[OLDV]], [[M]] ; CHECK: and [[MOLDV:[0-9]+]], [[OLDV]], [[M]]
; CHECK: srw [[SMOLDV:[0-9]+]], [[MOLDV]], [[SA]] ; CHECK: srw [[SMOLDV:[0-9]+]], [[MOLDV]], [[SA]]
; CHECK: extsb [[SESMOLDV:[0-9]+]], [[SMOLDV]] ; CHECK: extsb [[SESMOLDV:[0-9]+]], [[SMOLDV]]
; CHECK: cmpw 4, [[SESMOLDV]] ; CHECK: cmpw 4, [[SESMOLDV]]
; CHECK: blelr 0 ; CHECK: blelr 0
; CHECK: andc [[NOLDV:[0-9]+]], [[OLDV]], [[M]] ; CHECK: andc [[NOLDV:[0-9]+]], [[OLDV]], [[M]]
; CHECK: or [[NEWV:[0-9]+]], [[SMV]], [[NOLDV]] ; CHECK: or [[NEWV:[0-9]+]], [[SMV]], [[NOLDV]]
; CHECK: stwcx. [[NEWV]], 0, 3 ; CHECK: stwcx. [[NEWV]], 0, 3
; CHECK: bne 0, ; CHECK: bne 0,
; CHECK: blr ; CHECK: blr
} }
define void @ae8umin(i8* nocapture dereferenceable(4) %minimum, i8 %val) #0 { define void @ae8umin(i8* nocapture dereferenceable(4) %minimum, i8 %val) #0 {
entry: entry:
%0 = atomicrmw umin i8* %minimum, i8 %val monotonic %0 = atomicrmw umin i8* %minimum, i8 %val monotonic
ret void ret void
; CHECK-LABEL: @ae8umin ; CHECK-LABEL: @ae8umin
; CHECK-DAG: rlwinm [[SA1:[0-9]+]], 3, 3, 27, 28 ; CHECK-DAG: clrlslwi [[SA1:[0-9]+]], 3, 30, 3
; CHECK-DAG: li [[M1:[0-9]+]], 255 ; CHECK-DAG: li [[M1:[0-9]+]], 255
; CHECK-DAG: rldicr 3, 3, 0, 61 ; CHECK-DAG: clrrdi 3, 3, 2
; CHECK-DAG: xori [[SA:[0-9]+]], [[SA1]], 24 ; CHECK-DAG: xori [[SA:[0-9]+]], [[SA1]], 24
; CHECK-DAG: slw [[SV:[0-9]+]], 4, [[SA]] ; CHECK-DAG: slw [[SV:[0-9]+]], 4, [[SA]]
; CHECK-DAG: slw [[M:[0-9]+]], [[M1]], [[SA]] ; CHECK-DAG: slw [[M:[0-9]+]], [[M1]], [[SA]]
; CHECK-DAG: and [[SMV:[0-9]+]], [[SV]], [[M]] ; CHECK-DAG: and [[SMV:[0-9]+]], [[SV]], [[M]]
; CHECK: lwarx [[OLDV:[0-9]+]], 0, 3 ; CHECK: lwarx [[OLDV:[0-9]+]], 0, 3
; CHECK: and [[MOLDV:[0-9]+]], [[OLDV]], [[M]] ; CHECK: and [[MOLDV:[0-9]+]], [[OLDV]], [[M]]
; CHECK: cmplw 4, [[MOLDV]] ; CHECK: cmplw 4, [[MOLDV]]
; CHECK: bgelr 0 ; CHECK: bgelr 0
; CHECK: andc [[NOLDV:[0-9]+]], [[OLDV]], [[M]] ; CHECK: andc [[NOLDV:[0-9]+]], [[OLDV]], [[M]]
; CHECK: or [[NEWV:[0-9]+]], [[SMV]], [[NOLDV]] ; CHECK: or [[NEWV:[0-9]+]], [[SMV]], [[NOLDV]]
; CHECK: stwcx. [[NEWV]], 0, 3 ; CHECK: stwcx. [[NEWV]], 0, 3
; CHECK: bne 0, ; CHECK: bne 0,
; CHECK: blr ; CHECK: blr
} }
define void @ae8umax(i8* nocapture dereferenceable(4) %minimum, i8 %val) #0 { define void @ae8umax(i8* nocapture dereferenceable(4) %minimum, i8 %val) #0 {
entry: entry:
%0 = atomicrmw umax i8* %minimum, i8 %val monotonic %0 = atomicrmw umax i8* %minimum, i8 %val monotonic
ret void ret void
; CHECK-LABEL: @ae8umax ; CHECK-LABEL: @ae8umax
; CHECK-DAG: rlwinm [[SA1:[0-9]+]], 3, 3, 27, 28 ; CHECK-DAG: clrlslwi [[SA1:[0-9]+]], 3, 30, 3
; CHECK-DAG: li [[M1:[0-9]+]], 255 ; CHECK-DAG: li [[M1:[0-9]+]], 255
; CHECK-DAG: rldicr 3, 3, 0, 61 ; CHECK-DAG: clrrdi 3, 3, 2
; CHECK-DAG: xori [[SA:[0-9]+]], [[SA1]], 24 ; CHECK-DAG: xori [[SA:[0-9]+]], [[SA1]], 24
; CHECK-DAG: slw [[SV:[0-9]+]], 4, [[SA]] ; CHECK-DAG: slw [[SV:[0-9]+]], 4, [[SA]]
; CHECK-DAG: slw [[M:[0-9]+]], [[M1]], [[SA]] ; CHECK-DAG: slw [[M:[0-9]+]], [[M1]], [[SA]]
; CHECK-DAG: and [[SMV:[0-9]+]], [[SV]], [[M]] ; CHECK-DAG: and [[SMV:[0-9]+]], [[SV]], [[M]]
; CHECK: lwarx [[OLDV:[0-9]+]], 0, 3 ; CHECK: lwarx [[OLDV:[0-9]+]], 0, 3
; CHECK: and [[MOLDV:[0-9]+]], [[OLDV]], [[M]] ; CHECK: and [[MOLDV:[0-9]+]], [[OLDV]], [[M]]
; CHECK: cmplw 4, [[MOLDV]] ; CHECK: cmplw 4, [[MOLDV]]
; CHECK: blelr 0 ; CHECK: blelr 0
Show All 10 Lines

llvm/test/CodeGen/PowerPC/bitfieldinsert.ll

Show All 10 Lines
; p->b = v; ; p->b = v;
; } ; }
%struct.s64 = type { i64 } %struct.s64 = type { i64 }
define void @bitfieldinsert64(%struct.s64* nocapture %p, i16 zeroext %v) { define void @bitfieldinsert64(%struct.s64* nocapture %p, i16 zeroext %v) {
; CHECK-LABEL: @bitfieldinsert64 ; CHECK-LABEL: @bitfieldinsert64
; CHECK: ld [[REG1:[0-9]+]], 0(3) ; CHECK: ld [[REG1:[0-9]+]], 0(3)
; CHECK-NEXT: rlwimi [[REG1]], 4, 5, 11, 26 ; CHECK-NEXT: insrwi [[REG1]], 4, 16, 11
; CHECK-NEXT: std [[REG1]], 0(3) ; CHECK-NEXT: std [[REG1]], 0(3)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%0 = getelementptr inbounds %struct.s64, %struct.s64* %p, i64 0, i32 0 %0 = getelementptr inbounds %struct.s64, %struct.s64* %p, i64 0, i32 0
%1 = zext i16 %v to i64 %1 = zext i16 %v to i64
%bf.load = load i64, i64* %0, align 8 %bf.load = load i64, i64* %0, align 8
%bf.shl = shl nuw nsw i64 %1, 5 %bf.shl = shl nuw nsw i64 %1, 5
%bf.clear = and i64 %bf.load, -2097121 %bf.clear = and i64 %bf.load, -2097121
Show All 13 Lines
; p->b = v; ; p->b = v;
; } ; }
%struct.s32 = type { i32 } %struct.s32 = type { i32 }
define void @bitfieldinsert32(%struct.s32* nocapture %p, i32 zeroext %v) { define void @bitfieldinsert32(%struct.s32* nocapture %p, i32 zeroext %v) {
; CHECK-LABEL: @bitfieldinsert32 ; CHECK-LABEL: @bitfieldinsert32
; CHECK: lwz [[REG1:[0-9]+]], 0(3) ; CHECK: lwz [[REG1:[0-9]+]], 0(3)
; CHECK-NEXT: rlwimi [[REG1]], 4, 8, 8, 23 ; CHECK-NEXT: insrwi [[REG1]], 4, 16, 8
; CHECK-NEXT: stw [[REG1]], 0(3) ; CHECK-NEXT: stw [[REG1]], 0(3)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%0 = getelementptr inbounds %struct.s32, %struct.s32* %p, i64 0, i32 0 %0 = getelementptr inbounds %struct.s32, %struct.s32* %p, i64 0, i32 0
%bf.load = load i32, i32* %0, align 4 %bf.load = load i32, i32* %0, align 4
%bf.value = shl i32 %v, 8 %bf.value = shl i32 %v, 8
%bf.shl = and i32 %bf.value, 16776960 %bf.shl = and i32 %bf.value, 16776960
%bf.clear = and i32 %bf.load, -16776961 %bf.clear = and i32 %bf.load, -16776961
Show All 13 Lines
; p->b = v; ; p->b = v;
; } ; }
%struct.s64b = type { i24, i24 } %struct.s64b = type { i24, i24 }
define void @bitfieldinsert64b(%struct.s64b* nocapture %p, i8 zeroext %v) { define void @bitfieldinsert64b(%struct.s64b* nocapture %p, i8 zeroext %v) {
; CHECK-LABEL: @bitfieldinsert64b ; CHECK-LABEL: @bitfieldinsert64b
; CHECK: lwz [[REG1:[0-9]+]], 0(3) ; CHECK: lwz [[REG1:[0-9]+]], 0(3)
; CHECK-NEXT: rlwimi [[REG1]], 4, 4, 12, 27 ; CHECK-NEXT: insrwi [[REG1]], 4, 16, 12
; CHECK-NEXT: stw [[REG1]], 0(3) ; CHECK-NEXT: stw [[REG1]], 0(3)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%conv = zext i8 %v to i32 %conv = zext i8 %v to i32
%0 = bitcast %struct.s64b* %p to i32* %0 = bitcast %struct.s64b* %p to i32*
%bf.load = load i32, i32* %0, align 4 %bf.load = load i32, i32* %0, align 4
%bf.shl = shl nuw nsw i32 %conv, 4 %bf.shl = shl nuw nsw i32 %conv, 4
%bf.clear = and i32 %bf.load, -1048561 %bf.clear = and i32 %bf.load, -1048561
Show All 12 Lines
; p->b = v; ; p->b = v;
; } ; }
%struct.s64c = type { i32, [4 x i8] } %struct.s64c = type { i32, [4 x i8] }
define void @bitfieldinsert64c(%struct.s64c* nocapture %p, i16 zeroext %v) { define void @bitfieldinsert64c(%struct.s64c* nocapture %p, i16 zeroext %v) {
; CHECK-LABEL: @bitfieldinsert64c ; CHECK-LABEL: @bitfieldinsert64c
; CHECK: lwz [[REG1:[0-9]+]], 0(3) ; CHECK: lwz [[REG1:[0-9]+]], 0(3)
; CHECK-NEXT: rlwimi [[REG1]], 4, 5, 11, 26 ; CHECK-NEXT: insrwi [[REG1]], 4, 16, 11
; CHECK-NEXT: stw [[REG1]], 0(3) ; CHECK-NEXT: stw [[REG1]], 0(3)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%conv = zext i16 %v to i32 %conv = zext i16 %v to i32
%0 = getelementptr inbounds %struct.s64c, %struct.s64c* %p, i64 0, i32 0 %0 = getelementptr inbounds %struct.s64c, %struct.s64c* %p, i64 0, i32 0
%bf.load = load i32, i32* %0, align 8 %bf.load = load i32, i32* %0, align 8
%bf.shl = shl nuw nsw i32 %conv, 5 %bf.shl = shl nuw nsw i32 %conv, 5
%bf.clear = and i32 %bf.load, -2097121 %bf.clear = and i32 %bf.load, -2097121
%bf.set = or i32 %bf.clear, %bf.shl %bf.set = or i32 %bf.clear, %bf.shl
store i32 %bf.set, i32* %0, align 8 store i32 %bf.set, i32* %0, align 8
ret void ret void
} }

llvm/test/CodeGen/PowerPC/bperm.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
define zeroext i32 @bs4(i32 zeroext %a) #0 { define zeroext i32 @bs4(i32 zeroext %a) #0 {
entry: entry:
%0 = tail call i32 @llvm.bswap.i32(i32 %a) %0 = tail call i32 @llvm.bswap.i32(i32 %a)
ret i32 %0 ret i32 %0
; CHECK-LABEL: @bs4 ; CHECK-LABEL: @bs4
; CHECK: rotlwi [[REG1:[0-9]+]], 3, 8 ; CHECK: rotlwi [[REG1:[0-9]+]], 3, 8
; CHECK: rlwimi [[REG1]], 3, 24, 16, 23 ; CHECK: rlwimi [[REG1]], 3, 24, 16, 23
; CHECK: rlwimi [[REG1]], 3, 24, 0, 7 ; CHECK: insrwi [[REG1]], 3, 8, 0
; CHECK: mr 3, [[REG1]] ; CHECK: mr 3, [[REG1]]
; CHECK: blr ; CHECK: blr
} }
define i64 @bs8(i64 %x) #0 { define i64 @bs8(i64 %x) #0 {
entry: entry:
%0 = tail call i64 @llvm.bswap.i64(i64 %x) %0 = tail call i64 @llvm.bswap.i64(i64 %x)
ret i64 %0 ret i64 %0
; CHECK-LABEL: @bs8 ; CHECK-LABEL: @bs8
; CHECK-DAG: rotldi [[REG1:[0-9]+]], 3, 16 ; CHECK-DAG: rotldi [[REG1:[0-9]+]], 3, 16
; CHECK-DAG: rotldi [[REG2:[0-9]+]], 3, 8 ; CHECK-DAG: rotldi [[REG2:[0-9]+]], 3, 8
; CHECK-DAG: rotldi [[REG3:[0-9]+]], 3, 24 ; CHECK-DAG: rotldi [[REG3:[0-9]+]], 3, 24
; CHECK-DAG: rldimi [[REG2]], [[REG1]], 8, 48 ; CHECK-DAG: insrdi [[REG2]], [[REG1]], 8, 48
; CHECK-DAG: rotldi [[REG4:[0-9]+]], 3, 32 ; CHECK-DAG: rotldi [[REG4:[0-9]+]], 3, 32
; CHECK-DAG: rldimi [[REG2]], [[REG3]], 16, 40 ; CHECK-DAG: insrdi [[REG2]], [[REG3]], 8, 40
; CHECK-DAG: rotldi [[REG5:[0-9]+]], 3, 48 ; CHECK-DAG: rotldi [[REG5:[0-9]+]], 3, 48
; CHECK-DAG: rldimi [[REG2]], [[REG4]], 24, 32 ; CHECK-DAG: insrdi [[REG2]], [[REG4]], 8, 32
; CHECK-DAG: rotldi [[REG6:[0-9]+]], 3, 56 ; CHECK-DAG: rotldi [[REG6:[0-9]+]], 3, 56
; CHECK-DAG: rldimi [[REG2]], [[REG5]], 40, 16 ; CHECK-DAG: insrdi [[REG2]], [[REG5]], 8, 16
; CHECK-DAG: rldimi [[REG2]], [[REG6]], 48, 8 ; CHECK-DAG: nsrdi [[REG2]], [[REG6]], 8, 8
; CHECK-DAG: rldimi [[REG2]], 3, 56, 0 ; CHECK-DAG: insrdi [[REG2]], 3, 8, 0
; CHECK: mr 3, [[REG2]] ; CHECK: mr 3, [[REG2]]
; CHECK: blr ; CHECK: blr
} }
define i64 @test1(i64 %i0, i64 %i1) #0 { define i64 @test1(i64 %i0, i64 %i1) #0 {
entry: entry:
%0 = lshr i64 %i1, 8 %0 = lshr i64 %i1, 8
%and = and i64 %0, 5963776000 %and = and i64 %0, 5963776000
▲ Show 20 Lines • Show All 71 Lines • ▼ Show 20 Linesentry:
%and = lshr i32 %x, 16 %and = lshr i32 %x, 16
%shr = and i32 %and, 255 %shr = and i32 %and, 255
%and1 = shl i32 %x, 16 %and1 = shl i32 %x, 16
%shl = and i32 %and1, 16711680 %shl = and i32 %and1, 16711680
%or = or i32 %shr, %shl %or = or i32 %shr, %shl
ret i32 %or ret i32 %or
; CHECK-LABEL: @test6 ; CHECK-LABEL: @test6
; CHECK: rlwinm [[REG1:[0-9]+]], 3, 16, 24, 31 ; CHECK: extrwi [[REG1:[0-9]+]], 3, 8, 8
; CHECK: rlwimi [[REG1]], 3, 16, 8, 15 ; CHECK: insrwi [[REG1]], 3, 8, 8
; CHECK: mr 3, [[REG1]] ; CHECK: mr 3, [[REG1]]
; CHECK: blr ; CHECK: blr
} }
define i64 @test7(i64 %i0, i64 %i1) #0 { define i64 @test7(i64 %i0, i64 %i1) #0 {
entry: entry:
%0 = lshr i64 %i0, 5 %0 = lshr i64 %i0, 5
%and = and i64 %0, 58195968 %and = and i64 %0, 58195968
Show All 30 Linesentry:
%or4 = or i64 %and, %and3 %or4 = or i64 %and, %and3
ret i64 %or4 ret i64 %or4
; CHECK-LABEL: @test9 ; CHECK-LABEL: @test9
; CHECK-DAG: lis [[REG1:[0-9]+]], 1440 ; CHECK-DAG: lis [[REG1:[0-9]+]], 1440
; CHECK-DAG: rotldi [[REG5:[0-9]+]], 4, 62 ; CHECK-DAG: rotldi [[REG5:[0-9]+]], 4, 62
; CHECK-DAG: rotldi [[REG6:[0-9]+]], 4, 50 ; CHECK-DAG: rotldi [[REG6:[0-9]+]], 4, 50
; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 4 ; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 4
; CHECK-DAG: rldimi [[REG6]], [[REG5]], 53, 0 ; CHECK-DAG: insrdi [[REG6]], [[REG5]], 11, 0
; CHECK-DAG: sldi [[REG3:[0-9]+]], [[REG2]], 32 ; CHECK-DAG: sldi [[REG3:[0-9]+]], [[REG2]], 32
; CHECK-DAG: oris [[REG4:[0-9]+]], [[REG3]], 25464 ; CHECK-DAG: oris [[REG4:[0-9]+]], [[REG3]], 25464
; CHECK: and 3, [[REG6]], [[REG4]] ; CHECK: and 3, [[REG6]], [[REG4]]
; CHECK: blr ; CHECK: blr
} }
define i64 @test10(i64 %i0, i64 %i1) #0 { define i64 @test10(i64 %i0, i64 %i1) #0 {
entry: entry:
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Linesentry:
%shr = lshr i64 %x, 28 %shr = lshr i64 %x, 28
%and1 = and i64 %shr, 15 %and1 = and i64 %shr, 15
%and2 = and i64 %x, -4294967296 %and2 = and i64 %x, -4294967296
%or = or i64 %and1, %and2 %or = or i64 %and1, %and2
%or3 = or i64 %or, %and %or3 = or i64 %or, %and
ret i64 %or3 ret i64 %or3
; CHECK-LABEL: @test14 ; CHECK-LABEL: @test14
; CHECK: rldicr [[REG1:[0-9]+]], 3, 0, 31 ; CHECK: clrrdi [[REG1:[0-9]+]], 3, 32
; CHECK: rlwimi [[REG1]], 3, 4, 24, 31 ; CHECK: rlwimi [[REG1]], 3, 4, 24, 31
; CHECK: mr 3, [[REG1]] ; CHECK: mr 3, [[REG1]]
; CHECK: blr ; CHECK: blr
} }
define i64 @test15(i64 %x) #0 { define i64 @test15(i64 %x) #0 {
entry: entry:
%shl = shl i64 %x, 4 %shl = shl i64 %x, 4
Show All 13 Lines
define i64 @test16(i64 %a, i64 %b) #0 { define i64 @test16(i64 %a, i64 %b) #0 {
entry: entry:
%and = and i64 %a, 4294967295 %and = and i64 %a, 4294967295
%shl = shl i64 %b, 32 %shl = shl i64 %b, 32
%or = or i64 %and, %shl %or = or i64 %and, %shl
ret i64 %or ret i64 %or
; CHECK-LABEL: @test16 ; CHECK-LABEL: @test16
; CHECK: rldimi 3, 4, 32, 0 ; CHECK: insrdi 3, 4, 32, 0
; CHECK: blr ; CHECK: blr
} }
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
declare i32 @llvm.bswap.i32(i32) #0 declare i32 @llvm.bswap.i32(i32) #0
declare i64 @llvm.bswap.i64(i64) #0 declare i64 @llvm.bswap.i64(i64) #0
attributes #0 = { nounwind readnone } attributes #0 = { nounwind readnone }

llvm/test/CodeGen/PowerPC/bswap64.ll

Show All 12 Lines
; CHECK-NEXT: xxbrd 0, 34 ; CHECK-NEXT: xxbrd 0, 34
; CHECK-NEXT: mffprd 3, 0 ; CHECK-NEXT: mffprd 3, 0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; NO-ALTIVEC-LABEL: bswap64: ; NO-ALTIVEC-LABEL: bswap64:
; NO-ALTIVEC: # %bb.0: # %entry ; NO-ALTIVEC: # %bb.0: # %entry
; NO-ALTIVEC-NEXT: rotldi 5, 3, 16 ; NO-ALTIVEC-NEXT: rotldi 5, 3, 16
; NO-ALTIVEC-NEXT: rotldi 4, 3, 8 ; NO-ALTIVEC-NEXT: rotldi 4, 3, 8
; NO-ALTIVEC-NEXT: rldimi 4, 5, 8, 48 ; NO-ALTIVEC-NEXT: insrdi 4, 5, 8, 48
; NO-ALTIVEC-NEXT: rotldi 5, 3, 24 ; NO-ALTIVEC-NEXT: rotldi 5, 3, 24
; NO-ALTIVEC-NEXT: rldimi 4, 5, 16, 40 ; NO-ALTIVEC-NEXT: insrdi 4, 5, 8, 40
; NO-ALTIVEC-NEXT: rotldi 5, 3, 32 ; NO-ALTIVEC-NEXT: rotldi 5, 3, 32
; NO-ALTIVEC-NEXT: rldimi 4, 5, 24, 32 ; NO-ALTIVEC-NEXT: insrdi 4, 5, 8, 32
; NO-ALTIVEC-NEXT: rotldi 5, 3, 48 ; NO-ALTIVEC-NEXT: rotldi 5, 3, 48
; NO-ALTIVEC-NEXT: rldimi 4, 5, 40, 16 ; NO-ALTIVEC-NEXT: insrdi 4, 5, 8, 16
; NO-ALTIVEC-NEXT: rotldi 5, 3, 56 ; NO-ALTIVEC-NEXT: rotldi 5, 3, 56
; NO-ALTIVEC-NEXT: rldimi 4, 5, 48, 8 ; NO-ALTIVEC-NEXT: insrdi 4, 5, 8, 8
; NO-ALTIVEC-NEXT: rldimi 4, 3, 56, 0 ; NO-ALTIVEC-NEXT: insrdi 4, 3, 8, 0
; NO-ALTIVEC-NEXT: mr 3, 4 ; NO-ALTIVEC-NEXT: mr 3, 4
; NO-ALTIVEC-NEXT: blr ; NO-ALTIVEC-NEXT: blr
entry: entry:
%0 = call i64 @llvm.bswap.i64(i64 %x) %0 = call i64 @llvm.bswap.i64(i64 %x)
ret i64 %0 ret i64 %0
} }

llvm/test/CodeGen/PowerPC/build-vector-tests.ll

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; P8LE-NEXT: blr ; P8LE-NEXT: blr
entry: entry:
ret <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535> ret <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>
} }
define <4 x i32> @fromRegsi(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) { define <4 x i32> @fromRegsi(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) {
; P9BE-LABEL: fromRegsi: ; P9BE-LABEL: fromRegsi:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE-NEXT: rldimi r6, r5, 32, 0 ; P9BE-NEXT: insrdi r6, r5, 32, 0
; P9BE-NEXT: rldimi r4, r3, 32, 0 ; P9BE-NEXT: insrdi r4, r3, 32, 0
; P9BE-NEXT: mtvsrdd v2, r4, r6 ; P9BE-NEXT: mtvsrdd v2, r4, r6
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; ;
; P9LE-LABEL: fromRegsi: ; P9LE-LABEL: fromRegsi:
; P9LE: # %bb.0: # %entry ; P9LE: # %bb.0: # %entry
; P9LE-NEXT: rldimi r3, r4, 32, 0 ; P9LE-NEXT: insrdi r3, r4, 32, 0
; P9LE-NEXT: rldimi r5, r6, 32, 0 ; P9LE-NEXT: insrdi r5, r6, 32, 0
; P9LE-NEXT: mtvsrdd v2, r5, r3 ; P9LE-NEXT: mtvsrdd v2, r5, r3
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P8BE-LABEL: fromRegsi: ; P8BE-LABEL: fromRegsi:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: rldimi r6, r5, 32, 0 ; P8BE-NEXT: insrdi r6, r5, 32, 0
; P8BE-NEXT: rldimi r4, r3, 32, 0 ; P8BE-NEXT: insrdi r4, r3, 32, 0
; P8BE-NEXT: mtfprd f0, r6 ; P8BE-NEXT: mtfprd f0, r6
; P8BE-NEXT: mtfprd f1, r4 ; P8BE-NEXT: mtfprd f1, r4
; P8BE-NEXT: xxmrghd v2, vs1, vs0 ; P8BE-NEXT: xxmrghd v2, vs1, vs0
; P8BE-NEXT: blr ; P8BE-NEXT: blr
; ;
; P8LE-LABEL: fromRegsi: ; P8LE-LABEL: fromRegsi:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: rldimi r3, r4, 32, 0 ; P8LE-NEXT: insrdi r3, r4, 32, 0
; P8LE-NEXT: rldimi r5, r6, 32, 0 ; P8LE-NEXT: insrdi r5, r6, 32, 0
; P8LE-NEXT: mtfprd f0, r3 ; P8LE-NEXT: mtfprd f0, r3
; P8LE-NEXT: mtfprd f1, r5 ; P8LE-NEXT: mtfprd f1, r5
; P8LE-NEXT: xxmrghd v2, vs1, vs0 ; P8LE-NEXT: xxmrghd v2, vs1, vs0
; P8LE-NEXT: blr ; P8LE-NEXT: blr
entry: entry:
%vecinit = insertelement <4 x i32> undef, i32 %a, i32 0 %vecinit = insertelement <4 x i32> undef, i32 %a, i32 0
%vecinit1 = insertelement <4 x i32> %vecinit, i32 %b, i32 1 %vecinit1 = insertelement <4 x i32> %vecinit, i32 %b, i32 1
%vecinit2 = insertelement <4 x i32> %vecinit1, i32 %c, i32 2 %vecinit2 = insertelement <4 x i32> %vecinit1, i32 %c, i32 2
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define <4 x i32> @fromRandMemConsi(i32* nocapture readonly %arr) { define <4 x i32> @fromRandMemConsi(i32* nocapture readonly %arr) {
; P9BE-LABEL: fromRandMemConsi: ; P9BE-LABEL: fromRandMemConsi:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE-NEXT: lwz r4, 16(r3) ; P9BE-NEXT: lwz r4, 16(r3)
; P9BE-NEXT: lwz r5, 72(r3) ; P9BE-NEXT: lwz r5, 72(r3)
; P9BE-NEXT: lwz r6, 8(r3) ; P9BE-NEXT: lwz r6, 8(r3)
; P9BE-NEXT: lwz r3, 352(r3) ; P9BE-NEXT: lwz r3, 352(r3)
; P9BE-NEXT: rldimi r3, r6, 32, 0 ; P9BE-NEXT: insrdi r3, r6, 32, 0
; P9BE-NEXT: rldimi r5, r4, 32, 0 ; P9BE-NEXT: insrdi r5, r4, 32, 0
; P9BE-NEXT: mtvsrdd v2, r5, r3 ; P9BE-NEXT: mtvsrdd v2, r5, r3
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; ;
; P9LE-LABEL: fromRandMemConsi: ; P9LE-LABEL: fromRandMemConsi:
; P9LE: # %bb.0: # %entry ; P9LE: # %bb.0: # %entry
; P9LE-NEXT: lwz r4, 16(r3) ; P9LE-NEXT: lwz r4, 16(r3)
; P9LE-NEXT: lwz r5, 72(r3) ; P9LE-NEXT: lwz r5, 72(r3)
; P9LE-NEXT: lwz r6, 8(r3) ; P9LE-NEXT: lwz r6, 8(r3)
; P9LE-NEXT: lwz r3, 352(r3) ; P9LE-NEXT: lwz r3, 352(r3)
; P9LE-NEXT: rldimi r4, r5, 32, 0 ; P9LE-NEXT: insrdi r4, r5, 32, 0
; P9LE-NEXT: rldimi r6, r3, 32, 0 ; P9LE-NEXT: insrdi r6, r3, 32, 0
; P9LE-NEXT: mtvsrdd v2, r6, r4 ; P9LE-NEXT: mtvsrdd v2, r6, r4
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P8BE-LABEL: fromRandMemConsi: ; P8BE-LABEL: fromRandMemConsi:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: lwz r4, 8(r3) ; P8BE-NEXT: lwz r4, 8(r3)
; P8BE-NEXT: lwz r5, 352(r3) ; P8BE-NEXT: lwz r5, 352(r3)
; P8BE-NEXT: lwz r6, 16(r3) ; P8BE-NEXT: lwz r6, 16(r3)
; P8BE-NEXT: lwz r3, 72(r3) ; P8BE-NEXT: lwz r3, 72(r3)
; P8BE-NEXT: rldimi r5, r4, 32, 0 ; P8BE-NEXT: insrdi r5, r4, 32, 0
; P8BE-NEXT: rldimi r3, r6, 32, 0 ; P8BE-NEXT: insrdi r3, r6, 32, 0
; P8BE-NEXT: mtfprd f0, r5 ; P8BE-NEXT: mtfprd f0, r5
; P8BE-NEXT: mtfprd f1, r3 ; P8BE-NEXT: mtfprd f1, r3
; P8BE-NEXT: xxmrghd v2, vs1, vs0 ; P8BE-NEXT: xxmrghd v2, vs1, vs0
; P8BE-NEXT: blr ; P8BE-NEXT: blr
; ;
; P8LE-LABEL: fromRandMemConsi: ; P8LE-LABEL: fromRandMemConsi:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: lwz r4, 16(r3) ; P8LE-NEXT: lwz r4, 16(r3)
; P8LE-NEXT: lwz r5, 72(r3) ; P8LE-NEXT: lwz r5, 72(r3)
; P8LE-NEXT: lwz r6, 8(r3) ; P8LE-NEXT: lwz r6, 8(r3)
; P8LE-NEXT: lwz r3, 352(r3) ; P8LE-NEXT: lwz r3, 352(r3)
; P8LE-NEXT: rldimi r4, r5, 32, 0 ; P8LE-NEXT: insrdi r4, r5, 32, 0
; P8LE-NEXT: rldimi r6, r3, 32, 0 ; P8LE-NEXT: insrdi r6, r3, 32, 0
; P8LE-NEXT: mtfprd f0, r4 ; P8LE-NEXT: mtfprd f0, r4
; P8LE-NEXT: mtfprd f1, r6 ; P8LE-NEXT: mtfprd f1, r6
; P8LE-NEXT: xxmrghd v2, vs1, vs0 ; P8LE-NEXT: xxmrghd v2, vs1, vs0
; P8LE-NEXT: blr ; P8LE-NEXT: blr
entry: entry:
%arrayidx = getelementptr inbounds i32, i32* %arr, i64 4 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 4
%0 = load i32, i32* %arrayidx, align 4 %0 = load i32, i32* %arrayidx, align 4
%vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
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; P9BE-LABEL: fromRandMemVari: ; P9BE-LABEL: fromRandMemVari:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE-NEXT: sldi r4, r4, 2 ; P9BE-NEXT: sldi r4, r4, 2
; P9BE-NEXT: add r3, r3, r4 ; P9BE-NEXT: add r3, r3, r4
; P9BE-NEXT: lwz r4, 16(r3) ; P9BE-NEXT: lwz r4, 16(r3)
; P9BE-NEXT: lwz r5, 4(r3) ; P9BE-NEXT: lwz r5, 4(r3)
; P9BE-NEXT: lwz r6, 8(r3) ; P9BE-NEXT: lwz r6, 8(r3)
; P9BE-NEXT: lwz r3, 32(r3) ; P9BE-NEXT: lwz r3, 32(r3)
; P9BE-NEXT: rldimi r3, r6, 32, 0 ; P9BE-NEXT: insrdi r3, r6, 32, 0
; P9BE-NEXT: rldimi r5, r4, 32, 0 ; P9BE-NEXT: insrdi r5, r4, 32, 0
; P9BE-NEXT: mtvsrdd v2, r5, r3 ; P9BE-NEXT: mtvsrdd v2, r5, r3
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; ;
; P9LE-LABEL: fromRandMemVari: ; P9LE-LABEL: fromRandMemVari:
; P9LE: # %bb.0: # %entry ; P9LE: # %bb.0: # %entry
; P9LE-NEXT: sldi r4, r4, 2 ; P9LE-NEXT: sldi r4, r4, 2
; P9LE-NEXT: add r3, r3, r4 ; P9LE-NEXT: add r3, r3, r4
; P9LE-NEXT: lwz r4, 16(r3) ; P9LE-NEXT: lwz r4, 16(r3)
; P9LE-NEXT: lwz r5, 4(r3) ; P9LE-NEXT: lwz r5, 4(r3)
; P9LE-NEXT: lwz r6, 8(r3) ; P9LE-NEXT: lwz r6, 8(r3)
; P9LE-NEXT: lwz r3, 32(r3) ; P9LE-NEXT: lwz r3, 32(r3)
; P9LE-NEXT: rldimi r4, r5, 32, 0 ; P9LE-NEXT: insrdi r4, r5, 32, 0
; P9LE-NEXT: rldimi r6, r3, 32, 0 ; P9LE-NEXT: insrdi r6, r3, 32, 0
; P9LE-NEXT: mtvsrdd v2, r6, r4 ; P9LE-NEXT: mtvsrdd v2, r6, r4
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P8BE-LABEL: fromRandMemVari: ; P8BE-LABEL: fromRandMemVari:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: sldi r4, r4, 2 ; P8BE-NEXT: sldi r4, r4, 2
; P8BE-NEXT: add r3, r3, r4 ; P8BE-NEXT: add r3, r3, r4
; P8BE-NEXT: lwz r4, 8(r3) ; P8BE-NEXT: lwz r4, 8(r3)
; P8BE-NEXT: lwz r5, 32(r3) ; P8BE-NEXT: lwz r5, 32(r3)
; P8BE-NEXT: lwz r6, 16(r3) ; P8BE-NEXT: lwz r6, 16(r3)
; P8BE-NEXT: lwz r3, 4(r3) ; P8BE-NEXT: lwz r3, 4(r3)
; P8BE-NEXT: rldimi r5, r4, 32, 0 ; P8BE-NEXT: insrdi r5, r4, 32, 0
; P8BE-NEXT: rldimi r3, r6, 32, 0 ; P8BE-NEXT: insrdi r3, r6, 32, 0
; P8BE-NEXT: mtfprd f0, r5 ; P8BE-NEXT: mtfprd f0, r5
; P8BE-NEXT: mtfprd f1, r3 ; P8BE-NEXT: mtfprd f1, r3
; P8BE-NEXT: xxmrghd v2, vs1, vs0 ; P8BE-NEXT: xxmrghd v2, vs1, vs0
; P8BE-NEXT: blr ; P8BE-NEXT: blr
; ;
; P8LE-LABEL: fromRandMemVari: ; P8LE-LABEL: fromRandMemVari:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: sldi r4, r4, 2 ; P8LE-NEXT: sldi r4, r4, 2
; P8LE-NEXT: add r3, r3, r4 ; P8LE-NEXT: add r3, r3, r4
; P8LE-NEXT: lwz r4, 16(r3) ; P8LE-NEXT: lwz r4, 16(r3)
; P8LE-NEXT: lwz r5, 4(r3) ; P8LE-NEXT: lwz r5, 4(r3)
; P8LE-NEXT: lwz r6, 8(r3) ; P8LE-NEXT: lwz r6, 8(r3)
; P8LE-NEXT: lwz r3, 32(r3) ; P8LE-NEXT: lwz r3, 32(r3)
; P8LE-NEXT: rldimi r4, r5, 32, 0 ; P8LE-NEXT: insrdi r4, r5, 32, 0
; P8LE-NEXT: rldimi r6, r3, 32, 0 ; P8LE-NEXT: insrdi r6, r3, 32, 0
; P8LE-NEXT: mtfprd f0, r4 ; P8LE-NEXT: mtfprd f0, r4
; P8LE-NEXT: mtfprd f1, r6 ; P8LE-NEXT: mtfprd f1, r6
; P8LE-NEXT: xxmrghd v2, vs1, vs0 ; P8LE-NEXT: xxmrghd v2, vs1, vs0
; P8LE-NEXT: blr ; P8LE-NEXT: blr
entry: entry:
%add = add nsw i32 %elem, 4 %add = add nsw i32 %elem, 4
%idxprom = sext i32 %add to i64 %idxprom = sext i32 %add to i64
%arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom
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; P8LE-NEXT: blr ; P8LE-NEXT: blr
entry: entry:
ret <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535> ret <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>
} }
define <4 x i32> @fromRegsui(i32 zeroext %a, i32 zeroext %b, i32 zeroext %c, i32 zeroext %d) { define <4 x i32> @fromRegsui(i32 zeroext %a, i32 zeroext %b, i32 zeroext %c, i32 zeroext %d) {
; P9BE-LABEL: fromRegsui: ; P9BE-LABEL: fromRegsui:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE-NEXT: rldimi r6, r5, 32, 0 ; P9BE-NEXT: insrdi r6, r5, 32, 0
; P9BE-NEXT: rldimi r4, r3, 32, 0 ; P9BE-NEXT: insrdi r4, r3, 32, 0
; P9BE-NEXT: mtvsrdd v2, r4, r6 ; P9BE-NEXT: mtvsrdd v2, r4, r6
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; ;
; P9LE-LABEL: fromRegsui: ; P9LE-LABEL: fromRegsui:
; P9LE: # %bb.0: # %entry ; P9LE: # %bb.0: # %entry
; P9LE-NEXT: rldimi r3, r4, 32, 0 ; P9LE-NEXT: insrdi r3, r4, 32, 0
; P9LE-NEXT: rldimi r5, r6, 32, 0 ; P9LE-NEXT: insrdi r5, r6, 32, 0
; P9LE-NEXT: mtvsrdd v2, r5, r3 ; P9LE-NEXT: mtvsrdd v2, r5, r3
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P8BE-LABEL: fromRegsui: ; P8BE-LABEL: fromRegsui:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: rldimi r6, r5, 32, 0 ; P8BE-NEXT: insrdi r6, r5, 32, 0
; P8BE-NEXT: rldimi r4, r3, 32, 0 ; P8BE-NEXT: insrdi r4, r3, 32, 0
; P8BE-NEXT: mtfprd f0, r6 ; P8BE-NEXT: mtfprd f0, r6
; P8BE-NEXT: mtfprd f1, r4 ; P8BE-NEXT: mtfprd f1, r4
; P8BE-NEXT: xxmrghd v2, vs1, vs0 ; P8BE-NEXT: xxmrghd v2, vs1, vs0
; P8BE-NEXT: blr ; P8BE-NEXT: blr
; ;
; P8LE-LABEL: fromRegsui: ; P8LE-LABEL: fromRegsui:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: rldimi r3, r4, 32, 0 ; P8LE-NEXT: insrdi r3, r4, 32, 0
; P8LE-NEXT: rldimi r5, r6, 32, 0 ; P8LE-NEXT: insrdi r5, r6, 32, 0
; P8LE-NEXT: mtfprd f0, r3 ; P8LE-NEXT: mtfprd f0, r3
; P8LE-NEXT: mtfprd f1, r5 ; P8LE-NEXT: mtfprd f1, r5
; P8LE-NEXT: xxmrghd v2, vs1, vs0 ; P8LE-NEXT: xxmrghd v2, vs1, vs0
; P8LE-NEXT: blr ; P8LE-NEXT: blr
entry: entry:
%vecinit = insertelement <4 x i32> undef, i32 %a, i32 0 %vecinit = insertelement <4 x i32> undef, i32 %a, i32 0
%vecinit1 = insertelement <4 x i32> %vecinit, i32 %b, i32 1 %vecinit1 = insertelement <4 x i32> %vecinit, i32 %b, i32 1
%vecinit2 = insertelement <4 x i32> %vecinit1, i32 %c, i32 2 %vecinit2 = insertelement <4 x i32> %vecinit1, i32 %c, i32 2
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define <4 x i32> @fromRandMemConsui(i32* nocapture readonly %arr) { define <4 x i32> @fromRandMemConsui(i32* nocapture readonly %arr) {
; P9BE-LABEL: fromRandMemConsui: ; P9BE-LABEL: fromRandMemConsui:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE-NEXT: lwz r4, 16(r3) ; P9BE-NEXT: lwz r4, 16(r3)
; P9BE-NEXT: lwz r5, 72(r3) ; P9BE-NEXT: lwz r5, 72(r3)
; P9BE-NEXT: lwz r6, 8(r3) ; P9BE-NEXT: lwz r6, 8(r3)
; P9BE-NEXT: lwz r3, 352(r3) ; P9BE-NEXT: lwz r3, 352(r3)
; P9BE-NEXT: rldimi r3, r6, 32, 0 ; P9BE-NEXT: insrdi r3, r6, 32, 0
; P9BE-NEXT: rldimi r5, r4, 32, 0 ; P9BE-NEXT: insrdi r5, r4, 32, 0
; P9BE-NEXT: mtvsrdd v2, r5, r3 ; P9BE-NEXT: mtvsrdd v2, r5, r3
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; ;
; P9LE-LABEL: fromRandMemConsui: ; P9LE-LABEL: fromRandMemConsui:
; P9LE: # %bb.0: # %entry ; P9LE: # %bb.0: # %entry
; P9LE-NEXT: lwz r4, 16(r3) ; P9LE-NEXT: lwz r4, 16(r3)
; P9LE-NEXT: lwz r5, 72(r3) ; P9LE-NEXT: lwz r5, 72(r3)
; P9LE-NEXT: lwz r6, 8(r3) ; P9LE-NEXT: lwz r6, 8(r3)
; P9LE-NEXT: lwz r3, 352(r3) ; P9LE-NEXT: lwz r3, 352(r3)
; P9LE-NEXT: rldimi r4, r5, 32, 0 ; P9LE-NEXT: insrdi r4, r5, 32, 0
; P9LE-NEXT: rldimi r6, r3, 32, 0 ; P9LE-NEXT: insrdi r6, r3, 32, 0
; P9LE-NEXT: mtvsrdd v2, r6, r4 ; P9LE-NEXT: mtvsrdd v2, r6, r4
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P8BE-LABEL: fromRandMemConsui: ; P8BE-LABEL: fromRandMemConsui:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: lwz r4, 8(r3) ; P8BE-NEXT: lwz r4, 8(r3)
; P8BE-NEXT: lwz r5, 352(r3) ; P8BE-NEXT: lwz r5, 352(r3)
; P8BE-NEXT: lwz r6, 16(r3) ; P8BE-NEXT: lwz r6, 16(r3)
; P8BE-NEXT: lwz r3, 72(r3) ; P8BE-NEXT: lwz r3, 72(r3)
; P8BE-NEXT: rldimi r5, r4, 32, 0 ; P8BE-NEXT: insrdi r5, r4, 32, 0
; P8BE-NEXT: rldimi r3, r6, 32, 0 ; P8BE-NEXT: insrdi r3, r6, 32, 0
; P8BE-NEXT: mtfprd f0, r5 ; P8BE-NEXT: mtfprd f0, r5
; P8BE-NEXT: mtfprd f1, r3 ; P8BE-NEXT: mtfprd f1, r3
; P8BE-NEXT: xxmrghd v2, vs1, vs0 ; P8BE-NEXT: xxmrghd v2, vs1, vs0
; P8BE-NEXT: blr ; P8BE-NEXT: blr
; ;
; P8LE-LABEL: fromRandMemConsui: ; P8LE-LABEL: fromRandMemConsui:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: lwz r4, 16(r3) ; P8LE-NEXT: lwz r4, 16(r3)
; P8LE-NEXT: lwz r5, 72(r3) ; P8LE-NEXT: lwz r5, 72(r3)
; P8LE-NEXT: lwz r6, 8(r3) ; P8LE-NEXT: lwz r6, 8(r3)
; P8LE-NEXT: lwz r3, 352(r3) ; P8LE-NEXT: lwz r3, 352(r3)
; P8LE-NEXT: rldimi r4, r5, 32, 0 ; P8LE-NEXT: insrdi r4, r5, 32, 0
; P8LE-NEXT: rldimi r6, r3, 32, 0 ; P8LE-NEXT: insrdi r6, r3, 32, 0
; P8LE-NEXT: mtfprd f0, r4 ; P8LE-NEXT: mtfprd f0, r4
; P8LE-NEXT: mtfprd f1, r6 ; P8LE-NEXT: mtfprd f1, r6
; P8LE-NEXT: xxmrghd v2, vs1, vs0 ; P8LE-NEXT: xxmrghd v2, vs1, vs0
; P8LE-NEXT: blr ; P8LE-NEXT: blr
entry: entry:
%arrayidx = getelementptr inbounds i32, i32* %arr, i64 4 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 4
%0 = load i32, i32* %arrayidx, align 4 %0 = load i32, i32* %arrayidx, align 4
%vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
Show All 13 Lines
; P9BE-LABEL: fromRandMemVarui: ; P9BE-LABEL: fromRandMemVarui:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE-NEXT: sldi r4, r4, 2 ; P9BE-NEXT: sldi r4, r4, 2
; P9BE-NEXT: add r3, r3, r4 ; P9BE-NEXT: add r3, r3, r4
; P9BE-NEXT: lwz r4, 16(r3) ; P9BE-NEXT: lwz r4, 16(r3)
; P9BE-NEXT: lwz r5, 4(r3) ; P9BE-NEXT: lwz r5, 4(r3)
; P9BE-NEXT: lwz r6, 8(r3) ; P9BE-NEXT: lwz r6, 8(r3)
; P9BE-NEXT: lwz r3, 32(r3) ; P9BE-NEXT: lwz r3, 32(r3)
; P9BE-NEXT: rldimi r3, r6, 32, 0 ; P9BE-NEXT: insrdi r3, r6, 32, 0
; P9BE-NEXT: rldimi r5, r4, 32, 0 ; P9BE-NEXT: insrdi r5, r4, 32, 0
; P9BE-NEXT: mtvsrdd v2, r5, r3 ; P9BE-NEXT: mtvsrdd v2, r5, r3
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; ;
; P9LE-LABEL: fromRandMemVarui: ; P9LE-LABEL: fromRandMemVarui:
; P9LE: # %bb.0: # %entry ; P9LE: # %bb.0: # %entry
; P9LE-NEXT: sldi r4, r4, 2 ; P9LE-NEXT: sldi r4, r4, 2
; P9LE-NEXT: add r3, r3, r4 ; P9LE-NEXT: add r3, r3, r4
; P9LE-NEXT: lwz r4, 16(r3) ; P9LE-NEXT: lwz r4, 16(r3)
; P9LE-NEXT: lwz r5, 4(r3) ; P9LE-NEXT: lwz r5, 4(r3)
; P9LE-NEXT: lwz r6, 8(r3) ; P9LE-NEXT: lwz r6, 8(r3)
; P9LE-NEXT: lwz r3, 32(r3) ; P9LE-NEXT: lwz r3, 32(r3)
; P9LE-NEXT: rldimi r4, r5, 32, 0 ; P9LE-NEXT: insrdi r4, r5, 32, 0
; P9LE-NEXT: rldimi r6, r3, 32, 0 ; P9LE-NEXT: insrdi r6, r3, 32, 0
; P9LE-NEXT: mtvsrdd v2, r6, r4 ; P9LE-NEXT: mtvsrdd v2, r6, r4
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P8BE-LABEL: fromRandMemVarui: ; P8BE-LABEL: fromRandMemVarui:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: sldi r4, r4, 2 ; P8BE-NEXT: sldi r4, r4, 2
; P8BE-NEXT: add r3, r3, r4 ; P8BE-NEXT: add r3, r3, r4
; P8BE-NEXT: lwz r4, 8(r3) ; P8BE-NEXT: lwz r4, 8(r3)
; P8BE-NEXT: lwz r5, 32(r3) ; P8BE-NEXT: lwz r5, 32(r3)
; P8BE-NEXT: lwz r6, 16(r3) ; P8BE-NEXT: lwz r6, 16(r3)
; P8BE-NEXT: lwz r3, 4(r3) ; P8BE-NEXT: lwz r3, 4(r3)
; P8BE-NEXT: rldimi r5, r4, 32, 0 ; P8BE-NEXT: insrdi r5, r4, 32, 0
; P8BE-NEXT: rldimi r3, r6, 32, 0 ; P8BE-NEXT: insrdi r3, r6, 32, 0
; P8BE-NEXT: mtfprd f0, r5 ; P8BE-NEXT: mtfprd f0, r5
; P8BE-NEXT: mtfprd f1, r3 ; P8BE-NEXT: mtfprd f1, r3
; P8BE-NEXT: xxmrghd v2, vs1, vs0 ; P8BE-NEXT: xxmrghd v2, vs1, vs0
; P8BE-NEXT: blr ; P8BE-NEXT: blr
; ;
; P8LE-LABEL: fromRandMemVarui: ; P8LE-LABEL: fromRandMemVarui:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: sldi r4, r4, 2 ; P8LE-NEXT: sldi r4, r4, 2
; P8LE-NEXT: add r3, r3, r4 ; P8LE-NEXT: add r3, r3, r4
; P8LE-NEXT: lwz r4, 16(r3) ; P8LE-NEXT: lwz r4, 16(r3)
; P8LE-NEXT: lwz r5, 4(r3) ; P8LE-NEXT: lwz r5, 4(r3)
; P8LE-NEXT: lwz r6, 8(r3) ; P8LE-NEXT: lwz r6, 8(r3)
; P8LE-NEXT: lwz r3, 32(r3) ; P8LE-NEXT: lwz r3, 32(r3)
; P8LE-NEXT: rldimi r4, r5, 32, 0 ; P8LE-NEXT: insrdi r4, r5, 32, 0
; P8LE-NEXT: rldimi r6, r3, 32, 0 ; P8LE-NEXT: insrdi r6, r3, 32, 0
; P8LE-NEXT: mtfprd f0, r4 ; P8LE-NEXT: mtfprd f0, r4
; P8LE-NEXT: mtfprd f1, r6 ; P8LE-NEXT: mtfprd f1, r6
; P8LE-NEXT: xxmrghd v2, vs1, vs0 ; P8LE-NEXT: xxmrghd v2, vs1, vs0
; P8LE-NEXT: blr ; P8LE-NEXT: blr
entry: entry:
%add = add nsw i32 %elem, 4 %add = add nsw i32 %elem, 4
%idxprom = sext i32 %add to i64 %idxprom = sext i32 %add to i64
%arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom
▲ Show 20 Lines • Show All 3,800 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/collapse-rotates.mir

Show First 20 Lines • Show All 56 Lines • ▼ Show 20 Lines bb.0.entry:
%0:g8rc = COPY $x3 %0:g8rc = COPY $x3
%1:g8rc = RLDICL %0, 2, 32 %1:g8rc = RLDICL %0, 2, 32
%2:g8rc = RLDICR %1, 3, 58 %2:g8rc = RLDICR %1, 3, 58
$x3 = COPY %2 $x3 = COPY %2
BLR8 implicit $lr8, implicit $rm, implicit $x3 BLR8 implicit $lr8, implicit $rm, implicit $x3
... ...
# CHECK: rldic 3, 3, 5, 29 # CHECK: clrlsldi 3, 3, 34, 5

llvm/test/CodeGen/PowerPC/combine-setcc.ll

Show First 20 Lines • Show All 87 Lines • ▼ Show 20 Lines; CHECK-NEXT: blr
ret i32 %conv ret i32 %conv
} }
define i64 @eq7(i64 %x, i64 %y) { define i64 @eq7(i64 %x, i64 %y) {
; CHECK-LABEL: eq7: ; CHECK-LABEL: eq7:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: add r3, r4, r3 ; CHECK-NEXT: add r3, r4, r3
; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63 ; CHECK-NEXT: extrdi r3, r3, 1, 57
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%sub = sub nsw i64 0, %x %sub = sub nsw i64 0, %x
%cmp = icmp eq i64 %sub, %y %cmp = icmp eq i64 %sub, %y
%zext = zext i1 %cmp to i64 %zext = zext i1 %cmp to i64
ret i64 %zext ret i64 %zext
} }
define zeroext i1 @eq8(i1 zeroext %x, i1 zeroext %y) { define zeroext i1 @eq8(i1 zeroext %x, i1 zeroext %y) {
▲ Show 20 Lines • Show All 80 Lines • ▼ Show 20 Lines; CHECK-NEXT: blr
ret i32 %conv ret i32 %conv
} }
define i64 @eq14(i64 %x, i64 %y) { define i64 @eq14(i64 %x, i64 %y) {
; CHECK-LABEL: eq14: ; CHECK-LABEL: eq14:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: add r3, r3, r4 ; CHECK-NEXT: add r3, r3, r4
; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63 ; CHECK-NEXT: extrdi r3, r3, 1, 57
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%sub = sub nsw i64 0, %y %sub = sub nsw i64 0, %y
%cmp = icmp eq i64 %sub, %x %cmp = icmp eq i64 %sub, %x
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
define zeroext i1 @neq1(i1 zeroext %x, i1 zeroext %y) { define zeroext i1 @neq1(i1 zeroext %x, i1 zeroext %y) {
▲ Show 20 Lines • Show All 207 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-out-of-range.mir

Show First 20 Lines • Show All 358 Lines • ▼ Show 20 Lines bb.0.entry:
%1 = COPY $x4 %1 = COPY $x4
%0 = COPY $x3 %0 = COPY $x3
%2 = COPY %1.sub_32 %2 = COPY %1.sub_32
%3 = LI -22 %3 = LI -22
%4 = RLWNM_rec %2, %3, 24, 31, implicit-def $cr0 %4 = RLWNM_rec %2, %3, 24, 31, implicit-def $cr0
; CHECK: RLWINM_rec %2, 10, 24, 31, implicit-def $cr0 ; CHECK: RLWINM_rec %2, 10, 24, 31, implicit-def $cr0
; CHECK-LATE: li 3, -22 ; CHECK-LATE: li 3, -22
; CHECK-LATE: rlwinm. 5, 4, 10, 24, 31 ; CHECK-LATE: extrwi. 5, 4, 8, 2
%5 = COPY killed $cr0 %5 = COPY killed $cr0
%6 = ISEL %2, %3, %5.sub_eq %6 = ISEL %2, %3, %5.sub_eq
%8 = IMPLICIT_DEF %8 = IMPLICIT_DEF
%7 = INSERT_SUBREG %8, killed %6, 1 %7 = INSERT_SUBREG %8, killed %6, 1
%9 = RLDICL killed %7, 0, 32 %9 = RLDICL killed %7, 0, 32
$x3 = COPY %9 $x3 = COPY %9
BLR8 implicit $lr8, implicit $rm, implicit $x3 BLR8 implicit $lr8, implicit $rm, implicit $x3
▲ Show 20 Lines • Show All 565 Lines • ▼ Show 20 Lines bb.0.entry:
liveins: $x3, $x4 liveins: $x3, $x4
%1 = COPY $x4 %1 = COPY $x4
%0 = COPY $x3 %0 = COPY $x3
%2 = COPY %1.sub_32 %2 = COPY %1.sub_32
%3 = LI 300 %3 = LI 300
%4 = RLDCR %0, killed %3, 0 %4 = RLDCR %0, killed %3, 0
; CHECK: RLDICR %0, 44, 0 ; CHECK: RLDICR %0, 44, 0
; CHECK-LATE: rldicr 3, 3, 44, 0 ; CHECK-LATE: extldi 3, 3, 1, 44
$x3 = COPY %4 $x3 = COPY %4
BLR8 implicit $lr8, implicit $rm, implicit $x3 BLR8 implicit $lr8, implicit $rm, implicit $x3
... ...
--- ---
name: testRLDCR_rec name: testRLDCR_rec
# CHECK-ALL: name: testRLDCR_rec # CHECK-ALL: name: testRLDCR_rec
alignment: 16 alignment: 16
Show All 38 Lines bb.0.entry:
liveins: $x3, $x4 liveins: $x3, $x4
%1 = COPY $x4 %1 = COPY $x4
%0 = COPY $x3 %0 = COPY $x3
%2 = RLDICL %1, 0, 58 %2 = RLDICL %1, 0, 58
%3 = LI -18 %3 = LI -18
%4 = RLDCR_rec %0, killed %3, 0, implicit-def $cr0 %4 = RLDCR_rec %0, killed %3, 0, implicit-def $cr0
; CHECK: RLDICR_rec %0, 46, 0, implicit-def $cr0 ; CHECK: RLDICR_rec %0, 46, 0, implicit-def $cr0
; CHECK-LATE: rldicr. 5, 3, 46, 0 ; CHECK-LATE: extldi. 5, 3, 1, 46
%5 = COPY killed $cr0 %5 = COPY killed $cr0
%6 = ISEL8 %2, %0, %5.sub_eq %6 = ISEL8 %2, %0, %5.sub_eq
$x3 = COPY %6 $x3 = COPY %6
BLR8 implicit $lr8, implicit $rm, implicit $x3 BLR8 implicit $lr8, implicit $rm, implicit $x3
... ...
--- ---
name: testSLD name: testSLD
▲ Show 20 Lines • Show All 142 Lines • ▼ Show 20 Linesbody: |
bb.0.entry: bb.0.entry:
liveins: $x3, $x4 liveins: $x3, $x4
%1 = COPY $x4 %1 = COPY $x4
%0 = COPY $x3 %0 = COPY $x3
%2 = LI 400 %2 = LI 400
%3 = SRD %0, killed %2 %3 = SRD %0, killed %2
; CHECK: RLDICL %0, 48, 16 ; CHECK: RLDICL %0, 48, 16
; CHECK-LATE: rldicl 3, 3, 48, 16 ; CHECK-LATE: srdi 3, 3, 16
$x3 = COPY %3 $x3 = COPY %3
BLR8 implicit $lr8, implicit $rm, implicit $x3 BLR8 implicit $lr8, implicit $rm, implicit $x3
... ...
--- ---
name: testSRD_rec name: testSRD_rec
# CHECK-ALL: name: testSRD_rec # CHECK-ALL: name: testSRD_rec
alignment: 16 alignment: 16
▲ Show 20 Lines • Show All 158 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir

Show First 20 Lines • Show All 3,777 Lines • ▼ Show 20 Lines bb.0.entry:
liveins: $x3, $x4 liveins: $x3, $x4
%1 = COPY $x4 %1 = COPY $x4
%0 = COPY $x3 %0 = COPY $x3
%2 = COPY %1.sub_32 %2 = COPY %1.sub_32
%3 = LI 0 %3 = LI 0
%4 = RLDCR %0, killed %3, 0 %4 = RLDCR %0, killed %3, 0
; CHECK: RLDICR %0, 0, 0 ; CHECK: RLDICR %0, 0, 0
; CHECK-LATE: rldicr 3, 3, 0, 0 ; CHECK-LATE: clrrdi 3, 3, 63
$x3 = COPY %4 $x3 = COPY %4
BLR8 implicit $lr8, implicit $rm, implicit $x3 BLR8 implicit $lr8, implicit $rm, implicit $x3
... ...
--- ---
name: testRLDCR_rec name: testRLDCR_rec
# CHECK-ALL: name: testRLDCR_rec # CHECK-ALL: name: testRLDCR_rec
alignment: 16 alignment: 16
Show All 38 Lines bb.0.entry:
liveins: $x3, $x4 liveins: $x3, $x4
%1 = COPY $x4 %1 = COPY $x4
%0 = COPY $x3 %0 = COPY $x3
%2 = RLDICL %1, 0, 58 %2 = RLDICL %1, 0, 58
%3 = LI 18 %3 = LI 18
%4 = RLDCR_rec %0, killed %3, 0, implicit-def $cr0 %4 = RLDCR_rec %0, killed %3, 0, implicit-def $cr0
; CHECK: RLDICR_rec %0, 18, 0, implicit-def $cr0 ; CHECK: RLDICR_rec %0, 18, 0, implicit-def $cr0
; CHECK-LATE: rldicr. 5, 3, 18, 0 ; CHECK-LATE: extldi. 5, 3, 1, 18
%5 = COPY killed $cr0 %5 = COPY killed $cr0
%6 = ISEL8 %2, %0, %5.sub_eq %6 = ISEL8 %2, %0, %5.sub_eq
$x3 = COPY %6 $x3 = COPY %6
BLR8 implicit $lr8, implicit $rm, implicit $x3 BLR8 implicit $lr8, implicit $rm, implicit $x3
... ...
--- ---
name: testRLDICL name: testRLDICL
▲ Show 20 Lines • Show All 734 Lines • ▼ Show 20 Linesbody: |
bb.0.entry: bb.0.entry:
liveins: $x3, $x4 liveins: $x3, $x4
%1 = COPY $x4 %1 = COPY $x4
%0 = COPY $x3 %0 = COPY $x3
%2 = LI 17 %2 = LI 17
%3 = SLD_rec %0, killed %2, implicit-def $cr0 %3 = SLD_rec %0, killed %2, implicit-def $cr0
; CHECK: RLDICR_rec %0, 17, 46, implicit-def $cr0 ; CHECK: RLDICR_rec %0, 17, 46, implicit-def $cr0
; CHECK-LATE: rldicr. 5, 3, 17, 46 ; CHECK-LATE: sldi. 5, 3, 17
%4 = COPY killed $cr0 %4 = COPY killed $cr0
%5 = ISEL8 %1, %0, %4.sub_eq %5 = ISEL8 %1, %0, %4.sub_eq
$x3 = COPY %5 $x3 = COPY %5
BLR8 implicit $lr8, implicit $rm, implicit $x3 BLR8 implicit $lr8, implicit $rm, implicit $x3
... ...
--- ---
name: testSRD name: testSRD
Show All 36 Linesbody: |
bb.0.entry: bb.0.entry:
liveins: $x3, $x4 liveins: $x3, $x4
%1 = COPY $x4 %1 = COPY $x4
%0 = COPY $x3 %0 = COPY $x3
%2 = LI 4 %2 = LI 4
%3 = SRD %0, killed %2 %3 = SRD %0, killed %2
; CHECK: RLDICL %0, 60, 4 ; CHECK: RLDICL %0, 60, 4
; CHECK-LATE: rldicl 3, 3, 60, 4 ; CHECK-LATE: srdi 3, 3, 4
$x3 = COPY %3 $x3 = COPY %3
BLR8 implicit $lr8, implicit $rm, implicit $x3 BLR8 implicit $lr8, implicit $rm, implicit $x3
... ...
--- ---
name: testSRD_rec name: testSRD_rec
# CHECK-ALL: name: testSRD_rec # CHECK-ALL: name: testSRD_rec
alignment: 16 alignment: 16
Show All 36 Linesbody: |
bb.0.entry: bb.0.entry:
liveins: $x3, $x4 liveins: $x3, $x4
%1 = COPY $x4 %1 = COPY $x4
%0 = COPY $x3 %0 = COPY $x3
%2 = LI 17 %2 = LI 17
%3 = SRD_rec %0, killed %2, implicit-def $cr0 %3 = SRD_rec %0, killed %2, implicit-def $cr0
; CHECK: RLDICL_rec %0, 47, 17, implicit-def $cr0 ; CHECK: RLDICL_rec %0, 47, 17, implicit-def $cr0
; CHECK-LATE: rldicl. 5, 3, 47, 17 ; CHECK-LATE: srdi. 5, 3, 17
%4 = COPY killed $cr0 %4 = COPY killed $cr0
%5 = ISEL8 %1, %0, %4.sub_eq %5 = ISEL8 %1, %0, %4.sub_eq
$x3 = COPY %5 $x3 = COPY %5
BLR8 implicit $lr8, implicit $rm, implicit $x3 BLR8 implicit $lr8, implicit $rm, implicit $x3
... ...
--- ---
name: testSLW name: testSLW
▲ Show 20 Lines • Show All 100 Lines • ▼ Show 20 Lines bb.0.entry:
liveins: $x3, $x4 liveins: $x3, $x4
%1 = COPY $x4 %1 = COPY $x4
%0 = COPY $x3 %0 = COPY $x3
%2 = LI 11 %2 = LI 11
%3 = COPY %0.sub_32 %3 = COPY %0.sub_32
%4 = SLW_rec %3, %2, implicit-def $cr0 %4 = SLW_rec %3, %2, implicit-def $cr0
; CHECK: RLWINM_rec %3, 11, 0, 20, implicit-def $cr0 ; CHECK: RLWINM_rec %3, 11, 0, 20, implicit-def $cr0
; CHECK-LATE: rlwinm. 5, 3, 11, 0, 20 ; CHECK-LATE: slwi. 5, 3, 11
%5 = COPY killed $cr0 %5 = COPY killed $cr0
%6 = ISEL %2, %3, %5.sub_eq %6 = ISEL %2, %3, %5.sub_eq
%8 = IMPLICIT_DEF %8 = IMPLICIT_DEF
%7 = INSERT_SUBREG %8, killed %6, 1 %7 = INSERT_SUBREG %8, killed %6, 1
%9 = RLDICL killed %7, 0, 32 %9 = RLDICL killed %7, 0, 32
$x3 = COPY %9 $x3 = COPY %9
BLR8 implicit $lr8, implicit $rm, implicit $x3 BLR8 implicit $lr8, implicit $rm, implicit $x3
▲ Show 20 Lines • Show All 103 Lines • ▼ Show 20 Lines bb.0.entry:
liveins: $x3, $x4 liveins: $x3, $x4
%1 = COPY $x4 %1 = COPY $x4
%0 = COPY $x3 %0 = COPY $x3
%2 = LI 7 %2 = LI 7
%3 = COPY %0.sub_32 %3 = COPY %0.sub_32
%4 = SRW_rec %3, %2, implicit-def $cr0 %4 = SRW_rec %3, %2, implicit-def $cr0
; CHECK: RLWINM_rec %3, 25, 7, 31 ; CHECK: RLWINM_rec %3, 25, 7, 31
; CHECK-LATE: rlwinm. 5, 3, 25, 7, 31 ; CHECK-LATE: srwi. 5, 3, 7
%5 = COPY killed $cr0 %5 = COPY killed $cr0
%6 = ISEL %2, %3, %5.sub_eq %6 = ISEL %2, %3, %5.sub_eq
%8 = IMPLICIT_DEF %8 = IMPLICIT_DEF
%7 = INSERT_SUBREG %8, killed %6, 1 %7 = INSERT_SUBREG %8, killed %6, 1
%9 = RLDICL killed %7, 0, 32 %9 = RLDICL killed %7, 0, 32
$x3 = COPY %9 $x3 = COPY %9
BLR8 implicit $lr8, implicit $rm, implicit $x3 BLR8 implicit $lr8, implicit $rm, implicit $x3
▲ Show 20 Lines • Show All 1,567 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/expand-isel.ll

Show First 20 Lines • Show All 193 Lines • ▼ Show 20 Lines
; CHECK: cmplwi r3, 0 ; CHECK: cmplwi r3, 0
; CHECK: li r3, 1 ; CHECK: li r3, 1
; CHECK: beq cr0, [[TGT:.LBB[0-9_]+]] ; CHECK: beq cr0, [[TGT:.LBB[0-9_]+]]
; CHECK: clrldi r3, r3, 32 ; CHECK: clrldi r3, r3, 32
; CHECK: blr ; CHECK: blr
; CHECK: [[TGT]] ; CHECK: [[TGT]]
; CHECK: xor [[XOR:r[0-9]+]] ; CHECK: xor [[XOR:r[0-9]+]]
; CHECK: cntlzd [[CZ:r[0-9]+]], [[XOR]] ; CHECK: cntlzd [[CZ:r[0-9]+]], [[XOR]]
; CHECK: rldicl [[SH:r[0-9]+]], [[CZ]], 58, 63 ; CHECK: extrdi [[SH:r[0-9]+]], [[CZ]], 1, 57
} }
!1 = !{!2, !2, i64 0} !1 = !{!2, !2, i64 0}
!2 = !{!"int", !3, i64 0} !2 = !{!"int", !3, i64 0}
!3 = !{!"omnipotent char", !4, i64 0} !3 = !{!"omnipotent char", !4, i64 0}
!4 = !{!"Simple C/C++ TBAA"} !4 = !{!"Simple C/C++ TBAA"}

llvm/test/CodeGen/PowerPC/extract-and-store.ll

Show First 20 Lines • Show All 637 Lines • ▼ Show 20 Linesentry:
ret void ret void
} }
define void @test_5_consecutive_stores_of_bytes(<16 x i8> %a, i8* nocapture %b) local_unnamed_addr #0 { define void @test_5_consecutive_stores_of_bytes(<16 x i8> %a, i8* nocapture %b) local_unnamed_addr #0 {
; CHECK-LABEL: test_5_consecutive_stores_of_bytes: ; CHECK-LABEL: test_5_consecutive_stores_of_bytes:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxswapd vs0, vs34 ; CHECK-NEXT: xxswapd vs0, vs34
; CHECK-NEXT: mfvsrd r3, vs34 ; CHECK-NEXT: mfvsrd r3, vs34
; CHECK-NEXT: rldicl r6, r3, 32, 56 ; CHECK-NEXT: extrdi r6, r3, 8, 24
; CHECK-NEXT: rldicl r3, r3, 56, 56 ; CHECK-NEXT: extrdi r3, r3, 8, 48
; CHECK-NEXT: mffprd r4, f0 ; CHECK-NEXT: mffprd r4, f0
; CHECK-NEXT: stb r6, 1(r5) ; CHECK-NEXT: stb r6, 1(r5)
; CHECK-NEXT: stb r3, 2(r5) ; CHECK-NEXT: stb r3, 2(r5)
; CHECK-NEXT: rldicl r6, r4, 32, 56 ; CHECK-NEXT: extrdi r6, r4, 8, 24
; CHECK-NEXT: rldicl r3, r4, 8, 56 ; CHECK-NEXT: srdi r3, r4, 56
; CHECK-NEXT: rldicl r4, r4, 16, 56 ; CHECK-NEXT: extrdi r4, r4, 8, 8
; CHECK-NEXT: stb r6, 0(r5) ; CHECK-NEXT: stb r6, 0(r5)
; CHECK-NEXT: stb r3, 3(r5) ; CHECK-NEXT: stb r3, 3(r5)
; CHECK-NEXT: stb r4, 4(r5) ; CHECK-NEXT: stb r4, 4(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-BE-LABEL: test_5_consecutive_stores_of_bytes: ; CHECK-BE-LABEL: test_5_consecutive_stores_of_bytes:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xxswapd vs0, vs34 ; CHECK-BE-NEXT: xxswapd vs0, vs34
; CHECK-BE-NEXT: mfvsrd r3, vs34 ; CHECK-BE-NEXT: mfvsrd r3, vs34
; CHECK-BE-NEXT: rldicl r6, r3, 40, 56 ; CHECK-BE-NEXT: extrdi r6, r3, 8, 32
; CHECK-BE-NEXT: mffprd r4, f0 ; CHECK-BE-NEXT: mffprd r4, f0
; CHECK-BE-NEXT: stb r6, 0(r5) ; CHECK-BE-NEXT: stb r6, 0(r5)
; CHECK-BE-NEXT: rldicl r6, r4, 40, 56 ; CHECK-BE-NEXT: extrdi r6, r4, 8, 32
; CHECK-BE-NEXT: rldicl r4, r4, 16, 56 ; CHECK-BE-NEXT: extrdi r4, r4, 8, 8
; CHECK-BE-NEXT: stb r6, 1(r5) ; CHECK-BE-NEXT: stb r6, 1(r5)
; CHECK-BE-NEXT: clrldi r6, r3, 56 ; CHECK-BE-NEXT: clrldi r6, r3, 56
; CHECK-BE-NEXT: rldicl r3, r3, 56, 56 ; CHECK-BE-NEXT: extrdi r3, r3, 8, 48
; CHECK-BE-NEXT: stb r4, 2(r5) ; CHECK-BE-NEXT: stb r4, 2(r5)
; CHECK-BE-NEXT: stb r6, 3(r5) ; CHECK-BE-NEXT: stb r6, 3(r5)
; CHECK-BE-NEXT: stb r3, 4(r5) ; CHECK-BE-NEXT: stb r3, 4(r5)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-P9-LABEL: test_5_consecutive_stores_of_bytes: ; CHECK-P9-LABEL: test_5_consecutive_stores_of_bytes:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: vsldoi v3, v2, v2, 4 ; CHECK-P9-NEXT: vsldoi v3, v2, v2, 4
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Linesentry:
ret void ret void
} }
define void @test_13_consecutive_stores_of_bytes(<16 x i8> %a, i8* nocapture %b) local_unnamed_addr #0 { define void @test_13_consecutive_stores_of_bytes(<16 x i8> %a, i8* nocapture %b) local_unnamed_addr #0 {
; CHECK-LABEL: test_13_consecutive_stores_of_bytes: ; CHECK-LABEL: test_13_consecutive_stores_of_bytes:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxswapd vs0, vs34 ; CHECK-NEXT: xxswapd vs0, vs34
; CHECK-NEXT: mfvsrd r3, vs34 ; CHECK-NEXT: mfvsrd r3, vs34
; CHECK-NEXT: rldicl r4, r3, 32, 56 ; CHECK-NEXT: extrdi r4, r3, 8, 24
; CHECK-NEXT: rldicl r6, r3, 56, 56 ; CHECK-NEXT: extrdi r6, r3, 8, 48
; CHECK-NEXT: stb r4, 1(r5) ; CHECK-NEXT: stb r4, 1(r5)
; CHECK-NEXT: rldicl r4, r3, 40, 56 ; CHECK-NEXT: extrdi r4, r3, 8, 32
; CHECK-NEXT: mffprd r7, f0 ; CHECK-NEXT: mffprd r7, f0
; CHECK-NEXT: stb r6, 2(r5) ; CHECK-NEXT: stb r6, 2(r5)
; CHECK-NEXT: rldicl r6, r3, 24, 56 ; CHECK-NEXT: extrdi r6, r3, 8, 16
; CHECK-NEXT: stb r4, 6(r5) ; CHECK-NEXT: stb r4, 6(r5)
; CHECK-NEXT: rldicl r4, r3, 8, 56 ; CHECK-NEXT: srdi r4, r3, 56
; CHECK-NEXT: stb r6, 7(r5) ; CHECK-NEXT: stb r6, 7(r5)
; CHECK-NEXT: rldicl r3, r3, 16, 56 ; CHECK-NEXT: extrdi r3, r3, 8, 8
; CHECK-NEXT: stb r4, 9(r5) ; CHECK-NEXT: stb r4, 9(r5)
; CHECK-NEXT: rldicl r4, r7, 32, 56 ; CHECK-NEXT: extrdi r4, r7, 8, 24
; CHECK-NEXT: rldicl r6, r7, 8, 56 ; CHECK-NEXT: srdi r6, r7, 56
; CHECK-NEXT: stb r3, 12(r5) ; CHECK-NEXT: stb r3, 12(r5)
; CHECK-NEXT: stb r4, 0(r5) ; CHECK-NEXT: stb r4, 0(r5)
; CHECK-NEXT: rldicl r4, r7, 16, 56 ; CHECK-NEXT: extrdi r4, r7, 8, 8
; CHECK-NEXT: stb r6, 3(r5) ; CHECK-NEXT: stb r6, 3(r5)
; CHECK-NEXT: clrldi r6, r7, 56 ; CHECK-NEXT: clrldi r6, r7, 56
; CHECK-NEXT: stb r4, 4(r5) ; CHECK-NEXT: stb r4, 4(r5)
; CHECK-NEXT: rldicl r4, r7, 48, 56 ; CHECK-NEXT: extrdi r4, r7, 8, 40
; CHECK-NEXT: stb r6, 5(r5) ; CHECK-NEXT: stb r6, 5(r5)
; CHECK-NEXT: rldicl r6, r7, 56, 56 ; CHECK-NEXT: extrdi r6, r7, 8, 48
; CHECK-NEXT: stb r4, 8(r5) ; CHECK-NEXT: stb r4, 8(r5)
; CHECK-NEXT: rldicl r4, r7, 24, 56 ; CHECK-NEXT: extrdi r4, r7, 8, 16
; CHECK-NEXT: stb r6, 10(r5) ; CHECK-NEXT: stb r6, 10(r5)
; CHECK-NEXT: stb r4, 11(r5) ; CHECK-NEXT: stb r4, 11(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-BE-LABEL: test_13_consecutive_stores_of_bytes: ; CHECK-BE-LABEL: test_13_consecutive_stores_of_bytes:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mfvsrd r3, vs34 ; CHECK-BE-NEXT: mfvsrd r3, vs34
; CHECK-BE-NEXT: xxswapd vs0, vs34 ; CHECK-BE-NEXT: xxswapd vs0, vs34
; CHECK-BE-NEXT: rldicl r4, r3, 40, 56 ; CHECK-BE-NEXT: extrdi r4, r3, 8, 32
; CHECK-BE-NEXT: clrldi r6, r3, 56 ; CHECK-BE-NEXT: clrldi r6, r3, 56
; CHECK-BE-NEXT: stb r4, 0(r5) ; CHECK-BE-NEXT: stb r4, 0(r5)
; CHECK-BE-NEXT: rldicl r4, r3, 56, 56 ; CHECK-BE-NEXT: extrdi r4, r3, 8, 48
; CHECK-BE-NEXT: mffprd r7, f0 ; CHECK-BE-NEXT: mffprd r7, f0
; CHECK-BE-NEXT: stb r6, 3(r5) ; CHECK-BE-NEXT: stb r6, 3(r5)
; CHECK-BE-NEXT: rldicl r6, r3, 8, 56 ; CHECK-BE-NEXT: srdi r6, r3, 56
; CHECK-BE-NEXT: stb r4, 4(r5) ; CHECK-BE-NEXT: stb r4, 4(r5)
; CHECK-BE-NEXT: rldicl r4, r3, 24, 56 ; CHECK-BE-NEXT: extrdi r4, r3, 8, 16
; CHECK-BE-NEXT: stb r6, 5(r5) ; CHECK-BE-NEXT: stb r6, 5(r5)
; CHECK-BE-NEXT: rldicl r6, r3, 16, 56 ; CHECK-BE-NEXT: extrdi r6, r3, 8, 8
; CHECK-BE-NEXT: stb r4, 8(r5) ; CHECK-BE-NEXT: stb r4, 8(r5)
; CHECK-BE-NEXT: rldicl r4, r7, 40, 56 ; CHECK-BE-NEXT: extrdi r4, r7, 8, 32
; CHECK-BE-NEXT: stb r6, 10(r5) ; CHECK-BE-NEXT: stb r6, 10(r5)
; CHECK-BE-NEXT: rldicl r6, r7, 16, 56 ; CHECK-BE-NEXT: extrdi r6, r7, 8, 8
; CHECK-BE-NEXT: stb r4, 1(r5) ; CHECK-BE-NEXT: stb r4, 1(r5)
; CHECK-BE-NEXT: rldicl r4, r7, 32, 56 ; CHECK-BE-NEXT: extrdi r4, r7, 8, 24
; CHECK-BE-NEXT: stb r6, 2(r5) ; CHECK-BE-NEXT: stb r6, 2(r5)
; CHECK-BE-NEXT: rldicl r6, r7, 48, 56 ; CHECK-BE-NEXT: extrdi r6, r7, 8, 40
; CHECK-BE-NEXT: stb r4, 6(r5) ; CHECK-BE-NEXT: stb r4, 6(r5)
; CHECK-BE-NEXT: clrldi r4, r7, 56 ; CHECK-BE-NEXT: clrldi r4, r7, 56
; CHECK-BE-NEXT: stb r6, 7(r5) ; CHECK-BE-NEXT: stb r6, 7(r5)
; CHECK-BE-NEXT: rldicl r3, r3, 48, 56 ; CHECK-BE-NEXT: extrdi r3, r3, 8, 40
; CHECK-BE-NEXT: rldicl r6, r7, 56, 56 ; CHECK-BE-NEXT: extrdi r6, r7, 8, 48
; CHECK-BE-NEXT: stb r4, 9(r5) ; CHECK-BE-NEXT: stb r4, 9(r5)
; CHECK-BE-NEXT: stb r3, 11(r5) ; CHECK-BE-NEXT: stb r3, 11(r5)
; CHECK-BE-NEXT: stb r6, 12(r5) ; CHECK-BE-NEXT: stb r6, 12(r5)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-P9-LABEL: test_13_consecutive_stores_of_bytes: ; CHECK-P9-LABEL: test_13_consecutive_stores_of_bytes:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: vsldoi v3, v2, v2, 12 ; CHECK-P9-NEXT: vsldoi v3, v2, v2, 12
▲ Show 20 Lines • Show All 219 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/fold-rlwinm-1.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names < %s \ ; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names < %s \
; RUN: -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s ; RUN: -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s
@res = dso_local local_unnamed_addr global i32 0, align 4 @res = dso_local local_unnamed_addr global i32 0, align 4
@res2 = dso_local local_unnamed_addr global i32 0, align 4 @res2 = dso_local local_unnamed_addr global i32 0, align 4
define void @foo(i32 signext %var1) { define void @foo(i32 signext %var1) {
; CHECK-LABEL: foo: ; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: addis r4, r2, res@toc@ha ; CHECK-NEXT: addis r4, r2, res@toc@ha
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: rlwinm r3, r3, 14, 0, 12 ; CHECK-NEXT: extlwi r3, r3, 13, 14
; CHECK-NEXT: stw r3, res@toc@l(r4) ; CHECK-NEXT: stw r3, res@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp eq i32 %var1, 1 %cmp = icmp eq i32 %var1, 1
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
%shl = shl nuw nsw i32 %conv, 19 %shl = shl nuw nsw i32 %conv, 19
store i32 %shl, i32* @res, align 4 store i32 %shl, i32* @res, align 4
ret void ret void
} }
define void @foo_multiple_use(i32 signext %var1) { define void @foo_multiple_use(i32 signext %var1) {
; CHECK-LABEL: foo_multiple_use: ; CHECK-LABEL: foo_multiple_use:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: addis r4, r2, res2@toc@ha ; CHECK-NEXT: addis r4, r2, res2@toc@ha
; CHECK-NEXT: addis r6, r2, res@toc@ha ; CHECK-NEXT: addis r6, r2, res@toc@ha
; CHECK-NEXT: cntlzw r3, r3 ; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: srwi r5, r3, 5 ; CHECK-NEXT: srwi r5, r3, 5
; CHECK-NEXT: rlwinm r3, r3, 14, 0, 12 ; CHECK-NEXT: extlwi r3, r3, 13, 14
; CHECK-NEXT: stw r5, res2@toc@l(r4) ; CHECK-NEXT: stw r5, res2@toc@l(r4)
; CHECK-NEXT: stw r3, res@toc@l(r6) ; CHECK-NEXT: stw r3, res@toc@l(r6)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp eq i32 %var1, 1 %cmp = icmp eq i32 %var1, 1
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
store i32 %conv, i32* @res2, align 4 store i32 %conv, i32* @res2, align 4
%shl = shl nuw nsw i32 %conv, 19 %shl = shl nuw nsw i32 %conv, 19
store i32 %shl, i32* @res, align 4 store i32 %shl, i32* @res, align 4
ret void ret void
} }

llvm/test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s -check-prefix=PPC64-P8 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s -check-prefix=PPC64-P8
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s -check-prefix=PPC64 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s -check-prefix=PPC64
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s -check-prefix=PPC64-P8 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s -check-prefix=PPC64-P8
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s -check-prefix=PPC64 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s -check-prefix=PPC64
; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu < %s | FileCheck %s -check-prefix=PPC32 ; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu < %s | FileCheck %s -check-prefix=PPC32
define i128 @test_abs(ppc_fp128 %x) nounwind { define i128 @test_abs(ppc_fp128 %x) nounwind {
entry: entry:
; PPC64-LABEL: test_abs: ; PPC64-LABEL: test_abs:
; PPC64-DAG: stfd 2, [[OFFSET_HI:-?[0-9]+]]([[SP:[0-9]+]]) ; PPC64-DAG: stfd 2, [[OFFSET_HI:-?[0-9]+]]([[SP:[0-9]+]])
; PPC64-DAG: stfd 1, [[OFFSET_LO:-?[0-9]+]]([[SP]]) ; PPC64-DAG: stfd 1, [[OFFSET_LO:-?[0-9]+]]([[SP]])
; PPC64-DAG: ld [[HI:[0-9]+]], [[OFFSET_LO]]([[SP]]) ; PPC64-DAG: ld [[HI:[0-9]+]], [[OFFSET_LO]]([[SP]])
; PPC64-DAG: ld [[LO:[0-9]+]], [[OFFSET_HI]]([[SP]]) ; PPC64-DAG: ld [[LO:[0-9]+]], [[OFFSET_HI]]([[SP]])
; PPC64-DAG: rldicr [[FLIP_BIT:[0-9]+]], [[HI]], 0, 0 ; PPC64-DAG: clrrdi [[FLIP_BIT:[0-9]+]], [[HI]], 63
; PPC64-DAG: xor 3, [[HI]], [[FLIP_BIT]] ; PPC64-DAG: xor 3, [[HI]], [[FLIP_BIT]]
; PPC64-DAG: xor 4, [[LO]], [[FLIP_BIT]] ; PPC64-DAG: xor 4, [[LO]], [[FLIP_BIT]]
; PPC64: blr ; PPC64: blr
; PPC64-P8-LABEL: test_abs: ; PPC64-P8-LABEL: test_abs:
; PPC64-P8-DAG: mffprd [[LO:[0-9]+]], 2 ; PPC64-P8-DAG: mffprd [[LO:[0-9]+]], 2
; PPC64-P8-DAG: mffprd [[HI:[0-9]+]], 1 ; PPC64-P8-DAG: mffprd [[HI:[0-9]+]], 1
; PPC64-P8-DAG: rldicr [[FLIP_BIT:[0-9]+]], [[HI]], 0, 0 ; PPC64-P8-DAG: clrrdi [[FLIP_BIT:[0-9]+]], [[HI]], 63
; PPC64-P8-DAG: xor 3, [[HI]], [[FLIP_BIT]] ; PPC64-P8-DAG: xor 3, [[HI]], [[FLIP_BIT]]
; PPC64-P8-DAG: xor 4, [[LO]], [[FLIP_BIT]] ; PPC64-P8-DAG: xor 4, [[LO]], [[FLIP_BIT]]
; PPC64-P8: blr ; PPC64-P8: blr
; PPC32-DAG: stfd 1, 24(1) ; PPC32-DAG: stfd 1, 24(1)
; PPC32-DAG: stfd 2, 16(1) ; PPC32-DAG: stfd 2, 16(1)
; PPC32-DAG: lwz [[HI0:[0-9]+]], 24(1) ; PPC32-DAG: lwz [[HI0:[0-9]+]], 24(1)
; PPC32-DAG: lwz [[LO0:[0-9]+]], 16(1) ; PPC32-DAG: lwz [[LO0:[0-9]+]], 16(1)
; PPC32: rlwinm [[FLIP_BIT:[0-9]+]], [[HI0]], 0, 0, 0 ; PPC32: clrrwi [[FLIP_BIT:[0-9]+]], [[HI0]], 31
; PPC32-DAG: lwz [[HI1:[0-9]+]], 28(1) ; PPC32-DAG: lwz [[HI1:[0-9]+]], 28(1)
; PPC32-DAG: lwz [[LO1:[0-9]+]], 20(1) ; PPC32-DAG: lwz [[LO1:[0-9]+]], 20(1)
; PPC32-DAG: xor [[HI0]], [[HI0]], [[FLIP_BIT]] ; PPC32-DAG: xor [[HI0]], [[HI0]], [[FLIP_BIT]]
; PPC32-DAG: xor [[LO0]], [[LO0]], [[FLIP_BIT]] ; PPC32-DAG: xor [[LO0]], [[LO0]], [[FLIP_BIT]]
; PPC32: blr ; PPC32: blr
%0 = tail call ppc_fp128 @llvm.fabs.ppcf128(ppc_fp128 %x) %0 = tail call ppc_fp128 @llvm.fabs.ppcf128(ppc_fp128 %x)
%1 = bitcast ppc_fp128 %0 to i128 %1 = bitcast ppc_fp128 %0 to i128
ret i128 %1 ret i128 %1
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; PPC64-LABEL: test_copysign: ; PPC64-LABEL: test_copysign:
; PPC64-DAG: stfd 1, [[OFFSET:-?[0-9]+]](1) ; PPC64-DAG: stfd 1, [[OFFSET:-?[0-9]+]](1)
; PPC64-DAG: li [[HI_TMP:[0-9]+]], 16399 ; PPC64-DAG: li [[HI_TMP:[0-9]+]], 16399
; PPC64-DAG: li [[LO_TMP:[0-9]+]], 3019 ; PPC64-DAG: li [[LO_TMP:[0-9]+]], 3019
; PPC64-NOT: BARRIER ; PPC64-NOT: BARRIER
; PPC64-DAG: sldi [[CST_HI:[0-9]+]], [[HI_TMP]], 48 ; PPC64-DAG: sldi [[CST_HI:[0-9]+]], [[HI_TMP]], 48
; PPC64-DAG: sldi [[CST_LO:[0-9]+]], [[LO_TMP]], 52 ; PPC64-DAG: sldi [[CST_LO:[0-9]+]], [[LO_TMP]], 52
; PPC64-DAG: ld [[X_HI:[0-9]+]], [[OFFSET]](1) ; PPC64-DAG: ld [[X_HI:[0-9]+]], [[OFFSET]](1)
; PPC64-DAG: rldicr [[NEW_HI_TMP:[0-9]+]], [[X_HI]], 0, 0 ; PPC64-DAG: clrrdi [[NEW_HI_TMP:[0-9]+]], [[X_HI]], 63
; PPC64-DAG: or 3, [[NEW_HI_TMP]], [[CST_HI]] ; PPC64-DAG: or 3, [[NEW_HI_TMP]], [[CST_HI]]
; PPC64-DAG: xor 4, [[NEW_HI_TMP]], [[CST_LO]] ; PPC64-DAG: xor 4, [[NEW_HI_TMP]], [[CST_LO]]
; PPC64: blr ; PPC64: blr
; PPC64-P8-LABEL: test_copysign: ; PPC64-P8-LABEL: test_copysign:
; PPC64-P8-DAG: mffprd [[X_HI:[0-9]+]], 1 ; PPC64-P8-DAG: mffprd [[X_HI:[0-9]+]], 1
; PPC64-P8-DAG: li [[HI_TMP:[0-9]+]], 16399 ; PPC64-P8-DAG: li [[HI_TMP:[0-9]+]], 16399
; PPC64-P8-DAG: li [[LO_TMP:[0-9]+]], 3019 ; PPC64-P8-DAG: li [[LO_TMP:[0-9]+]], 3019
; PPC64-P8-NOT: BARRIER ; PPC64-P8-NOT: BARRIER
; PPC64-P8-DAG: sldi [[CST_HI:[0-9]+]], [[HI_TMP]], 48 ; PPC64-P8-DAG: sldi [[CST_HI:[0-9]+]], [[HI_TMP]], 48
; PPC64-P8-DAG: sldi [[CST_LO:[0-9]+]], [[LO_TMP]], 52 ; PPC64-P8-DAG: sldi [[CST_LO:[0-9]+]], [[LO_TMP]], 52
; PPC64-P8-DAG: rldicr [[NEW_HI_TMP:[0-9]+]], [[X_HI]], 0, 0 ; PPC64-P8-DAG: clrrdi [[NEW_HI_TMP:[0-9]+]], [[X_HI]], 63
; PPC64-P8-DAG: or 3, [[NEW_HI_TMP]], [[CST_HI]] ; PPC64-P8-DAG: or 3, [[NEW_HI_TMP]], [[CST_HI]]
; PPC64-P8-DAG: xor 4, [[NEW_HI_TMP]], [[CST_LO]] ; PPC64-P8-DAG: xor 4, [[NEW_HI_TMP]], [[CST_LO]]
; PPC64-P8: blr ; PPC64-P8: blr
; PPC32: stfd 1, [[STACK:[0-9]+]](1) ; PPC32: stfd 1, [[STACK:[0-9]+]](1)
; PPC32: lwz [[HI:[0-9]+]], [[STACK]](1) ; PPC32: lwz [[HI:[0-9]+]], [[STACK]](1)
; PPC32: rlwinm [[FLIP_BIT:[0-9]+]], [[HI]], 0, 0, 0 ; PPC32: clrrwi [[FLIP_BIT:[0-9]+]], [[HI]], 31
; PPC32-NOT: BARRIER ; PPC32-NOT: BARRIER
; PPC32-DAG: oris {{[0-9]+}}, [[FLIP_BIT]], 16399 ; PPC32-DAG: oris {{[0-9]+}}, [[FLIP_BIT]], 16399
; PPC32-DAG: xoris {{[0-9]+}}, [[FLIP_BIT]], 48304 ; PPC32-DAG: xoris {{[0-9]+}}, [[FLIP_BIT]], 48304
; PPC32: blr ; PPC32: blr
%0 = tail call ppc_fp128 @llvm.copysign.ppcf128(ppc_fp128 0xM400F000000000000BCB0000000000000, ppc_fp128 %x) %0 = tail call ppc_fp128 @llvm.copysign.ppcf128(ppc_fp128 0xM400F000000000000BCB0000000000000, ppc_fp128 %x)
%1 = bitcast ppc_fp128 %0 to i128 %1 = bitcast ppc_fp128 %0 to i128
ret i128 %1 ret i128 %1
} }
declare ppc_fp128 @llvm.fabs.ppcf128(ppc_fp128) declare ppc_fp128 @llvm.fabs.ppcf128(ppc_fp128)
declare ppc_fp128 @llvm.copysign.ppcf128(ppc_fp128, ppc_fp128) declare ppc_fp128 @llvm.copysign.ppcf128(ppc_fp128, ppc_fp128)

llvm/test/CodeGen/PowerPC/funnel-shift-rot.ll

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declare <4 x i32> @llvm.fshr.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) declare <4 x i32> @llvm.fshr.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
; When first 2 operands match, it's a rotate. ; When first 2 operands match, it's a rotate.
define i8 @rotl_i8_const_shift(i8 %x) { define i8 @rotl_i8_const_shift(i8 %x) {
; CHECK-LABEL: rotl_i8_const_shift: ; CHECK-LABEL: rotl_i8_const_shift:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: rotlwi 4, 3, 27 ; CHECK-NEXT: rotlwi 4, 3, 27
; CHECK-NEXT: rlwimi 4, 3, 3, 0, 28 ; CHECK-NEXT: insrwi 4, 3, 29, 0
; CHECK-NEXT: mr 3, 4 ; CHECK-NEXT: mr 3, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%f = call i8 @llvm.fshl.i8(i8 %x, i8 %x, i8 3) %f = call i8 @llvm.fshl.i8(i8 %x, i8 %x, i8 3)
ret i8 %f ret i8 %f
} }
define i64 @rotl_i64_const_shift(i64 %x) { define i64 @rotl_i64_const_shift(i64 %x) {
; CHECK-LABEL: rotl_i64_const_shift: ; CHECK-LABEL: rotl_i64_const_shift:
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} }
; Repeat everything for funnel shift right. ; Repeat everything for funnel shift right.
define i8 @rotr_i8_const_shift(i8 %x) { define i8 @rotr_i8_const_shift(i8 %x) {
; CHECK-LABEL: rotr_i8_const_shift: ; CHECK-LABEL: rotr_i8_const_shift:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: rotlwi 4, 3, 29 ; CHECK-NEXT: rotlwi 4, 3, 29
; CHECK-NEXT: rlwimi 4, 3, 5, 0, 26 ; CHECK-NEXT: insrwi 4, 3, 27, 0
; CHECK-NEXT: mr 3, 4 ; CHECK-NEXT: mr 3, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%f = call i8 @llvm.fshr.i8(i8 %x, i8 %x, i8 3) %f = call i8 @llvm.fshr.i8(i8 %x, i8 %x, i8 3)
ret i8 %f ret i8 %f
} }
define i32 @rotr_i32_const_shift(i32 %x) { define i32 @rotr_i32_const_shift(i32 %x) {
; CHECK-LABEL: rotr_i32_const_shift: ; CHECK-LABEL: rotr_i32_const_shift:
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llvm/test/CodeGen/PowerPC/funnel-shift.ll

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; CHECK-NEXT: lis 6, -8857 ; CHECK-NEXT: lis 6, -8857
; CHECK-NEXT: clrldi 5, 5, 27 ; CHECK-NEXT: clrldi 5, 5, 27
; CHECK-NEXT: ori 6, 6, 51366 ; CHECK-NEXT: ori 6, 6, 51366
; CHECK-NEXT: clrldi 4, 4, 27 ; CHECK-NEXT: clrldi 4, 4, 27
; CHECK-NEXT: sldi 6, 6, 32 ; CHECK-NEXT: sldi 6, 6, 32
; CHECK-NEXT: oris 6, 6, 3542 ; CHECK-NEXT: oris 6, 6, 3542
; CHECK-NEXT: ori 6, 6, 31883 ; CHECK-NEXT: ori 6, 6, 31883
; CHECK-NEXT: mulhdu 6, 5, 6 ; CHECK-NEXT: mulhdu 6, 5, 6
; CHECK-NEXT: rldicl 6, 6, 59, 5 ; CHECK-NEXT: srdi 6, 6, 5
; CHECK-NEXT: mulli 6, 6, 37 ; CHECK-NEXT: mulli 6, 6, 37
; CHECK-NEXT: sub. 5, 5, 6 ; CHECK-NEXT: sub. 5, 5, 6
; CHECK-NEXT: subfic 6, 5, 37 ; CHECK-NEXT: subfic 6, 5, 37
; CHECK-NEXT: sld 5, 3, 5 ; CHECK-NEXT: sld 5, 3, 5
; CHECK-NEXT: srd 4, 4, 6 ; CHECK-NEXT: srd 4, 4, 6
; CHECK-NEXT: or 4, 5, 4 ; CHECK-NEXT: or 4, 5, 4
; CHECK-NEXT: iseleq 3, 3, 4 ; CHECK-NEXT: iseleq 3, 3, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
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} }
; With constant shift amount, this is rotate + insert (missing extended mnemonics). ; With constant shift amount, this is rotate + insert (missing extended mnemonics).
define i32 @fshl_i32_const_shift(i32 %x, i32 %y) { define i32 @fshl_i32_const_shift(i32 %x, i32 %y) {
; CHECK-LABEL: fshl_i32_const_shift: ; CHECK-LABEL: fshl_i32_const_shift:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: rotlwi 4, 4, 9 ; CHECK-NEXT: rotlwi 4, 4, 9
; CHECK-NEXT: rlwimi 4, 3, 9, 0, 22 ; CHECK-NEXT: insrwi 4, 3, 23, 0
; CHECK-NEXT: mr 3, 4 ; CHECK-NEXT: mr 3, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%f = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 9) %f = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 9)
ret i32 %f ret i32 %f
} }
; Check modulo math on shift amount. ; Check modulo math on shift amount.
define i32 @fshl_i32_const_overshift(i32 %x, i32 %y) { define i32 @fshl_i32_const_overshift(i32 %x, i32 %y) {
; CHECK-LABEL: fshl_i32_const_overshift: ; CHECK-LABEL: fshl_i32_const_overshift:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: rotlwi 4, 4, 9 ; CHECK-NEXT: rotlwi 4, 4, 9
; CHECK-NEXT: rlwimi 4, 3, 9, 0, 22 ; CHECK-NEXT: insrwi 4, 3, 23, 0
; CHECK-NEXT: mr 3, 4 ; CHECK-NEXT: mr 3, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%f = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 41) %f = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 41)
ret i32 %f ret i32 %f
} }
; 64-bit should also work. ; 64-bit should also work.
define i64 @fshl_i64_const_overshift(i64 %x, i64 %y) { define i64 @fshl_i64_const_overshift(i64 %x, i64 %y) {
; CHECK-LABEL: fshl_i64_const_overshift: ; CHECK-LABEL: fshl_i64_const_overshift:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: rotldi 4, 4, 41 ; CHECK-NEXT: rotldi 4, 4, 41
; CHECK-NEXT: rldimi 4, 3, 41, 0 ; CHECK-NEXT: insrdi 4, 3, 23, 0
; CHECK-NEXT: mr 3, 4 ; CHECK-NEXT: mr 3, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%f = call i64 @llvm.fshl.i64(i64 %x, i64 %y, i64 105) %f = call i64 @llvm.fshl.i64(i64 %x, i64 %y, i64 105)
ret i64 %f ret i64 %f
} }
; This should work without any node-specific logic. ; This should work without any node-specific logic.
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; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lis 6, -8857 ; CHECK-NEXT: lis 6, -8857
; CHECK-NEXT: clrldi 5, 5, 27 ; CHECK-NEXT: clrldi 5, 5, 27
; CHECK-NEXT: ori 6, 6, 51366 ; CHECK-NEXT: ori 6, 6, 51366
; CHECK-NEXT: sldi 6, 6, 32 ; CHECK-NEXT: sldi 6, 6, 32
; CHECK-NEXT: oris 6, 6, 3542 ; CHECK-NEXT: oris 6, 6, 3542
; CHECK-NEXT: ori 6, 6, 31883 ; CHECK-NEXT: ori 6, 6, 31883
; CHECK-NEXT: mulhdu 6, 5, 6 ; CHECK-NEXT: mulhdu 6, 5, 6
; CHECK-NEXT: rldicl 6, 6, 59, 5 ; CHECK-NEXT: srdi 6, 6, 5
; CHECK-NEXT: mulli 6, 6, 37 ; CHECK-NEXT: mulli 6, 6, 37
; CHECK-NEXT: sub. 5, 5, 6 ; CHECK-NEXT: sub. 5, 5, 6
; CHECK-NEXT: clrldi 6, 4, 27 ; CHECK-NEXT: clrldi 6, 4, 27
; CHECK-NEXT: subfic 7, 5, 37 ; CHECK-NEXT: subfic 7, 5, 37
; CHECK-NEXT: srd 5, 6, 5 ; CHECK-NEXT: srd 5, 6, 5
; CHECK-NEXT: sld 3, 3, 7 ; CHECK-NEXT: sld 3, 3, 7
; CHECK-NEXT: or 3, 3, 5 ; CHECK-NEXT: or 3, 3, 5
; CHECK-NEXT: iseleq 3, 4, 3 ; CHECK-NEXT: iseleq 3, 4, 3
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} }
; With constant shift amount, this is rotate + insert (missing extended mnemonics). ; With constant shift amount, this is rotate + insert (missing extended mnemonics).
define i32 @fshr_i32_const_shift(i32 %x, i32 %y) { define i32 @fshr_i32_const_shift(i32 %x, i32 %y) {
; CHECK-LABEL: fshr_i32_const_shift: ; CHECK-LABEL: fshr_i32_const_shift:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: rotlwi 4, 4, 23 ; CHECK-NEXT: rotlwi 4, 4, 23
; CHECK-NEXT: rlwimi 4, 3, 23, 0, 8 ; CHECK-NEXT: insrwi 4, 3, 9, 0
; CHECK-NEXT: mr 3, 4 ; CHECK-NEXT: mr 3, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%f = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 9) %f = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 9)
ret i32 %f ret i32 %f
} }
; Check modulo math on shift amount. 41-32=9. ; Check modulo math on shift amount. 41-32=9.
define i32 @fshr_i32_const_overshift(i32 %x, i32 %y) { define i32 @fshr_i32_const_overshift(i32 %x, i32 %y) {
; CHECK-LABEL: fshr_i32_const_overshift: ; CHECK-LABEL: fshr_i32_const_overshift:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: rotlwi 4, 4, 23 ; CHECK-NEXT: rotlwi 4, 4, 23
; CHECK-NEXT: rlwimi 4, 3, 23, 0, 8 ; CHECK-NEXT: insrwi 4, 3, 9, 0
; CHECK-NEXT: mr 3, 4 ; CHECK-NEXT: mr 3, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%f = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 41) %f = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 41)
ret i32 %f ret i32 %f
} }
; 64-bit should also work. 105-64 = 41. ; 64-bit should also work. 105-64 = 41.
define i64 @fshr_i64_const_overshift(i64 %x, i64 %y) { define i64 @fshr_i64_const_overshift(i64 %x, i64 %y) {
; CHECK-LABEL: fshr_i64_const_overshift: ; CHECK-LABEL: fshr_i64_const_overshift:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: rotldi 4, 4, 23 ; CHECK-NEXT: rotldi 4, 4, 23
; CHECK-NEXT: rldimi 4, 3, 23, 0 ; CHECK-NEXT: insrdi 4, 3, 41, 0
; CHECK-NEXT: mr 3, 4 ; CHECK-NEXT: mr 3, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%f = call i64 @llvm.fshr.i64(i64 %x, i64 %y, i64 105) %f = call i64 @llvm.fshr.i64(i64 %x, i64 %y, i64 105)
ret i64 %f ret i64 %f
} }
; This should work without any node-specific logic. ; This should work without any node-specific logic.
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llvm/test/CodeGen/PowerPC/htm-ttest.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs \ ; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs \
; RUN: -mcpu=pwr8 -mattr=+htm < %s | FileCheck %s ; RUN: -mcpu=pwr8 -mattr=+htm < %s | FileCheck %s
define dso_local void @main() #0 { define dso_local void @main() #0 {
; CHECK-LABEL: main: ; CHECK-LABEL: main:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li 3, 0 ; CHECK-NEXT: li 3, 0
; CHECK-NEXT: tabortwci. 0, 3, 0 ; CHECK-NEXT: tabortwci. 0, 3, 0
; CHECK-NEXT: mfocrf 3, 128 ; CHECK-NEXT: mfocrf 3, 128
; CHECK-NEXT: rldicl 3, 3, 36, 28 ; CHECK-NEXT: srdi 3, 3, 28
; CHECK-NEXT: rlwinm. 3, 3, 31, 30, 31 ; CHECK-NEXT: extrwi. 3, 3, 2, 29
; CHECK-NEXT: beqlr+ 0 ; CHECK-NEXT: beqlr+ 0
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
%1 = call i64 @llvm.ppc.ttest() #1 %1 = call i64 @llvm.ppc.ttest() #1
%2 = lshr i64 %1, 1 %2 = lshr i64 %1, 1
%3 = and i64 %2, 3 %3 = and i64 %2, 3
%4 = icmp eq i64 %3, 0 %4 = icmp eq i64 %3, 0
br i1 %4, label %5, label %6 br i1 %4, label %5, label %6
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llvm/test/CodeGen/PowerPC/htm.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mattr=+htm < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mattr=+htm < %s | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
define zeroext i32 @test1() { define zeroext i32 @test1() {
entry: entry:
%0 = tail call i32 @llvm.ppc.tbegin(i32 0) %0 = tail call i32 @llvm.ppc.tbegin(i32 0)
ret i32 %0 ret i32 %0
; CHECK-LABEL: @test1 ; CHECK-LABEL: @test1
; CHECK: tbegin. 0 ; CHECK: tbegin. 0
; CHECK: mfocrf [[REGISTER1:[0-9]+]], 128 ; CHECK: mfocrf [[REGISTER1:[0-9]+]], 128
; CHECK: rlwinm [[REGISTER2:[0-9]+]], [[REGISTER1]], 3, 31, 31 ; CHECK: extrwi [[REGISTER2:[0-9]+]], [[REGISTER1]], 1, 2
; CHECK: xori {{[0-9]+}}, [[REGISTER2]], 1 ; CHECK: xori {{[0-9]+}}, [[REGISTER2]], 1
} }
declare i32 @llvm.ppc.tbegin(i32) #1 declare i32 @llvm.ppc.tbegin(i32) #1
define zeroext i32 @test2() { define zeroext i32 @test2() {
entry: entry:
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llvm/test/CodeGen/PowerPC/i64_fp_round.ll

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; for minor code generation differences. ; for minor code generation differences.
;CHECK-LABEL: test ;CHECK-LABEL: test
;CHECK-NO-ISEL-LABEL: test ;CHECK-NO-ISEL-LABEL: test
; CHECK: sradi [[REG1:[0-9]+]], 3, 53 ; CHECK: sradi [[REG1:[0-9]+]], 3, 53
; CHECK: addi [[REG2:[0-9]+]], [[REG1]], 1 ; CHECK: addi [[REG2:[0-9]+]], [[REG1]], 1
; CHECK: cmpldi [[REG2]], 1 ; CHECK: cmpldi [[REG2]], 1
; CHECK: iselgt [[REG3:[0-9]+]], {{[0-9]+}}, 3 ; CHECK: iselgt [[REG3:[0-9]+]], {{[0-9]+}}, 3
; CHECK-NO-ISEL: rldicr [[REG2:[0-9]+]], {{[0-9]+}}, 0, 52 ; CHECK-NO-ISEL: clrrdi [[REG2:[0-9]+]], {{[0-9]+}}, 11
; CHECK-NO-ISEL: bc 12, 1, [[TRUE:.LBB[0-9]+]] ; CHECK-NO-ISEL: bc 12, 1, [[TRUE:.LBB[0-9]+]]
; CHECK-NO-ISEL: b [[SUCCESSOR:.LBB[0-9]+]] ; CHECK-NO-ISEL: b [[SUCCESSOR:.LBB[0-9]+]]
; CHECK-NO-ISEL-NEXT: [[TRUE]] ; CHECK-NO-ISEL-NEXT: [[TRUE]]
; CHECK-NO-ISEL-NEXT: addi {{[0-9]+}}, [[REG2]], 0 ; CHECK-NO-ISEL-NEXT: addi {{[0-9]+}}, [[REG2]], 0
; CHECK-NO-ISEL-NEXT: [[SUCCESSOR]] ; CHECK-NO-ISEL-NEXT: [[SUCCESSOR]]
; CHECK-NO-ISEL: std {{[0-9]+}}, -{{[0-9]+}}(1) ; CHECK-NO-ISEL: std {{[0-9]+}}, -{{[0-9]+}}(1)
; CHECK: std [[REG3]], -{{[0-9]+}}(1) ; CHECK: std [[REG3]], -{{[0-9]+}}(1)
; Also check that with -enable-unsafe-fp-math we do not get that extra ; Also check that with -enable-unsafe-fp-math we do not get that extra
; code sequence. Simply verify that there is no "isel" present. ; code sequence. Simply verify that there is no "isel" present.
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-fpcvt -enable-unsafe-fp-math < %s | FileCheck %s -check-prefix=CHECK-UNSAFE ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-fpcvt -enable-unsafe-fp-math < %s | FileCheck %s -check-prefix=CHECK-UNSAFE
; CHECK-UNSAFE-NOT: isel ; CHECK-UNSAFE-NOT: isel

llvm/test/CodeGen/PowerPC/jump-tables-collapse-rotate-remove-SrcMI.mir

Show All 40 Lines bb.0.entry:
%2:g8rc = RLDICL killed %1, 0, 32 %2:g8rc = RLDICL killed %1, 0, 32
%3:g8rc = RLDICR %2, 2, 61 %3:g8rc = RLDICR %2, 2, 61
$x3 = COPY %3 $x3 = COPY %3
BLR8 implicit $lr8, implicit $rm, implicit $x3 BLR8 implicit $lr8, implicit $rm, implicit $x3
... ...
# CHECK-LABEL: test: # CHECK-LABEL: test:
# CHECK: # %bb.0: # %entry # CHECK: # %bb.0: # %entry
# CHECK-NEXT: rldic 3, 4, 2, 30 # CHECK-NEXT: clrlsldi 3, 4, 32, 2
# CHECK-NEXT: blr # CHECK-NEXT: blr
# #
# CHECK-PASS-NOT: %2:g8rc = RLDICL killed %1, 0, 32 # CHECK-PASS-NOT: %2:g8rc = RLDICL killed %1, 0, 32
# CHECK-PASS-NOT: %3:g8rc = RLDICR %2, 2, 61 # CHECK-PASS-NOT: %3:g8rc = RLDICR %2, 2, 61
# CHECK-PASS: %3:g8rc = RLDIC %1, 2, 30 # CHECK-PASS: %3:g8rc = RLDIC %1, 2, 30

llvm/test/CodeGen/PowerPC/jump-tables-collapse-rotate.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -o - \ ; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -o - \
; RUN: -ppc-asm-full-reg-names -verify-machineinstrs %s | FileCheck %s ; RUN: -ppc-asm-full-reg-names -verify-machineinstrs %s | FileCheck %s
; Function Attrs: nounwind ; Function Attrs: nounwind
define dso_local zeroext i32 @test(i32 signext %l) nounwind { define dso_local zeroext i32 @test(i32 signext %l) nounwind {
; CHECK-LABEL: test: ; CHECK-LABEL: test:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: std r0, 16(r1) ; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -32(r1) ; CHECK-NEXT: stdu r1, -32(r1)
; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: cmplwi r3, 5 ; CHECK-NEXT: cmplwi r3, 5
; CHECK-NEXT: bgt cr0, .LBB0_3 ; CHECK-NEXT: bgt cr0, .LBB0_3
; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: rldic r3, r3, 2, 30 ; CHECK-NEXT: clrlsldi r3, r3, 32, 2
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: lwax r3, r3, r4 ; CHECK-NEXT: lwax r3, r3, r4
; CHECK-NEXT: add r3, r3, r4 ; CHECK-NEXT: add r3, r3, r4
; CHECK-NEXT: mtctr r3 ; CHECK-NEXT: mtctr r3
; CHECK-NEXT: bctr ; CHECK-NEXT: bctr
; CHECK-NEXT: .LBB0_2: # %sw.bb ; CHECK-NEXT: .LBB0_2: # %sw.bb
; CHECK-NEXT: li r3, 2 ; CHECK-NEXT: li r3, 2
; CHECK-NEXT: bl test1 ; CHECK-NEXT: bl test1
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llvm/test/CodeGen/PowerPC/knowCRBitSpill.ll

Show All 16 Lines
@a = common dso_local global i64 0, align 8 @a = common dso_local global i64 0, align 8
; Function Attrs: nounwind ; Function Attrs: nounwind
define dso_local signext i32 @spillCRSET(i32 signext %p1, i32 signext %p2) { define dso_local signext i32 @spillCRSET(i32 signext %p1, i32 signext %p2) {
; CHECK-LABEL: spillCRSET: ; CHECK-LABEL: spillCRSET:
; CHECK: # %bb.2: ; CHECK: # %bb.2:
; CHECK-DAG: crnot [[CREG:.*]]*cr5+lt, eq ; CHECK-DAG: crnot [[CREG:.*]]*cr5+lt, eq
; CHECK-DAG: mfocrf [[REG2:.*]], [[CREG]] ; CHECK-DAG: mfocrf [[REG2:.*]], [[CREG]]
; CHECK-DAG: rlwinm [[REG2]], [[REG2]] ; CHECK-DAG: extlwi [[REG2]], [[REG2]]
; CHECK: .LBB0_3: ; CHECK: .LBB0_3:
; CHECK-NOT: #UNENCODED_NOP ; CHECK-NOT: #UNENCODED_NOP
; CHECK: lis [[REG1:.*]], -32768 ; CHECK: lis [[REG1:.*]], -32768
; CHECK: .LBB0_4: ; CHECK: .LBB0_4:
; CHECK-NOT: mfocrf [[REG2:.*]], [[CREG]] ; CHECK-NOT: mfocrf [[REG2:.*]], [[CREG]]
; CHECK-NOT: rlwinm [[REG2]], [[REG2]] ; CHECK-NOT: extlwi [[REG2]], [[REG2]]
; CHECK: stw [[REG1]] ; CHECK: stw [[REG1]]
; CHECK: # %bb.5: ; CHECK: # %bb.5:
entry: entry:
%tobool = icmp eq i32 %p2, 0 %tobool = icmp eq i32 %p2, 0
%tobool2 = icmp eq i32 %p1, 0 %tobool2 = icmp eq i32 %p1, 0
br label %redo_first_pass br label %redo_first_pass
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llvm/test/CodeGen/PowerPC/legalize-vaarg.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
;RUN: llc < %s --mtriple=powerpc64-unknown-linux-gnu -mattr=+altivec | FileCheck %s -check-prefix=BE ;RUN: llc < %s --mtriple=powerpc64-unknown-linux-gnu -mattr=+altivec | FileCheck %s -check-prefix=BE
;RUN: llc < %s --mtriple=powerpc64le-unknown-linux-gnu -mattr=+altivec | FileCheck %s -check-prefix=LE ;RUN: llc < %s --mtriple=powerpc64le-unknown-linux-gnu -mattr=+altivec | FileCheck %s -check-prefix=LE
define <8 x i32> @test_large_vec_vaarg(i32 %n, ...) { define <8 x i32> @test_large_vec_vaarg(i32 %n, ...) {
; BE-LABEL: test_large_vec_vaarg: ; BE-LABEL: test_large_vec_vaarg:
; BE: # %bb.0: ; BE: # %bb.0:
; BE-NEXT: ld 3, -8(1) ; BE-NEXT: ld 3, -8(1)
; BE-NEXT: std 4, 56(1) ; BE-NEXT: std 4, 56(1)
; BE-NEXT: std 5, 64(1) ; BE-NEXT: std 5, 64(1)
; BE-NEXT: std 6, 72(1) ; BE-NEXT: std 6, 72(1)
; BE-NEXT: std 7, 80(1) ; BE-NEXT: std 7, 80(1)
; BE-NEXT: std 8, 88(1) ; BE-NEXT: std 8, 88(1)
; BE-NEXT: std 9, 96(1) ; BE-NEXT: std 9, 96(1)
; BE-NEXT: std 10, 104(1) ; BE-NEXT: std 10, 104(1)
; BE-NEXT: addi 3, 3, 15 ; BE-NEXT: addi 3, 3, 15
; BE-NEXT: rldicr 3, 3, 0, 59 ; BE-NEXT: clrrdi 3, 3, 4
; BE-NEXT: addi 4, 3, 16 ; BE-NEXT: addi 4, 3, 16
; BE-NEXT: addi 5, 3, 31 ; BE-NEXT: addi 5, 3, 31
; BE-NEXT: std 4, -8(1) ; BE-NEXT: std 4, -8(1)
; BE-NEXT: rldicr 4, 5, 0, 59 ; BE-NEXT: clrrdi 4, 5, 4
; BE-NEXT: lvx 2, 0, 3 ; BE-NEXT: lvx 2, 0, 3
; BE-NEXT: addi 3, 4, 16 ; BE-NEXT: addi 3, 4, 16
; BE-NEXT: std 3, -8(1) ; BE-NEXT: std 3, -8(1)
; BE-NEXT: lvx 3, 0, 4 ; BE-NEXT: lvx 3, 0, 4
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; LE-LABEL: test_large_vec_vaarg: ; LE-LABEL: test_large_vec_vaarg:
; LE: # %bb.0: ; LE: # %bb.0:
; LE-NEXT: ld 3, -8(1) ; LE-NEXT: ld 3, -8(1)
; LE-NEXT: std 4, 40(1) ; LE-NEXT: std 4, 40(1)
; LE-NEXT: std 5, 48(1) ; LE-NEXT: std 5, 48(1)
; LE-NEXT: std 6, 56(1) ; LE-NEXT: std 6, 56(1)
; LE-NEXT: std 7, 64(1) ; LE-NEXT: std 7, 64(1)
; LE-NEXT: addi 3, 3, 15 ; LE-NEXT: addi 3, 3, 15
; LE-NEXT: rldicr 3, 3, 0, 59 ; LE-NEXT: clrrdi 3, 3, 4
; LE-NEXT: std 8, 72(1) ; LE-NEXT: std 8, 72(1)
; LE-NEXT: std 9, 80(1) ; LE-NEXT: std 9, 80(1)
; LE-NEXT: std 10, 88(1) ; LE-NEXT: std 10, 88(1)
; LE-NEXT: addi 4, 3, 31 ; LE-NEXT: addi 4, 3, 31
; LE-NEXT: addi 5, 3, 16 ; LE-NEXT: addi 5, 3, 16
; LE-NEXT: rldicr 4, 4, 0, 59 ; LE-NEXT: clrrdi 4, 4, 4
; LE-NEXT: std 5, -8(1) ; LE-NEXT: std 5, -8(1)
; LE-NEXT: addi 5, 4, 16 ; LE-NEXT: addi 5, 4, 16
; LE-NEXT: lvx 2, 0, 3 ; LE-NEXT: lvx 2, 0, 3
; LE-NEXT: std 5, -8(1) ; LE-NEXT: std 5, -8(1)
; LE-NEXT: lvx 3, 0, 4 ; LE-NEXT: lvx 3, 0, 4
; LE-NEXT: blr ; LE-NEXT: blr
%args = alloca i8*, align 4 %args = alloca i8*, align 4
%x = va_arg i8** %args, <8 x i32> %x = va_arg i8** %args, <8 x i32>
ret <8 x i32> %x ret <8 x i32> %x
} }

llvm/test/CodeGen/PowerPC/loop-instr-form-prepare.ll

Show First 20 Lines • Show All 504 Lines • ▼ Show 20 Lines
; CHECK-NEXT: mulld r0, r0, r30 ; CHECK-NEXT: mulld r0, r0, r30
; CHECK-NEXT: mulld r0, r0, r12 ; CHECK-NEXT: mulld r0, r0, r12
; CHECK-NEXT: mulld r0, r0, r11 ; CHECK-NEXT: mulld r0, r0, r11
; CHECK-NEXT: maddld r3, r0, r7, r3 ; CHECK-NEXT: maddld r3, r0, r7, r3
; CHECK-NEXT: bdz .LBB6_9 ; CHECK-NEXT: bdz .LBB6_9
; CHECK-NEXT: .LBB6_4: # ; CHECK-NEXT: .LBB6_4: #
; CHECK-NEXT: lbzu r0, 1(r5) ; CHECK-NEXT: lbzu r0, 1(r5)
; CHECK-NEXT: mulhwu r27, r0, r4 ; CHECK-NEXT: mulhwu r27, r0, r4
; CHECK-NEXT: rlwinm r26, r27, 0, 0, 30 ; CHECK-NEXT: clrrwi r26, r27, 1
; CHECK-NEXT: srwi r27, r27, 1 ; CHECK-NEXT: srwi r27, r27, 1
; CHECK-NEXT: add r27, r27, r26 ; CHECK-NEXT: add r27, r27, r26
; CHECK-NEXT: sub r0, r0, r27 ; CHECK-NEXT: sub r0, r0, r27
; CHECK-NEXT: cmplwi r0, 1 ; CHECK-NEXT: cmplwi r0, 1
; CHECK-NEXT: beq cr0, .LBB6_2 ; CHECK-NEXT: beq cr0, .LBB6_2
; CHECK-NEXT: # %bb.5: # ; CHECK-NEXT: # %bb.5: #
; CHECK-NEXT: clrlwi r0, r0, 24 ; CHECK-NEXT: clrlwi r0, r0, 24
; CHECK-NEXT: cmplwi r0, 2 ; CHECK-NEXT: cmplwi r0, 2
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llvm/test/CodeGen/PowerPC/machine-pre.ll

Show First 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; CHECK-P9-NEXT: # %bb.8: # %if.then8 ; CHECK-P9-NEXT: # %bb.8: # %if.then8
; CHECK-P9-NEXT: mulli r3, r29, 13 ; CHECK-P9-NEXT: mulli r3, r29, 13
; CHECK-P9-NEXT: mulli r5, r30, 23 ; CHECK-P9-NEXT: mulli r5, r30, 23
; CHECK-P9-NEXT: extsw r4, r28 ; CHECK-P9-NEXT: extsw r4, r28
; CHECK-P9-NEXT: extsw r3, r3 ; CHECK-P9-NEXT: extsw r3, r3
; CHECK-P9-NEXT: extsw r5, r5 ; CHECK-P9-NEXT: extsw r5, r5
; CHECK-P9-NEXT: sub r3, r4, r3 ; CHECK-P9-NEXT: sub r3, r4, r3
; CHECK-P9-NEXT: sub r4, r5, r4 ; CHECK-P9-NEXT: sub r4, r5, r4
; CHECK-P9-NEXT: rldicl r3, r3, 1, 63 ; CHECK-P9-NEXT: srdi r3, r3, 63
; CHECK-P9-NEXT: rldicl r4, r4, 1, 63 ; CHECK-P9-NEXT: srdi r4, r4, 63
; CHECK-P9-NEXT: or r3, r3, r4 ; CHECK-P9-NEXT: or r3, r3, r4
; CHECK-P9-NEXT: b .LBB1_10 ; CHECK-P9-NEXT: b .LBB1_10
; CHECK-P9-NEXT: .LBB1_9: # %cleanup20 ; CHECK-P9-NEXT: .LBB1_9: # %cleanup20
; CHECK-P9-NEXT: li r3, 0 ; CHECK-P9-NEXT: li r3, 0
; CHECK-P9-NEXT: .LBB1_10: # %cleanup20 ; CHECK-P9-NEXT: .LBB1_10: # %cleanup20
; CHECK-P9-NEXT: addi r1, r1, 80 ; CHECK-P9-NEXT: addi r1, r1, 80
; CHECK-P9-NEXT: ld r0, 16(r1) ; CHECK-P9-NEXT: ld r0, 16(r1)
; CHECK-P9-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P9-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
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llvm/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll

Show First 20 Lines • Show All 154 Lines • ▼ Show 20 Lines
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: std 0, 16(1) ; CHECK-NEXT: std 0, 16(1)
; CHECK-NEXT: stdu 1, -32(1) ; CHECK-NEXT: stdu 1, -32(1)
; CHECK-NEXT: li 5, 2 ; CHECK-NEXT: li 5, 2
; CHECK-NEXT: bl memcmp ; CHECK-NEXT: bl memcmp
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: cntlzw 3, 3 ; CHECK-NEXT: cntlzw 3, 3
; CHECK-NEXT: rlwinm 3, 3, 27, 31, 31 ; CHECK-NEXT: extrwi 3, 3, 1, 26
; CHECK-NEXT: addi 1, 1, 32 ; CHECK-NEXT: addi 1, 1, 32
; CHECK-NEXT: ld 0, 16(1) ; CHECK-NEXT: ld 0, 16(1)
; CHECK-NEXT: mtlr 0 ; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%m = tail call signext i32 @memcmp(i8* %X, i8* %Y, i64 2) nobuiltin %m = tail call signext i32 @memcmp(i8* %X, i8* %Y, i64 2) nobuiltin
%c = icmp eq i32 %m, 0 %c = icmp eq i32 %m, 0
ret i1 %c ret i1 %c
} }

llvm/test/CodeGen/PowerPC/memcmp-mergeexpand.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-gnu-linux < %s | FileCheck %s -check-prefix=PPC64LE ; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-gnu-linux < %s | FileCheck %s -check-prefix=PPC64LE
; This tests interaction between MergeICmp and ExpandMemCmp. ; This tests interaction between MergeICmp and ExpandMemCmp.
%"struct.std::pair" = type { i32, i32 } %"struct.std::pair" = type { i32, i32 }
define zeroext i1 @opeq1( define zeroext i1 @opeq1(
; PPC64LE-LABEL: opeq1: ; PPC64LE-LABEL: opeq1:
; PPC64LE: # %bb.0: # %"entry+land.rhs.i" ; PPC64LE: # %bb.0: # %"entry+land.rhs.i"
; PPC64LE-NEXT: ldx 3, 0, 3 ; PPC64LE-NEXT: ldx 3, 0, 3
; PPC64LE-NEXT: ldx 4, 0, 4 ; PPC64LE-NEXT: ldx 4, 0, 4
; PPC64LE-NEXT: xor 3, 3, 4 ; PPC64LE-NEXT: xor 3, 3, 4
; PPC64LE-NEXT: cntlzd 3, 3 ; PPC64LE-NEXT: cntlzd 3, 3
; PPC64LE-NEXT: rldicl 3, 3, 58, 63 ; PPC64LE-NEXT: extrdi 3, 3, 1, 57
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%"struct.std::pair"* nocapture readonly dereferenceable(8) %a, %"struct.std::pair"* nocapture readonly dereferenceable(8) %a,
%"struct.std::pair"* nocapture readonly dereferenceable(8) %b) local_unnamed_addr #0 { %"struct.std::pair"* nocapture readonly dereferenceable(8) %b) local_unnamed_addr #0 {
entry: entry:
%first.i = getelementptr inbounds %"struct.std::pair", %"struct.std::pair"* %a, i64 0, i32 0 %first.i = getelementptr inbounds %"struct.std::pair", %"struct.std::pair"* %a, i64 0, i32 0
%0 = load i32, i32* %first.i, align 4 %0 = load i32, i32* %first.i, align 4
%first1.i = getelementptr inbounds %"struct.std::pair", %"struct.std::pair"* %b, i64 0, i32 0 %first1.i = getelementptr inbounds %"struct.std::pair", %"struct.std::pair"* %b, i64 0, i32 0
%1 = load i32, i32* %first1.i, align 4 %1 = load i32, i32* %first1.i, align 4
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llvm/test/CodeGen/PowerPC/memcmp.ll

Show All 22 Lines
define signext i32 @memcmp4(i32* nocapture readonly %buffer1, i32* nocapture readonly %buffer2) { define signext i32 @memcmp4(i32* nocapture readonly %buffer1, i32* nocapture readonly %buffer2) {
; CHECK-LABEL: memcmp4: ; CHECK-LABEL: memcmp4:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lwbrx 3, 0, 3 ; CHECK-NEXT: lwbrx 3, 0, 3
; CHECK-NEXT: lwbrx 4, 0, 4 ; CHECK-NEXT: lwbrx 4, 0, 4
; CHECK-NEXT: sub 5, 4, 3 ; CHECK-NEXT: sub 5, 4, 3
; CHECK-NEXT: sub 3, 3, 4 ; CHECK-NEXT: sub 3, 3, 4
; CHECK-NEXT: rldicl 4, 5, 1, 63 ; CHECK-NEXT: srdi 4, 5, 63
; CHECK-NEXT: rldicl 3, 3, 1, 63 ; CHECK-NEXT: srdi 3, 3, 63
; CHECK-NEXT: sub 3, 4, 3 ; CHECK-NEXT: sub 3, 4, 3
; CHECK-NEXT: extsw 3, 3 ; CHECK-NEXT: extsw 3, 3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%t0 = bitcast i32* %buffer1 to i8* %t0 = bitcast i32* %buffer1 to i8*
%t1 = bitcast i32* %buffer2 to i8* %t1 = bitcast i32* %buffer2 to i8*
%call = tail call signext i32 @memcmp(i8* %t0, i8* %t1, i64 4) %call = tail call signext i32 @memcmp(i8* %t0, i8* %t1, i64 4)
ret i32 %call ret i32 %call
} }
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llvm/test/CodeGen/PowerPC/optcmp.ll

Show First 20 Lines • Show All 198 Lines • ▼ Show 20 Lines
define i64 @foo2l(i64 %a, i64 %b, i64* nocapture %c) #0 { define i64 @foo2l(i64 %a, i64 %b, i64* nocapture %c) #0 {
; CHECK-LABEL: foo2l: ; CHECK-LABEL: foo2l:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sld 4, 3, 4 ; CHECK-NEXT: sld 4, 3, 4
; CHECK-NEXT: addi 3, 4, -1 ; CHECK-NEXT: addi 3, 4, -1
; CHECK-NEXT: std 4, 0(5) ; CHECK-NEXT: std 4, 0(5)
; CHECK-NEXT: nor 3, 3, 4 ; CHECK-NEXT: nor 3, 3, 4
; CHECK-NEXT: rldicl 3, 3, 1, 63 ; CHECK-NEXT: srdi 3, 3, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-NO-ISEL-LABEL: foo2l: ; CHECK-NO-ISEL-LABEL: foo2l:
; CHECK-NO-ISEL: # %bb.0: # %entry ; CHECK-NO-ISEL: # %bb.0: # %entry
; CHECK-NO-ISEL-NEXT: sld 4, 3, 4 ; CHECK-NO-ISEL-NEXT: sld 4, 3, 4
; CHECK-NO-ISEL-NEXT: addi 3, 4, -1 ; CHECK-NO-ISEL-NEXT: addi 3, 4, -1
; CHECK-NO-ISEL-NEXT: std 4, 0(5) ; CHECK-NO-ISEL-NEXT: std 4, 0(5)
; CHECK-NO-ISEL-NEXT: nor 3, 3, 4 ; CHECK-NO-ISEL-NEXT: nor 3, 3, 4
; CHECK-NO-ISEL-NEXT: rldicl 3, 3, 1, 63 ; CHECK-NO-ISEL-NEXT: srdi 3, 3, 63
; CHECK-NO-ISEL-NEXT: blr ; CHECK-NO-ISEL-NEXT: blr
entry: entry:
%shl = shl i64 %a, %b %shl = shl i64 %a, %b
store i64 %shl, i64* %c, align 8 store i64 %shl, i64* %c, align 8
%cmp = icmp sgt i64 %shl, 0 %cmp = icmp sgt i64 %shl, 0
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
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define signext i64 @fooct(i64 signext %a, i64 signext %b, i64* nocapture %c) #0 { define signext i64 @fooct(i64 signext %a, i64 signext %b, i64* nocapture %c) #0 {
; CHECK-LABEL: fooct: ; CHECK-LABEL: fooct:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lis 6, 21845 ; CHECK-NEXT: lis 6, 21845
; CHECK-NEXT: sub 7, 3, 4 ; CHECK-NEXT: sub 7, 3, 4
; CHECK-NEXT: ori 6, 6, 21845 ; CHECK-NEXT: ori 6, 6, 21845
; CHECK-NEXT: lis 9, 13107 ; CHECK-NEXT: lis 9, 13107
; CHECK-NEXT: rotldi 8, 7, 63 ; CHECK-NEXT: rotldi 8, 7, 63
; CHECK-NEXT: rldimi 6, 6, 32, 0 ; CHECK-NEXT: insrdi 6, 6, 32, 0
; CHECK-NEXT: and 6, 8, 6 ; CHECK-NEXT: and 6, 8, 6
; CHECK-NEXT: ori 8, 9, 13107 ; CHECK-NEXT: ori 8, 9, 13107
; CHECK-NEXT: sub 6, 7, 6 ; CHECK-NEXT: sub 6, 7, 6
; CHECK-NEXT: rldimi 8, 8, 32, 0 ; CHECK-NEXT: insrdi 8, 8, 32, 0
; CHECK-NEXT: lis 9, 257 ; CHECK-NEXT: lis 9, 257
; CHECK-NEXT: rotldi 7, 6, 62 ; CHECK-NEXT: rotldi 7, 6, 62
; CHECK-NEXT: and 6, 6, 8 ; CHECK-NEXT: and 6, 6, 8
; CHECK-NEXT: ori 9, 9, 257 ; CHECK-NEXT: ori 9, 9, 257
; CHECK-NEXT: and 7, 7, 8 ; CHECK-NEXT: and 7, 7, 8
; CHECK-NEXT: lis 8, 3855 ; CHECK-NEXT: lis 8, 3855
; CHECK-NEXT: add 6, 6, 7 ; CHECK-NEXT: add 6, 6, 7
; CHECK-NEXT: ori 7, 8, 3855 ; CHECK-NEXT: ori 7, 8, 3855
; CHECK-NEXT: rldicl 8, 6, 60, 4 ; CHECK-NEXT: srdi 8, 6, 4
; CHECK-NEXT: rldimi 7, 7, 32, 0 ; CHECK-NEXT: insrdi 7, 7, 32, 0
; CHECK-NEXT: rldimi 9, 9, 32, 0 ; CHECK-NEXT: insrdi 9, 9, 32, 0
; CHECK-NEXT: add 6, 6, 8 ; CHECK-NEXT: add 6, 6, 8
; CHECK-NEXT: and 6, 6, 7 ; CHECK-NEXT: and 6, 6, 7
; CHECK-NEXT: mulld 6, 6, 9 ; CHECK-NEXT: mulld 6, 6, 9
; CHECK-NEXT: rldicl. 6, 6, 8, 56 ; CHECK-NEXT: srdi. 6, 6, 56
; CHECK-NEXT: iselgt 3, 3, 4 ; CHECK-NEXT: iselgt 3, 3, 4
; CHECK-NEXT: std 6, 0(5) ; CHECK-NEXT: std 6, 0(5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-NO-ISEL-LABEL: fooct: ; CHECK-NO-ISEL-LABEL: fooct:
; CHECK-NO-ISEL: # %bb.0: # %entry ; CHECK-NO-ISEL: # %bb.0: # %entry
; CHECK-NO-ISEL-NEXT: lis 6, 21845 ; CHECK-NO-ISEL-NEXT: lis 6, 21845
; CHECK-NO-ISEL-NEXT: sub 7, 3, 4 ; CHECK-NO-ISEL-NEXT: sub 7, 3, 4
; CHECK-NO-ISEL-NEXT: ori 6, 6, 21845 ; CHECK-NO-ISEL-NEXT: ori 6, 6, 21845
; CHECK-NO-ISEL-NEXT: lis 9, 13107 ; CHECK-NO-ISEL-NEXT: lis 9, 13107
; CHECK-NO-ISEL-NEXT: rotldi 8, 7, 63 ; CHECK-NO-ISEL-NEXT: rotldi 8, 7, 63
; CHECK-NO-ISEL-NEXT: rldimi 6, 6, 32, 0 ; CHECK-NO-ISEL-NEXT: insrdi 6, 6, 32, 0
; CHECK-NO-ISEL-NEXT: and 6, 8, 6 ; CHECK-NO-ISEL-NEXT: and 6, 8, 6
; CHECK-NO-ISEL-NEXT: ori 8, 9, 13107 ; CHECK-NO-ISEL-NEXT: ori 8, 9, 13107
; CHECK-NO-ISEL-NEXT: sub 6, 7, 6 ; CHECK-NO-ISEL-NEXT: sub 6, 7, 6
; CHECK-NO-ISEL-NEXT: rldimi 8, 8, 32, 0 ; CHECK-NO-ISEL-NEXT: insrdi 8, 8, 32, 0
; CHECK-NO-ISEL-NEXT: lis 9, 257 ; CHECK-NO-ISEL-NEXT: lis 9, 257
; CHECK-NO-ISEL-NEXT: rotldi 7, 6, 62 ; CHECK-NO-ISEL-NEXT: rotldi 7, 6, 62
; CHECK-NO-ISEL-NEXT: and 6, 6, 8 ; CHECK-NO-ISEL-NEXT: and 6, 6, 8
; CHECK-NO-ISEL-NEXT: ori 9, 9, 257 ; CHECK-NO-ISEL-NEXT: ori 9, 9, 257
; CHECK-NO-ISEL-NEXT: and 7, 7, 8 ; CHECK-NO-ISEL-NEXT: and 7, 7, 8
; CHECK-NO-ISEL-NEXT: lis 8, 3855 ; CHECK-NO-ISEL-NEXT: lis 8, 3855
; CHECK-NO-ISEL-NEXT: add 6, 6, 7 ; CHECK-NO-ISEL-NEXT: add 6, 6, 7
; CHECK-NO-ISEL-NEXT: ori 7, 8, 3855 ; CHECK-NO-ISEL-NEXT: ori 7, 8, 3855
; CHECK-NO-ISEL-NEXT: rldicl 8, 6, 60, 4 ; CHECK-NO-ISEL-NEXT: srdi 8, 6, 4
; CHECK-NO-ISEL-NEXT: rldimi 7, 7, 32, 0 ; CHECK-NO-ISEL-NEXT: insrdi 7, 7, 32, 0
; CHECK-NO-ISEL-NEXT: rldimi 9, 9, 32, 0 ; CHECK-NO-ISEL-NEXT: insrdi 9, 9, 32, 0
; CHECK-NO-ISEL-NEXT: add 6, 6, 8 ; CHECK-NO-ISEL-NEXT: add 6, 6, 8
; CHECK-NO-ISEL-NEXT: and 6, 6, 7 ; CHECK-NO-ISEL-NEXT: and 6, 6, 7
; CHECK-NO-ISEL-NEXT: mulld 6, 6, 9 ; CHECK-NO-ISEL-NEXT: mulld 6, 6, 9
; CHECK-NO-ISEL-NEXT: rldicl. 6, 6, 8, 56 ; CHECK-NO-ISEL-NEXT: srdi. 6, 6, 56
; CHECK-NO-ISEL-NEXT: bc 12, 1, .LBB10_2 ; CHECK-NO-ISEL-NEXT: bc 12, 1, .LBB10_2
; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry ; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
; CHECK-NO-ISEL-NEXT: ori 3, 4, 0 ; CHECK-NO-ISEL-NEXT: ori 3, 4, 0
; CHECK-NO-ISEL-NEXT: b .LBB10_2 ; CHECK-NO-ISEL-NEXT: b .LBB10_2
; CHECK-NO-ISEL-NEXT: .LBB10_2: # %entry ; CHECK-NO-ISEL-NEXT: .LBB10_2: # %entry
; CHECK-NO-ISEL-NEXT: std 6, 0(5) ; CHECK-NO-ISEL-NEXT: std 6, 0(5)
; CHECK-NO-ISEL-NEXT: blr ; CHECK-NO-ISEL-NEXT: blr
entry: entry:
%sub = sub nsw i64 %a, %b %sub = sub nsw i64 %a, %b
%subc = call i64 @llvm.ctpop.i64(i64 %sub) %subc = call i64 @llvm.ctpop.i64(i64 %sub)
store i64 %subc, i64* %c, align 4 store i64 %subc, i64* %c, align 4
%cmp = icmp sgt i64 %subc, 0 %cmp = icmp sgt i64 %subc, 0
%cond = select i1 %cmp, i64 %a, i64 %b %cond = select i1 %cmp, i64 %a, i64 %b
ret i64 %cond ret i64 %cond
} }

llvm/test/CodeGen/PowerPC/ori_imm32.ll

Show All 11 Linesentry:
%or = or i64 %a, 4294967295 %or = or i64 %a, 4294967295
ret i64 %or ret i64 %or
} }
define i64 @ori_test_b(i64 %a) { define i64 @ori_test_b(i64 %a) {
; CHECK-LABEL: ori_test_b: ; CHECK-LABEL: ori_test_b:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: li 4, -1 ; CHECK-NEXT: li 4, -1
; CHECK-NEXT: rldimi 3, 4, 32, 31 ; CHECK-NEXT: insrdi 3, 4, 1, 31
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%or = or i64 %a, 4294967296 %or = or i64 %a, 4294967296
ret i64 %or ret i64 %or
} }
define i64 @ori_test_c(i64 %a) { define i64 @ori_test_c(i64 %a) {
; CHECK-LABEL: ori_test_c: ; CHECK-LABEL: ori_test_c:
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llvm/test/CodeGen/PowerPC/ori_imm64.ll

Show All 10 Linesentry:
%or = or i64 %a, 18446744073709551615 ; 0xffffffffffffffff %or = or i64 %a, 18446744073709551615 ; 0xffffffffffffffff
ret i64 %or ret i64 %or
} }
define i64 @ori_test_2(i64 %a) { define i64 @ori_test_2(i64 %a) {
; CHECK-LABEL: ori_test_2: ; CHECK-LABEL: ori_test_2:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: li 4, -1 ; CHECK-NEXT: li 4, -1
; CHECK-NEXT: rldimi 3, 4, 29, 15 ; CHECK-NEXT: insrdi 3, 4, 20, 15
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%or = or i64 %a, 562949416550400 ; 0x1ffffe0000000 %or = or i64 %a, 562949416550400 ; 0x1ffffe0000000
ret i64 %or ret i64 %or
} }
define i64 @ori_test_3(i64 %a) { define i64 @ori_test_3(i64 %a) {
; CHECK-LABEL: ori_test_3: ; CHECK-LABEL: ori_test_3:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: li 4, -1 ; CHECK-NEXT: li 4, -1
; CHECK-NEXT: rldimi 3, 4, 3, 28 ; CHECK-NEXT: insrdi 3, 4, 33, 28
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%or = or i64 %a, 68719476728 ; 0xffffffff8 %or = or i64 %a, 68719476728 ; 0xffffffff8
ret i64 %or ret i64 %or
} }
define i64 @ori_test_4(i64 %a) { define i64 @ori_test_4(i64 %a) {
; CHECK-LABEL: ori_test_4: ; CHECK-LABEL: ori_test_4:
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llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll

Show First 20 Lines • Show All 98 Lines • ▼ Show 20 Lines
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i8 @getsc0(<16 x i8> %vsc) { define signext i8 @getsc0(<16 x i8> %vsc) {
entry: entry:
%vecext = extractelement <16 x i8> %vsc, i32 0 %vecext = extractelement <16 x i8> %vsc, i32 0
ret i8 %vecext ret i8 %vecext
; CHECK-LABEL: @getsc0 ; CHECK-LABEL: @getsc0
; CHECK: mfvsrd r3, v2 ; CHECK: mfvsrd r3, v2
; CHECK: rldicl r3, r3, 8, 56 ; CHECK: srdi r3, r3, 56
; CHECK: extsb r3, r3 ; CHECK: extsb r3, r3
; CHECK-LE-LABEL: @getsc0 ; CHECK-LE-LABEL: @getsc0
; CHECK-LE: mffprd r3, f0 ; CHECK-LE: mffprd r3, f0
; CHECK-LE: clrldi r3, r3, 56 ; CHECK-LE: clrldi r3, r3, 56
; CHECK-LE: extsb r3, r3 ; CHECK-LE: extsb r3, r3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i8 @getsc1(<16 x i8> %vsc) { define signext i8 @getsc1(<16 x i8> %vsc) {
entry: entry:
%vecext = extractelement <16 x i8> %vsc, i32 1 %vecext = extractelement <16 x i8> %vsc, i32 1
ret i8 %vecext ret i8 %vecext
; CHECK-LABEL: @getsc1 ; CHECK-LABEL: @getsc1
; CHECK: mfvsrd r3, v2 ; CHECK: mfvsrd r3, v2
; CHECK: rldicl r3, r3, 16, 56 ; CHECK: extrdi r3, r3, 8, 8
; CHECK: extsb r3, r3 ; CHECK: extsb r3, r3
; CHECK-LE-LABEL: @getsc1 ; CHECK-LE-LABEL: @getsc1
; CHECK-LE: mffprd r3, f0 ; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 56, 56 ; CHECK-LE: extrdi r3, r3, 8, 48
; CHECK-LE: extsb r3, r3 ; CHECK-LE: extsb r3, r3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i8 @getsc2(<16 x i8> %vsc) { define signext i8 @getsc2(<16 x i8> %vsc) {
entry: entry:
%vecext = extractelement <16 x i8> %vsc, i32 2 %vecext = extractelement <16 x i8> %vsc, i32 2
ret i8 %vecext ret i8 %vecext
; CHECK-LABEL: @getsc2 ; CHECK-LABEL: @getsc2
; CHECK: mfvsrd r3, v2 ; CHECK: mfvsrd r3, v2
; CHECK: rldicl r3, r3, 24, 56 ; CHECK: extrdi r3, r3, 8, 16
; CHECK: extsb r3, r3 ; CHECK: extsb r3, r3
; CHECK-LE-LABEL: @getsc2 ; CHECK-LE-LABEL: @getsc2
; CHECK-LE: mffprd r3, f0 ; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 48, 56 ; CHECK-LE: extrdi r3, r3, 8, 40
; CHECK-LE: extsb r3, r3 ; CHECK-LE: extsb r3, r3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i8 @getsc3(<16 x i8> %vsc) { define signext i8 @getsc3(<16 x i8> %vsc) {
entry: entry:
%vecext = extractelement <16 x i8> %vsc, i32 3 %vecext = extractelement <16 x i8> %vsc, i32 3
ret i8 %vecext ret i8 %vecext
; CHECK-LABEL: @getsc3 ; CHECK-LABEL: @getsc3
; CHECK: mfvsrd r3, v2 ; CHECK: mfvsrd r3, v2
; CHECK: rldicl r3, r3, 32, 56 ; CHECK: extrdi r3, r3, 8, 24
; CHECK: extsb r3, r3 ; CHECK: extsb r3, r3
; CHECK-LE-LABEL: @getsc3 ; CHECK-LE-LABEL: @getsc3
; CHECK-LE: mffprd r3, f0 ; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 40, 56 ; CHECK-LE: extrdi r3, r3, 8, 32
; CHECK-LE: extsb r3, r3 ; CHECK-LE: extsb r3, r3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i8 @getsc4(<16 x i8> %vsc) { define signext i8 @getsc4(<16 x i8> %vsc) {
entry: entry:
%vecext = extractelement <16 x i8> %vsc, i32 4 %vecext = extractelement <16 x i8> %vsc, i32 4
ret i8 %vecext ret i8 %vecext
; CHECK-LABEL: @getsc4 ; CHECK-LABEL: @getsc4
; CHECK: mfvsrd r3, v2 ; CHECK: mfvsrd r3, v2
; CHECK: rldicl r3, r3, 40, 56 ; CHECK: extrdi r3, r3, 8, 32
; CHECK: extsb r3, r3 ; CHECK: extsb r3, r3
; CHECK-LE-LABEL: @getsc4 ; CHECK-LE-LABEL: @getsc4
; CHECK-LE: mffprd r3, f0 ; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 32, 56 ; CHECK-LE: extrdi r3, r3, 8, 24
; CHECK-LE: extsb r3, r3 ; CHECK-LE: extsb r3, r3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i8 @getsc5(<16 x i8> %vsc) { define signext i8 @getsc5(<16 x i8> %vsc) {
entry: entry:
%vecext = extractelement <16 x i8> %vsc, i32 5 %vecext = extractelement <16 x i8> %vsc, i32 5
ret i8 %vecext ret i8 %vecext
; CHECK-LABEL: @getsc5 ; CHECK-LABEL: @getsc5
; CHECK: mfvsrd r3, v2 ; CHECK: mfvsrd r3, v2
; CHECK: rldicl r3, r3, 48, 56 ; CHECK: extrdi r3, r3, 8, 40
; CHECK: extsb r3, r3 ; CHECK: extsb r3, r3
; CHECK-LE-LABEL: @getsc5 ; CHECK-LE-LABEL: @getsc5
; CHECK-LE: mffprd r3, f0 ; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 24, 56 ; CHECK-LE: extrdi r3, r3, 8, 16
; CHECK-LE: extsb r3, r3 ; CHECK-LE: extsb r3, r3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i8 @getsc6(<16 x i8> %vsc) { define signext i8 @getsc6(<16 x i8> %vsc) {
entry: entry:
%vecext = extractelement <16 x i8> %vsc, i32 6 %vecext = extractelement <16 x i8> %vsc, i32 6
ret i8 %vecext ret i8 %vecext
; CHECK-LABEL: @getsc6 ; CHECK-LABEL: @getsc6
; CHECK: mfvsrd r3, v2 ; CHECK: mfvsrd r3, v2
; CHECK: rldicl r3, r3, 56, 56 ; CHECK: extrdi r3, r3, 8, 48
; CHECK: extsb r3, r3 ; CHECK: extsb r3, r3
; CHECK-LE-LABEL: @getsc6 ; CHECK-LE-LABEL: @getsc6
; CHECK-LE: mffprd r3, f0 ; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 16, 56 ; CHECK-LE: extrdi r3, r3, 8, 8
; CHECK-LE: extsb r3, r3 ; CHECK-LE: extsb r3, r3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i8 @getsc7(<16 x i8> %vsc) { define signext i8 @getsc7(<16 x i8> %vsc) {
entry: entry:
%vecext = extractelement <16 x i8> %vsc, i32 7 %vecext = extractelement <16 x i8> %vsc, i32 7
ret i8 %vecext ret i8 %vecext
; CHECK-LABEL: @getsc7 ; CHECK-LABEL: @getsc7
; CHECK: mfvsrd r3, v2 ; CHECK: mfvsrd r3, v2
; CHECK: clrldi r3, r3, 56 ; CHECK: clrldi r3, r3, 56
; CHECK: extsb r3, r3 ; CHECK: extsb r3, r3
; CHECK-LE-LABEL: @getsc7 ; CHECK-LE-LABEL: @getsc7
; CHECK-LE: mffprd r3, f0 ; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 8, 56 ; CHECK-LE: srdi r3, r3, 56
; CHECK-LE: extsb r3, r3 ; CHECK-LE: extsb r3, r3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i8 @getsc8(<16 x i8> %vsc) { define signext i8 @getsc8(<16 x i8> %vsc) {
entry: entry:
%vecext = extractelement <16 x i8> %vsc, i32 8 %vecext = extractelement <16 x i8> %vsc, i32 8
ret i8 %vecext ret i8 %vecext
; CHECK-LABEL: @getsc8 ; CHECK-LABEL: @getsc8
; CHECK: mffprd r3, f0 ; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 8, 56 ; CHECK: srdi r3, r3, 56
; CHECK: extsb r3, r3 ; CHECK: extsb r3, r3
; CHECK-LE-LABEL: @getsc8 ; CHECK-LE-LABEL: @getsc8
; CHECK-LE: mfvsrd r3, v2 ; CHECK-LE: mfvsrd r3, v2
; CHECK-LE: clrldi r3, r3, 56 ; CHECK-LE: clrldi r3, r3, 56
; CHECK-LE: extsb r3, r3 ; CHECK-LE: extsb r3, r3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i8 @getsc9(<16 x i8> %vsc) { define signext i8 @getsc9(<16 x i8> %vsc) {
entry: entry:
%vecext = extractelement <16 x i8> %vsc, i32 9 %vecext = extractelement <16 x i8> %vsc, i32 9
ret i8 %vecext ret i8 %vecext
; CHECK-LABEL: @getsc9 ; CHECK-LABEL: @getsc9
; CHECK: mffprd r3, f0 ; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 16, 56 ; CHECK: extrdi r3, r3, 8, 8
; CHECK: extsb r3, r3 ; CHECK: extsb r3, r3
; CHECK-LE-LABEL: @getsc9 ; CHECK-LE-LABEL: @getsc9
; CHECK-LE: mfvsrd r3, v2 ; CHECK-LE: mfvsrd r3, v2
; CHECK-LE: rldicl r3, r3, 56, 56 ; CHECK-LE: extrdi r3, r3, 8, 48
; CHECK-LE: extsb r3, r3 ; CHECK-LE: extsb r3, r3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i8 @getsc10(<16 x i8> %vsc) { define signext i8 @getsc10(<16 x i8> %vsc) {
entry: entry:
%vecext = extractelement <16 x i8> %vsc, i32 10 %vecext = extractelement <16 x i8> %vsc, i32 10
ret i8 %vecext ret i8 %vecext
; CHECK-LABEL: @getsc10 ; CHECK-LABEL: @getsc10
; CHECK: mffprd r3, f0 ; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 24, 56 ; CHECK: extrdi r3, r3, 8, 16
; CHECK: extsb r3, r3 ; CHECK: extsb r3, r3
; CHECK-LE-LABEL: @getsc10 ; CHECK-LE-LABEL: @getsc10
; CHECK-LE: mfvsrd r3, v2 ; CHECK-LE: mfvsrd r3, v2
; CHECK-LE: rldicl r3, r3, 48, 56 ; CHECK-LE: extrdi r3, r3, 8, 40
; CHECK-LE: extsb r3, r3 ; CHECK-LE: extsb r3, r3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i8 @getsc11(<16 x i8> %vsc) { define signext i8 @getsc11(<16 x i8> %vsc) {
entry: entry:
%vecext = extractelement <16 x i8> %vsc, i32 11 %vecext = extractelement <16 x i8> %vsc, i32 11
ret i8 %vecext ret i8 %vecext
; CHECK-LABEL: @getsc11 ; CHECK-LABEL: @getsc11
; CHECK: mffprd r3, f0 ; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 32, 56 ; CHECK: extrdi r3, r3, 8, 24
; CHECK: extsb r3, r3 ; CHECK: extsb r3, r3
; CHECK-LE-LABEL: @getsc11 ; CHECK-LE-LABEL: @getsc11
; CHECK-LE: mfvsrd r3, v2 ; CHECK-LE: mfvsrd r3, v2
; CHECK-LE: rldicl r3, r3, 40, 56 ; CHECK-LE: extrdi r3, r3, 8, 32
; CHECK-LE: extsb r3, r3 ; CHECK-LE: extsb r3, r3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i8 @getsc12(<16 x i8> %vsc) { define signext i8 @getsc12(<16 x i8> %vsc) {
entry: entry:
%vecext = extractelement <16 x i8> %vsc, i32 12 %vecext = extractelement <16 x i8> %vsc, i32 12
ret i8 %vecext ret i8 %vecext
; CHECK-LABEL: @getsc12 ; CHECK-LABEL: @getsc12
; CHECK: mffprd r3, f0 ; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 40, 56 ; CHECK: extrdi r3, r3, 8, 32
; CHECK: extsb r3, r3 ; CHECK: extsb r3, r3
; CHECK-LE-LABEL: @getsc12 ; CHECK-LE-LABEL: @getsc12
; CHECK-LE: mfvsrd r3, v2 ; CHECK-LE: mfvsrd r3, v2
; CHECK-LE: rldicl r3, r3, 32, 56 ; CHECK-LE: extrdi r3, r3, 8, 24
; CHECK-LE: extsb r3, r3 ; CHECK-LE: extsb r3, r3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i8 @getsc13(<16 x i8> %vsc) { define signext i8 @getsc13(<16 x i8> %vsc) {
entry: entry:
%vecext = extractelement <16 x i8> %vsc, i32 13 %vecext = extractelement <16 x i8> %vsc, i32 13
ret i8 %vecext ret i8 %vecext
; CHECK-LABEL: @getsc13 ; CHECK-LABEL: @getsc13
; CHECK: mffprd r3, f0 ; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 48, 56 ; CHECK: extrdi r3, r3, 8, 40
; CHECK: extsb r3, r3 ; CHECK: extsb r3, r3
; CHECK-LE-LABEL: @getsc13 ; CHECK-LE-LABEL: @getsc13
; CHECK-LE: mfvsrd r3, v2 ; CHECK-LE: mfvsrd r3, v2
; CHECK-LE: rldicl r3, r3, 24, 56 ; CHECK-LE: extrdi r3, r3, 8, 16
; CHECK-LE: extsb r3, r3 ; CHECK-LE: extsb r3, r3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i8 @getsc14(<16 x i8> %vsc) { define signext i8 @getsc14(<16 x i8> %vsc) {
entry: entry:
%vecext = extractelement <16 x i8> %vsc, i32 14 %vecext = extractelement <16 x i8> %vsc, i32 14
ret i8 %vecext ret i8 %vecext
; CHECK-LABEL: @getsc14 ; CHECK-LABEL: @getsc14
; CHECK: mffprd r3, f0 ; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 56, 56 ; CHECK: extrdi r3, r3, 8, 48
; CHECK: extsb r3, r3 ; CHECK: extsb r3, r3
; CHECK-LE-LABEL: @getsc14 ; CHECK-LE-LABEL: @getsc14
; CHECK-LE: mfvsrd r3, v2 ; CHECK-LE: mfvsrd r3, v2
; CHECK-LE: rldicl r3, r3, 16, 56 ; CHECK-LE: extrdi r3, r3, 8, 8
; CHECK-LE: extsb r3, r3 ; CHECK-LE: extsb r3, r3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i8 @getsc15(<16 x i8> %vsc) { define signext i8 @getsc15(<16 x i8> %vsc) {
entry: entry:
%vecext = extractelement <16 x i8> %vsc, i32 15 %vecext = extractelement <16 x i8> %vsc, i32 15
ret i8 %vecext ret i8 %vecext
; CHECK-LABEL: @getsc15 ; CHECK-LABEL: @getsc15
; CHECK: mffprd r3, f0 ; CHECK: mffprd r3, f0
; CHECK: clrldi r3, r3, 56 ; CHECK: clrldi r3, r3, 56
; CHECK: extsb r3, r3 ; CHECK: extsb r3, r3
; CHECK-LE-LABEL: @getsc15 ; CHECK-LE-LABEL: @getsc15
; CHECK-LE: mfvsrd r3, v2 ; CHECK-LE: mfvsrd r3, v2
; CHECK-LE: rldicl r3, r3, 8, 56 ; CHECK-LE: srdi r3, r3, 56
; CHECK-LE: extsb r3, r3 ; CHECK-LE: extsb r3, r3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i8 @getuc0(<16 x i8> %vuc) { define zeroext i8 @getuc0(<16 x i8> %vuc) {
entry: entry:
%vecext = extractelement <16 x i8> %vuc, i32 0 %vecext = extractelement <16 x i8> %vuc, i32 0
ret i8 %vecext ret i8 %vecext
; CHECK-LABEL: @getuc0 ; CHECK-LABEL: @getuc0
; CHECK: mfvsrd r3, v2 ; CHECK: mfvsrd r3, v2
; CHECK: rldicl r3, r3, 8, 56 ; CHECK: srdi r3, r3, 56
; CHECK-LE-LABEL: @getuc0 ; CHECK-LE-LABEL: @getuc0
; CHECK-LE: mffprd r3, f0 ; CHECK-LE: mffprd r3, f0
; CHECK-LE: clrldi r3, r3, 56 ; CHECK-LE: clrldi r3, r3, 56
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i8 @getuc1(<16 x i8> %vuc) { define zeroext i8 @getuc1(<16 x i8> %vuc) {
entry: entry:
%vecext = extractelement <16 x i8> %vuc, i32 1 %vecext = extractelement <16 x i8> %vuc, i32 1
ret i8 %vecext ret i8 %vecext
; CHECK-LABEL: @getuc1 ; CHECK-LABEL: @getuc1
; CHECK: mfvsrd r3, v2 ; CHECK: mfvsrd r3, v2
; CHECK: rldicl r3, r3, 16, 56 ; CHECK: extrdi r3, r3, 8, 8
; CHECK-LE-LABEL: @getuc1 ; CHECK-LE-LABEL: @getuc1
; CHECK-LE: mffprd r3, f0 ; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 56, 56 ; CHECK-LE: extrdi r3, r3, 8, 48
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i8 @getuc2(<16 x i8> %vuc) { define zeroext i8 @getuc2(<16 x i8> %vuc) {
entry: entry:
%vecext = extractelement <16 x i8> %vuc, i32 2 %vecext = extractelement <16 x i8> %vuc, i32 2
ret i8 %vecext ret i8 %vecext
; CHECK-LABEL: @getuc2 ; CHECK-LABEL: @getuc2
; CHECK: mfvsrd r3, v2 ; CHECK: mfvsrd r3, v2
; CHECK: rldicl r3, r3, 24, 56 ; CHECK: extrdi r3, r3, 8, 16
; CHECK-LE-LABEL: @getuc2 ; CHECK-LE-LABEL: @getuc2
; CHECK-LE: mffprd r3, f0 ; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 48, 56 ; CHECK-LE: extrdi r3, r3, 8, 40
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i8 @getuc3(<16 x i8> %vuc) { define zeroext i8 @getuc3(<16 x i8> %vuc) {
entry: entry:
%vecext = extractelement <16 x i8> %vuc, i32 3 %vecext = extractelement <16 x i8> %vuc, i32 3
ret i8 %vecext ret i8 %vecext
; CHECK-LABEL: @getuc3 ; CHECK-LABEL: @getuc3
; CHECK: mfvsrd r3, v2 ; CHECK: mfvsrd r3, v2
; CHECK: rldicl r3, r3, 32, 56 ; CHECK: extrdi r3, r3, 8, 24
; CHECK-LE-LABEL: @getuc3 ; CHECK-LE-LABEL: @getuc3
; CHECK-LE: mffprd r3, f0 ; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 40, 56 ; CHECK-LE: extrdi r3, r3, 8, 32
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i8 @getuc4(<16 x i8> %vuc) { define zeroext i8 @getuc4(<16 x i8> %vuc) {
entry: entry:
%vecext = extractelement <16 x i8> %vuc, i32 4 %vecext = extractelement <16 x i8> %vuc, i32 4
ret i8 %vecext ret i8 %vecext
; CHECK-LABEL: @getuc4 ; CHECK-LABEL: @getuc4
; CHECK: mfvsrd r3, v2 ; CHECK: mfvsrd r3, v2
; CHECK: rldicl r3, r3, 40, 56 ; CHECK: extrdi r3, r3, 8, 32
; CHECK-LE-LABEL: @getuc4 ; CHECK-LE-LABEL: @getuc4
; CHECK-LE: mffprd r3, f0 ; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 32, 56 ; CHECK-LE: extrdi r3, r3, 8, 24
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i8 @getuc5(<16 x i8> %vuc) { define zeroext i8 @getuc5(<16 x i8> %vuc) {
entry: entry:
%vecext = extractelement <16 x i8> %vuc, i32 5 %vecext = extractelement <16 x i8> %vuc, i32 5
ret i8 %vecext ret i8 %vecext
; CHECK-LABEL: @getuc5 ; CHECK-LABEL: @getuc5
; CHECK: mfvsrd r3, v2 ; CHECK: mfvsrd r3, v2
; CHECK: rldicl r3, r3, 48, 56 ; CHECK: extrdi r3, r3, 8, 40
; CHECK-LE-LABEL: @getuc5 ; CHECK-LE-LABEL: @getuc5
; CHECK-LE: mffprd r3, f0 ; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 24, 56 ; CHECK-LE: extrdi r3, r3, 8, 16
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i8 @getuc6(<16 x i8> %vuc) { define zeroext i8 @getuc6(<16 x i8> %vuc) {
entry: entry:
%vecext = extractelement <16 x i8> %vuc, i32 6 %vecext = extractelement <16 x i8> %vuc, i32 6
ret i8 %vecext ret i8 %vecext
; CHECK-LABEL: @getuc6 ; CHECK-LABEL: @getuc6
; CHECK: mfvsrd r3, v2 ; CHECK: mfvsrd r3, v2
; CHECK: rldicl r3, r3, 56, 56 ; CHECK: extrdi r3, r3, 8, 48
; CHECK-LE-LABEL: @getuc6 ; CHECK-LE-LABEL: @getuc6
; CHECK-LE: mffprd r3, f0 ; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 16, 56 ; CHECK-LE: extrdi r3, r3, 8, 8
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i8 @getuc7(<16 x i8> %vuc) { define zeroext i8 @getuc7(<16 x i8> %vuc) {
entry: entry:
%vecext = extractelement <16 x i8> %vuc, i32 7 %vecext = extractelement <16 x i8> %vuc, i32 7
ret i8 %vecext ret i8 %vecext
; CHECK-LABEL: @getuc7 ; CHECK-LABEL: @getuc7
; CHECK: mfvsrd r3, v2 ; CHECK: mfvsrd r3, v2
; CHECK: clrldi r3, r3, 56 ; CHECK: clrldi r3, r3, 56
; CHECK-LE-LABEL: @getuc7 ; CHECK-LE-LABEL: @getuc7
; CHECK-LE: mffprd r3, f0 ; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 8, 56 ; CHECK-LE: srdi r3, r3, 56
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i8 @getuc8(<16 x i8> %vuc) { define zeroext i8 @getuc8(<16 x i8> %vuc) {
entry: entry:
%vecext = extractelement <16 x i8> %vuc, i32 8 %vecext = extractelement <16 x i8> %vuc, i32 8
ret i8 %vecext ret i8 %vecext
; CHECK-LABEL: @getuc8 ; CHECK-LABEL: @getuc8
; CHECK: mffprd r3, f0 ; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 8, 56 ; CHECK: srdi r3, r3, 56
; CHECK-LE-LABEL: @getuc8 ; CHECK-LE-LABEL: @getuc8
; CHECK-LE: mfvsrd r3, v2 ; CHECK-LE: mfvsrd r3, v2
; CHECK-LE: clrldi r3, r3, 56 ; CHECK-LE: clrldi r3, r3, 56
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i8 @getuc9(<16 x i8> %vuc) { define zeroext i8 @getuc9(<16 x i8> %vuc) {
entry: entry:
%vecext = extractelement <16 x i8> %vuc, i32 9 %vecext = extractelement <16 x i8> %vuc, i32 9
ret i8 %vecext ret i8 %vecext
; CHECK-LABEL: @getuc9 ; CHECK-LABEL: @getuc9
; CHECK: mffprd r3, f0 ; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 16, 56 ; CHECK: extrdi r3, r3, 8, 8
; CHECK-LE-LABEL: @getuc9 ; CHECK-LE-LABEL: @getuc9
; CHECK-LE: mfvsrd r3, v2 ; CHECK-LE: mfvsrd r3, v2
; CHECK-LE: rldicl r3, r3, 56, 56 ; CHECK-LE: extrdi r3, r3, 8, 48
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i8 @getuc10(<16 x i8> %vuc) { define zeroext i8 @getuc10(<16 x i8> %vuc) {
entry: entry:
%vecext = extractelement <16 x i8> %vuc, i32 10 %vecext = extractelement <16 x i8> %vuc, i32 10
ret i8 %vecext ret i8 %vecext
; CHECK-LABEL: @getuc10 ; CHECK-LABEL: @getuc10
; CHECK: mffprd r3, f0 ; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 24, 56 ; CHECK: extrdi r3, r3, 8, 16
; CHECK-LE-LABEL: @getuc10 ; CHECK-LE-LABEL: @getuc10
; CHECK-LE: mfvsrd r3, v2 ; CHECK-LE: mfvsrd r3, v2
; CHECK-LE: rldicl r3, r3, 48, 56 ; CHECK-LE: extrdi r3, r3, 8, 40
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i8 @getuc11(<16 x i8> %vuc) { define zeroext i8 @getuc11(<16 x i8> %vuc) {
entry: entry:
%vecext = extractelement <16 x i8> %vuc, i32 11 %vecext = extractelement <16 x i8> %vuc, i32 11
ret i8 %vecext ret i8 %vecext
; CHECK-LABEL: @getuc11 ; CHECK-LABEL: @getuc11
; CHECK: mffprd r3, f0 ; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 32, 56 ; CHECK: extrdi r3, r3, 8, 24
; CHECK-LE-LABEL: @getuc11 ; CHECK-LE-LABEL: @getuc11
; CHECK-LE: mfvsrd r3, v2 ; CHECK-LE: mfvsrd r3, v2
; CHECK-LE: rldicl r3, r3, 40, 56 ; CHECK-LE: extrdi r3, r3, 8, 32
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i8 @getuc12(<16 x i8> %vuc) { define zeroext i8 @getuc12(<16 x i8> %vuc) {
entry: entry:
%vecext = extractelement <16 x i8> %vuc, i32 12 %vecext = extractelement <16 x i8> %vuc, i32 12
ret i8 %vecext ret i8 %vecext
; CHECK-LABEL: @getuc12 ; CHECK-LABEL: @getuc12
; CHECK: mffprd r3, f0 ; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 40, 56 ; CHECK: extrdi r3, r3, 8, 32
; CHECK-LE-LABEL: @getuc12 ; CHECK-LE-LABEL: @getuc12
; CHECK-LE: mfvsrd r3, v2 ; CHECK-LE: mfvsrd r3, v2
; CHECK-LE: rldicl r3, r3, 32, 56 ; CHECK-LE: extrdi r3, r3, 8, 24
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i8 @getuc13(<16 x i8> %vuc) { define zeroext i8 @getuc13(<16 x i8> %vuc) {
entry: entry:
%vecext = extractelement <16 x i8> %vuc, i32 13 %vecext = extractelement <16 x i8> %vuc, i32 13
ret i8 %vecext ret i8 %vecext
; CHECK-LABEL: @getuc13 ; CHECK-LABEL: @getuc13
; CHECK: mffprd r3, f0 ; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 48, 56 ; CHECK: extrdi r3, r3, 8, 40
; CHECK-LE-LABEL: @getuc13 ; CHECK-LE-LABEL: @getuc13
; CHECK-LE: mfvsrd r3, v2 ; CHECK-LE: mfvsrd r3, v2
; CHECK-LE: rldicl r3, r3, 24, 56 ; CHECK-LE: extrdi r3, r3, 8, 16
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i8 @getuc14(<16 x i8> %vuc) { define zeroext i8 @getuc14(<16 x i8> %vuc) {
entry: entry:
%vecext = extractelement <16 x i8> %vuc, i32 14 %vecext = extractelement <16 x i8> %vuc, i32 14
ret i8 %vecext ret i8 %vecext
; CHECK-LABEL: @getuc14 ; CHECK-LABEL: @getuc14
; CHECK: mffprd r3, f0 ; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 56, 56 ; CHECK: extrdi r3, r3, 8, 48
; CHECK-LE-LABEL: @getuc14 ; CHECK-LE-LABEL: @getuc14
; CHECK-LE: mfvsrd r3, v2 ; CHECK-LE: mfvsrd r3, v2
; CHECK-LE: rldicl r3, r3, 16, 56 ; CHECK-LE: extrdi r3, r3, 8, 8
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i8 @getuc15(<16 x i8> %vuc) { define zeroext i8 @getuc15(<16 x i8> %vuc) {
entry: entry:
%vecext = extractelement <16 x i8> %vuc, i32 15 %vecext = extractelement <16 x i8> %vuc, i32 15
ret i8 %vecext ret i8 %vecext
; CHECK-LABEL: @getuc15 ; CHECK-LABEL: @getuc15
; CHECK: mffprd r3, f0 ; CHECK: mffprd r3, f0
; CHECK: clrldi r3, r3, 56 ; CHECK: clrldi r3, r3, 56
; CHECK-LE-LABEL: @getuc15 ; CHECK-LE-LABEL: @getuc15
; CHECK-LE: mfvsrd r3, v2 ; CHECK-LE: mfvsrd r3, v2
; CHECK-LE: rldicl r3, r3, 8, 56 ; CHECK-LE: srdi r3, r3, 56
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i8 @getvelsc(<16 x i8> %vsc, i32 signext %i) { define signext i8 @getvelsc(<16 x i8> %vsc, i32 signext %i) {
; CHECK-LABEL: @getvelsc ; CHECK-LABEL: @getvelsc
; CHECK: andi. r4, r5, 8 ; CHECK: andi. r4, r5, 8
; CHECK: li r3, 7 ; CHECK: li r3, 7
; CHECK: lvsl v3, 0, r4 ; CHECK: lvsl v3, 0, r4
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Lines
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i16 @getss0(<8 x i16> %vss) { define signext i16 @getss0(<8 x i16> %vss) {
entry: entry:
%vecext = extractelement <8 x i16> %vss, i32 0 %vecext = extractelement <8 x i16> %vss, i32 0
ret i16 %vecext ret i16 %vecext
; CHECK-LABEL: @getss0 ; CHECK-LABEL: @getss0
; CHECK: mfvsrd r3, v2 ; CHECK: mfvsrd r3, v2
; CHECK: rldicl r3, r3, 16, 48 ; CHECK: srdi r3, r3, 48
; CHECK: extsh r3, r3 ; CHECK: extsh r3, r3
; CHECK-LE-LABEL: @getss0 ; CHECK-LE-LABEL: @getss0
; CHECK-LE: mffprd r3, f0 ; CHECK-LE: mffprd r3, f0
; CHECK-LE: clrldi r3, r3, 48 ; CHECK-LE: clrldi r3, r3, 48
; CHECK-LE: extsh r3, r3 ; CHECK-LE: extsh r3, r3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i16 @getss1(<8 x i16> %vss) { define signext i16 @getss1(<8 x i16> %vss) {
entry: entry:
%vecext = extractelement <8 x i16> %vss, i32 1 %vecext = extractelement <8 x i16> %vss, i32 1
ret i16 %vecext ret i16 %vecext
; CHECK-LABEL: @getss1 ; CHECK-LABEL: @getss1
; CHECK: mfvsrd r3, v2 ; CHECK: mfvsrd r3, v2
; CHECK: rldicl r3, r3, 32, 48 ; CHECK: extrdi r3, r3, 16, 16
; CHECK: extsh r3, r3 ; CHECK: extsh r3, r3
; CHECK-LE-LABEL: @getss1 ; CHECK-LE-LABEL: @getss1
; CHECK-LE: mffprd r3, f0 ; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 48, 48 ; CHECK-LE: extrdi r3, r3, 16, 32
; CHECK-LE: extsh r3, r3 ; CHECK-LE: extsh r3, r3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i16 @getss2(<8 x i16> %vss) { define signext i16 @getss2(<8 x i16> %vss) {
entry: entry:
%vecext = extractelement <8 x i16> %vss, i32 2 %vecext = extractelement <8 x i16> %vss, i32 2
ret i16 %vecext ret i16 %vecext
; CHECK-LABEL: @getss2 ; CHECK-LABEL: @getss2
; CHECK: mfvsrd r3, v2 ; CHECK: mfvsrd r3, v2
; CHECK: rldicl r3, r3, 48, 48 ; CHECK: extrdi r3, r3, 16, 32
; CHECK: extsh r3, r3 ; CHECK: extsh r3, r3
; CHECK-LE-LABEL: @getss2 ; CHECK-LE-LABEL: @getss2
; CHECK-LE: mffprd r3, f0 ; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 32, 48 ; CHECK-LE: extrdi r3, r3, 16, 16
; CHECK-LE: extsh r3, r3 ; CHECK-LE: extsh r3, r3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i16 @getss3(<8 x i16> %vss) { define signext i16 @getss3(<8 x i16> %vss) {
entry: entry:
%vecext = extractelement <8 x i16> %vss, i32 3 %vecext = extractelement <8 x i16> %vss, i32 3
ret i16 %vecext ret i16 %vecext
; CHECK-LABEL: @getss3 ; CHECK-LABEL: @getss3
; CHECK: mfvsrd r3, v2 ; CHECK: mfvsrd r3, v2
; CHECK: clrldi r3, r3, 48 ; CHECK: clrldi r3, r3, 48
; CHECK: extsh r3, r3 ; CHECK: extsh r3, r3
; CHECK-LE-LABEL: @getss3 ; CHECK-LE-LABEL: @getss3
; CHECK-LE: mffprd r3, f0 ; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 16, 48 ; CHECK-LE: srdi r3, r3, 48
; CHECK-LE: extsh r3, r3 ; CHECK-LE: extsh r3, r3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i16 @getss4(<8 x i16> %vss) { define signext i16 @getss4(<8 x i16> %vss) {
entry: entry:
%vecext = extractelement <8 x i16> %vss, i32 4 %vecext = extractelement <8 x i16> %vss, i32 4
ret i16 %vecext ret i16 %vecext
; CHECK-LABEL: @getss4 ; CHECK-LABEL: @getss4
; CHECK: mffprd r3, f0 ; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 16, 48 ; CHECK: srdi r3, r3, 48
; CHECK: extsh r3, r3 ; CHECK: extsh r3, r3
; CHECK-LE-LABEL: @getss4 ; CHECK-LE-LABEL: @getss4
; CHECK-LE: mfvsrd r3, v2 ; CHECK-LE: mfvsrd r3, v2
; CHECK-LE: clrldi r3, r3, 48 ; CHECK-LE: clrldi r3, r3, 48
; CHECK-LE: extsh r3, r3 ; CHECK-LE: extsh r3, r3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i16 @getss5(<8 x i16> %vss) { define signext i16 @getss5(<8 x i16> %vss) {
entry: entry:
%vecext = extractelement <8 x i16> %vss, i32 5 %vecext = extractelement <8 x i16> %vss, i32 5
ret i16 %vecext ret i16 %vecext
; CHECK-LABEL: @getss5 ; CHECK-LABEL: @getss5
; CHECK: mffprd r3, f0 ; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 32, 48 ; CHECK: extrdi r3, r3, 16, 16
; CHECK: extsh r3, r3 ; CHECK: extsh r3, r3
; CHECK-LE-LABEL: @getss5 ; CHECK-LE-LABEL: @getss5
; CHECK-LE: mfvsrd r3, v2 ; CHECK-LE: mfvsrd r3, v2
; CHECK-LE: rldicl r3, r3, 48, 48 ; CHECK-LE: extrdi r3, r3, 16, 32
; CHECK-LE: extsh r3, r3 ; CHECK-LE: extsh r3, r3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i16 @getss6(<8 x i16> %vss) { define signext i16 @getss6(<8 x i16> %vss) {
entry: entry:
%vecext = extractelement <8 x i16> %vss, i32 6 %vecext = extractelement <8 x i16> %vss, i32 6
ret i16 %vecext ret i16 %vecext
; CHECK-LABEL: @getss6 ; CHECK-LABEL: @getss6
; CHECK: mffprd r3, f0 ; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 48, 48 ; CHECK: extrdi r3, r3, 16, 32
; CHECK: extsh r3, r3 ; CHECK: extsh r3, r3
; CHECK-LE-LABEL: @getss6 ; CHECK-LE-LABEL: @getss6
; CHECK-LE: mfvsrd r3, v2 ; CHECK-LE: mfvsrd r3, v2
; CHECK-LE: rldicl r3, r3, 32, 48 ; CHECK-LE: extrdi r3, r3, 16, 16
; CHECK-LE: extsh r3, r3 ; CHECK-LE: extsh r3, r3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i16 @getss7(<8 x i16> %vss) { define signext i16 @getss7(<8 x i16> %vss) {
entry: entry:
%vecext = extractelement <8 x i16> %vss, i32 7 %vecext = extractelement <8 x i16> %vss, i32 7
ret i16 %vecext ret i16 %vecext
; CHECK-LABEL: @getss7 ; CHECK-LABEL: @getss7
; CHECK: mffprd r3, f0 ; CHECK: mffprd r3, f0
; CHECK: clrldi r3, r3, 48 ; CHECK: clrldi r3, r3, 48
; CHECK: extsh r3, r3 ; CHECK: extsh r3, r3
; CHECK-LE-LABEL: @getss7 ; CHECK-LE-LABEL: @getss7
; CHECK-LE: mfvsrd r3, v2 ; CHECK-LE: mfvsrd r3, v2
; CHECK-LE: rldicl r3, r3, 16, 48 ; CHECK-LE: srdi r3, r3, 48
; CHECK-LE: extsh r3, r3 ; CHECK-LE: extsh r3, r3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i16 @getus0(<8 x i16> %vus) { define zeroext i16 @getus0(<8 x i16> %vus) {
entry: entry:
%vecext = extractelement <8 x i16> %vus, i32 0 %vecext = extractelement <8 x i16> %vus, i32 0
ret i16 %vecext ret i16 %vecext
; CHECK-LABEL: @getus0 ; CHECK-LABEL: @getus0
; CHECK: mfvsrd r3, v2 ; CHECK: mfvsrd r3, v2
; CHECK: rldicl r3, r3, 16, 48 ; CHECK: srdi r3, r3, 48
; CHECK-LE-LABEL: @getus0 ; CHECK-LE-LABEL: @getus0
; CHECK-LE: mffprd r3, f0 ; CHECK-LE: mffprd r3, f0
; CHECK-LE: clrldi r3, r3, 48 ; CHECK-LE: clrldi r3, r3, 48
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i16 @getus1(<8 x i16> %vus) { define zeroext i16 @getus1(<8 x i16> %vus) {
entry: entry:
%vecext = extractelement <8 x i16> %vus, i32 1 %vecext = extractelement <8 x i16> %vus, i32 1
ret i16 %vecext ret i16 %vecext
; CHECK-LABEL: @getus1 ; CHECK-LABEL: @getus1
; CHECK: mfvsrd r3, v2 ; CHECK: mfvsrd r3, v2
; CHECK: rldicl r3, r3, 32, 48 ; CHECK: extrdi r3, r3, 16, 16
; CHECK-LE-LABEL: @getus1 ; CHECK-LE-LABEL: @getus1
; CHECK-LE: mffprd r3, f0 ; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 48, 48 ; CHECK-LE: extrdi r3, r3, 16, 32
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i16 @getus2(<8 x i16> %vus) { define zeroext i16 @getus2(<8 x i16> %vus) {
entry: entry:
%vecext = extractelement <8 x i16> %vus, i32 2 %vecext = extractelement <8 x i16> %vus, i32 2
ret i16 %vecext ret i16 %vecext
; CHECK-LABEL: @getus2 ; CHECK-LABEL: @getus2
; CHECK: mfvsrd r3, v2 ; CHECK: mfvsrd r3, v2
; CHECK: rldicl r3, r3, 48, 48 ; CHECK: extrdi r3, r3, 16, 32
; CHECK-LE-LABEL: @getus2 ; CHECK-LE-LABEL: @getus2
; CHECK-LE: mffprd r3, f0 ; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 32, 48 ; CHECK-LE: extrdi r3, r3, 16, 16
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i16 @getus3(<8 x i16> %vus) { define zeroext i16 @getus3(<8 x i16> %vus) {
entry: entry:
%vecext = extractelement <8 x i16> %vus, i32 3 %vecext = extractelement <8 x i16> %vus, i32 3
ret i16 %vecext ret i16 %vecext
; CHECK-LABEL: @getus3 ; CHECK-LABEL: @getus3
; CHECK: mfvsrd r3, v2 ; CHECK: mfvsrd r3, v2
; CHECK: clrldi r3, r3, 48 ; CHECK: clrldi r3, r3, 48
; CHECK-LE-LABEL: @getus3 ; CHECK-LE-LABEL: @getus3
; CHECK-LE: mffprd r3, f0 ; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 16, 48 ; CHECK-LE: srdi r3, r3, 48
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i16 @getus4(<8 x i16> %vus) { define zeroext i16 @getus4(<8 x i16> %vus) {
entry: entry:
%vecext = extractelement <8 x i16> %vus, i32 4 %vecext = extractelement <8 x i16> %vus, i32 4
ret i16 %vecext ret i16 %vecext
; CHECK-LABEL: @getus4 ; CHECK-LABEL: @getus4
; CHECK: mffprd r3, f0 ; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 16, 48 ; CHECK: srdi r3, r3, 48
; CHECK-LE-LABEL: @getus4 ; CHECK-LE-LABEL: @getus4
; CHECK-LE: mfvsrd r3, v2 ; CHECK-LE: mfvsrd r3, v2
; CHECK-LE: clrldi r3, r3, 48 ; CHECK-LE: clrldi r3, r3, 48
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i16 @getus5(<8 x i16> %vus) { define zeroext i16 @getus5(<8 x i16> %vus) {
entry: entry:
%vecext = extractelement <8 x i16> %vus, i32 5 %vecext = extractelement <8 x i16> %vus, i32 5
ret i16 %vecext ret i16 %vecext
; CHECK-LABEL: @getus5 ; CHECK-LABEL: @getus5
; CHECK: mffprd r3, f0 ; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 32, 48 ; CHECK: extrdi r3, r3, 16, 16
; CHECK-LE-LABEL: @getus5 ; CHECK-LE-LABEL: @getus5
; CHECK-LE: mfvsrd r3, v2 ; CHECK-LE: mfvsrd r3, v2
; CHECK-LE: rldicl r3, r3, 48, 48 ; CHECK-LE: extrdi r3, r3, 16, 32
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i16 @getus6(<8 x i16> %vus) { define zeroext i16 @getus6(<8 x i16> %vus) {
entry: entry:
%vecext = extractelement <8 x i16> %vus, i32 6 %vecext = extractelement <8 x i16> %vus, i32 6
ret i16 %vecext ret i16 %vecext
; CHECK-LABEL: @getus6 ; CHECK-LABEL: @getus6
; CHECK: mffprd r3, f0 ; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 48, 48 ; CHECK: extrdi r3, r3, 16, 32
; CHECK-LE-LABEL: @getus6 ; CHECK-LE-LABEL: @getus6
; CHECK-LE: mfvsrd r3, v2 ; CHECK-LE: mfvsrd r3, v2
; CHECK-LE: rldicl r3, r3, 32, 48 ; CHECK-LE: extrdi r3, r3, 16, 16
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i16 @getus7(<8 x i16> %vus) { define zeroext i16 @getus7(<8 x i16> %vus) {
entry: entry:
%vecext = extractelement <8 x i16> %vus, i32 7 %vecext = extractelement <8 x i16> %vus, i32 7
ret i16 %vecext ret i16 %vecext
; CHECK-LABEL: @getus7 ; CHECK-LABEL: @getus7
; CHECK: mffprd r3, f0 ; CHECK: mffprd r3, f0
; CHECK: clrldi r3, r3, 48 ; CHECK: clrldi r3, r3, 48
; CHECK-LE-LABEL: @getus7 ; CHECK-LE-LABEL: @getus7
; CHECK-LE: mfvsrd r3, v2 ; CHECK-LE: mfvsrd r3, v2
; CHECK-LE: rldicl r3, r3, 16, 48 ; CHECK-LE: srdi r3, r3, 48
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i16 @getvelss(<8 x i16> %vss, i32 signext %i) { define signext i16 @getvelss(<8 x i16> %vss, i32 signext %i) {
; CHECK-LABEL: @getvelss ; CHECK-LABEL: @getvelss
; CHECK: andi. r4, r5, 4 ; CHECK: andi. r4, r5, 4
; CHECK: li r3, 3 ; CHECK: li r3, 3
; CHECK: sldi r4, r4, 1 ; CHECK: sldi r4, r4, 1
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llvm/test/CodeGen/PowerPC/pcrel-jump-table.ll

; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=future -ppc-asm-full-reg-names < %s | FileCheck %s \ ; RUN: -mcpu=future -ppc-asm-full-reg-names < %s | FileCheck %s \
; RUN: --check-prefix=CHECK-R ; RUN: --check-prefix=CHECK-R
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=future -ppc-use-absolute-jumptables \ ; RUN: -mcpu=future -ppc-use-absolute-jumptables \
; RUN: -ppc-asm-full-reg-names < %s | FileCheck %s \ ; RUN: -ppc-asm-full-reg-names < %s | FileCheck %s \
; RUN: --check-prefix=CHECK-A ; RUN: --check-prefix=CHECK-A
; This test checks for getting relative and absolute jump table base address ; This test checks for getting relative and absolute jump table base address
; using PC Relative addressing. ; using PC Relative addressing.
define dso_local signext i32 @jumptable(i32 signext %param) { define dso_local signext i32 @jumptable(i32 signext %param) {
; CHECK-R-LABEL: jumptable: ; CHECK-R-LABEL: jumptable:
; CHECK-R: # %bb.1: # %entry ; CHECK-R: # %bb.1: # %entry
; CHECK-R-NEXT: rldic r4, r4 ; CHECK-R-NEXT: clrlsldi r4, r4, 32, 2
; CHECK-R-NEXT: paddi r5, 0, .LJTI0_0@PCREL, 1 ; CHECK-R-NEXT: paddi r5, 0, .LJTI0_0@PCREL, 1
; CHECK-R-NEXT: lwax r4, r4, r5 ; CHECK-R-NEXT: lwax r4, r4, r5
; CHECK-R-NEXT: add r4, r4, r5 ; CHECK-R-NEXT: add r4, r4, r5
; CHECK-R-NEXT: mtctr r4 ; CHECK-R-NEXT: mtctr r4
; CHECK-R-NEXT: bctr ; CHECK-R-NEXT: bctr
; CHECK-A-LABEL: jumptable: ; CHECK-A-LABEL: jumptable:
; CHECK-A: # %bb.1: # %entry ; CHECK-A: # %bb.1: # %entry
; CHECK-A-NEXT: rldic r4, r4 ; CHECK-A-NEXT: clrlsldi r4, r4, 32, 3
; CHECK-A-NEXT: paddi r5, 0, .LJTI0_0@PCREL, 1 ; CHECK-A-NEXT: paddi r5, 0, .LJTI0_0@PCREL, 1
; CHECK-A-NEXT: ldx r4, r4, r5 ; CHECK-A-NEXT: ldx r4, r4, r5
; CHECK-A-NEXT: mtctr r4 ; CHECK-A-NEXT: mtctr r4
; CHECK-A-NEXT: bctr ; CHECK-A-NEXT: bctr
entry: entry:
switch i32 %param, label %sw.default [ switch i32 %param, label %sw.default [
i32 1, label %return i32 1, label %return
Show All 26 Lines

llvm/test/CodeGen/PowerPC/popcnt-zext.ll

Show First 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
; SLOW-NEXT: lis 5, 3855 ; SLOW-NEXT: lis 5, 3855
; SLOW-NEXT: srwi 4, 3, 4 ; SLOW-NEXT: srwi 4, 3, 4
; SLOW-NEXT: add 3, 3, 4 ; SLOW-NEXT: add 3, 3, 4
; SLOW-NEXT: lis 4, 257 ; SLOW-NEXT: lis 4, 257
; SLOW-NEXT: ori 5, 5, 3855 ; SLOW-NEXT: ori 5, 5, 3855
; SLOW-NEXT: and 3, 3, 5 ; SLOW-NEXT: and 3, 3, 5
; SLOW-NEXT: ori 4, 4, 257 ; SLOW-NEXT: ori 4, 4, 257
; SLOW-NEXT: mullw 3, 3, 4 ; SLOW-NEXT: mullw 3, 3, 4
; SLOW-NEXT: rlwinm 3, 3, 8, 24, 31 ; SLOW-NEXT: srwi 3, 3, 24
; SLOW-NEXT: blr ; SLOW-NEXT: blr
%pop = tail call i8 @llvm.ctpop.i8(i8 %x) %pop = tail call i8 @llvm.ctpop.i8(i8 %x)
%z = zext i8 %pop to i16 %z = zext i8 %pop to i16
ret i16 %z ret i16 %z
} }
define i32 @zpop_i8_i32(i8 %x) { define i32 @zpop_i8_i32(i8 %x) {
; FAST-LABEL: zpop_i8_i32: ; FAST-LABEL: zpop_i8_i32:
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
; SLOW-NEXT: lis 5, 3855 ; SLOW-NEXT: lis 5, 3855
; SLOW-NEXT: srwi 4, 3, 4 ; SLOW-NEXT: srwi 4, 3, 4
; SLOW-NEXT: add 3, 3, 4 ; SLOW-NEXT: add 3, 3, 4
; SLOW-NEXT: lis 4, 257 ; SLOW-NEXT: lis 4, 257
; SLOW-NEXT: ori 5, 5, 3855 ; SLOW-NEXT: ori 5, 5, 3855
; SLOW-NEXT: and 3, 3, 5 ; SLOW-NEXT: and 3, 3, 5
; SLOW-NEXT: ori 4, 4, 257 ; SLOW-NEXT: ori 4, 4, 257
; SLOW-NEXT: mullw 3, 3, 4 ; SLOW-NEXT: mullw 3, 3, 4
; SLOW-NEXT: rlwinm 3, 3, 8, 24, 31 ; SLOW-NEXT: srwi 3, 3, 24
; SLOW-NEXT: blr ; SLOW-NEXT: blr
%pop = tail call i8 @llvm.ctpop.i8(i8 %x) %pop = tail call i8 @llvm.ctpop.i8(i8 %x)
%z = zext i8 %pop to i32 %z = zext i8 %pop to i32
ret i32 %z ret i32 %z
} }
define i32 @zpop_i16_i32(i16 %x) { define i32 @zpop_i16_i32(i16 %x) {
; FAST-LABEL: zpop_i16_i32: ; FAST-LABEL: zpop_i16_i32:
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; SLOW-NEXT: lis 5, 3855 ; SLOW-NEXT: lis 5, 3855
; SLOW-NEXT: srwi 4, 3, 4 ; SLOW-NEXT: srwi 4, 3, 4
; SLOW-NEXT: add 3, 3, 4 ; SLOW-NEXT: add 3, 3, 4
; SLOW-NEXT: lis 4, 257 ; SLOW-NEXT: lis 4, 257
; SLOW-NEXT: ori 5, 5, 3855 ; SLOW-NEXT: ori 5, 5, 3855
; SLOW-NEXT: and 3, 3, 5 ; SLOW-NEXT: and 3, 3, 5
; SLOW-NEXT: ori 4, 4, 257 ; SLOW-NEXT: ori 4, 4, 257
; SLOW-NEXT: mullw 3, 3, 4 ; SLOW-NEXT: mullw 3, 3, 4
; SLOW-NEXT: rlwinm 3, 3, 8, 24, 31 ; SLOW-NEXT: srwi 3, 3, 24
; SLOW-NEXT: blr ; SLOW-NEXT: blr
%pop = tail call i16 @llvm.ctpop.i16(i16 %x) %pop = tail call i16 @llvm.ctpop.i16(i16 %x)
%z = zext i16 %pop to i32 %z = zext i16 %pop to i32
ret i32 %z ret i32 %z
} }
define i64 @zpop_i32_i64(i32 %x) { define i64 @zpop_i32_i64(i32 %x) {
; FAST-LABEL: zpop_i32_i64: ; FAST-LABEL: zpop_i32_i64:
; FAST: # %bb.0: ; FAST: # %bb.0:
; FAST-NEXT: clrldi 3, 3, 32 ; FAST-NEXT: clrldi 3, 3, 32
; FAST-NEXT: popcntd 3, 3 ; FAST-NEXT: popcntd 3, 3
; FAST-NEXT: blr ; FAST-NEXT: blr
; ;
; SLOW-LABEL: zpop_i32_i64: ; SLOW-LABEL: zpop_i32_i64:
; SLOW: # %bb.0: ; SLOW: # %bb.0:
; SLOW-NEXT: rlwinm 5, 3, 31, 1, 0 ; SLOW-NEXT: rlwinm 5, 3, 31, 1, 0
; SLOW-NEXT: lis 4, 13107 ; SLOW-NEXT: lis 4, 13107
; SLOW-NEXT: andis. 6, 5, 21845 ; SLOW-NEXT: andis. 6, 5, 21845
; SLOW-NEXT: andi. 5, 5, 21845 ; SLOW-NEXT: andi. 5, 5, 21845
; SLOW-NEXT: ori 4, 4, 13107 ; SLOW-NEXT: ori 4, 4, 13107
; SLOW-NEXT: or 5, 5, 6 ; SLOW-NEXT: or 5, 5, 6
; SLOW-NEXT: clrldi 3, 3, 32 ; SLOW-NEXT: clrldi 3, 3, 32
; SLOW-NEXT: rldimi 4, 4, 32, 0 ; SLOW-NEXT: insrdi 4, 4, 32, 0
; SLOW-NEXT: sub 3, 3, 5 ; SLOW-NEXT: sub 3, 3, 5
; SLOW-NEXT: and 5, 3, 4 ; SLOW-NEXT: and 5, 3, 4
; SLOW-NEXT: rotldi 3, 3, 62 ; SLOW-NEXT: rotldi 3, 3, 62
; SLOW-NEXT: and 3, 3, 4 ; SLOW-NEXT: and 3, 3, 4
; SLOW-NEXT: add 3, 5, 3 ; SLOW-NEXT: add 3, 5, 3
; SLOW-NEXT: lis 4, 3855 ; SLOW-NEXT: lis 4, 3855
; SLOW-NEXT: rldicl 5, 3, 60, 4 ; SLOW-NEXT: srdi 5, 3, 4
; SLOW-NEXT: ori 4, 4, 3855 ; SLOW-NEXT: ori 4, 4, 3855
; SLOW-NEXT: add 3, 3, 5 ; SLOW-NEXT: add 3, 3, 5
; SLOW-NEXT: lis 5, 257 ; SLOW-NEXT: lis 5, 257
; SLOW-NEXT: rldimi 4, 4, 32, 0 ; SLOW-NEXT: insrdi 4, 4, 32, 0
; SLOW-NEXT: ori 5, 5, 257 ; SLOW-NEXT: ori 5, 5, 257
; SLOW-NEXT: and 3, 3, 4 ; SLOW-NEXT: and 3, 3, 4
; SLOW-NEXT: rldimi 5, 5, 32, 0 ; SLOW-NEXT: insrdi 5, 5, 32, 0
; SLOW-NEXT: mulld 3, 3, 5 ; SLOW-NEXT: mulld 3, 3, 5
; SLOW-NEXT: rldicl 3, 3, 8, 56 ; SLOW-NEXT: srdi 3, 3, 56
; SLOW-NEXT: blr ; SLOW-NEXT: blr
%z = zext i32 %x to i64 %z = zext i32 %x to i64
%pop = tail call i64 @llvm.ctpop.i64(i64 %z) %pop = tail call i64 @llvm.ctpop.i64(i64 %z)
ret i64 %pop ret i64 %pop
} }
define i64 @popz_i32_i64(i32 %x) { define i64 @popz_i32_i64(i32 %x) {
; FAST-LABEL: popz_i32_i64: ; FAST-LABEL: popz_i32_i64:
Show All 20 Lines
; SLOW-NEXT: lis 5, 3855 ; SLOW-NEXT: lis 5, 3855
; SLOW-NEXT: srwi 4, 3, 4 ; SLOW-NEXT: srwi 4, 3, 4
; SLOW-NEXT: add 3, 3, 4 ; SLOW-NEXT: add 3, 3, 4
; SLOW-NEXT: lis 4, 257 ; SLOW-NEXT: lis 4, 257
; SLOW-NEXT: ori 5, 5, 3855 ; SLOW-NEXT: ori 5, 5, 3855
; SLOW-NEXT: and 3, 3, 5 ; SLOW-NEXT: and 3, 3, 5
; SLOW-NEXT: ori 4, 4, 257 ; SLOW-NEXT: ori 4, 4, 257
; SLOW-NEXT: mullw 3, 3, 4 ; SLOW-NEXT: mullw 3, 3, 4
; SLOW-NEXT: rlwinm 3, 3, 8, 24, 31 ; SLOW-NEXT: srwi 3, 3, 24
; SLOW-NEXT: blr ; SLOW-NEXT: blr
%pop = tail call i32 @llvm.ctpop.i32(i32 %x) %pop = tail call i32 @llvm.ctpop.i32(i32 %x)
%z = zext i32 %pop to i64 %z = zext i32 %pop to i64
ret i64 %z ret i64 %z
} }
define i64 @popa_i16_i64(i16 %x) { define i64 @popa_i16_i64(i16 %x) {
; FAST-LABEL: popa_i16_i64: ; FAST-LABEL: popa_i16_i64:
▲ Show 20 Lines • Show All 41 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/ppc64-P9-setb.ll

Show First 20 Lines • Show All 124 Lines • ▼ Show 20 Lines
; CHECK-NEXT: setb r3, cr0 ; CHECK-NEXT: setb r3, cr0
; CHECK-NOT: subc ; CHECK-NOT: subc
; CHECK-NOT: adde ; CHECK-NOT: adde
; CHECK-NOT: xori ; CHECK-NOT: xori
; CHECK-NOT: isel ; CHECK-NOT: isel
; CHECK: blr ; CHECK: blr
; CHECK-PWR8-LABEL: setb5 ; CHECK-PWR8-LABEL: setb5
; CHECK-PWR8-DAG: sradi ; CHECK-PWR8-DAG: sradi
; CHECK-PWR8-DAG: rldicl ; CHECK-PWR8-DAG: srdi
; CHECK-PWR8-DAG: li ; CHECK-PWR8-DAG: li
; CHECK-PWR8-DAG: cmpd ; CHECK-PWR8-DAG: cmpd
; CHECK-PWR8-DAG: subc ; CHECK-PWR8-DAG: subc
; CHECK-PWR8-DAG: adde ; CHECK-PWR8-DAG: adde
; CHECK-PWR8-DAG: xori ; CHECK-PWR8-DAG: xori
; CHECK-PWR8: isel ; CHECK-PWR8: isel
; CHECK-PWR8: blr ; CHECK-PWR8: blr
} }
Show All 13 Lines
; CHECK-NEXT: setb r3, cr0 ; CHECK-NEXT: setb r3, cr0
; CHECK-NOT: subc ; CHECK-NOT: subc
; CHECK-NOT: adde ; CHECK-NOT: adde
; CHECK-NOT: xori ; CHECK-NOT: xori
; CHECK-NOT: isel ; CHECK-NOT: isel
; CHECK: blr ; CHECK: blr
; CHECK-PWR8-LABEL: setb6 ; CHECK-PWR8-LABEL: setb6
; CHECK-PWR8-DAG: sradi ; CHECK-PWR8-DAG: sradi
; CHECK-PWR8-DAG: rldicl ; CHECK-PWR8-DAG: srdi
; CHECK-PWR8-DAG: li ; CHECK-PWR8-DAG: li
; CHECK-PWR8-DAG: cmpd ; CHECK-PWR8-DAG: cmpd
; CHECK-PWR8-DAG: subc ; CHECK-PWR8-DAG: subc
; CHECK-PWR8-DAG: adde ; CHECK-PWR8-DAG: adde
; CHECK-PWR8-DAG: xori ; CHECK-PWR8-DAG: xori
; CHECK-PWR8: isel ; CHECK-PWR8: isel
; CHECK-PWR8: blr ; CHECK-PWR8: blr
} }
Show All 13 Lines
; CHECK-NEXT: setb r3, cr0 ; CHECK-NEXT: setb r3, cr0
; CHECK-NOT: subc ; CHECK-NOT: subc
; CHECK-NOT: adde ; CHECK-NOT: adde
; CHECK-NOT: xori ; CHECK-NOT: xori
; CHECK-NOT: isel ; CHECK-NOT: isel
; CHECK: blr ; CHECK: blr
; CHECK-PWR8-LABEL: setb7 ; CHECK-PWR8-LABEL: setb7
; CHECK-PWR8-DAG: sradi ; CHECK-PWR8-DAG: sradi
; CHECK-PWR8-DAG: rldicl ; CHECK-PWR8-DAG: srdi
; CHECK-PWR8-DAG: li ; CHECK-PWR8-DAG: li
; CHECK-PWR8-DAG: cmpd ; CHECK-PWR8-DAG: cmpd
; CHECK-PWR8-DAG: subc ; CHECK-PWR8-DAG: subc
; CHECK-PWR8-DAG: adde ; CHECK-PWR8-DAG: adde
; CHECK-PWR8-DAG: xori ; CHECK-PWR8-DAG: xori
; CHECK-PWR8: isel ; CHECK-PWR8: isel
; CHECK-PWR8: blr ; CHECK-PWR8: blr
} }
Show All 13 Lines
; CHECK-NEXT: setb r3, cr0 ; CHECK-NEXT: setb r3, cr0
; CHECK-NOT: subc ; CHECK-NOT: subc
; CHECK-NOT: adde ; CHECK-NOT: adde
; CHECK-NOT: xori ; CHECK-NOT: xori
; CHECK-NOT: isel ; CHECK-NOT: isel
; CHECK: blr ; CHECK: blr
; CHECK-PWR8-LABEL: setb8 ; CHECK-PWR8-LABEL: setb8
; CHECK-PWR8-DAG: sradi ; CHECK-PWR8-DAG: sradi
; CHECK-PWR8-DAG: rldicl ; CHECK-PWR8-DAG: srdi
; CHECK-PWR8-DAG: li ; CHECK-PWR8-DAG: li
; CHECK-PWR8-DAG: cmpd ; CHECK-PWR8-DAG: cmpd
; CHECK-PWR8-DAG: subc ; CHECK-PWR8-DAG: subc
; CHECK-PWR8-DAG: adde ; CHECK-PWR8-DAG: adde
; CHECK-PWR8-DAG: xori ; CHECK-PWR8-DAG: xori
; CHECK-PWR8: isel ; CHECK-PWR8: isel
; CHECK-PWR8: blr ; CHECK-PWR8: blr
} }
▲ Show 20 Lines • Show All 118 Lines • ▼ Show 20 Lines
; CHECK-NOT: subc ; CHECK-NOT: subc
; CHECK-NOT: adde ; CHECK-NOT: adde
; CHECK-NOT: xori ; CHECK-NOT: xori
; CHECK-NOT: neg ; CHECK-NOT: neg
; CHECK-NOT: isel ; CHECK-NOT: isel
; CHECK: blr ; CHECK: blr
; CHECK-PWR8-LABEL: setb13 ; CHECK-PWR8-LABEL: setb13
; CHECK-PWR8-DAG: sradi ; CHECK-PWR8-DAG: sradi
; CHECK-PWR8-DAG: rldicl ; CHECK-PWR8-DAG: srdi
; CHECK-PWR8-DAG: li ; CHECK-PWR8-DAG: li
; CHECK-PWR8-DAG: cmpd ; CHECK-PWR8-DAG: cmpd
; CHECK-PWR8-DAG: subc ; CHECK-PWR8-DAG: subc
; CHECK-PWR8-DAG: adde ; CHECK-PWR8-DAG: adde
; CHECK-PWR8-DAG: xori ; CHECK-PWR8-DAG: xori
; CHECK-PWR8-DAG: neg ; CHECK-PWR8-DAG: neg
; CHECK-PWR8: isel ; CHECK-PWR8: isel
; CHECK-PWR8: blr ; CHECK-PWR8: blr
Show All 15 Lines
; CHECK-NOT: subc ; CHECK-NOT: subc
; CHECK-NOT: adde ; CHECK-NOT: adde
; CHECK-NOT: xori ; CHECK-NOT: xori
; CHECK-NOT: neg ; CHECK-NOT: neg
; CHECK-NOT: isel ; CHECK-NOT: isel
; CHECK: blr ; CHECK: blr
; CHECK-PWR8-LABEL: setb14 ; CHECK-PWR8-LABEL: setb14
; CHECK-PWR8-DAG: sradi ; CHECK-PWR8-DAG: sradi
; CHECK-PWR8-DAG: rldicl ; CHECK-PWR8-DAG: srdi
; CHECK-PWR8-DAG: li ; CHECK-PWR8-DAG: li
; CHECK-PWR8-DAG: cmpd ; CHECK-PWR8-DAG: cmpd
; CHECK-PWR8-DAG: subc ; CHECK-PWR8-DAG: subc
; CHECK-PWR8-DAG: adde ; CHECK-PWR8-DAG: adde
; CHECK-PWR8-DAG: xori ; CHECK-PWR8-DAG: xori
; CHECK-PWR8-DAG: neg ; CHECK-PWR8-DAG: neg
; CHECK-PWR8: isel ; CHECK-PWR8: isel
; CHECK-PWR8: blr ; CHECK-PWR8: blr
Show All 15 Lines
; CHECK-NOT: subc ; CHECK-NOT: subc
; CHECK-NOT: adde ; CHECK-NOT: adde
; CHECK-NOT: xori ; CHECK-NOT: xori
; CHECK-NOT: neg ; CHECK-NOT: neg
; CHECK-NOT: isel ; CHECK-NOT: isel
; CHECK: blr ; CHECK: blr
; CHECK-PWR8-LABEL: setb15 ; CHECK-PWR8-LABEL: setb15
; CHECK-PWR8-DAG: sradi ; CHECK-PWR8-DAG: sradi
; CHECK-PWR8-DAG: rldicl ; CHECK-PWR8-DAG: srdi
; CHECK-PWR8-DAG: li ; CHECK-PWR8-DAG: li
; CHECK-PWR8-DAG: cmpd ; CHECK-PWR8-DAG: cmpd
; CHECK-PWR8-DAG: subc ; CHECK-PWR8-DAG: subc
; CHECK-PWR8-DAG: adde ; CHECK-PWR8-DAG: adde
; CHECK-PWR8-DAG: xori ; CHECK-PWR8-DAG: xori
; CHECK-PWR8-DAG: neg ; CHECK-PWR8-DAG: neg
; CHECK-PWR8: isel ; CHECK-PWR8: isel
; CHECK-PWR8: blr ; CHECK-PWR8: blr
Show All 15 Lines
; CHECK-NOT: subc ; CHECK-NOT: subc
; CHECK-NOT: adde ; CHECK-NOT: adde
; CHECK-NOT: xori ; CHECK-NOT: xori
; CHECK-NOT: neg ; CHECK-NOT: neg
; CHECK-NOT: isel ; CHECK-NOT: isel
; CHECK: blr ; CHECK: blr
; CHECK-PWR8-LABEL: setb16 ; CHECK-PWR8-LABEL: setb16
; CHECK-PWR8-DAG: sradi ; CHECK-PWR8-DAG: sradi
; CHECK-PWR8-DAG: rldicl ; CHECK-PWR8-DAG: srdi
; CHECK-PWR8-DAG: li ; CHECK-PWR8-DAG: li
; CHECK-PWR8-DAG: cmpd ; CHECK-PWR8-DAG: cmpd
; CHECK-PWR8-DAG: subc ; CHECK-PWR8-DAG: subc
; CHECK-PWR8-DAG: adde ; CHECK-PWR8-DAG: adde
; CHECK-PWR8-DAG: xori ; CHECK-PWR8-DAG: xori
; CHECK-PWR8-DAG: neg ; CHECK-PWR8-DAG: neg
; CHECK-PWR8: isel ; CHECK-PWR8: isel
; CHECK-PWR8: blr ; CHECK-PWR8: blr
▲ Show 20 Lines • Show All 467 Lines • ▼ Show 20 Lines
; CHECK-NOT: isel ; CHECK-NOT: isel
; CHECK: blr ; CHECK: blr
; CHECK-PWR8-LABEL: setbsc1 ; CHECK-PWR8-LABEL: setbsc1
; CHECK-PWR8-DAG: extsb ; CHECK-PWR8-DAG: extsb
; CHECK-PWR8-DAG: extsb ; CHECK-PWR8-DAG: extsb
; CHECK-PWR8-DAG: extsw ; CHECK-PWR8-DAG: extsw
; CHECK-PWR8-DAG: extsw ; CHECK-PWR8-DAG: extsw
; CHECK-PWR8-DAG: cmpw ; CHECK-PWR8-DAG: cmpw
; CHECK-PWR8-DAG: rldicl ; CHECK-PWR8-DAG: srdi
; CHECK-PWR8: isel ; CHECK-PWR8: isel
; CHECK-PWR8: blr ; CHECK-PWR8: blr
} }
; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setgt)), setgt ; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setgt)), setgt
define i64 @setbsc2(i8 %a, i8 %b) { define i64 @setbsc2(i8 %a, i8 %b) {
%t1 = icmp sgt i8 %b, %a %t1 = icmp sgt i8 %b, %a
%t2 = icmp sgt i8 %a, %b %t2 = icmp sgt i8 %a, %b
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; CHECK-NOT: isel ; CHECK-NOT: isel
; CHECK: blr ; CHECK: blr
; CHECK-PWR8-LABEL: setbsc2 ; CHECK-PWR8-LABEL: setbsc2
; CHECK-PWR8-DAG: extsb ; CHECK-PWR8-DAG: extsb
; CHECK-PWR8-DAG: extsb ; CHECK-PWR8-DAG: extsb
; CHECK-PWR8-DAG: extsw ; CHECK-PWR8-DAG: extsw
; CHECK-PWR8-DAG: extsw ; CHECK-PWR8-DAG: extsw
; CHECK-PWR8-DAG: cmpw ; CHECK-PWR8-DAG: cmpw
; CHECK-PWR8-DAG: rldicl ; CHECK-PWR8-DAG: srdi
; CHECK-PWR8: isel ; CHECK-PWR8: isel
; CHECK-PWR8: blr ; CHECK-PWR8: blr
} }
; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setlt)), setlt ; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setlt)), setlt
define i64 @setbsc3(i4 %a, i4 %b) { define i64 @setbsc3(i4 %a, i4 %b) {
%t1 = icmp slt i4 %a, %b %t1 = icmp slt i4 %a, %b
%t2 = icmp slt i4 %b, %a %t2 = icmp slt i4 %b, %a
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; CHECK-PWR8-LABEL: setbsc3 ; CHECK-PWR8-LABEL: setbsc3
; CHECK-PWR8-DAG: slwi ; CHECK-PWR8-DAG: slwi
; CHECK-PWR8-DAG: slwi ; CHECK-PWR8-DAG: slwi
; CHECK-PWR8-DAG: srawi ; CHECK-PWR8-DAG: srawi
; CHECK-PWR8-DAG: srawi ; CHECK-PWR8-DAG: srawi
; CHECK-PWR8-DAG: extsw ; CHECK-PWR8-DAG: extsw
; CHECK-PWR8-DAG: extsw ; CHECK-PWR8-DAG: extsw
; CHECK-PWR8-DAG: cmpw ; CHECK-PWR8-DAG: cmpw
; CHECK-PWR8-DAG: rldicl ; CHECK-PWR8-DAG: srdi
; CHECK-PWR8: isel ; CHECK-PWR8: isel
; CHECK-PWR8: blr ; CHECK-PWR8: blr
} }
; Test with unsigned integer type i64/i32/i16/i8 for input parameter ; Test with unsigned integer type i64/i32/i16/i8 for input parameter
; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setult)), setugt ; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setult)), setugt
define i64 @setbud1(i64 %a, i64 %b) { define i64 @setbud1(i64 %a, i64 %b) {
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; CHECK-NEXT: setb r3, cr0 ; CHECK-NEXT: setb r3, cr0
; CHECK-NOT: cntlzw ; CHECK-NOT: cntlzw
; CHECK-NOT: srwi ; CHECK-NOT: srwi
; CHECK-NOT: xori ; CHECK-NOT: xori
; CHECK-NOT: neg ; CHECK-NOT: neg
; CHECK-NOT: isel ; CHECK-NOT: isel
; CHECK: blr ; CHECK: blr
; CHECK-PWR8-LABEL: setbuh ; CHECK-PWR8-LABEL: setbuh
; CHECK-PWR8: clrlwi ; CHECK-PWR8: clrlwi
; CHECK-PWR8: clrlwi ; CHECK-PWR8: clrlwi
; CHECK-PWR8-DAG: cmplw ; CHECK-PWR8-DAG: cmplw
; CHECK-PWR8-DAG: cntlzw ; CHECK-PWR8-DAG: cntlzw
; CHECK-PWR8: srwi ; CHECK-PWR8: srwi
; CHECK-PWR8: xori ; CHECK-PWR8: xori
; CHECK-PWR8: neg ; CHECK-PWR8: neg
; CHECK-PWR8: isel ; CHECK-PWR8: isel
; CHECK-PWR8: blr ; CHECK-PWR8: blr
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; CHECK-NOT: clrldi ; CHECK-NOT: clrldi
; CHECK: cmplw {{c?r?(0, )?}}[[RA]], [[RB]] ; CHECK: cmplw {{c?r?(0, )?}}[[RA]], [[RB]]
; CHECK-NEXT: setb r3, cr0 ; CHECK-NEXT: setb r3, cr0
; CHECK-NOT: sub ; CHECK-NOT: sub
; CHECK-NOT: sradi ; CHECK-NOT: sradi
; CHECK-NOT: isel ; CHECK-NOT: isel
; CHECK: blr ; CHECK: blr
; CHECK-PWR8-LABEL: setbuc ; CHECK-PWR8-LABEL: setbuc
; CHECK-PWR8: clrlwi ; CHECK-PWR8: clrlwi
; CHECK-PWR8: clrlwi ; CHECK-PWR8: clrlwi
; CHECK-PWR8-DAG: clrldi ; CHECK-PWR8-DAG: clrldi
; CHECK-PWR8-DAG: clrldi ; CHECK-PWR8-DAG: clrldi
; CHECK-PWR8-DAG: cmplw ; CHECK-PWR8-DAG: cmplw
; CHECK-PWR8: sradi ; CHECK-PWR8: sradi
; CHECK-PWR8: isel ; CHECK-PWR8: isel
; CHECK-PWR8: blr ; CHECK-PWR8: blr
} }
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llvm/test/CodeGen/PowerPC/ppc64-patchpoint.ll

; RUN: llc -verify-machineinstrs < %s | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-BE ; RUN: llc -verify-machineinstrs < %s | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-BE
; RUN: llc -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-BE ; RUN: llc -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-BE
; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs < %s | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-LE ; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs < %s | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-LE
; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-LE ; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-LE
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
; Trivial patchpoint codegen ; Trivial patchpoint codegen
; ;
define i64 @trivial_patchpoint_codegen(i64 %p1, i64 %p2, i64 %p3, i64 %p4) { define i64 @trivial_patchpoint_codegen(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
entry: entry:
; CHECK-LABEL: trivial_patchpoint_codegen: ; CHECK-LABEL: trivial_patchpoint_codegen:
; CHECK: li 12, -8531 ; CHECK: li 12, -8531
; CHECK-NEXT: rldic 12, 12, 32, 16 ; CHECK-NEXT: clrlsldi 12, 12, 48, 32
; CHECK-NEXT: oris 12, 12, 48879 ; CHECK-NEXT: oris 12, 12, 48879
; CHECK-NEXT: ori 12, 12, 51966 ; CHECK-NEXT: ori 12, 12, 51966
; CHECK-LE-NEXT: std 2, 24(1) ; CHECK-LE-NEXT: std 2, 24(1)
; CHECK-BE-NEXT: std 2, 40(1) ; CHECK-BE-NEXT: std 2, 40(1)
; CHECK-BE-NEXT: ld 2, 8(12) ; CHECK-BE-NEXT: ld 2, 8(12)
; CHECK-BE-NEXT: ld 12, 0(12) ; CHECK-BE-NEXT: ld 12, 0(12)
; CHECK-NEXT: mtctr 12 ; CHECK-NEXT: mtctr 12
; CHECK-NEXT: bctrl ; CHECK-NEXT: bctrl
; CHECK-LE-NEXT: ld 2, 24(1) ; CHECK-LE-NEXT: ld 2, 24(1)
; CHECK-BE-NEXT: ld 2, 40(1) ; CHECK-BE-NEXT: ld 2, 40(1)
; CHECK: li 12, -8531 ; CHECK: li 12, -8531
; CHECK-NEXT: rldic 12, 12, 32, 16 ; CHECK-NEXT: clrlsldi 12, 12, 48, 32
; CHECK-NEXT: oris 12, 12, 48879 ; CHECK-NEXT: oris 12, 12, 48879
; CHECK-NEXT: ori 12, 12, 51967 ; CHECK-NEXT: ori 12, 12, 51967
; CHECK-LE-NEXT: std 2, 24(1) ; CHECK-LE-NEXT: std 2, 24(1)
; CHECK-BE-NEXT: std 2, 40(1) ; CHECK-BE-NEXT: std 2, 40(1)
; CHECK-BE-NEXT: ld 2, 8(12) ; CHECK-BE-NEXT: ld 2, 8(12)
; CHECK-BE-NEXT: ld 12, 0(12) ; CHECK-BE-NEXT: ld 12, 0(12)
; CHECK-NEXT: mtctr 12 ; CHECK-NEXT: mtctr 12
; CHECK-NEXT: bctrl ; CHECK-NEXT: bctrl
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llvm/test/CodeGen/PowerPC/ppc64le-aggregates.ll

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declare void @test0([7 x float], [7 x float]) declare void @test0([7 x float], [7 x float])
define float @callee1([8 x float] %a, [8 x float] %b) { define float @callee1([8 x float] %a, [8 x float] %b) {
entry: entry:
%b.extract = extractvalue [8 x float] %b, 7 %b.extract = extractvalue [8 x float] %b, 7
ret float %b.extract ret float %b.extract
} }
; CHECK-LABEL: @callee1 ; CHECK-LABEL: @callee1
; CHECK: rldicl [[REG:[0-9]+]], 10, 32, 32 ; CHECK: srdi [[REG:[0-9]+]], 10, 32
; CHECK: stw [[REG]], [[OFF:.*]](1) ; CHECK: stw [[REG]], [[OFF:.*]](1)
; CHECK: lfs 1, [[OFF]](1) ; CHECK: lfs 1, [[OFF]](1)
; CHECK: blr ; CHECK: blr
define void @caller1([8 x float] %a) { define void @caller1([8 x float] %a) {
entry: entry:
tail call void @test1([8 x float] %a, [8 x float] %a) tail call void @test1([8 x float] %a, [8 x float] %a)
ret void ret void
} }
; CHECK-LABEL: @caller1 ; CHECK-LABEL: @caller1
; CHECK-DAG: fmr 9, 1 ; CHECK-DAG: fmr 9, 1
; CHECK-DAG: fmr 10, 2 ; CHECK-DAG: fmr 10, 2
; CHECK-DAG: fmr 11, 3 ; CHECK-DAG: fmr 11, 3
; CHECK-DAG: fmr 12, 4 ; CHECK-DAG: fmr 12, 4
; CHECK-DAG: fmr 13, 5 ; CHECK-DAG: fmr 13, 5
; CHECK-DAG: stfs 5, [[OFF0:[0-9]+]](1) ; CHECK-DAG: stfs 5, [[OFF0:[0-9]+]](1)
; CHECK-DAG: stfs 6, [[OFF1:[0-9]+]](1) ; CHECK-DAG: stfs 6, [[OFF1:[0-9]+]](1)
; CHECK-DAG: stfs 7, [[OFF2:[0-9]+]](1) ; CHECK-DAG: stfs 7, [[OFF2:[0-9]+]](1)
; CHECK-DAG: stfs 8, [[OFF3:[0-9]+]](1) ; CHECK-DAG: stfs 8, [[OFF3:[0-9]+]](1)
; CHECK-DAG: lwz 9, [[OFF0]](1) ; CHECK-DAG: lwz 9, [[OFF0]](1)
; CHECK-DAG: lwz [[REG1:[0-9]+]], [[OFF1]](1) ; CHECK-DAG: lwz [[REG1:[0-9]+]], [[OFF1]](1)
; CHECK-DAG: lwz 10, [[OFF2]](1) ; CHECK-DAG: lwz 10, [[OFF2]](1)
; CHECK-DAG: lwz [[REG3:[0-9]+]], [[OFF3]](1) ; CHECK-DAG: lwz [[REG3:[0-9]+]], [[OFF3]](1)
; CHECK-DAG: rldimi 9, [[REG1]], 32, 0 ; CHECK-DAG: insrdi 9, [[REG1]], 32, 0
; CHECK-DAG: rldimi 10, [[REG3]], 32, 0 ; CHECK-DAG: insrdi 10, [[REG3]], 32, 0
; CHECK: bl test1 ; CHECK: bl test1
declare void @test1([8 x float], [8 x float]) declare void @test1([8 x float], [8 x float])
define float @callee2([8 x float] %a, [5 x float] %b, [2 x float] %c) { define float @callee2([8 x float] %a, [5 x float] %b, [2 x float] %c) {
entry: entry:
%c.extract = extractvalue [2 x float] %c, 1 %c.extract = extractvalue [2 x float] %c, 1
ret float %c.extract ret float %c.extract
} }
; CHECK-LABEL: @callee2 ; CHECK-LABEL: @callee2
; CHECK: rldicl [[REG:[0-9]+]], 10, 32, 32 ; CHECK: srdi [[REG:[0-9]+]], 10, 32
; CHECK: stw [[REG]], [[OFF:.*]](1) ; CHECK: stw [[REG]], [[OFF:.*]](1)
; CHECK: lfs 1, [[OFF]](1) ; CHECK: lfs 1, [[OFF]](1)
; CHECK: blr ; CHECK: blr
define void @caller2() { define void @caller2() {
entry: entry:
%0 = load [8 x float], [8 x float]* getelementptr inbounds (%struct.float8, %struct.float8* @g8, i64 0, i32 0), align 4 %0 = load [8 x float], [8 x float]* getelementptr inbounds (%struct.float8, %struct.float8* @g8, i64 0, i32 0), align 4
%1 = load [5 x float], [5 x float]* getelementptr inbounds (%struct.float5, %struct.float5* @g5, i64 0, i32 0), align 4 %1 = load [5 x float], [5 x float]* getelementptr inbounds (%struct.float5, %struct.float5* @g5, i64 0, i32 0), align 4
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llvm/test/CodeGen/PowerPC/pr30640.ll

; RUN: llc -O2 -mtriple=powerpc64-linux-gnu -mcpu=pwr8 < %s | FileCheck %s ; RUN: llc -O2 -mtriple=powerpc64-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
define i64 @foo() { define i64 @foo() {
entry: entry:
ret i64 -3617008641903833651 ret i64 -3617008641903833651
; CHECK: lis [[REG1:[0-9]+]], -12851 ; CHECK: lis [[REG1:[0-9]+]], -12851
; CHECK: ori [[REG2:[0-9]+]], [[REG1]], 52685 ; CHECK: ori [[REG2:[0-9]+]], [[REG1]], 52685
; CHECK: rldimi 3, 3, 32, 0 ; CHECK: insrdi 3, 3, 32, 0
} }

llvm/test/CodeGen/PowerPC/pr32140.ll

Show All 17 Lines
; CHECK-NEXT: stwbrx 3, 0, 4 ; CHECK-NEXT: stwbrx 3, 0, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-LE-LABEL: bswapStorei64Toi32: ; CHECK-LE-LABEL: bswapStorei64Toi32:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: addis 3, 2, ai@toc@ha ; CHECK-LE-NEXT: addis 3, 2, ai@toc@ha
; CHECK-LE-NEXT: addis 4, 2, bi@toc@ha ; CHECK-LE-NEXT: addis 4, 2, bi@toc@ha
; CHECK-LE-NEXT: lwa 3, ai@toc@l(3) ; CHECK-LE-NEXT: lwa 3, ai@toc@l(3)
; CHECK-LE-NEXT: addi 4, 4, bi@toc@l ; CHECK-LE-NEXT: addi 4, 4, bi@toc@l
; CHECK-LE-NEXT: rldicl 3, 3, 32, 32 ; CHECK-LE-NEXT: srdi 3, 3, 32
; CHECK-LE-NEXT: stwbrx 3, 0, 4 ; CHECK-LE-NEXT: stwbrx 3, 0, 4
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
; ;
; CHECK-BE-LABEL: bswapStorei64Toi32: ; CHECK-BE-LABEL: bswapStorei64Toi32:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis 3, 2, .LC0@toc@ha ; CHECK-BE-NEXT: addis 3, 2, .LC0@toc@ha
; CHECK-BE-NEXT: addis 4, 2, .LC1@toc@ha ; CHECK-BE-NEXT: addis 4, 2, .LC1@toc@ha
; CHECK-BE-NEXT: ld 3, .LC0@toc@l(3) ; CHECK-BE-NEXT: ld 3, .LC0@toc@l(3)
; CHECK-BE-NEXT: ld 4, .LC1@toc@l(4) ; CHECK-BE-NEXT: ld 4, .LC1@toc@l(4)
; CHECK-BE-NEXT: lwa 3, 0(3) ; CHECK-BE-NEXT: lwa 3, 0(3)
; CHECK-BE-NEXT: rldicl 3, 3, 32, 32 ; CHECK-BE-NEXT: srdi 3, 3, 32
; CHECK-BE-NEXT: stwbrx 3, 0, 4 ; CHECK-BE-NEXT: stwbrx 3, 0, 4
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = load i32, i32* @ai, align 4 %0 = load i32, i32* @ai, align 4
%conv.i = sext i32 %0 to i64 %conv.i = sext i32 %0 to i64
%or26.i = tail call i64 @llvm.bswap.i64(i64 %conv.i) %or26.i = tail call i64 @llvm.bswap.i64(i64 %conv.i)
%conv = trunc i64 %or26.i to i32 %conv = trunc i64 %or26.i to i32
store i32 %conv, i32* @bi, align 4 store i32 %conv, i32* @bi, align 4
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; CHECK-NEXT: sthbrx 3, 0, 4 ; CHECK-NEXT: sthbrx 3, 0, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-LE-LABEL: bswapStorei64Toi16: ; CHECK-LE-LABEL: bswapStorei64Toi16:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: addis 3, 2, as@toc@ha ; CHECK-LE-NEXT: addis 3, 2, as@toc@ha
; CHECK-LE-NEXT: addis 4, 2, bs@toc@ha ; CHECK-LE-NEXT: addis 4, 2, bs@toc@ha
; CHECK-LE-NEXT: lha 3, as@toc@l(3) ; CHECK-LE-NEXT: lha 3, as@toc@l(3)
; CHECK-LE-NEXT: addi 4, 4, bs@toc@l ; CHECK-LE-NEXT: addi 4, 4, bs@toc@l
; CHECK-LE-NEXT: rldicl 3, 3, 16, 48 ; CHECK-LE-NEXT: srdi 3, 3, 48
; CHECK-LE-NEXT: sthbrx 3, 0, 4 ; CHECK-LE-NEXT: sthbrx 3, 0, 4
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
; ;
; CHECK-BE-LABEL: bswapStorei64Toi16: ; CHECK-BE-LABEL: bswapStorei64Toi16:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis 3, 2, .LC2@toc@ha ; CHECK-BE-NEXT: addis 3, 2, .LC2@toc@ha
; CHECK-BE-NEXT: addis 4, 2, .LC3@toc@ha ; CHECK-BE-NEXT: addis 4, 2, .LC3@toc@ha
; CHECK-BE-NEXT: ld 3, .LC2@toc@l(3) ; CHECK-BE-NEXT: ld 3, .LC2@toc@l(3)
; CHECK-BE-NEXT: ld 4, .LC3@toc@l(4) ; CHECK-BE-NEXT: ld 4, .LC3@toc@l(4)
; CHECK-BE-NEXT: lha 3, 0(3) ; CHECK-BE-NEXT: lha 3, 0(3)
; CHECK-BE-NEXT: rldicl 3, 3, 16, 48 ; CHECK-BE-NEXT: srdi 3, 3, 48
; CHECK-BE-NEXT: sthbrx 3, 0, 4 ; CHECK-BE-NEXT: sthbrx 3, 0, 4
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = load i16, i16* @as, align 2 %0 = load i16, i16* @as, align 2
%conv.i = sext i16 %0 to i64 %conv.i = sext i16 %0 to i64
%or26.i = tail call i64 @llvm.bswap.i64(i64 %conv.i) %or26.i = tail call i64 @llvm.bswap.i64(i64 %conv.i)
%conv = trunc i64 %or26.i to i16 %conv = trunc i64 %or26.i to i16
store i16 %conv, i16* @bs, align 2 store i16 %conv, i16* @bs, align 2
ret void ret void
} }
declare i32 @llvm.bswap.i32(i32) declare i32 @llvm.bswap.i32(i32)
declare i64 @llvm.bswap.i64(i64) declare i64 @llvm.bswap.i64(i64)

llvm/test/CodeGen/PowerPC/pr33093.ll

Show All 28 Lines
; CHECK-NEXT: slwi 6, 3, 4 ; CHECK-NEXT: slwi 6, 3, 4
; CHECK-NEXT: ori 4, 4, 61680 ; CHECK-NEXT: ori 4, 4, 61680
; CHECK-NEXT: srwi 3, 3, 4 ; CHECK-NEXT: srwi 3, 3, 4
; CHECK-NEXT: and 4, 6, 4 ; CHECK-NEXT: and 4, 6, 4
; CHECK-NEXT: and 3, 3, 5 ; CHECK-NEXT: and 3, 3, 5
; CHECK-NEXT: or 3, 3, 4 ; CHECK-NEXT: or 3, 3, 4
; CHECK-NEXT: rotlwi 4, 3, 24 ; CHECK-NEXT: rotlwi 4, 3, 24
; CHECK-NEXT: rlwimi 4, 3, 8, 8, 15 ; CHECK-NEXT: rlwimi 4, 3, 8, 8, 15
; CHECK-NEXT: rlwimi 4, 3, 8, 24, 31 ; CHECK-NEXT: inslwi 4, 3, 8, 24
; CHECK-NEXT: rldicl 3, 4, 0, 32 ; CHECK-NEXT: rldicl 3, 4, 0, 32
; CHECK-NEXT: clrldi 3, 3, 32 ; CHECK-NEXT: clrldi 3, 3, 32
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%shr = lshr i32 %n, 1 %shr = lshr i32 %n, 1
%and = and i32 %shr, 1431655765 %and = and i32 %shr, 1431655765
%and1 = shl i32 %n, 1 %and1 = shl i32 %n, 1
%shl = and i32 %and1, -1431655766 %shl = and i32 %and1, -1431655766
Show All 31 Lines
; CHECK-NEXT: ori 5, 5, 21845 ; CHECK-NEXT: ori 5, 5, 21845
; CHECK-NEXT: ori 7, 7, 52428 ; CHECK-NEXT: ori 7, 7, 52428
; CHECK-NEXT: ori 8, 8, 13107 ; CHECK-NEXT: ori 8, 8, 13107
; CHECK-NEXT: sldi 4, 4, 32 ; CHECK-NEXT: sldi 4, 4, 32
; CHECK-NEXT: sldi 5, 5, 32 ; CHECK-NEXT: sldi 5, 5, 32
; CHECK-NEXT: oris 4, 4, 43690 ; CHECK-NEXT: oris 4, 4, 43690
; CHECK-NEXT: oris 5, 5, 21845 ; CHECK-NEXT: oris 5, 5, 21845
; CHECK-NEXT: sldi 6, 3, 1 ; CHECK-NEXT: sldi 6, 3, 1
; CHECK-NEXT: rldicl 3, 3, 63, 1 ; CHECK-NEXT: srdi 3, 3, 1
; CHECK-NEXT: ori 4, 4, 43690 ; CHECK-NEXT: ori 4, 4, 43690
; CHECK-NEXT: ori 5, 5, 21845 ; CHECK-NEXT: ori 5, 5, 21845
; CHECK-NEXT: sldi 7, 7, 32 ; CHECK-NEXT: sldi 7, 7, 32
; CHECK-NEXT: sldi 8, 8, 32 ; CHECK-NEXT: sldi 8, 8, 32
; CHECK-NEXT: and 4, 6, 4 ; CHECK-NEXT: and 4, 6, 4
; CHECK-NEXT: and 3, 3, 5 ; CHECK-NEXT: and 3, 3, 5
; CHECK-NEXT: lis 5, -3856 ; CHECK-NEXT: lis 5, -3856
; CHECK-NEXT: oris 6, 7, 52428 ; CHECK-NEXT: oris 6, 7, 52428
; CHECK-NEXT: oris 7, 8, 13107 ; CHECK-NEXT: oris 7, 8, 13107
; CHECK-NEXT: or 3, 3, 4 ; CHECK-NEXT: or 3, 3, 4
; CHECK-NEXT: lis 4, 3855 ; CHECK-NEXT: lis 4, 3855
; CHECK-NEXT: ori 5, 5, 61680 ; CHECK-NEXT: ori 5, 5, 61680
; CHECK-NEXT: ori 6, 6, 52428 ; CHECK-NEXT: ori 6, 6, 52428
; CHECK-NEXT: ori 7, 7, 13107 ; CHECK-NEXT: ori 7, 7, 13107
; CHECK-NEXT: ori 4, 4, 3855 ; CHECK-NEXT: ori 4, 4, 3855
; CHECK-NEXT: sldi 8, 3, 2 ; CHECK-NEXT: sldi 8, 3, 2
; CHECK-NEXT: rldicl 3, 3, 62, 2 ; CHECK-NEXT: srdi 3, 3, 2
; CHECK-NEXT: and 6, 8, 6 ; CHECK-NEXT: and 6, 8, 6
; CHECK-NEXT: and 3, 3, 7 ; CHECK-NEXT: and 3, 3, 7
; CHECK-NEXT: sldi 5, 5, 32 ; CHECK-NEXT: sldi 5, 5, 32
; CHECK-NEXT: sldi 4, 4, 32 ; CHECK-NEXT: sldi 4, 4, 32
; CHECK-NEXT: or 3, 3, 6 ; CHECK-NEXT: or 3, 3, 6
; CHECK-NEXT: oris 5, 5, 61680 ; CHECK-NEXT: oris 5, 5, 61680
; CHECK-NEXT: oris 4, 4, 3855 ; CHECK-NEXT: oris 4, 4, 3855
; CHECK-NEXT: sldi 6, 3, 4 ; CHECK-NEXT: sldi 6, 3, 4
; CHECK-NEXT: ori 5, 5, 61680 ; CHECK-NEXT: ori 5, 5, 61680
; CHECK-NEXT: ori 4, 4, 3855 ; CHECK-NEXT: ori 4, 4, 3855
; CHECK-NEXT: rldicl 3, 3, 60, 4 ; CHECK-NEXT: srdi 3, 3, 4
; CHECK-NEXT: and 5, 6, 5 ; CHECK-NEXT: and 5, 6, 5
; CHECK-NEXT: and 3, 3, 4 ; CHECK-NEXT: and 3, 3, 4
; CHECK-NEXT: or 3, 3, 5 ; CHECK-NEXT: or 3, 3, 5
; CHECK-NEXT: rldicl 4, 3, 32, 32 ; CHECK-NEXT: srdi 4, 3, 32
; CHECK-NEXT: rotlwi 5, 3, 24 ; CHECK-NEXT: rotlwi 5, 3, 24
; CHECK-NEXT: rotlwi 6, 4, 24 ; CHECK-NEXT: rotlwi 6, 4, 24
; CHECK-NEXT: rlwimi 5, 3, 8, 8, 15 ; CHECK-NEXT: rlwimi 5, 3, 8, 8, 15
; CHECK-NEXT: rlwimi 5, 3, 8, 24, 31 ; CHECK-NEXT: inslwi 5, 3, 8, 24
; CHECK-NEXT: rlwimi 6, 4, 8, 8, 15 ; CHECK-NEXT: rlwimi 6, 4, 8, 8, 15
; CHECK-NEXT: rlwimi 6, 4, 8, 24, 31 ; CHECK-NEXT: inslwi 6, 4, 8, 24
; CHECK-NEXT: sldi 3, 5, 32 ; CHECK-NEXT: sldi 3, 5, 32
; CHECK-NEXT: or 3, 3, 6 ; CHECK-NEXT: or 3, 3, 6
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%shr = lshr i64 %n, 1 %shr = lshr i64 %n, 1
%and = and i64 %shr, 6148914691236517205 %and = and i64 %shr, 6148914691236517205
%and1 = shl i64 %n, 1 %and1 = shl i64 %n, 1
%shl = and i64 %and1, -6148914691236517206 %shl = and i64 %and1, -6148914691236517206
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llvm/test/CodeGen/PowerPC/pr41088.ll

Show First 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
; CHECK-NEXT: std r0, 16(r1) ; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -32(r1) ; CHECK-NEXT: stdu r1, -32(r1)
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset lr, 16 ; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: li r3, 0 ; CHECK-NEXT: li r3, 0
; CHECK-NEXT: # %bb.1: # %bb9 ; CHECK-NEXT: # %bb.1: # %bb9
; CHECK-NEXT: bl test5 ; CHECK-NEXT: bl test5
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: rlwinm r3, r3, 8, 16, 23 ; CHECK-NEXT: clrlslwi r3, r3, 24, 8
; CHECK-NEXT: # %bb.2: # %bb12 ; CHECK-NEXT: # %bb.2: # %bb12
; CHECK-NEXT: clrldi r4, r3, 32 ; CHECK-NEXT: clrldi r4, r3, 32
; CHECK-NEXT: bl test3 ; CHECK-NEXT: bl test3
; CHECK-NEXT: addi r1, r1, 32 ; CHECK-NEXT: addi r1, r1, 32
; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
bb: bb:
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llvm/test/CodeGen/PowerPC/pr44183.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s ; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s
%struct.m.2.5.8.11 = type { %struct.l.0.3.6.9, [7 x i8], %struct.a.1.4.7.10 } %struct.m.2.5.8.11 = type { %struct.l.0.3.6.9, [7 x i8], %struct.a.1.4.7.10 }
%struct.l.0.3.6.9 = type { i8 } %struct.l.0.3.6.9 = type { i8 }
%struct.a.1.4.7.10 = type { [27 x i8], [0 x i32], [4 x i8] } %struct.a.1.4.7.10 = type { [27 x i8], [0 x i32], [4 x i8] }
define void @_ZN1m1nEv(%struct.m.2.5.8.11* %this) local_unnamed_addr nounwind align 2 { define void @_ZN1m1nEv(%struct.m.2.5.8.11* %this) local_unnamed_addr nounwind align 2 {
; CHECK-LABEL: _ZN1m1nEv: ; CHECK-LABEL: _ZN1m1nEv:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-NEXT: std r0, 16(r1) ; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -48(r1) ; CHECK-NEXT: stdu r1, -48(r1)
; CHECK-NEXT: mr r30, r3 ; CHECK-NEXT: mr r30, r3
; CHECK-NEXT: ld r4, 8(r30) ; CHECK-NEXT: ld r4, 8(r30)
; CHECK-NEXT: lwz r5, 36(r30) ; CHECK-NEXT: lwz r5, 36(r30)
; CHECK-NEXT: rldicl r4, r4, 60, 4 ; CHECK-NEXT: srdi r4, r4, 4
; CHECK-NEXT: rlwinm r3, r4, 31, 0, 0 ; CHECK-NEXT: slwi r3, r4, 31
; CHECK-NEXT: clrlwi r4, r5, 31 ; CHECK-NEXT: clrlwi r4, r5, 31
; CHECK-NEXT: or r4, r4, r3 ; CHECK-NEXT: or r4, r4, r3
; CHECK-NEXT: bl _ZN1llsE1d ; CHECK-NEXT: bl _ZN1llsE1d
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: ld r3, 16(r30) ; CHECK-NEXT: ld r3, 16(r30)
; CHECK-NEXT: ld r4, 8(r30) ; CHECK-NEXT: ld r4, 8(r30)
; CHECK-NEXT: rldicl r4, r4, 60, 4 ; CHECK-NEXT: srdi r4, r4, 4
; CHECK-NEXT: sldi r3, r3, 60 ; CHECK-NEXT: sldi r3, r3, 60
; CHECK-NEXT: or r3, r4, r3 ; CHECK-NEXT: or r3, r4, r3
; CHECK-NEXT: sldi r3, r3, 31 ; CHECK-NEXT: sldi r3, r3, 31
; CHECK-NEXT: clrldi r4, r3, 32 ; CHECK-NEXT: clrldi r4, r3, 32
; CHECK-NEXT: bl _ZN1llsE1d ; CHECK-NEXT: bl _ZN1llsE1d
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: addi r1, r1, 48 ; CHECK-NEXT: addi r1, r1, 48
; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: ld r0, 16(r1)
Show All 23 Lines

llvm/test/CodeGen/PowerPC/rlwimi-and.ll

Show All 24 LinescodeRepl17: ; preds = %codeRepl4
%not.tobool.i.1.i.i = icmp eq i8 %4, 0 %not.tobool.i.1.i.i = icmp eq i8 %4, 0
%rvml38.sroa.1.1.insert.ext = select i1 %not.tobool.i.1.i.i, i16 0, i16 1 %rvml38.sroa.1.1.insert.ext = select i1 %not.tobool.i.1.i.i, i16 0, i16 1
%rvml38.sroa.0.0.insert.insert = or i16 %rvml38.sroa.1.1.insert.ext, %2 %rvml38.sroa.0.0.insert.insert = or i16 %rvml38.sroa.1.1.insert.ext, %2
store i16 %rvml38.sroa.0.0.insert.insert, i16* undef, align 2 store i16 %rvml38.sroa.0.0.insert.insert, i16* undef, align 2
unreachable unreachable
; CHECK: @test ; CHECK: @test
; CHECK: clrlwi [[R1:[0-9]+]], {{[0-9]+}}, 31 ; CHECK: clrlwi [[R1:[0-9]+]], {{[0-9]+}}, 31
; CHECK: rlwimi [[R1]], {{[0-9]+}}, 8, 23, 23 ; CHECK: insrwi [[R1]], {{[0-9]+}}, 1, 23
codeRepl29: ; preds = %codeRepl1 codeRepl29: ; preds = %codeRepl1
unreachable unreachable
codeRepl31: ; preds = %entry codeRepl31: ; preds = %entry
ret void ret void
} }

llvm/test/CodeGen/PowerPC/rlwimi-dyn-and.ll

Show All 33 Linesnext:
%0 = load i8, i8* undef, align 1 %0 = load i8, i8* undef, align 1
%conv169 = zext i8 %0 to i32 %conv169 = zext i8 %0 to i32
%shl170 = shl nuw nsw i32 %conv169, 7 %shl170 = shl nuw nsw i32 %conv169, 7
%shl161.masked = and i32 %shl161, 32768 %shl161.masked = and i32 %shl161, 32768
%conv174 = or i32 %shl170, %shl161.masked %conv174 = or i32 %shl170, %shl161.masked
ret i32 %conv174 ret i32 %conv174
; CHECK-LABEL: @test2 ; CHECK-LABEL: @test2
; CHECK: rlwinm 3, {{[0-9]+}}, 7, 17, 24 ; CHECK: clrlslwi 3, {{[0-9]+}}, 24, 7
; CHECK: rlwimi 3, {{[0-9]+}}, 15, 16, 16 ; CHECK: insrwi 3, {{[0-9]+}}, 1, 16
; CHECK: blr ; CHECK: blr
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }

llvm/test/CodeGen/PowerPC/rlwimi-keep-rsh.ll

; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu | FileCheck %s ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu | FileCheck %s
; Formerly dropped the RHS of %tmp6 when constructing rlwimi. ; Formerly dropped the RHS of %tmp6 when constructing rlwimi.
; 7346117 ; 7346117
@foo = external global i32 @foo = external global i32
define void @xxx(i32 %a, i32 %b, i32 %c, i32 %d) nounwind optsize { define void @xxx(i32 %a, i32 %b, i32 %c, i32 %d) nounwind optsize {
; CHECK: xxx: ; CHECK: xxx:
; CHECK: or ; CHECK: or
; CHECK: and ; CHECK: and
; CHECK: rlwimi ; CHECK: insrwi
entry: entry:
%tmp0 = ashr i32 %d, 31 %tmp0 = ashr i32 %d, 31
%tmp1 = and i32 %tmp0, 255 %tmp1 = and i32 %tmp0, 255
%tmp2 = xor i32 %tmp1, 255 %tmp2 = xor i32 %tmp1, 255
%tmp3 = ashr i32 %b, 31 %tmp3 = ashr i32 %b, 31
%tmp4 = ashr i32 %a, 4 %tmp4 = ashr i32 %a, 4
%tmp5 = or i32 %tmp3, %tmp4 %tmp5 = or i32 %tmp3, %tmp4
%tmp6 = and i32 %tmp2, %tmp5 %tmp6 = and i32 %tmp2, %tmp5
Show All 9 Lines

llvm/test/CodeGen/PowerPC/rlwimi.ll

; All of these ands and shifts should be folded into rlwimi's ; All of these ands and shifts should be folded into rlwimi's
; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | not grep and ; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | not grep and
; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | grep rlwimi | count 8 ; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | grep rlwimi | count 2
; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | grep inslwi | count 2
; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | grep insrwi | count 4
define i32 @test1(i32 %x, i32 %y) { define i32 @test1(i32 %x, i32 %y) {
entry: entry:
%tmp.3 = shl i32 %x, 16 ; <i32> [#uses=1] %tmp.3 = shl i32 %x, 16 ; <i32> [#uses=1]
%tmp.7 = and i32 %y, 65535 ; <i32> [#uses=1] %tmp.7 = and i32 %y, 65535 ; <i32> [#uses=1]
%tmp.9 = or i32 %tmp.7, %tmp.3 ; <i32> [#uses=1] %tmp.9 = or i32 %tmp.7, %tmp.3 ; <i32> [#uses=1]
ret i32 %tmp.9 ret i32 %tmp.9
} }
▲ Show 20 Lines • Show All 59 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/rlwinm.ll

; All of these ands and shifts should be folded into rlwimi's ; All of these ands and shifts should be folded into rlwimi's
; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -o %t ; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -o %t
; RUN: not grep and %t ; RUN: not grep and %t
; RUN: not grep srawi %t ; RUN: not grep srawi %t
; RUN: not grep srwi %t ; RUN: not grep srwi %t
; RUN: not grep slwi %t ; RUN: not grep slwi %t
; RUN: grep rlwinm %t | count 8 ; RUN: grep extrwi %t | count 4
; RUN: grep extlwi %t | count 2
; RUN: grep rlwinm %t | count 2
define i32 @test1(i32 %a) { define i32 @test1(i32 %a) {
entry: entry:
%tmp.1 = and i32 %a, 268431360 ; <i32> [#uses=1] %tmp.1 = and i32 %a, 268431360 ; <i32> [#uses=1]
ret i32 %tmp.1 ret i32 %tmp.1
} }
define i32 @test2(i32 %a) { define i32 @test2(i32 %a) {
▲ Show 20 Lines • Show All 46 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/sched-addi.ll

Show All 10 Lines
define void @test([0 x %_elem_type_of_x]* noalias %.x, [0 x %_elem_type_of_a]* %.a, i64* noalias %.n) { define void @test([0 x %_elem_type_of_x]* noalias %.x, [0 x %_elem_type_of_a]* %.a, i64* noalias %.n) {
; CHECK-P9-LABEL: test: ; CHECK-P9-LABEL: test:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: ld 5, 0(5) ; CHECK-P9-NEXT: ld 5, 0(5)
; CHECK-P9-NEXT: addis 6, 2, scalars@toc@ha ; CHECK-P9-NEXT: addis 6, 2, scalars@toc@ha
; CHECK-P9-NEXT: addi 6, 6, scalars@toc@l ; CHECK-P9-NEXT: addi 6, 6, scalars@toc@l
; CHECK-P9-NEXT: addi 6, 6, 16 ; CHECK-P9-NEXT: addi 6, 6, 16
; CHECK-P9-NEXT: rldicr 5, 5, 0, 58 ; CHECK-P9-NEXT: clrrdi 5, 5, 5
; CHECK-P9-NEXT: addi 5, 5, -32 ; CHECK-P9-NEXT: addi 5, 5, -32
; CHECK-P9-NEXT: rldicl 5, 5, 59, 5 ; CHECK-P9-NEXT: srdi 5, 5, 5
; CHECK-P9-NEXT: addi 5, 5, 1 ; CHECK-P9-NEXT: addi 5, 5, 1
; CHECK-P9-NEXT: lxvdsx 0, 0, 6 ; CHECK-P9-NEXT: lxvdsx 0, 0, 6
; CHECK-P9-NEXT: mtctr 5 ; CHECK-P9-NEXT: mtctr 5
; CHECK-P9-NEXT: .p2align 4 ; CHECK-P9-NEXT: .p2align 4
; CHECK-P9-NEXT: .LBB0_1: # %vector.body ; CHECK-P9-NEXT: .LBB0_1: # %vector.body
; CHECK-P9-NEXT: # ; CHECK-P9-NEXT: #
; CHECK-P9-NEXT: lxv 1, 16(4) ; CHECK-P9-NEXT: lxv 1, 16(4)
; CHECK-P9-NEXT: lxv 2, 0(4) ; CHECK-P9-NEXT: lxv 2, 0(4)
Show All 19 Lines
; CHECK-P9-NEXT: # %bb.2: # %return.block ; CHECK-P9-NEXT: # %bb.2: # %return.block
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-P9-NO-HEURISTIC-LABEL: test: ; CHECK-P9-NO-HEURISTIC-LABEL: test:
; CHECK-P9-NO-HEURISTIC: # %bb.0: # %entry ; CHECK-P9-NO-HEURISTIC: # %bb.0: # %entry
; CHECK-P9-NO-HEURISTIC-NEXT: ld 5, 0(5) ; CHECK-P9-NO-HEURISTIC-NEXT: ld 5, 0(5)
; CHECK-P9-NO-HEURISTIC-NEXT: addis 6, 2, scalars@toc@ha ; CHECK-P9-NO-HEURISTIC-NEXT: addis 6, 2, scalars@toc@ha
; CHECK-P9-NO-HEURISTIC-NEXT: addi 6, 6, scalars@toc@l ; CHECK-P9-NO-HEURISTIC-NEXT: addi 6, 6, scalars@toc@l
; CHECK-P9-NO-HEURISTIC-NEXT: rldicr 5, 5, 0, 58 ; CHECK-P9-NO-HEURISTIC-NEXT: clrrdi 5, 5, 5
; CHECK-P9-NO-HEURISTIC-NEXT: addi 6, 6, 16 ; CHECK-P9-NO-HEURISTIC-NEXT: addi 6, 6, 16
; CHECK-P9-NO-HEURISTIC-NEXT: addi 5, 5, -32 ; CHECK-P9-NO-HEURISTIC-NEXT: addi 5, 5, -32
; CHECK-P9-NO-HEURISTIC-NEXT: rldicl 5, 5, 59, 5 ; CHECK-P9-NO-HEURISTIC-NEXT: srdi 5, 5, 5
; CHECK-P9-NO-HEURISTIC-NEXT: addi 5, 5, 1 ; CHECK-P9-NO-HEURISTIC-NEXT: addi 5, 5, 1
; CHECK-P9-NO-HEURISTIC-NEXT: lxvdsx 0, 0, 6 ; CHECK-P9-NO-HEURISTIC-NEXT: lxvdsx 0, 0, 6
; CHECK-P9-NO-HEURISTIC-NEXT: mtctr 5 ; CHECK-P9-NO-HEURISTIC-NEXT: mtctr 5
; CHECK-P9-NO-HEURISTIC-NEXT: .p2align 4 ; CHECK-P9-NO-HEURISTIC-NEXT: .p2align 4
; CHECK-P9-NO-HEURISTIC-NEXT: .LBB0_1: # %vector.body ; CHECK-P9-NO-HEURISTIC-NEXT: .LBB0_1: # %vector.body
; CHECK-P9-NO-HEURISTIC-NEXT: # ; CHECK-P9-NO-HEURISTIC-NEXT: #
; CHECK-P9-NO-HEURISTIC-NEXT: lxv 1, 16(4) ; CHECK-P9-NO-HEURISTIC-NEXT: lxv 1, 16(4)
; CHECK-P9-NO-HEURISTIC-NEXT: lxv 2, 0(4) ; CHECK-P9-NO-HEURISTIC-NEXT: lxv 2, 0(4)
▲ Show 20 Lines • Show All 93 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/setcc-logic.ll

Show First 20 Lines • Show All 479 Lines • ▼ Show 20 Lines
define i1 @or_icmps_const_1bit_diff(i64 %x) { define i1 @or_icmps_const_1bit_diff(i64 %x) {
; CHECK-LABEL: or_icmps_const_1bit_diff: ; CHECK-LABEL: or_icmps_const_1bit_diff:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi 3, 3, -13 ; CHECK-NEXT: addi 3, 3, -13
; CHECK-NEXT: rldicl 3, 3, 61, 1 ; CHECK-NEXT: rldicl 3, 3, 61, 1
; CHECK-NEXT: rotldi 3, 3, 3 ; CHECK-NEXT: rotldi 3, 3, 3
; CHECK-NEXT: cntlzd 3, 3 ; CHECK-NEXT: cntlzd 3, 3
; CHECK-NEXT: rldicl 3, 3, 58, 63 ; CHECK-NEXT: extrdi 3, 3, 1, 57
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%a = icmp eq i64 %x, 17 %a = icmp eq i64 %x, 17
%b = icmp eq i64 %x, 13 %b = icmp eq i64 %x, 13
%r = or i1 %a, %b %r = or i1 %a, %b
ret i1 %r ret i1 %r
} }
define i1 @and_icmps_const_1bit_diff(i32 %x) { define i1 @and_icmps_const_1bit_diff(i32 %x) {
; CHECK-LABEL: and_icmps_const_1bit_diff: ; CHECK-LABEL: and_icmps_const_1bit_diff:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi 3, 3, -4625 ; CHECK-NEXT: addi 3, 3, -4625
; CHECK-NEXT: rlwinm 3, 3, 0, 28, 26 ; CHECK-NEXT: rlwinm 3, 3, 0, 28, 26
; CHECK-NEXT: cntlzw 3, 3 ; CHECK-NEXT: cntlzw 3, 3
; CHECK-NEXT: not 3, 3 ; CHECK-NEXT: not 3, 3
; CHECK-NEXT: rlwinm 3, 3, 27, 31, 31 ; CHECK-NEXT: extrwi 3, 3, 1, 26
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%a = icmp ne i32 %x, 4625 %a = icmp ne i32 %x, 4625
%b = icmp ne i32 %x, 4641 %b = icmp ne i32 %x, 4641
%r = and i1 %a, %b %r = and i1 %a, %b
ret i1 %r ret i1 %r
} }

llvm/test/CodeGen/PowerPC/setcc-to-sub.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr8 < %s | FileCheck %s ; RUN: -mcpu=pwr8 < %s | FileCheck %s
%class.PB2 = type { [1 x i32], %class.PB1* } %class.PB2 = type { [1 x i32], %class.PB1* }
%class.PB1 = type { [1 x i32], i64, i64, i32 } %class.PB1 = type { [1 x i32], i64, i64, i32 }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define zeroext i1 @test1(%class.PB2* %s_a, %class.PB2* %s_b) local_unnamed_addr #0 { define zeroext i1 @test1(%class.PB2* %s_a, %class.PB2* %s_b) local_unnamed_addr #0 {
; CHECK-LABEL: test1: ; CHECK-LABEL: test1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lwz 3, 0(3) ; CHECK-NEXT: lwz 3, 0(3)
; CHECK-NEXT: lwz 4, 0(4) ; CHECK-NEXT: lwz 4, 0(4)
; CHECK-NEXT: rlwinm 3, 3, 0, 28, 28 ; CHECK-NEXT: rlwinm 3, 3, 0, 28, 28
; CHECK-NEXT: rlwinm 4, 4, 0, 28, 28 ; CHECK-NEXT: rlwinm 4, 4, 0, 28, 28
; CHECK-NEXT: sub 3, 3, 4 ; CHECK-NEXT: sub 3, 3, 4
; CHECK-NEXT: rldicl 3, 3, 1, 63 ; CHECK-NEXT: srdi 3, 3, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%arrayidx.i6 = bitcast %class.PB2* %s_a to i32* %arrayidx.i6 = bitcast %class.PB2* %s_a to i32*
%0 = load i32, i32* %arrayidx.i6, align 8, !tbaa !1 %0 = load i32, i32* %arrayidx.i6, align 8, !tbaa !1
%and.i = and i32 %0, 8 %and.i = and i32 %0, 8
%arrayidx.i37 = bitcast %class.PB2* %s_b to i32* %arrayidx.i37 = bitcast %class.PB2* %s_b to i32*
%1 = load i32, i32* %arrayidx.i37, align 8, !tbaa !1 %1 = load i32, i32* %arrayidx.i37, align 8, !tbaa !1
%and.i4 = and i32 %1, 8 %and.i4 = and i32 %1, 8
%cmp.i5 = icmp ult i32 %and.i, %and.i4 %cmp.i5 = icmp ult i32 %and.i, %and.i4
ret i1 %cmp.i5 ret i1 %cmp.i5
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define zeroext i1 @test2(%class.PB2* %s_a, %class.PB2* %s_b) local_unnamed_addr #0 { define zeroext i1 @test2(%class.PB2* %s_a, %class.PB2* %s_b) local_unnamed_addr #0 {
; CHECK-LABEL: test2: ; CHECK-LABEL: test2:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lwz 3, 0(3) ; CHECK-NEXT: lwz 3, 0(3)
; CHECK-NEXT: lwz 4, 0(4) ; CHECK-NEXT: lwz 4, 0(4)
; CHECK-NEXT: rlwinm 3, 3, 0, 28, 28 ; CHECK-NEXT: rlwinm 3, 3, 0, 28, 28
; CHECK-NEXT: rlwinm 4, 4, 0, 28, 28 ; CHECK-NEXT: rlwinm 4, 4, 0, 28, 28
; CHECK-NEXT: sub 3, 4, 3 ; CHECK-NEXT: sub 3, 4, 3
; CHECK-NEXT: not 3, 3 ; CHECK-NEXT: not 3, 3
; CHECK-NEXT: rldicl 3, 3, 1, 63 ; CHECK-NEXT: srdi 3, 3, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%arrayidx.i6 = bitcast %class.PB2* %s_a to i32* %arrayidx.i6 = bitcast %class.PB2* %s_a to i32*
%0 = load i32, i32* %arrayidx.i6, align 8, !tbaa !1 %0 = load i32, i32* %arrayidx.i6, align 8, !tbaa !1
%and.i = and i32 %0, 8 %and.i = and i32 %0, 8
%arrayidx.i37 = bitcast %class.PB2* %s_b to i32* %arrayidx.i37 = bitcast %class.PB2* %s_b to i32*
%1 = load i32, i32* %arrayidx.i37, align 8, !tbaa !1 %1 = load i32, i32* %arrayidx.i37, align 8, !tbaa !1
%and.i4 = and i32 %1, 8 %and.i4 = and i32 %1, 8
%cmp.i5 = icmp ule i32 %and.i, %and.i4 %cmp.i5 = icmp ule i32 %and.i, %and.i4
ret i1 %cmp.i5 ret i1 %cmp.i5
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define zeroext i1 @test3(%class.PB2* %s_a, %class.PB2* %s_b) local_unnamed_addr #0 { define zeroext i1 @test3(%class.PB2* %s_a, %class.PB2* %s_b) local_unnamed_addr #0 {
; CHECK-LABEL: test3: ; CHECK-LABEL: test3:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lwz 3, 0(3) ; CHECK-NEXT: lwz 3, 0(3)
; CHECK-NEXT: lwz 4, 0(4) ; CHECK-NEXT: lwz 4, 0(4)
; CHECK-NEXT: rlwinm 3, 3, 0, 28, 28 ; CHECK-NEXT: rlwinm 3, 3, 0, 28, 28
; CHECK-NEXT: rlwinm 4, 4, 0, 28, 28 ; CHECK-NEXT: rlwinm 4, 4, 0, 28, 28
; CHECK-NEXT: sub 3, 4, 3 ; CHECK-NEXT: sub 3, 4, 3
; CHECK-NEXT: rldicl 3, 3, 1, 63 ; CHECK-NEXT: srdi 3, 3, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%arrayidx.i6 = bitcast %class.PB2* %s_a to i32* %arrayidx.i6 = bitcast %class.PB2* %s_a to i32*
%0 = load i32, i32* %arrayidx.i6, align 8, !tbaa !1 %0 = load i32, i32* %arrayidx.i6, align 8, !tbaa !1
%and.i = and i32 %0, 8 %and.i = and i32 %0, 8
%arrayidx.i37 = bitcast %class.PB2* %s_b to i32* %arrayidx.i37 = bitcast %class.PB2* %s_b to i32*
%1 = load i32, i32* %arrayidx.i37, align 8, !tbaa !1 %1 = load i32, i32* %arrayidx.i37, align 8, !tbaa !1
%and.i4 = and i32 %1, 8 %and.i4 = and i32 %1, 8
%cmp.i5 = icmp ugt i32 %and.i, %and.i4 %cmp.i5 = icmp ugt i32 %and.i, %and.i4
ret i1 %cmp.i5 ret i1 %cmp.i5
} }
; Function Attrs: norecurse nounwind readonly ; Function Attrs: norecurse nounwind readonly
define zeroext i1 @test4(%class.PB2* %s_a, %class.PB2* %s_b) local_unnamed_addr #0 { define zeroext i1 @test4(%class.PB2* %s_a, %class.PB2* %s_b) local_unnamed_addr #0 {
; CHECK-LABEL: test4: ; CHECK-LABEL: test4:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lwz 3, 0(3) ; CHECK-NEXT: lwz 3, 0(3)
; CHECK-NEXT: lwz 4, 0(4) ; CHECK-NEXT: lwz 4, 0(4)
; CHECK-NEXT: rlwinm 3, 3, 0, 28, 28 ; CHECK-NEXT: rlwinm 3, 3, 0, 28, 28
; CHECK-NEXT: rlwinm 4, 4, 0, 28, 28 ; CHECK-NEXT: rlwinm 4, 4, 0, 28, 28
; CHECK-NEXT: sub 3, 3, 4 ; CHECK-NEXT: sub 3, 3, 4
; CHECK-NEXT: not 3, 3 ; CHECK-NEXT: not 3, 3
; CHECK-NEXT: rldicl 3, 3, 1, 63 ; CHECK-NEXT: srdi 3, 3, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%arrayidx.i6 = bitcast %class.PB2* %s_a to i32* %arrayidx.i6 = bitcast %class.PB2* %s_a to i32*
%0 = load i32, i32* %arrayidx.i6, align 8, !tbaa !1 %0 = load i32, i32* %arrayidx.i6, align 8, !tbaa !1
%and.i = and i32 %0, 8 %and.i = and i32 %0, 8
%arrayidx.i37 = bitcast %class.PB2* %s_b to i32* %arrayidx.i37 = bitcast %class.PB2* %s_b to i32*
%1 = load i32, i32* %arrayidx.i37, align 8, !tbaa !1 %1 = load i32, i32* %arrayidx.i37, align 8, !tbaa !1
%and.i4 = and i32 %1, 8 %and.i4 = and i32 %1, 8
%cmp.i5 = icmp uge i32 %and.i, %and.i4 %cmp.i5 = icmp uge i32 %and.i, %and.i4
ret i1 %cmp.i5 ret i1 %cmp.i5
} }
!1 = !{!2, !2, i64 0} !1 = !{!2, !2, i64 0}
!2 = !{!"int", !3, i64 0} !2 = !{!"int", !3, i64 0}
!3 = !{!"omnipotent char", !4, i64 0} !3 = !{!"omnipotent char", !4, i64 0}
!4 = !{!"Simple C++ TBAA"} !4 = !{!"Simple C++ TBAA"}

llvm/test/CodeGen/PowerPC/setcc_no_zext.ll

; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | not grep rlwinm ; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | not grep extrwi
; FIXME: This optimization has temporarily regressed with crbits enabled by ; FIXME: This optimization has temporarily regressed with crbits enabled by
; default at the default CodeOpt level. ; default at the default CodeOpt level.
; XFAIL: * ; XFAIL: *
define i32 @setcc_one_or_zero(i32* %a) { define i32 @setcc_one_or_zero(i32* %a) {
entry: entry:
%tmp.1 = icmp ne i32* %a, null ; <i1> [#uses=1] %tmp.1 = icmp ne i32* %a, null ; <i1> [#uses=1]
%inc.1 = zext i1 %tmp.1 to i32 ; <i32> [#uses=1] %inc.1 = zext i1 %tmp.1 to i32 ; <i32> [#uses=1]
ret i32 %inc.1 ret i32 %inc.1
} }

llvm/test/CodeGen/PowerPC/seteq-0.ll

; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu | FileCheck %s ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu | FileCheck %s
define i32 @eq0(i32 %a) { define i32 @eq0(i32 %a) {
%tmp.1 = icmp eq i32 %a, 0 ; <i1> [#uses=1] %tmp.1 = icmp eq i32 %a, 0 ; <i1> [#uses=1]
%tmp.2 = zext i1 %tmp.1 to i32 ; <i32> [#uses=1] %tmp.2 = zext i1 %tmp.1 to i32 ; <i32> [#uses=1]
ret i32 %tmp.2 ret i32 %tmp.2
; CHECK: cntlzw [[REG:[0-9]+]], 3 ; CHECK: cntlzw [[REG:[0-9]+]], 3
; CHECK: rlwinm 3, [[REG]], 27, 31, 31 ; CHECK: extrwi 3, [[REG]], 1, 26
; CHECK: blr ; CHECK: blr
} }

llvm/test/CodeGen/PowerPC/setrnd.ll

Show All 40 Lines
; AFTER-FINALIZE-ISEL: test_setrnd ; AFTER-FINALIZE-ISEL: test_setrnd
; AFTER-FINALIZE-ISEL: MFFS implicit $rm ; AFTER-FINALIZE-ISEL: MFFS implicit $rm
; AFTER-FINALIZE-ISEL: MTFSF 255, %7, 0, 0 ; AFTER-FINALIZE-ISEL: MTFSF 255, %7, 0, 0
; CHECK-LABEL: @test_setrnd ; CHECK-LABEL: @test_setrnd
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-DAG: mffs 1 ; CHECK-DAG: mffs 1
; CHECK-DAG: mffprd [[REG1:[0-9]+]], 1 ; CHECK-DAG: mffprd [[REG1:[0-9]+]], 1
; CHECK-DAG: rldimi [[REG1]], 3, 0, 62 ; CHECK-DAG: insrdi [[REG1]], 3, 2, 62
; CHECK-DAG: mtfprd [[REG2:[0-9]+]], [[REG1]] ; CHECK-DAG: mtfprd [[REG2:[0-9]+]], [[REG1]]
; CHECK-DAG: mtfsf 255, [[REG2]] ; CHECK-DAG: mtfsf 255, [[REG2]]
; CHECK: blr ; CHECK: blr
; CHECK-PWR7-LABEL: @test_setrnd ; CHECK-PWR7-LABEL: @test_setrnd
; CHECK-PWR7: # %bb.0: ; CHECK-PWR7: # %bb.0:
; CHECK-PWR7-DAG: mffs 1 ; CHECK-PWR7-DAG: mffs 1
; CHECK-PWR7-DAG: stfd 1, -8(1) ; CHECK-PWR7-DAG: stfd 1, -8(1)
; CHECK-PWR7-DAG: ld [[REG1:[0-9]+]], -8(1) ; CHECK-PWR7-DAG: ld [[REG1:[0-9]+]], -8(1)
; CHECK-PWR7-DAG: rldimi [[REG1]], 3, 0, 62 ; CHECK-PWR7-DAG: insrdi [[REG1]], 3, 2, 62
; CHECK-PWR7-DAG: std [[REG1]], -16(1) ; CHECK-PWR7-DAG: std [[REG1]], -16(1)
; CHECK-PWR7-DAG: lfd [[REG2:[0-9]+]], -16(1) ; CHECK-PWR7-DAG: lfd [[REG2:[0-9]+]], -16(1)
; CHECK-PWR7-DAG: mtfsf 255, [[REG2]] ; CHECK-PWR7-DAG: mtfsf 255, [[REG2]]
; CHECK-PWR7: blr ; CHECK-PWR7: blr
} }
declare double @llvm.ppc.setrnd(i32) declare double @llvm.ppc.setrnd(i32)

llvm/test/CodeGen/PowerPC/sms-phi-5.ll

Show All 9 Lines
; CHECK-NEXT: li 4, 1 ; CHECK-NEXT: li 4, 1
; CHECK-NEXT: slw 3, 4, 3 ; CHECK-NEXT: slw 3, 4, 3
; CHECK-NEXT: andi. 3, 3, 6336 ; CHECK-NEXT: andi. 3, 3, 6336
; CHECK-NEXT: beqlr 0 ; CHECK-NEXT: beqlr 0
; CHECK-NEXT: # %bb.2: ; CHECK-NEXT: # %bb.2:
; CHECK-NEXT: lhz 3, 0(3) ; CHECK-NEXT: lhz 3, 0(3)
; CHECK-NEXT: slwi 3, 3, 15 ; CHECK-NEXT: slwi 3, 3, 15
; CHECK-NEXT: clrlwi 3, 3, 31 ; CHECK-NEXT: clrlwi 3, 3, 31
; CHECK-NEXT: rlwinm 4, 3, 31, 17, 31 ; CHECK-NEXT: extrwi 4, 3, 15, 16
; CHECK-NEXT: or 3, 3, 4 ; CHECK-NEXT: or 3, 3, 4
; CHECK-NEXT: rlwimi 3, 3, 15, 0, 16 ; CHECK-NEXT: insrwi 3, 3, 17, 0
; CHECK-NEXT: # %bb.3: ; CHECK-NEXT: # %bb.3:
; CHECK-NEXT: blr ; CHECK-NEXT: blr
switch i12 undef, label %21 [ switch i12 undef, label %21 [
i12 6, label %1 i12 6, label %1
i12 7, label %1 i12 7, label %1
i12 12, label %1 i12 12, label %1
i12 11, label %1 i12 11, label %1
] ]
Show All 28 Lines

llvm/test/CodeGen/PowerPC/smulfixsat.ll

Show All 28 Lines
define i32 @func2(i32 %x, i32 %y) nounwind { define i32 @func2(i32 %x, i32 %y) nounwind {
; CHECK-LABEL: func2: ; CHECK-LABEL: func2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: mulhw. 6, 3, 4 ; CHECK-NEXT: mulhw. 6, 3, 4
; CHECK-NEXT: lis 5, 32767 ; CHECK-NEXT: lis 5, 32767
; CHECK-NEXT: mullw 3, 3, 4 ; CHECK-NEXT: mullw 3, 3, 4
; CHECK-NEXT: rotlwi 3, 3, 31 ; CHECK-NEXT: rotlwi 3, 3, 31
; CHECK-NEXT: ori 4, 5, 65535 ; CHECK-NEXT: ori 4, 5, 65535
; CHECK-NEXT: rlwimi 3, 6, 31, 0, 0 ; CHECK-NEXT: insrwi 3, 6, 1, 0
; CHECK-NEXT: bc 12, 1, .LBB1_1 ; CHECK-NEXT: bc 12, 1, .LBB1_1
; CHECK-NEXT: b .LBB1_2 ; CHECK-NEXT: b .LBB1_2
; CHECK-NEXT: .LBB1_1: ; CHECK-NEXT: .LBB1_1:
; CHECK-NEXT: addi 3, 4, 0 ; CHECK-NEXT: addi 3, 4, 0
; CHECK-NEXT: .LBB1_2: ; CHECK-NEXT: .LBB1_2:
; CHECK-NEXT: cmpwi 6, -1 ; CHECK-NEXT: cmpwi 6, -1
; CHECK-NEXT: lis 4, -32768 ; CHECK-NEXT: lis 4, -32768
; CHECK-NEXT: bc 12, 0, .LBB1_3 ; CHECK-NEXT: bc 12, 0, .LBB1_3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-NEXT: .LBB1_3: ; CHECK-NEXT: .LBB1_3:
; CHECK-NEXT: addi 3, 4, 0 ; CHECK-NEXT: addi 3, 4, 0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%tmp = call i32 @llvm.smul.fix.sat.i32(i32 %x, i32 %y, i32 1) %tmp = call i32 @llvm.smul.fix.sat.i32(i32 %x, i32 %y, i32 1)
ret i32 %tmp ret i32 %tmp
} }

llvm/test/CodeGen/PowerPC/spill_p9_setb.ll

Show All 21 Lines
; CHECK-P9-DAG: stw [[REG1]] ; CHECK-P9-DAG: stw [[REG1]]
; CHECK-P9: blr ; CHECK-P9: blr
; CHECK-P9: .LBB0_4: # %if.then1 ; CHECK-P9: .LBB0_4: # %if.then1
; ;
; CHECK-P8-LABEL: p9_setb_spill: ; CHECK-P8-LABEL: p9_setb_spill:
; CHECK-P8: # %bb.1: # %if.then ; CHECK-P8: # %bb.1: # %if.then
; CHECK-P8-DAG: crnot 4*cr[[CREG2:.*]]+lt, eq ; CHECK-P8-DAG: crnot 4*cr[[CREG2:.*]]+lt, eq
; CHECK-P8-DAG: mfocrf [[REG2:.*]], ; CHECK-P8-DAG: mfocrf [[REG2:.*]],
; CHECK-P8-DAG: rlwinm [[REG2]], [[REG2]] ; CHECK-P8-DAG: extlwi [[REG2]], [[REG2]]
; CHECK-P8-DAG: stw [[REG2]] ; CHECK-P8-DAG: stw [[REG2]]
; CHECK-P8: blr ; CHECK-P8: blr
; CHECK-P8: .LBB0_4: # %if.then1 ; CHECK-P8: .LBB0_4: # %if.then1
entry: entry:
br i1 undef, label %if.end, label %if.then br i1 undef, label %if.end, label %if.then
if.then: ; preds = %entry if.then: ; preds = %entry
%call = tail call signext i32 bitcast (i32 (...)* @fn_call to i32 ()*)() %call = tail call signext i32 bitcast (i32 (...)* @fn_call to i32 ()*)()
Show All 18 Lines

llvm/test/CodeGen/PowerPC/srem-vector-lkk.ll

Show First 20 Lines • Show All 136 Lines • ▼ Show 20 Lines
; P8LE-NEXT: lis r3, 21399 ; P8LE-NEXT: lis r3, 21399
; P8LE-NEXT: lis r9, -21386 ; P8LE-NEXT: lis r9, -21386
; P8LE-NEXT: lis r11, 31710 ; P8LE-NEXT: lis r11, 31710
; P8LE-NEXT: lis r8, -16728 ; P8LE-NEXT: lis r8, -16728
; P8LE-NEXT: ori r3, r3, 33437 ; P8LE-NEXT: ori r3, r3, 33437
; P8LE-NEXT: ori r9, r9, 37253 ; P8LE-NEXT: ori r9, r9, 37253
; P8LE-NEXT: ori r8, r8, 63249 ; P8LE-NEXT: ori r8, r8, 63249
; P8LE-NEXT: mffprd r4, f0 ; P8LE-NEXT: mffprd r4, f0
; P8LE-NEXT: rldicl r5, r4, 32, 48 ; P8LE-NEXT: extrdi r5, r4, 16, 16
; P8LE-NEXT: clrldi r7, r4, 48 ; P8LE-NEXT: clrldi r7, r4, 48
; P8LE-NEXT: rldicl r6, r4, 16, 48 ; P8LE-NEXT: srdi r6, r4, 48
; P8LE-NEXT: rldicl r4, r4, 48, 48 ; P8LE-NEXT: extrdi r4, r4, 16, 32
; P8LE-NEXT: extsh r10, r5 ; P8LE-NEXT: extsh r10, r5
; P8LE-NEXT: extsh r0, r7 ; P8LE-NEXT: extsh r0, r7
; P8LE-NEXT: mulhw r3, r10, r3 ; P8LE-NEXT: mulhw r3, r10, r3
; P8LE-NEXT: ori r10, r11, 63421 ; P8LE-NEXT: ori r10, r11, 63421
; P8LE-NEXT: extsh r11, r4 ; P8LE-NEXT: extsh r11, r4
; P8LE-NEXT: extsh r12, r6 ; P8LE-NEXT: extsh r12, r6
; P8LE-NEXT: mulhw r9, r0, r9 ; P8LE-NEXT: mulhw r9, r0, r9
; P8LE-NEXT: mulhw r10, r11, r10 ; P8LE-NEXT: mulhw r10, r11, r10
Show All 40 Lines
; P8BE-NEXT: lis r8, 21399 ; P8BE-NEXT: lis r8, 21399
; P8BE-NEXT: lis r9, 31710 ; P8BE-NEXT: lis r9, 31710
; P8BE-NEXT: lis r10, -21386 ; P8BE-NEXT: lis r10, -21386
; P8BE-NEXT: ori r3, r3, 63249 ; P8BE-NEXT: ori r3, r3, 63249
; P8BE-NEXT: ori r8, r8, 33437 ; P8BE-NEXT: ori r8, r8, 33437
; P8BE-NEXT: ori r9, r9, 63421 ; P8BE-NEXT: ori r9, r9, 63421
; P8BE-NEXT: ori r10, r10, 37253 ; P8BE-NEXT: ori r10, r10, 37253
; P8BE-NEXT: clrldi r5, r4, 48 ; P8BE-NEXT: clrldi r5, r4, 48
; P8BE-NEXT: rldicl r6, r4, 48, 48 ; P8BE-NEXT: extrdi r6, r4, 16, 32
; P8BE-NEXT: rldicl r7, r4, 32, 48 ; P8BE-NEXT: extrdi r7, r4, 16, 16
; P8BE-NEXT: extsh r5, r5 ; P8BE-NEXT: extsh r5, r5
; P8BE-NEXT: extsh r6, r6 ; P8BE-NEXT: extsh r6, r6
; P8BE-NEXT: rldicl r4, r4, 16, 48 ; P8BE-NEXT: srdi r4, r4, 48
; P8BE-NEXT: extsh r7, r7 ; P8BE-NEXT: extsh r7, r7
; P8BE-NEXT: mulhw r3, r5, r3 ; P8BE-NEXT: mulhw r3, r5, r3
; P8BE-NEXT: extsh r4, r4 ; P8BE-NEXT: extsh r4, r4
; P8BE-NEXT: mulhw r8, r6, r8 ; P8BE-NEXT: mulhw r8, r6, r8
; P8BE-NEXT: mulhw r9, r7, r9 ; P8BE-NEXT: mulhw r9, r7, r9
; P8BE-NEXT: mulhw r10, r4, r10 ; P8BE-NEXT: mulhw r10, r4, r10
; P8BE-NEXT: srwi r11, r3, 31 ; P8BE-NEXT: srwi r11, r3, 31
; P8BE-NEXT: srawi r3, r3, 8 ; P8BE-NEXT: srawi r3, r3, 8
▲ Show 20 Lines • Show All 151 Lines • ▼ Show 20 Lines
; P8LE-LABEL: fold_srem_vec_2: ; P8LE-LABEL: fold_srem_vec_2:
; P8LE: # %bb.0: ; P8LE: # %bb.0:
; P8LE-NEXT: xxswapd vs0, v2 ; P8LE-NEXT: xxswapd vs0, v2
; P8LE-NEXT: lis r3, -21386 ; P8LE-NEXT: lis r3, -21386
; P8LE-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; P8LE-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; P8LE-NEXT: ori r3, r3, 37253 ; P8LE-NEXT: ori r3, r3, 37253
; P8LE-NEXT: mffprd r4, f0 ; P8LE-NEXT: mffprd r4, f0
; P8LE-NEXT: clrldi r5, r4, 48 ; P8LE-NEXT: clrldi r5, r4, 48
; P8LE-NEXT: rldicl r6, r4, 48, 48 ; P8LE-NEXT: extrdi r6, r4, 16, 32
; P8LE-NEXT: extsh r8, r5 ; P8LE-NEXT: extsh r8, r5
; P8LE-NEXT: rldicl r7, r4, 32, 48 ; P8LE-NEXT: extrdi r7, r4, 16, 16
; P8LE-NEXT: extsh r9, r6 ; P8LE-NEXT: extsh r9, r6
; P8LE-NEXT: mulhw r10, r8, r3 ; P8LE-NEXT: mulhw r10, r8, r3
; P8LE-NEXT: rldicl r4, r4, 16, 48 ; P8LE-NEXT: srdi r4, r4, 48
; P8LE-NEXT: extsh r11, r7 ; P8LE-NEXT: extsh r11, r7
; P8LE-NEXT: mulhw r12, r9, r3 ; P8LE-NEXT: mulhw r12, r9, r3
; P8LE-NEXT: extsh r0, r4 ; P8LE-NEXT: extsh r0, r4
; P8LE-NEXT: mulhw r30, r11, r3 ; P8LE-NEXT: mulhw r30, r11, r3
; P8LE-NEXT: mulhw r3, r0, r3 ; P8LE-NEXT: mulhw r3, r0, r3
; P8LE-NEXT: add r8, r10, r8 ; P8LE-NEXT: add r8, r10, r8
; P8LE-NEXT: add r9, r12, r9 ; P8LE-NEXT: add r9, r12, r9
; P8LE-NEXT: srwi r10, r8, 31 ; P8LE-NEXT: srwi r10, r8, 31
Show All 33 Lines
; P8LE-NEXT: blr ; P8LE-NEXT: blr
; ;
; P8BE-LABEL: fold_srem_vec_2: ; P8BE-LABEL: fold_srem_vec_2:
; P8BE: # %bb.0: ; P8BE: # %bb.0:
; P8BE-NEXT: mfvsrd r4, v2 ; P8BE-NEXT: mfvsrd r4, v2
; P8BE-NEXT: lis r3, -21386 ; P8BE-NEXT: lis r3, -21386
; P8BE-NEXT: ori r3, r3, 37253 ; P8BE-NEXT: ori r3, r3, 37253
; P8BE-NEXT: clrldi r5, r4, 48 ; P8BE-NEXT: clrldi r5, r4, 48
; P8BE-NEXT: rldicl r6, r4, 48, 48 ; P8BE-NEXT: extrdi r6, r4, 16, 32
; P8BE-NEXT: extsh r5, r5 ; P8BE-NEXT: extsh r5, r5
; P8BE-NEXT: rldicl r7, r4, 32, 48 ; P8BE-NEXT: extrdi r7, r4, 16, 16
; P8BE-NEXT: extsh r6, r6 ; P8BE-NEXT: extsh r6, r6
; P8BE-NEXT: mulhw r8, r5, r3 ; P8BE-NEXT: mulhw r8, r5, r3
; P8BE-NEXT: rldicl r4, r4, 16, 48 ; P8BE-NEXT: srdi r4, r4, 48
; P8BE-NEXT: extsh r7, r7 ; P8BE-NEXT: extsh r7, r7
; P8BE-NEXT: mulhw r9, r6, r3 ; P8BE-NEXT: mulhw r9, r6, r3
; P8BE-NEXT: extsh r4, r4 ; P8BE-NEXT: extsh r4, r4
; P8BE-NEXT: mulhw r10, r7, r3 ; P8BE-NEXT: mulhw r10, r7, r3
; P8BE-NEXT: mulhw r3, r4, r3 ; P8BE-NEXT: mulhw r3, r4, r3
; P8BE-NEXT: add r8, r8, r5 ; P8BE-NEXT: add r8, r8, r5
; P8BE-NEXT: add r9, r9, r6 ; P8BE-NEXT: add r9, r9, r6
; P8BE-NEXT: srwi r11, r8, 31 ; P8BE-NEXT: srwi r11, r8, 31
▲ Show 20 Lines • Show All 178 Lines • ▼ Show 20 Lines
; P8LE-LABEL: combine_srem_sdiv: ; P8LE-LABEL: combine_srem_sdiv:
; P8LE: # %bb.0: ; P8LE: # %bb.0:
; P8LE-NEXT: xxswapd vs0, v2 ; P8LE-NEXT: xxswapd vs0, v2
; P8LE-NEXT: lis r4, -21386 ; P8LE-NEXT: lis r4, -21386
; P8LE-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; P8LE-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; P8LE-NEXT: ori r4, r4, 37253 ; P8LE-NEXT: ori r4, r4, 37253
; P8LE-NEXT: mffprd r5, f0 ; P8LE-NEXT: mffprd r5, f0
; P8LE-NEXT: clrldi r3, r5, 48 ; P8LE-NEXT: clrldi r3, r5, 48
; P8LE-NEXT: rldicl r6, r5, 48, 48 ; P8LE-NEXT: extrdi r6, r5, 16, 32
; P8LE-NEXT: rldicl r7, r5, 32, 48 ; P8LE-NEXT: extrdi r7, r5, 16, 16
; P8LE-NEXT: extsh r8, r3 ; P8LE-NEXT: extsh r8, r3
; P8LE-NEXT: extsh r9, r6 ; P8LE-NEXT: extsh r9, r6
; P8LE-NEXT: extsh r10, r7 ; P8LE-NEXT: extsh r10, r7
; P8LE-NEXT: mulhw r11, r8, r4 ; P8LE-NEXT: mulhw r11, r8, r4
; P8LE-NEXT: rldicl r5, r5, 16, 48 ; P8LE-NEXT: srdi r5, r5, 48
; P8LE-NEXT: mulhw r12, r9, r4 ; P8LE-NEXT: mulhw r12, r9, r4
; P8LE-NEXT: mulhw r0, r10, r4 ; P8LE-NEXT: mulhw r0, r10, r4
; P8LE-NEXT: extsh r30, r5 ; P8LE-NEXT: extsh r30, r5
; P8LE-NEXT: mulhw r4, r30, r4 ; P8LE-NEXT: mulhw r4, r30, r4
; P8LE-NEXT: add r8, r11, r8 ; P8LE-NEXT: add r8, r11, r8
; P8LE-NEXT: add r9, r12, r9 ; P8LE-NEXT: add r9, r12, r9
; P8LE-NEXT: srwi r11, r8, 31 ; P8LE-NEXT: srwi r11, r8, 31
; P8LE-NEXT: add r10, r0, r10 ; P8LE-NEXT: add r10, r0, r10
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
; P8LE-NEXT: blr ; P8LE-NEXT: blr
; ;
; P8BE-LABEL: combine_srem_sdiv: ; P8BE-LABEL: combine_srem_sdiv:
; P8BE: # %bb.0: ; P8BE: # %bb.0:
; P8BE-NEXT: mfvsrd r5, v2 ; P8BE-NEXT: mfvsrd r5, v2
; P8BE-NEXT: lis r4, -21386 ; P8BE-NEXT: lis r4, -21386
; P8BE-NEXT: ori r4, r4, 37253 ; P8BE-NEXT: ori r4, r4, 37253
; P8BE-NEXT: clrldi r3, r5, 48 ; P8BE-NEXT: clrldi r3, r5, 48
; P8BE-NEXT: rldicl r6, r5, 48, 48 ; P8BE-NEXT: extrdi r6, r5, 16, 32
; P8BE-NEXT: extsh r8, r3 ; P8BE-NEXT: extsh r8, r3
; P8BE-NEXT: rldicl r7, r5, 32, 48 ; P8BE-NEXT: extrdi r7, r5, 16, 16
; P8BE-NEXT: extsh r9, r6 ; P8BE-NEXT: extsh r9, r6
; P8BE-NEXT: rldicl r5, r5, 16, 48 ; P8BE-NEXT: srdi r5, r5, 48
; P8BE-NEXT: mulhw r11, r8, r4 ; P8BE-NEXT: mulhw r11, r8, r4
; P8BE-NEXT: extsh r10, r7 ; P8BE-NEXT: extsh r10, r7
; P8BE-NEXT: extsh r5, r5 ; P8BE-NEXT: extsh r5, r5
; P8BE-NEXT: mulhw r12, r9, r4 ; P8BE-NEXT: mulhw r12, r9, r4
; P8BE-NEXT: mulhw r0, r10, r4 ; P8BE-NEXT: mulhw r0, r10, r4
; P8BE-NEXT: mulhw r4, r5, r4 ; P8BE-NEXT: mulhw r4, r5, r4
; P8BE-NEXT: add r8, r11, r8 ; P8BE-NEXT: add r8, r11, r8
; P8BE-NEXT: add r9, r12, r9 ; P8BE-NEXT: add r9, r12, r9
▲ Show 20 Lines • Show All 148 Lines • ▼ Show 20 Lines
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; ;
; P8LE-LABEL: dont_fold_srem_power_of_two: ; P8LE-LABEL: dont_fold_srem_power_of_two:
; P8LE: # %bb.0: ; P8LE: # %bb.0:
; P8LE-NEXT: xxswapd vs0, v2 ; P8LE-NEXT: xxswapd vs0, v2
; P8LE-NEXT: lis r3, -21386 ; P8LE-NEXT: lis r3, -21386
; P8LE-NEXT: ori r3, r3, 37253 ; P8LE-NEXT: ori r3, r3, 37253
; P8LE-NEXT: mffprd r4, f0 ; P8LE-NEXT: mffprd r4, f0
; P8LE-NEXT: rldicl r5, r4, 16, 48 ; P8LE-NEXT: srdi r5, r4, 48
; P8LE-NEXT: clrldi r7, r4, 48 ; P8LE-NEXT: clrldi r7, r4, 48
; P8LE-NEXT: extsh r6, r5 ; P8LE-NEXT: extsh r6, r5
; P8LE-NEXT: extsh r8, r7 ; P8LE-NEXT: extsh r8, r7
; P8LE-NEXT: mulhw r3, r6, r3 ; P8LE-NEXT: mulhw r3, r6, r3
; P8LE-NEXT: rldicl r9, r4, 48, 48 ; P8LE-NEXT: extrdi r9, r4, 16, 32
; P8LE-NEXT: srawi r8, r8, 6 ; P8LE-NEXT: srawi r8, r8, 6
; P8LE-NEXT: extsh r10, r9 ; P8LE-NEXT: extsh r10, r9
; P8LE-NEXT: addze r8, r8 ; P8LE-NEXT: addze r8, r8
; P8LE-NEXT: rldicl r4, r4, 32, 48 ; P8LE-NEXT: extrdi r4, r4, 16, 16
; P8LE-NEXT: srawi r10, r10, 5 ; P8LE-NEXT: srawi r10, r10, 5
; P8LE-NEXT: slwi r8, r8, 6 ; P8LE-NEXT: slwi r8, r8, 6
; P8LE-NEXT: add r3, r3, r6 ; P8LE-NEXT: add r3, r3, r6
; P8LE-NEXT: addze r6, r10 ; P8LE-NEXT: addze r6, r10
; P8LE-NEXT: sub r7, r7, r8 ; P8LE-NEXT: sub r7, r7, r8
; P8LE-NEXT: srwi r10, r3, 31 ; P8LE-NEXT: srwi r10, r3, 31
; P8LE-NEXT: srawi r3, r3, 6 ; P8LE-NEXT: srawi r3, r3, 6
; P8LE-NEXT: mtfprd f0, r7 ; P8LE-NEXT: mtfprd f0, r7
Show All 20 Lines
; P8LE-NEXT: blr ; P8LE-NEXT: blr
; ;
; P8BE-LABEL: dont_fold_srem_power_of_two: ; P8BE-LABEL: dont_fold_srem_power_of_two:
; P8BE: # %bb.0: ; P8BE: # %bb.0:
; P8BE-NEXT: mfvsrd r4, v2 ; P8BE-NEXT: mfvsrd r4, v2
; P8BE-NEXT: lis r3, -21386 ; P8BE-NEXT: lis r3, -21386
; P8BE-NEXT: ori r3, r3, 37253 ; P8BE-NEXT: ori r3, r3, 37253
; P8BE-NEXT: clrldi r5, r4, 48 ; P8BE-NEXT: clrldi r5, r4, 48
; P8BE-NEXT: rldicl r6, r4, 32, 48 ; P8BE-NEXT: extrdi r6, r4, 16, 16
; P8BE-NEXT: extsh r5, r5 ; P8BE-NEXT: extsh r5, r5
; P8BE-NEXT: extsh r6, r6 ; P8BE-NEXT: extsh r6, r6
; P8BE-NEXT: mulhw r3, r5, r3 ; P8BE-NEXT: mulhw r3, r5, r3
; P8BE-NEXT: rldicl r7, r4, 16, 48 ; P8BE-NEXT: srdi r7, r4, 48
; P8BE-NEXT: srawi r8, r6, 5 ; P8BE-NEXT: srawi r8, r6, 5
; P8BE-NEXT: extsh r7, r7 ; P8BE-NEXT: extsh r7, r7
; P8BE-NEXT: addze r8, r8 ; P8BE-NEXT: addze r8, r8
; P8BE-NEXT: rldicl r4, r4, 48, 48 ; P8BE-NEXT: extrdi r4, r4, 16, 32
; P8BE-NEXT: srawi r9, r7, 6 ; P8BE-NEXT: srawi r9, r7, 6
; P8BE-NEXT: extsh r4, r4 ; P8BE-NEXT: extsh r4, r4
; P8BE-NEXT: slwi r8, r8, 5 ; P8BE-NEXT: slwi r8, r8, 5
; P8BE-NEXT: add r3, r3, r5 ; P8BE-NEXT: add r3, r3, r5
; P8BE-NEXT: addze r9, r9 ; P8BE-NEXT: addze r9, r9
; P8BE-NEXT: sub r6, r6, r8 ; P8BE-NEXT: sub r6, r6, r8
; P8BE-NEXT: srwi r10, r3, 31 ; P8BE-NEXT: srwi r10, r3, 31
; P8BE-NEXT: srawi r3, r3, 6 ; P8BE-NEXT: srawi r3, r3, 6
▲ Show 20 Lines • Show All 129 Lines • ▼ Show 20 Lines
; P8LE-NEXT: xxswapd vs0, v2 ; P8LE-NEXT: xxswapd vs0, v2
; P8LE-NEXT: lis r3, 24749 ; P8LE-NEXT: lis r3, 24749
; P8LE-NEXT: lis r7, -19946 ; P8LE-NEXT: lis r7, -19946
; P8LE-NEXT: lis r9, -14230 ; P8LE-NEXT: lis r9, -14230
; P8LE-NEXT: xxlxor v5, v5, v5 ; P8LE-NEXT: xxlxor v5, v5, v5
; P8LE-NEXT: ori r3, r3, 47143 ; P8LE-NEXT: ori r3, r3, 47143
; P8LE-NEXT: ori r7, r7, 17097 ; P8LE-NEXT: ori r7, r7, 17097
; P8LE-NEXT: mffprd r4, f0 ; P8LE-NEXT: mffprd r4, f0
; P8LE-NEXT: rldicl r5, r4, 16, 48 ; P8LE-NEXT: srdi r5, r4, 48
; P8LE-NEXT: rldicl r6, r4, 32, 48 ; P8LE-NEXT: extrdi r6, r4, 16, 16
; P8LE-NEXT: rldicl r4, r4, 48, 48 ; P8LE-NEXT: extrdi r4, r4, 16, 32
; P8LE-NEXT: extsh r8, r5 ; P8LE-NEXT: extsh r8, r5
; P8LE-NEXT: extsh r10, r6 ; P8LE-NEXT: extsh r10, r6
; P8LE-NEXT: mulhw r3, r8, r3 ; P8LE-NEXT: mulhw r3, r8, r3
; P8LE-NEXT: ori r8, r9, 30865 ; P8LE-NEXT: ori r8, r9, 30865
; P8LE-NEXT: extsh r9, r4 ; P8LE-NEXT: extsh r9, r4
; P8LE-NEXT: mulhw r7, r10, r7 ; P8LE-NEXT: mulhw r7, r10, r7
; P8LE-NEXT: mulhw r8, r9, r8 ; P8LE-NEXT: mulhw r8, r9, r8
; P8LE-NEXT: add r7, r7, r10 ; P8LE-NEXT: add r7, r7, r10
Show All 29 Lines
; P8BE-NEXT: mfvsrd r3, v2 ; P8BE-NEXT: mfvsrd r3, v2
; P8BE-NEXT: lis r5, 24749 ; P8BE-NEXT: lis r5, 24749
; P8BE-NEXT: lis r6, -19946 ; P8BE-NEXT: lis r6, -19946
; P8BE-NEXT: lis r8, -14230 ; P8BE-NEXT: lis r8, -14230
; P8BE-NEXT: ori r5, r5, 47143 ; P8BE-NEXT: ori r5, r5, 47143
; P8BE-NEXT: ori r6, r6, 17097 ; P8BE-NEXT: ori r6, r6, 17097
; P8BE-NEXT: ori r8, r8, 30865 ; P8BE-NEXT: ori r8, r8, 30865
; P8BE-NEXT: clrldi r4, r3, 48 ; P8BE-NEXT: clrldi r4, r3, 48
; P8BE-NEXT: rldicl r7, r3, 48, 48 ; P8BE-NEXT: extrdi r7, r3, 16, 32
; P8BE-NEXT: rldicl r3, r3, 32, 48 ; P8BE-NEXT: extrdi r3, r3, 16, 16
; P8BE-NEXT: extsh r4, r4 ; P8BE-NEXT: extsh r4, r4
; P8BE-NEXT: extsh r7, r7 ; P8BE-NEXT: extsh r7, r7
; P8BE-NEXT: extsh r3, r3 ; P8BE-NEXT: extsh r3, r3
; P8BE-NEXT: mulhw r5, r4, r5 ; P8BE-NEXT: mulhw r5, r4, r5
; P8BE-NEXT: mulhw r6, r7, r6 ; P8BE-NEXT: mulhw r6, r7, r6
; P8BE-NEXT: mulhw r8, r3, r8 ; P8BE-NEXT: mulhw r8, r3, r8
; P8BE-NEXT: srwi r9, r5, 31 ; P8BE-NEXT: srwi r9, r5, 31
; P8BE-NEXT: srawi r5, r5, 11 ; P8BE-NEXT: srawi r5, r5, 11
▲ Show 20 Lines • Show All 125 Lines • ▼ Show 20 Lines
; P8LE: # %bb.0: ; P8LE: # %bb.0:
; P8LE-NEXT: xxswapd vs0, v2 ; P8LE-NEXT: xxswapd vs0, v2
; P8LE-NEXT: lis r4, 24749 ; P8LE-NEXT: lis r4, 24749
; P8LE-NEXT: lis r5, -19946 ; P8LE-NEXT: lis r5, -19946
; P8LE-NEXT: xxlxor v5, v5, v5 ; P8LE-NEXT: xxlxor v5, v5, v5
; P8LE-NEXT: ori r4, r4, 47143 ; P8LE-NEXT: ori r4, r4, 47143
; P8LE-NEXT: ori r5, r5, 17097 ; P8LE-NEXT: ori r5, r5, 17097
; P8LE-NEXT: mffprd r3, f0 ; P8LE-NEXT: mffprd r3, f0
; P8LE-NEXT: rldicl r6, r3, 16, 48 ; P8LE-NEXT: srdi r6, r3, 48
; P8LE-NEXT: rldicl r7, r3, 32, 48 ; P8LE-NEXT: extrdi r7, r3, 16, 16
; P8LE-NEXT: extsh r8, r6 ; P8LE-NEXT: extsh r8, r6
; P8LE-NEXT: extsh r9, r7 ; P8LE-NEXT: extsh r9, r7
; P8LE-NEXT: mulhw r4, r8, r4 ; P8LE-NEXT: mulhw r4, r8, r4
; P8LE-NEXT: mulhw r5, r9, r5 ; P8LE-NEXT: mulhw r5, r9, r5
; P8LE-NEXT: rldicl r3, r3, 48, 48 ; P8LE-NEXT: extrdi r3, r3, 16, 32
; P8LE-NEXT: srwi r8, r4, 31 ; P8LE-NEXT: srwi r8, r4, 31
; P8LE-NEXT: srawi r4, r4, 11 ; P8LE-NEXT: srawi r4, r4, 11
; P8LE-NEXT: add r5, r5, r9 ; P8LE-NEXT: add r5, r5, r9
; P8LE-NEXT: add r4, r4, r8 ; P8LE-NEXT: add r4, r4, r8
; P8LE-NEXT: srwi r8, r5, 31 ; P8LE-NEXT: srwi r8, r5, 31
; P8LE-NEXT: srawi r5, r5, 4 ; P8LE-NEXT: srawi r5, r5, 4
; P8LE-NEXT: mulli r4, r4, 5423 ; P8LE-NEXT: mulli r4, r4, 5423
; P8LE-NEXT: add r5, r5, r8 ; P8LE-NEXT: add r5, r5, r8
Show All 19 Lines
; P8BE-LABEL: dont_fold_urem_i16_smax: ; P8BE-LABEL: dont_fold_urem_i16_smax:
; P8BE: # %bb.0: ; P8BE: # %bb.0:
; P8BE-NEXT: mfvsrd r3, v2 ; P8BE-NEXT: mfvsrd r3, v2
; P8BE-NEXT: lis r4, 24749 ; P8BE-NEXT: lis r4, 24749
; P8BE-NEXT: lis r5, -19946 ; P8BE-NEXT: lis r5, -19946
; P8BE-NEXT: ori r4, r4, 47143 ; P8BE-NEXT: ori r4, r4, 47143
; P8BE-NEXT: ori r5, r5, 17097 ; P8BE-NEXT: ori r5, r5, 17097
; P8BE-NEXT: clrldi r6, r3, 48 ; P8BE-NEXT: clrldi r6, r3, 48
; P8BE-NEXT: rldicl r7, r3, 48, 48 ; P8BE-NEXT: extrdi r7, r3, 16, 32
; P8BE-NEXT: extsh r6, r6 ; P8BE-NEXT: extsh r6, r6
; P8BE-NEXT: extsh r7, r7 ; P8BE-NEXT: extsh r7, r7
; P8BE-NEXT: mulhw r4, r6, r4 ; P8BE-NEXT: mulhw r4, r6, r4
; P8BE-NEXT: mulhw r5, r7, r5 ; P8BE-NEXT: mulhw r5, r7, r5
; P8BE-NEXT: rldicl r3, r3, 32, 48 ; P8BE-NEXT: extrdi r3, r3, 16, 16
; P8BE-NEXT: extsh r3, r3 ; P8BE-NEXT: extsh r3, r3
; P8BE-NEXT: srwi r8, r4, 31 ; P8BE-NEXT: srwi r8, r4, 31
; P8BE-NEXT: srawi r4, r4, 11 ; P8BE-NEXT: srawi r4, r4, 11
; P8BE-NEXT: add r5, r5, r7 ; P8BE-NEXT: add r5, r5, r7
; P8BE-NEXT: add r4, r4, r8 ; P8BE-NEXT: add r4, r4, r8
; P8BE-NEXT: srwi r8, r5, 31 ; P8BE-NEXT: srwi r8, r5, 31
; P8BE-NEXT: srawi r5, r5, 4 ; P8BE-NEXT: srawi r5, r5, 4
; P8BE-NEXT: mulli r4, r4, 5423 ; P8BE-NEXT: mulli r4, r4, 5423
Show All 28 Lines
; P9LE: # %bb.0: ; P9LE: # %bb.0:
; P9LE-NEXT: lis r4, 24749 ; P9LE-NEXT: lis r4, 24749
; P9LE-NEXT: ori r4, r4, 47142 ; P9LE-NEXT: ori r4, r4, 47142
; P9LE-NEXT: sldi r4, r4, 32 ; P9LE-NEXT: sldi r4, r4, 32
; P9LE-NEXT: oris r4, r4, 58853 ; P9LE-NEXT: oris r4, r4, 58853
; P9LE-NEXT: mfvsrd r3, v3 ; P9LE-NEXT: mfvsrd r3, v3
; P9LE-NEXT: ori r4, r4, 6055 ; P9LE-NEXT: ori r4, r4, 6055
; P9LE-NEXT: mulhd r4, r3, r4 ; P9LE-NEXT: mulhd r4, r3, r4
; P9LE-NEXT: rldicl r5, r4, 1, 63 ; P9LE-NEXT: srdi r5, r4, 63
; P9LE-NEXT: sradi r4, r4, 11 ; P9LE-NEXT: sradi r4, r4, 11
; P9LE-NEXT: add r4, r4, r5 ; P9LE-NEXT: add r4, r4, r5
; P9LE-NEXT: lis r5, -19946 ; P9LE-NEXT: lis r5, -19946
; P9LE-NEXT: mulli r4, r4, 5423 ; P9LE-NEXT: mulli r4, r4, 5423
; P9LE-NEXT: ori r5, r5, 17096 ; P9LE-NEXT: ori r5, r5, 17096
; P9LE-NEXT: sldi r5, r5, 32 ; P9LE-NEXT: sldi r5, r5, 32
; P9LE-NEXT: oris r5, r5, 22795 ; P9LE-NEXT: oris r5, r5, 22795
; P9LE-NEXT: sub r3, r3, r4 ; P9LE-NEXT: sub r3, r3, r4
; P9LE-NEXT: mfvsrld r4, v3 ; P9LE-NEXT: mfvsrld r4, v3
; P9LE-NEXT: ori r5, r5, 8549 ; P9LE-NEXT: ori r5, r5, 8549
; P9LE-NEXT: mulhd r5, r4, r5 ; P9LE-NEXT: mulhd r5, r4, r5
; P9LE-NEXT: add r5, r5, r4 ; P9LE-NEXT: add r5, r5, r4
; P9LE-NEXT: rldicl r6, r5, 1, 63 ; P9LE-NEXT: srdi r6, r5, 63
; P9LE-NEXT: sradi r5, r5, 4 ; P9LE-NEXT: sradi r5, r5, 4
; P9LE-NEXT: add r5, r5, r6 ; P9LE-NEXT: add r5, r5, r6
; P9LE-NEXT: mulli r5, r5, 23 ; P9LE-NEXT: mulli r5, r5, 23
; P9LE-NEXT: sub r4, r4, r5 ; P9LE-NEXT: sub r4, r4, r5
; P9LE-NEXT: mtvsrdd v3, r3, r4 ; P9LE-NEXT: mtvsrdd v3, r3, r4
; P9LE-NEXT: lis r4, 25653 ; P9LE-NEXT: lis r4, 25653
; P9LE-NEXT: ori r4, r4, 15432 ; P9LE-NEXT: ori r4, r4, 15432
; P9LE-NEXT: sldi r4, r4, 32 ; P9LE-NEXT: sldi r4, r4, 32
; P9LE-NEXT: oris r4, r4, 1603 ; P9LE-NEXT: oris r4, r4, 1603
; P9LE-NEXT: mfvsrd r3, v2 ; P9LE-NEXT: mfvsrd r3, v2
; P9LE-NEXT: ori r4, r4, 21445 ; P9LE-NEXT: ori r4, r4, 21445
; P9LE-NEXT: mulhd r4, r3, r4 ; P9LE-NEXT: mulhd r4, r3, r4
; P9LE-NEXT: rldicl r5, r4, 1, 63 ; P9LE-NEXT: srdi r5, r4, 63
; P9LE-NEXT: sradi r4, r4, 8 ; P9LE-NEXT: sradi r4, r4, 8
; P9LE-NEXT: add r4, r4, r5 ; P9LE-NEXT: add r4, r4, r5
; P9LE-NEXT: mulli r4, r4, 654 ; P9LE-NEXT: mulli r4, r4, 654
; P9LE-NEXT: sub r3, r3, r4 ; P9LE-NEXT: sub r3, r3, r4
; P9LE-NEXT: li r4, 0 ; P9LE-NEXT: li r4, 0
; P9LE-NEXT: mtvsrdd v2, r3, r4 ; P9LE-NEXT: mtvsrdd v2, r3, r4
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P9BE-LABEL: dont_fold_srem_i64: ; P9BE-LABEL: dont_fold_srem_i64:
; P9BE: # %bb.0: ; P9BE: # %bb.0:
; P9BE-NEXT: lis r4, 24749 ; P9BE-NEXT: lis r4, 24749
; P9BE-NEXT: ori r4, r4, 47142 ; P9BE-NEXT: ori r4, r4, 47142
; P9BE-NEXT: sldi r4, r4, 32 ; P9BE-NEXT: sldi r4, r4, 32
; P9BE-NEXT: oris r4, r4, 58853 ; P9BE-NEXT: oris r4, r4, 58853
; P9BE-NEXT: mfvsrld r3, v3 ; P9BE-NEXT: mfvsrld r3, v3
; P9BE-NEXT: ori r4, r4, 6055 ; P9BE-NEXT: ori r4, r4, 6055
; P9BE-NEXT: mulhd r4, r3, r4 ; P9BE-NEXT: mulhd r4, r3, r4
; P9BE-NEXT: rldicl r5, r4, 1, 63 ; P9BE-NEXT: srdi r5, r4, 63
; P9BE-NEXT: sradi r4, r4, 11 ; P9BE-NEXT: sradi r4, r4, 11
; P9BE-NEXT: add r4, r4, r5 ; P9BE-NEXT: add r4, r4, r5
; P9BE-NEXT: lis r5, -19946 ; P9BE-NEXT: lis r5, -19946
; P9BE-NEXT: ori r5, r5, 17096 ; P9BE-NEXT: ori r5, r5, 17096
; P9BE-NEXT: mulli r4, r4, 5423 ; P9BE-NEXT: mulli r4, r4, 5423
; P9BE-NEXT: sldi r5, r5, 32 ; P9BE-NEXT: sldi r5, r5, 32
; P9BE-NEXT: oris r5, r5, 22795 ; P9BE-NEXT: oris r5, r5, 22795
; P9BE-NEXT: sub r3, r3, r4 ; P9BE-NEXT: sub r3, r3, r4
; P9BE-NEXT: mfvsrd r4, v3 ; P9BE-NEXT: mfvsrd r4, v3
; P9BE-NEXT: ori r5, r5, 8549 ; P9BE-NEXT: ori r5, r5, 8549
; P9BE-NEXT: mulhd r5, r4, r5 ; P9BE-NEXT: mulhd r5, r4, r5
; P9BE-NEXT: add r5, r5, r4 ; P9BE-NEXT: add r5, r5, r4
; P9BE-NEXT: rldicl r6, r5, 1, 63 ; P9BE-NEXT: srdi r6, r5, 63
; P9BE-NEXT: sradi r5, r5, 4 ; P9BE-NEXT: sradi r5, r5, 4
; P9BE-NEXT: add r5, r5, r6 ; P9BE-NEXT: add r5, r5, r6
; P9BE-NEXT: mulli r5, r5, 23 ; P9BE-NEXT: mulli r5, r5, 23
; P9BE-NEXT: sub r4, r4, r5 ; P9BE-NEXT: sub r4, r4, r5
; P9BE-NEXT: mtvsrdd v3, r4, r3 ; P9BE-NEXT: mtvsrdd v3, r4, r3
; P9BE-NEXT: lis r4, 25653 ; P9BE-NEXT: lis r4, 25653
; P9BE-NEXT: ori r4, r4, 15432 ; P9BE-NEXT: ori r4, r4, 15432
; P9BE-NEXT: sldi r4, r4, 32 ; P9BE-NEXT: sldi r4, r4, 32
; P9BE-NEXT: oris r4, r4, 1603 ; P9BE-NEXT: oris r4, r4, 1603
; P9BE-NEXT: mfvsrld r3, v2 ; P9BE-NEXT: mfvsrld r3, v2
; P9BE-NEXT: ori r4, r4, 21445 ; P9BE-NEXT: ori r4, r4, 21445
; P9BE-NEXT: mulhd r4, r3, r4 ; P9BE-NEXT: mulhd r4, r3, r4
; P9BE-NEXT: rldicl r5, r4, 1, 63 ; P9BE-NEXT: srdi r5, r4, 63
; P9BE-NEXT: sradi r4, r4, 8 ; P9BE-NEXT: sradi r4, r4, 8
; P9BE-NEXT: add r4, r4, r5 ; P9BE-NEXT: add r4, r4, r5
; P9BE-NEXT: mulli r4, r4, 654 ; P9BE-NEXT: mulli r4, r4, 654
; P9BE-NEXT: sub r3, r3, r4 ; P9BE-NEXT: sub r3, r3, r4
; P9BE-NEXT: mtvsrdd v2, 0, r3 ; P9BE-NEXT: mtvsrdd v2, 0, r3
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; ;
; P8LE-LABEL: dont_fold_srem_i64: ; P8LE-LABEL: dont_fold_srem_i64:
Show All 15 Lines
; P8LE-NEXT: mffprd r8, f0 ; P8LE-NEXT: mffprd r8, f0
; P8LE-NEXT: oris r5, r5, 1603 ; P8LE-NEXT: oris r5, r5, 1603
; P8LE-NEXT: ori r3, r3, 6055 ; P8LE-NEXT: ori r3, r3, 6055
; P8LE-NEXT: ori r4, r4, 8549 ; P8LE-NEXT: ori r4, r4, 8549
; P8LE-NEXT: ori r5, r5, 21445 ; P8LE-NEXT: ori r5, r5, 21445
; P8LE-NEXT: mulhd r3, r6, r3 ; P8LE-NEXT: mulhd r3, r6, r3
; P8LE-NEXT: mulhd r5, r7, r5 ; P8LE-NEXT: mulhd r5, r7, r5
; P8LE-NEXT: mulhd r4, r8, r4 ; P8LE-NEXT: mulhd r4, r8, r4
; P8LE-NEXT: rldicl r9, r3, 1, 63 ; P8LE-NEXT: srdi r9, r3, 63
; P8LE-NEXT: sradi r3, r3, 11 ; P8LE-NEXT: sradi r3, r3, 11
; P8LE-NEXT: add r3, r3, r9 ; P8LE-NEXT: add r3, r3, r9
; P8LE-NEXT: rldicl r9, r5, 1, 63 ; P8LE-NEXT: srdi r9, r5, 63
; P8LE-NEXT: add r4, r4, r8 ; P8LE-NEXT: add r4, r4, r8
; P8LE-NEXT: sradi r5, r5, 8 ; P8LE-NEXT: sradi r5, r5, 8
; P8LE-NEXT: mulli r3, r3, 5423 ; P8LE-NEXT: mulli r3, r3, 5423
; P8LE-NEXT: add r5, r5, r9 ; P8LE-NEXT: add r5, r5, r9
; P8LE-NEXT: rldicl r9, r4, 1, 63 ; P8LE-NEXT: srdi r9, r4, 63
; P8LE-NEXT: sradi r4, r4, 4 ; P8LE-NEXT: sradi r4, r4, 4
; P8LE-NEXT: mulli r5, r5, 654 ; P8LE-NEXT: mulli r5, r5, 654
; P8LE-NEXT: add r4, r4, r9 ; P8LE-NEXT: add r4, r4, r9
; P8LE-NEXT: mulli r4, r4, 23 ; P8LE-NEXT: mulli r4, r4, 23
; P8LE-NEXT: sub r3, r6, r3 ; P8LE-NEXT: sub r3, r6, r3
; P8LE-NEXT: mtfprd f0, r3 ; P8LE-NEXT: mtfprd f0, r3
; P8LE-NEXT: sub r5, r7, r5 ; P8LE-NEXT: sub r5, r7, r5
; P8LE-NEXT: mtfprd f1, r5 ; P8LE-NEXT: mtfprd f1, r5
Show All 26 Lines
; P8BE-NEXT: ori r3, r3, 6055 ; P8BE-NEXT: ori r3, r3, 6055
; P8BE-NEXT: oris r5, r5, 1603 ; P8BE-NEXT: oris r5, r5, 1603
; P8BE-NEXT: mffprd r8, f1 ; P8BE-NEXT: mffprd r8, f1
; P8BE-NEXT: mulhd r4, r6, r4 ; P8BE-NEXT: mulhd r4, r6, r4
; P8BE-NEXT: mulhd r3, r7, r3 ; P8BE-NEXT: mulhd r3, r7, r3
; P8BE-NEXT: ori r5, r5, 21445 ; P8BE-NEXT: ori r5, r5, 21445
; P8BE-NEXT: mulhd r5, r8, r5 ; P8BE-NEXT: mulhd r5, r8, r5
; P8BE-NEXT: add r4, r4, r6 ; P8BE-NEXT: add r4, r4, r6
; P8BE-NEXT: rldicl r9, r3, 1, 63 ; P8BE-NEXT: srdi r9, r3, 63
; P8BE-NEXT: sradi r3, r3, 11 ; P8BE-NEXT: sradi r3, r3, 11
; P8BE-NEXT: rldicl r10, r4, 1, 63 ; P8BE-NEXT: srdi r10, r4, 63
; P8BE-NEXT: sradi r4, r4, 4 ; P8BE-NEXT: sradi r4, r4, 4
; P8BE-NEXT: add r3, r3, r9 ; P8BE-NEXT: add r3, r3, r9
; P8BE-NEXT: rldicl r9, r5, 1, 63 ; P8BE-NEXT: srdi r9, r5, 63
; P8BE-NEXT: add r4, r4, r10 ; P8BE-NEXT: add r4, r4, r10
; P8BE-NEXT: sradi r5, r5, 8 ; P8BE-NEXT: sradi r5, r5, 8
; P8BE-NEXT: mulli r3, r3, 5423 ; P8BE-NEXT: mulli r3, r3, 5423
; P8BE-NEXT: add r5, r5, r9 ; P8BE-NEXT: add r5, r5, r9
; P8BE-NEXT: mulli r4, r4, 23 ; P8BE-NEXT: mulli r4, r4, 23
; P8BE-NEXT: mulli r5, r5, 654 ; P8BE-NEXT: mulli r5, r5, 654
; P8BE-NEXT: sub r3, r7, r3 ; P8BE-NEXT: sub r3, r7, r3
; P8BE-NEXT: sub r4, r6, r4 ; P8BE-NEXT: sub r4, r6, r4
Show All 12 Lines

llvm/test/CodeGen/PowerPC/srl-mask.ll

; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 | FileCheck %s ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 | FileCheck %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
define i64 @foo(i64 %x) #0 { define i64 @foo(i64 %x) #0 {
entry: entry:
; CHECK-LABEL: @foo ; CHECK-LABEL: @foo
%a = lshr i64 %x, 35 %a = lshr i64 %x, 35
%b = and i64 %a, 65535 %b = and i64 %a, 65535
; CHECK: rldicl 3, 3, 29, 48 ; CHECK: extrdi 3, 3, 16, 13
ret i64 %b ret i64 %b
; CHECK: blr ; CHECK: blr
} }
; for AND with an immediate like (x & ~0xFFFF) ; for AND with an immediate like (x & ~0xFFFF)
; we should use rldicl instruction ; we should use rldicl instruction
define i64 @bar(i64 %x) #0 { define i64 @bar(i64 %x) #0 {
entry: entry:
; CHECK-LABEL: @bar ; CHECK-LABEL: @bar
%a = and i64 %x, 18446744073709486080 %a = and i64 %x, 18446744073709486080
; CHECK: rldicr 3, 3, 0, 47 ; CHECK: clrrdi 3, 3, 16
ret i64 %a ret i64 %a
; CHECK: blr ; CHECK: blr
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }

llvm/test/CodeGen/PowerPC/testBitReverse.ll

Show All 29 Lines
; PPC32-NEXT: and 4, 4, 5 ; PPC32-NEXT: and 4, 4, 5
; PPC32-NEXT: lis 5, 3855 ; PPC32-NEXT: lis 5, 3855
; PPC32-NEXT: ori 5, 5, 3855 ; PPC32-NEXT: ori 5, 5, 3855
; PPC32-NEXT: srwi 3, 3, 4 ; PPC32-NEXT: srwi 3, 3, 4
; PPC32-NEXT: and 3, 3, 5 ; PPC32-NEXT: and 3, 3, 5
; PPC32-NEXT: or 4, 3, 4 ; PPC32-NEXT: or 4, 3, 4
; PPC32-NEXT: rotlwi 3, 4, 24 ; PPC32-NEXT: rotlwi 3, 4, 24
; PPC32-NEXT: rlwimi 3, 4, 8, 8, 15 ; PPC32-NEXT: rlwimi 3, 4, 8, 8, 15
; PPC32-NEXT: rlwimi 3, 4, 8, 24, 31 ; PPC32-NEXT: inslwi 3, 4, 8, 24
; PPC32-NEXT: blr ; PPC32-NEXT: blr
; ;
; CHECK-LABEL: testBitReverseIntrinsicI32: ; CHECK-LABEL: testBitReverseIntrinsicI32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lis 4, -21846 ; CHECK-NEXT: lis 4, -21846
; CHECK-NEXT: lis 5, 21845 ; CHECK-NEXT: lis 5, 21845
; CHECK-NEXT: slwi 6, 3, 1 ; CHECK-NEXT: slwi 6, 3, 1
; CHECK-NEXT: srwi 3, 3, 1 ; CHECK-NEXT: srwi 3, 3, 1
Show All 17 Lines
; CHECK-NEXT: slwi 6, 3, 4 ; CHECK-NEXT: slwi 6, 3, 4
; CHECK-NEXT: ori 4, 4, 61680 ; CHECK-NEXT: ori 4, 4, 61680
; CHECK-NEXT: srwi 3, 3, 4 ; CHECK-NEXT: srwi 3, 3, 4
; CHECK-NEXT: and 4, 6, 4 ; CHECK-NEXT: and 4, 6, 4
; CHECK-NEXT: and 3, 3, 5 ; CHECK-NEXT: and 3, 3, 5
; CHECK-NEXT: or 3, 3, 4 ; CHECK-NEXT: or 3, 3, 4
; CHECK-NEXT: rotlwi 4, 3, 24 ; CHECK-NEXT: rotlwi 4, 3, 24
; CHECK-NEXT: rlwimi 4, 3, 8, 8, 15 ; CHECK-NEXT: rlwimi 4, 3, 8, 8, 15
; CHECK-NEXT: rlwimi 4, 3, 8, 24, 31 ; CHECK-NEXT: inslwi 4, 3, 8, 24
; CHECK-NEXT: rldicl 3, 4, 0, 32 ; CHECK-NEXT: rldicl 3, 4, 0, 32
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%res = call i32 @llvm.bitreverse.i32(i32 %arg) %res = call i32 @llvm.bitreverse.i32(i32 %arg)
ret i32 %res ret i32 %res
} }
declare i64 @llvm.bitreverse.i64(i64) declare i64 @llvm.bitreverse.i64(i64)
define i64 @testBitReverseIntrinsicI64(i64 %arg) { define i64 @testBitReverseIntrinsicI64(i64 %arg) {
Show All 40 Lines
; PPC32-NEXT: and 6, 6, 9 ; PPC32-NEXT: and 6, 6, 9
; PPC32-NEXT: and 3, 3, 11 ; PPC32-NEXT: and 3, 3, 11
; PPC32-NEXT: or 5, 4, 5 ; PPC32-NEXT: or 5, 4, 5
; PPC32-NEXT: or 6, 3, 6 ; PPC32-NEXT: or 6, 3, 6
; PPC32-NEXT: rotlwi 3, 5, 24 ; PPC32-NEXT: rotlwi 3, 5, 24
; PPC32-NEXT: rotlwi 4, 6, 24 ; PPC32-NEXT: rotlwi 4, 6, 24
; PPC32-NEXT: rlwimi 3, 5, 8, 8, 15 ; PPC32-NEXT: rlwimi 3, 5, 8, 8, 15
; PPC32-NEXT: rlwimi 4, 6, 8, 8, 15 ; PPC32-NEXT: rlwimi 4, 6, 8, 8, 15
; PPC32-NEXT: rlwimi 3, 5, 8, 24, 31 ; PPC32-NEXT: inslwi 3, 5, 8, 24
; PPC32-NEXT: rlwimi 4, 6, 8, 24, 31 ; PPC32-NEXT: inslwi 4, 6, 8, 24
; PPC32-NEXT: blr ; PPC32-NEXT: blr
; ;
; CHECK-LABEL: testBitReverseIntrinsicI64: ; CHECK-LABEL: testBitReverseIntrinsicI64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lis 4, -21846 ; CHECK-NEXT: lis 4, -21846
; CHECK-NEXT: lis 5, 21845 ; CHECK-NEXT: lis 5, 21845
; CHECK-NEXT: lis 7, -13108 ; CHECK-NEXT: lis 7, -13108
; CHECK-NEXT: lis 8, 13107 ; CHECK-NEXT: lis 8, 13107
; CHECK-NEXT: ori 4, 4, 43690 ; CHECK-NEXT: ori 4, 4, 43690
; CHECK-NEXT: ori 5, 5, 21845 ; CHECK-NEXT: ori 5, 5, 21845
; CHECK-NEXT: ori 7, 7, 52428 ; CHECK-NEXT: ori 7, 7, 52428
; CHECK-NEXT: ori 8, 8, 13107 ; CHECK-NEXT: ori 8, 8, 13107
; CHECK-NEXT: sldi 4, 4, 32 ; CHECK-NEXT: sldi 4, 4, 32
; CHECK-NEXT: sldi 5, 5, 32 ; CHECK-NEXT: sldi 5, 5, 32
; CHECK-NEXT: oris 4, 4, 43690 ; CHECK-NEXT: oris 4, 4, 43690
; CHECK-NEXT: oris 5, 5, 21845 ; CHECK-NEXT: oris 5, 5, 21845
; CHECK-NEXT: sldi 6, 3, 1 ; CHECK-NEXT: sldi 6, 3, 1
; CHECK-NEXT: rldicl 3, 3, 63, 1 ; CHECK-NEXT: srdi 3, 3, 1
; CHECK-NEXT: ori 4, 4, 43690 ; CHECK-NEXT: ori 4, 4, 43690
; CHECK-NEXT: ori 5, 5, 21845 ; CHECK-NEXT: ori 5, 5, 21845
; CHECK-NEXT: sldi 7, 7, 32 ; CHECK-NEXT: sldi 7, 7, 32
; CHECK-NEXT: sldi 8, 8, 32 ; CHECK-NEXT: sldi 8, 8, 32
; CHECK-NEXT: and 4, 6, 4 ; CHECK-NEXT: and 4, 6, 4
; CHECK-NEXT: and 3, 3, 5 ; CHECK-NEXT: and 3, 3, 5
; CHECK-NEXT: lis 5, -3856 ; CHECK-NEXT: lis 5, -3856
; CHECK-NEXT: oris 6, 7, 52428 ; CHECK-NEXT: oris 6, 7, 52428
; CHECK-NEXT: oris 7, 8, 13107 ; CHECK-NEXT: oris 7, 8, 13107
; CHECK-NEXT: or 3, 3, 4 ; CHECK-NEXT: or 3, 3, 4
; CHECK-NEXT: lis 4, 3855 ; CHECK-NEXT: lis 4, 3855
; CHECK-NEXT: ori 5, 5, 61680 ; CHECK-NEXT: ori 5, 5, 61680
; CHECK-NEXT: ori 6, 6, 52428 ; CHECK-NEXT: ori 6, 6, 52428
; CHECK-NEXT: ori 7, 7, 13107 ; CHECK-NEXT: ori 7, 7, 13107
; CHECK-NEXT: ori 4, 4, 3855 ; CHECK-NEXT: ori 4, 4, 3855
; CHECK-NEXT: sldi 8, 3, 2 ; CHECK-NEXT: sldi 8, 3, 2
; CHECK-NEXT: rldicl 3, 3, 62, 2 ; CHECK-NEXT: srdi 3, 3, 2
; CHECK-NEXT: and 6, 8, 6 ; CHECK-NEXT: and 6, 8, 6
; CHECK-NEXT: and 3, 3, 7 ; CHECK-NEXT: and 3, 3, 7
; CHECK-NEXT: sldi 5, 5, 32 ; CHECK-NEXT: sldi 5, 5, 32
; CHECK-NEXT: sldi 4, 4, 32 ; CHECK-NEXT: sldi 4, 4, 32
; CHECK-NEXT: or 3, 3, 6 ; CHECK-NEXT: or 3, 3, 6
; CHECK-NEXT: oris 5, 5, 61680 ; CHECK-NEXT: oris 5, 5, 61680
; CHECK-NEXT: oris 4, 4, 3855 ; CHECK-NEXT: oris 4, 4, 3855
; CHECK-NEXT: sldi 6, 3, 4 ; CHECK-NEXT: sldi 6, 3, 4
; CHECK-NEXT: ori 5, 5, 61680 ; CHECK-NEXT: ori 5, 5, 61680
; CHECK-NEXT: ori 4, 4, 3855 ; CHECK-NEXT: ori 4, 4, 3855
; CHECK-NEXT: rldicl 3, 3, 60, 4 ; CHECK-NEXT: srdi 3, 3, 4
; CHECK-NEXT: and 5, 6, 5 ; CHECK-NEXT: and 5, 6, 5
; CHECK-NEXT: and 3, 3, 4 ; CHECK-NEXT: and 3, 3, 4
; CHECK-NEXT: or 3, 3, 5 ; CHECK-NEXT: or 3, 3, 5
; CHECK-NEXT: rldicl 4, 3, 32, 32 ; CHECK-NEXT: srdi 4, 3, 32
; CHECK-NEXT: rotlwi 5, 3, 24 ; CHECK-NEXT: rotlwi 5, 3, 24
; CHECK-NEXT: rotlwi 6, 4, 24 ; CHECK-NEXT: rotlwi 6, 4, 24
; CHECK-NEXT: rlwimi 5, 3, 8, 8, 15 ; CHECK-NEXT: rlwimi 5, 3, 8, 8, 15
; CHECK-NEXT: rlwimi 5, 3, 8, 24, 31 ; CHECK-NEXT: inslwi 5, 3, 8, 24
; CHECK-NEXT: rlwimi 6, 4, 8, 8, 15 ; CHECK-NEXT: rlwimi 6, 4, 8, 8, 15
; CHECK-NEXT: rlwimi 6, 4, 8, 24, 31 ; CHECK-NEXT: inslwi 6, 4, 8, 24
; CHECK-NEXT: sldi 3, 5, 32 ; CHECK-NEXT: sldi 3, 5, 32
; CHECK-NEXT: or 3, 3, 6 ; CHECK-NEXT: or 3, 3, 6
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%res = call i64 @llvm.bitreverse.i64(i64 %arg) %res = call i64 @llvm.bitreverse.i64(i64 %arg)
ret i64 %res ret i64 %res
} }

llvm/test/CodeGen/PowerPC/testComparesi32gtu.ll

Show All 21 Lines
; BE-NEXT: lbz r3, 0(r3) ; BE-NEXT: lbz r3, 0(r3)
; BE-NEXT: ld r4, .LC0@toc@l(r4) ; BE-NEXT: ld r4, .LC0@toc@l(r4)
; BE-NEXT: clrlwi r3, r3, 31 ; BE-NEXT: clrlwi r3, r3, 31
; BE-NEXT: clrldi r3, r3, 32 ; BE-NEXT: clrldi r3, r3, 32
; BE-NEXT: lbz r4, 0(r4) ; BE-NEXT: lbz r4, 0(r4)
; BE-NEXT: clrlwi r4, r4, 31 ; BE-NEXT: clrlwi r4, r4, 31
; BE-NEXT: clrldi r4, r4, 32 ; BE-NEXT: clrldi r4, r4, 32
; BE-NEXT: sub r3, r3, r4 ; BE-NEXT: sub r3, r3, r4
; BE-NEXT: rldicl r3, r3, 1, 63 ; BE-NEXT: srdi r3, r3, 63
; BE-NEXT: bl fn2 ; BE-NEXT: bl fn2
; BE-NEXT: nop ; BE-NEXT: nop
; BE-NEXT: addi r1, r1, 112 ; BE-NEXT: addi r1, r1, 112
; BE-NEXT: ld r0, 16(r1) ; BE-NEXT: ld r0, 16(r1)
; BE-NEXT: mtlr r0 ; BE-NEXT: mtlr r0
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; LE-LABEL: testCompare1: ; LE-LABEL: testCompare1:
; LE: # %bb.0: # %entry ; LE: # %bb.0: # %entry
; LE-NEXT: mflr r0 ; LE-NEXT: mflr r0
; LE-NEXT: std r0, 16(r1) ; LE-NEXT: std r0, 16(r1)
; LE-NEXT: stdu r1, -32(r1) ; LE-NEXT: stdu r1, -32(r1)
; LE-NEXT: addis r4, r2, .LC0@toc@ha ; LE-NEXT: addis r4, r2, .LC0@toc@ha
; LE-NEXT: lbz r3, 0(r3) ; LE-NEXT: lbz r3, 0(r3)
; LE-NEXT: ld r4, .LC0@toc@l(r4) ; LE-NEXT: ld r4, .LC0@toc@l(r4)
; LE-NEXT: clrlwi r3, r3, 31 ; LE-NEXT: clrlwi r3, r3, 31
; LE-NEXT: clrldi r3, r3, 32 ; LE-NEXT: clrldi r3, r3, 32
; LE-NEXT: lbz r4, 0(r4) ; LE-NEXT: lbz r4, 0(r4)
; LE-NEXT: clrlwi r4, r4, 31 ; LE-NEXT: clrlwi r4, r4, 31
; LE-NEXT: clrldi r4, r4, 32 ; LE-NEXT: clrldi r4, r4, 32
; LE-NEXT: sub r3, r3, r4 ; LE-NEXT: sub r3, r3, r4
; LE-NEXT: rldicl r3, r3, 1, 63 ; LE-NEXT: srdi r3, r3, 63
; LE-NEXT: bl fn2 ; LE-NEXT: bl fn2
; LE-NEXT: nop ; LE-NEXT: nop
; LE-NEXT: addi r1, r1, 32 ; LE-NEXT: addi r1, r1, 32
; LE-NEXT: ld r0, 16(r1) ; LE-NEXT: ld r0, 16(r1)
; LE-NEXT: mtlr r0 ; LE-NEXT: mtlr r0
; LE-NEXT: blr ; LE-NEXT: blr
entry: entry:
%bf.load = load i8, i8* bitcast (i32 (%struct.tree_common*)* @testCompare1 to i8*), align 4 %bf.load = load i8, i8* bitcast (i32 (%struct.tree_common*)* @testCompare1 to i8*), align 4
Show All 11 Lines
define signext i32 @testCompare2(i32 zeroext %a, i32 zeroext %b) { define signext i32 @testCompare2(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: testCompare2: ; CHECK-LABEL: testCompare2:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: clrlwi r3, r3, 31 ; CHECK-NEXT: clrlwi r3, r3, 31
; CHECK-NEXT: clrlwi r4, r4, 31 ; CHECK-NEXT: clrlwi r4, r4, 31
; CHECK-NEXT: clrldi r3, r3, 32 ; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: clrldi r4, r4, 32 ; CHECK-NEXT: clrldi r4, r4, 32
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%and = and i32 %a, 1 %and = and i32 %a, 1
%and1 = and i32 %b, 1 %and1 = and i32 %b, 1
%cmp = icmp ugt i32 %and, %and1 %cmp = icmp ugt i32 %and, %and1
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }

llvm/test/CodeGen/PowerPC/testComparesi32leu.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
define signext i32 @test(i8 zeroext %a, i8 zeroext %b) { define signext i32 @test(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test: ; CHECK-LABEL: test:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: clrlwi r3, r3, 31 ; CHECK-NEXT: clrlwi r3, r3, 31
; CHECK-NEXT: clrlwi r4, r4, 31 ; CHECK-NEXT: clrlwi r4, r4, 31
; CHECK-NEXT: clrldi r3, r3, 32 ; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: clrldi r4, r4, 32 ; CHECK-NEXT: clrldi r4, r4, 32
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%0 = and i8 %a, 1 %0 = and i8 %a, 1
%1 = and i8 %b, 1 %1 = and i8 %b, 1
%cmp = icmp ule i8 %0, %1 %cmp = icmp ule i8 %0, %1
%conv3 = zext i1 %cmp to i32 %conv3 = zext i1 %cmp to i32
ret i32 %conv3 ret i32 %conv3
} }

llvm/test/CodeGen/PowerPC/testComparesi32ltu.ll

Show All 21 Lines
; BE-NEXT: lbz r3, 0(r3) ; BE-NEXT: lbz r3, 0(r3)
; BE-NEXT: ld r4, .LC0@toc@l(r4) ; BE-NEXT: ld r4, .LC0@toc@l(r4)
; BE-NEXT: clrlwi r3, r3, 31 ; BE-NEXT: clrlwi r3, r3, 31
; BE-NEXT: clrldi r3, r3, 32 ; BE-NEXT: clrldi r3, r3, 32
; BE-NEXT: lbz r4, 0(r4) ; BE-NEXT: lbz r4, 0(r4)
; BE-NEXT: clrlwi r4, r4, 31 ; BE-NEXT: clrlwi r4, r4, 31
; BE-NEXT: clrldi r4, r4, 32 ; BE-NEXT: clrldi r4, r4, 32
; BE-NEXT: sub r3, r4, r3 ; BE-NEXT: sub r3, r4, r3
; BE-NEXT: rldicl r3, r3, 1, 63 ; BE-NEXT: srdi r3, r3, 63
; BE-NEXT: bl fn2 ; BE-NEXT: bl fn2
; BE-NEXT: nop ; BE-NEXT: nop
; BE-NEXT: addi r1, r1, 112 ; BE-NEXT: addi r1, r1, 112
; BE-NEXT: ld r0, 16(r1) ; BE-NEXT: ld r0, 16(r1)
; BE-NEXT: mtlr r0 ; BE-NEXT: mtlr r0
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; LE-LABEL: testCompare1: ; LE-LABEL: testCompare1:
; LE: # %bb.0: # %entry ; LE: # %bb.0: # %entry
; LE-NEXT: mflr r0 ; LE-NEXT: mflr r0
; LE-NEXT: std r0, 16(r1) ; LE-NEXT: std r0, 16(r1)
; LE-NEXT: stdu r1, -32(r1) ; LE-NEXT: stdu r1, -32(r1)
; LE-NEXT: addis r4, r2, .LC0@toc@ha ; LE-NEXT: addis r4, r2, .LC0@toc@ha
; LE-NEXT: lbz r3, 0(r3) ; LE-NEXT: lbz r3, 0(r3)
; LE-NEXT: ld r4, .LC0@toc@l(r4) ; LE-NEXT: ld r4, .LC0@toc@l(r4)
; LE-NEXT: clrlwi r3, r3, 31 ; LE-NEXT: clrlwi r3, r3, 31
; LE-NEXT: clrldi r3, r3, 32 ; LE-NEXT: clrldi r3, r3, 32
; LE-NEXT: lbz r4, 0(r4) ; LE-NEXT: lbz r4, 0(r4)
; LE-NEXT: clrlwi r4, r4, 31 ; LE-NEXT: clrlwi r4, r4, 31
; LE-NEXT: clrldi r4, r4, 32 ; LE-NEXT: clrldi r4, r4, 32
; LE-NEXT: sub r3, r4, r3 ; LE-NEXT: sub r3, r4, r3
; LE-NEXT: rldicl r3, r3, 1, 63 ; LE-NEXT: srdi r3, r3, 63
; LE-NEXT: bl fn2 ; LE-NEXT: bl fn2
; LE-NEXT: nop ; LE-NEXT: nop
; LE-NEXT: addi r1, r1, 32 ; LE-NEXT: addi r1, r1, 32
; LE-NEXT: ld r0, 16(r1) ; LE-NEXT: ld r0, 16(r1)
; LE-NEXT: mtlr r0 ; LE-NEXT: mtlr r0
; LE-NEXT: blr ; LE-NEXT: blr
entry: entry:
%bf.load = load i8, i8* bitcast (i32 (%struct.tree_common*)* @testCompare1 to i8*), align 4 %bf.load = load i8, i8* bitcast (i32 (%struct.tree_common*)* @testCompare1 to i8*), align 4
Show All 11 Lines
define signext i32 @testCompare2(i32 zeroext %a, i32 zeroext %b) { define signext i32 @testCompare2(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: testCompare2: ; CHECK-LABEL: testCompare2:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: clrlwi r3, r3, 31 ; CHECK-NEXT: clrlwi r3, r3, 31
; CHECK-NEXT: clrlwi r4, r4, 31 ; CHECK-NEXT: clrlwi r4, r4, 31
; CHECK-NEXT: clrldi r3, r3, 32 ; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: clrldi r4, r4, 32 ; CHECK-NEXT: clrldi r4, r4, 32
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%and = and i32 %a, 1 %and = and i32 %a, 1
%and1 = and i32 %b, 1 %and1 = and i32 %b, 1
%cmp = icmp ult i32 %and, %and1 %cmp = icmp ult i32 %and, %and1
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }

llvm/test/CodeGen/PowerPC/testComparesieqsll.ll

Show All 15 Lines
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63 ; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ieqsll: ; CHECK-BE-LABEL: test_ieqsll:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xor r3, r3, r4 ; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: cntlzd r3, r3 ; CHECK-BE-NEXT: cntlzd r3, r3
; CHECK-BE-NEXT: rldicl r3, r3, 58, 63 ; CHECK-BE-NEXT: extrdi r3, r3, 1, 57
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_ieqsll: ; CHECK-LE-LABEL: test_ieqsll:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4 ; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: cntlzd r3, r3 ; CHECK-LE-NEXT: cntlzd r3, r3
; CHECK-LE-NEXT: rldicl r3, r3, 58, 63 ; CHECK-LE-NEXT: extrdi r3, r3, 1, 57
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i64 %a, %b %cmp = icmp eq i64 %a, %b
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
Show All 28 Lines
; CHECK-LABEL: test_ieqsll_z: ; CHECK-LABEL: test_ieqsll_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63 ; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ieqsll_z: ; CHECK-BE-LABEL: test_ieqsll_z:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: cntlzd r3, r3 ; CHECK-BE-NEXT: cntlzd r3, r3
; CHECK-BE-NEXT: rldicl r3, r3, 58, 63 ; CHECK-BE-NEXT: extrdi r3, r3, 1, 57
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_ieqsll_z: ; CHECK-LE-LABEL: test_ieqsll_z:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzd r3, r3 ; CHECK-LE-NEXT: cntlzd r3, r3
; CHECK-LE-NEXT: rldicl r3, r3, 58, 63 ; CHECK-LE-NEXT: extrdi r3, r3, 1, 57
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i64 %a, 0 %cmp = icmp eq i64 %a, 0
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
Show All 31 Lines
; CHECK-NEXT: std r3, glob@toc@l(r5) ; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ieqsll_store: ; CHECK-BE-LABEL: test_ieqsll_store:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: xor r3, r3, r4 ; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: cntlzd r3, r3 ; CHECK-BE-NEXT: cntlzd r3, r3
; CHECK-BE-NEXT: rldicl r3, r3, 58, 63 ; CHECK-BE-NEXT: extrdi r3, r3, 1, 57
; CHECK-BE-NEXT: std r3, 0(r4) ; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_ieqsll_store: ; CHECK-LE-LABEL: test_ieqsll_store:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4 ; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha ; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: cntlzd r3, r3 ; CHECK-LE-NEXT: cntlzd r3, r3
; CHECK-LE-NEXT: rldicl r3, r3, 58, 63 ; CHECK-LE-NEXT: extrdi r3, r3, 1, 57
; CHECK-LE-NEXT: std r3, glob@toc@l(r5) ; CHECK-LE-NEXT: std r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i64 %a, %b %cmp = icmp eq i64 %a, %b
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
; CHECK-NEXT: rldicl r3, r3, 58, 63 ; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: std r3, glob@toc@l(r4) ; CHECK-NEXT: std r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ieqsll_z_store: ; CHECK-BE-LABEL: test_ieqsll_z_store:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: cntlzd r3, r3 ; CHECK-BE-NEXT: cntlzd r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: rldicl r3, r3, 58, 63 ; CHECK-BE-NEXT: extrdi r3, r3, 1, 57
; CHECK-BE-NEXT: std r3, 0(r4) ; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_ieqsll_z_store: ; CHECK-LE-LABEL: test_ieqsll_z_store:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzd r3, r3 ; CHECK-LE-NEXT: cntlzd r3, r3
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha ; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: rldicl r3, r3, 58, 63 ; CHECK-LE-NEXT: extrdi r3, r3, 1, 57
; CHECK-LE-NEXT: std r3, glob@toc@l(r4) ; CHECK-LE-NEXT: std r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i64 %a, 0 %cmp = icmp eq i64 %a, 0
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }
Show All 32 Lines

llvm/test/CodeGen/PowerPC/testComparesiequll.ll

Show All 15 Lines
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63 ; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iequll: ; CHECK-BE-LABEL: test_iequll:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xor r3, r3, r4 ; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: cntlzd r3, r3 ; CHECK-BE-NEXT: cntlzd r3, r3
; CHECK-BE-NEXT: rldicl r3, r3, 58, 63 ; CHECK-BE-NEXT: extrdi r3, r3, 1, 57
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_iequll: ; CHECK-LE-LABEL: test_iequll:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4 ; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: cntlzd r3, r3 ; CHECK-LE-NEXT: cntlzd r3, r3
; CHECK-LE-NEXT: rldicl r3, r3, 58, 63 ; CHECK-LE-NEXT: extrdi r3, r3, 1, 57
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i64 %a, %b %cmp = icmp eq i64 %a, %b
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
Show All 28 Lines
; CHECK-LABEL: test_iequll_z: ; CHECK-LABEL: test_iequll_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63 ; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iequll_z: ; CHECK-BE-LABEL: test_iequll_z:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: cntlzd r3, r3 ; CHECK-BE-NEXT: cntlzd r3, r3
; CHECK-BE-NEXT: rldicl r3, r3, 58, 63 ; CHECK-BE-NEXT: extrdi r3, r3, 1, 57
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_iequll_z: ; CHECK-LE-LABEL: test_iequll_z:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzd r3, r3 ; CHECK-LE-NEXT: cntlzd r3, r3
; CHECK-LE-NEXT: rldicl r3, r3, 58, 63 ; CHECK-LE-NEXT: extrdi r3, r3, 1, 57
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i64 %a, 0 %cmp = icmp eq i64 %a, 0
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
Show All 31 Lines
; CHECK-NEXT: std r3, glob@toc@l(r5) ; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iequll_store: ; CHECK-BE-LABEL: test_iequll_store:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: xor r3, r3, r4 ; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: cntlzd r3, r3 ; CHECK-BE-NEXT: cntlzd r3, r3
; CHECK-BE-NEXT: rldicl r3, r3, 58, 63 ; CHECK-BE-NEXT: extrdi r3, r3, 1, 57
; CHECK-BE-NEXT: std r3, 0(r4) ; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_iequll_store: ; CHECK-LE-LABEL: test_iequll_store:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4 ; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha ; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: cntlzd r3, r3 ; CHECK-LE-NEXT: cntlzd r3, r3
; CHECK-LE-NEXT: rldicl r3, r3, 58, 63 ; CHECK-LE-NEXT: extrdi r3, r3, 1, 57
; CHECK-LE-NEXT: std r3, glob@toc@l(r5) ; CHECK-LE-NEXT: std r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i64 %a, %b %cmp = icmp eq i64 %a, %b
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
; CHECK-NEXT: rldicl r3, r3, 58, 63 ; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: std r3, glob@toc@l(r4) ; CHECK-NEXT: std r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iequll_z_store: ; CHECK-BE-LABEL: test_iequll_z_store:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: cntlzd r3, r3 ; CHECK-BE-NEXT: cntlzd r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: rldicl r3, r3, 58, 63 ; CHECK-BE-NEXT: extrdi r3, r3, 1, 57
; CHECK-BE-NEXT: std r3, 0(r4) ; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_iequll_z_store: ; CHECK-LE-LABEL: test_iequll_z_store:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzd r3, r3 ; CHECK-LE-NEXT: cntlzd r3, r3
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha ; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: rldicl r3, r3, 58, 63 ; CHECK-LE-NEXT: extrdi r3, r3, 1, 57
; CHECK-LE-NEXT: std r3, glob@toc@l(r4) ; CHECK-LE-NEXT: std r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i64 %a, 0 %cmp = icmp eq i64 %a, 0
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }
Show All 32 Lines

llvm/test/CodeGen/PowerPC/testComparesigesc.ll

Show All 11 Lines
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_igesc: ; CHECK-BE-LABEL: test_igesc:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sub r3, r3, r4 ; CHECK-BE-NEXT: sub r3, r3, r4
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-BE-NEXT: srdi r3, r3, 63
; CHECK-BE-NEXT: xori r3, r3, 1 ; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_igesc: ; CHECK-LE-LABEL: test_igesc:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r3, r4 ; CHECK-LE-NEXT: sub r3, r3, r4
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-LE-NEXT: srdi r3, r3, 63
; CHECK-LE-NEXT: xori r3, r3, 1 ; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i8 %a, %b %cmp = icmp sge i8 %a, %b
%conv2 = zext i1 %cmp to i32 %conv2 = zext i1 %cmp to i32
ret i32 %conv2 ret i32 %conv2
} }
define signext i32 @test_igesc_sext(i8 signext %a, i8 signext %b) { define signext i32 @test_igesc_sext(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_igesc_sext: ; CHECK-LABEL: test_igesc_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_igesc_sext: ; CHECK-BE-LABEL: test_igesc_sext:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sub r3, r3, r4 ; CHECK-BE-NEXT: sub r3, r3, r4
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-BE-NEXT: srdi r3, r3, 63
; CHECK-BE-NEXT: addi r3, r3, -1 ; CHECK-BE-NEXT: addi r3, r3, -1
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_igesc_sext: ; CHECK-LE-LABEL: test_igesc_sext:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r3, r4 ; CHECK-LE-NEXT: sub r3, r3, r4
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-LE-NEXT: srdi r3, r3, 63
; CHECK-LE-NEXT: addi r3, r3, -1 ; CHECK-LE-NEXT: addi r3, r3, -1
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i8 %a, %b %cmp = icmp sge i8 %a, %b
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
ret i32 %sub ret i32 %sub
} }
define void @test_igesc_store(i8 signext %a, i8 signext %b) { define void @test_igesc_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_igesc_store: ; CHECK-LABEL: test_igesc_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stb r3, glob@toc@l(r5) ; CHECK-NEXT: stb r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_igesc_store: ; CHECK-BE-LABEL: test_igesc_store:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sub r3, r3, r4 ; CHECK-BE-NEXT: sub r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-BE-NEXT: srdi r3, r3, 63
; CHECK-BE-NEXT: xori r3, r3, 1 ; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: stb r3, 0(r4) ; CHECK-BE-NEXT: stb r3, 0(r4)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_igesc_store: ; CHECK-LE-LABEL: test_igesc_store:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r3, r4 ; CHECK-LE-NEXT: sub r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha ; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-LE-NEXT: srdi r3, r3, 63
; CHECK-LE-NEXT: xori r3, r3, 1 ; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: stb r3, glob@toc@l(r5) ; CHECK-LE-NEXT: stb r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i8 %a, %b %cmp = icmp sge i8 %a, %b
%conv3 = zext i1 %cmp to i8 %conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1 store i8 %conv3, i8* @glob, align 1
ret void ret void
} }
define void @test_igesc_sext_store(i8 signext %a, i8 signext %b) { define void @test_igesc_sext_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_igesc_sext_store: ; CHECK-LABEL: test_igesc_sext_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: stb r3, glob@toc@l(r5) ; CHECK-NEXT: stb r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_igesc_sext_store: ; CHECK-BE-LABEL: test_igesc_sext_store:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sub r3, r3, r4 ; CHECK-BE-NEXT: sub r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-BE-NEXT: srdi r3, r3, 63
; CHECK-BE-NEXT: addi r3, r3, -1 ; CHECK-BE-NEXT: addi r3, r3, -1
; CHECK-BE-NEXT: stb r3, 0(r4) ; CHECK-BE-NEXT: stb r3, 0(r4)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_igesc_sext_store: ; CHECK-LE-LABEL: test_igesc_sext_store:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r3, r4 ; CHECK-LE-NEXT: sub r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha ; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-LE-NEXT: srdi r3, r3, 63
; CHECK-LE-NEXT: addi r3, r3, -1 ; CHECK-LE-NEXT: addi r3, r3, -1
; CHECK-LE-NEXT: stb r3, glob@toc@l(r5) ; CHECK-LE-NEXT: stb r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i8 %a, %b %cmp = icmp sge i8 %a, %b
%conv3 = sext i1 %cmp to i8 %conv3 = sext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1 store i8 %conv3, i8* @glob, align 1
ret void ret void
} }

llvm/test/CodeGen/PowerPC/testComparesigesi.ll

Show All 11 Lines
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_igesi: ; CHECK-BE-LABEL: test_igesi:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sub r3, r3, r4 ; CHECK-BE-NEXT: sub r3, r3, r4
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-BE-NEXT: srdi r3, r3, 63
; CHECK-BE-NEXT: xori r3, r3, 1 ; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_igesi: ; CHECK-LE-LABEL: test_igesi:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r3, r4 ; CHECK-LE-NEXT: sub r3, r3, r4
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-LE-NEXT: srdi r3, r3, 63
; CHECK-LE-NEXT: xori r3, r3, 1 ; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i32 %a, %b %cmp = icmp sge i32 %a, %b
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
define signext i32 @test_igesi_sext(i32 signext %a, i32 signext %b) { define signext i32 @test_igesi_sext(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_igesi_sext: ; CHECK-LABEL: test_igesi_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_igesi_sext: ; CHECK-BE-LABEL: test_igesi_sext:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sub r3, r3, r4 ; CHECK-BE-NEXT: sub r3, r3, r4
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-BE-NEXT: srdi r3, r3, 63
; CHECK-BE-NEXT: addi r3, r3, -1 ; CHECK-BE-NEXT: addi r3, r3, -1
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_igesi_sext: ; CHECK-LE-LABEL: test_igesi_sext:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r3, r4 ; CHECK-LE-NEXT: sub r3, r3, r4
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-LE-NEXT: srdi r3, r3, 63
; CHECK-LE-NEXT: addi r3, r3, -1 ; CHECK-LE-NEXT: addi r3, r3, -1
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i32 %a, %b %cmp = icmp sge i32 %a, %b
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
ret i32 %sub ret i32 %sub
} }
define void @test_igesi_store(i32 signext %a, i32 signext %b) { define void @test_igesi_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_igesi_store: ; CHECK-LABEL: test_igesi_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stw r3, glob@toc@l(r5) ; CHECK-NEXT: stw r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_igesi_store: ; CHECK-BE-LABEL: test_igesi_store:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sub r3, r3, r4 ; CHECK-BE-NEXT: sub r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-BE-NEXT: srdi r3, r3, 63
; CHECK-BE-NEXT: xori r3, r3, 1 ; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: stw r3, 0(r4) ; CHECK-BE-NEXT: stw r3, 0(r4)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_igesi_store: ; CHECK-LE-LABEL: test_igesi_store:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r3, r4 ; CHECK-LE-NEXT: sub r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha ; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-LE-NEXT: srdi r3, r3, 63
; CHECK-LE-NEXT: xori r3, r3, 1 ; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: stw r3, glob@toc@l(r5) ; CHECK-LE-NEXT: stw r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i32 %a, %b %cmp = icmp sge i32 %a, %b
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4 store i32 %conv, i32* @glob, align 4
ret void ret void
} }
define void @test_igesi_sext_store(i32 signext %a, i32 signext %b) { define void @test_igesi_sext_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_igesi_sext_store: ; CHECK-LABEL: test_igesi_sext_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: stw r3, glob@toc@l(r5) ; CHECK-NEXT: stw r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_igesi_sext_store: ; CHECK-BE-LABEL: test_igesi_sext_store:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sub r3, r3, r4 ; CHECK-BE-NEXT: sub r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-BE-NEXT: srdi r3, r3, 63
; CHECK-BE-NEXT: addi r3, r3, -1 ; CHECK-BE-NEXT: addi r3, r3, -1
; CHECK-BE-NEXT: stw r3, 0(r4) ; CHECK-BE-NEXT: stw r3, 0(r4)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_igesi_sext_store: ; CHECK-LE-LABEL: test_igesi_sext_store:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r3, r4 ; CHECK-LE-NEXT: sub r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha ; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-LE-NEXT: srdi r3, r3, 63
; CHECK-LE-NEXT: addi r3, r3, -1 ; CHECK-LE-NEXT: addi r3, r3, -1
; CHECK-LE-NEXT: stw r3, glob@toc@l(r5) ; CHECK-LE-NEXT: stw r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i32 %a, %b %cmp = icmp sge i32 %a, %b
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4 store i32 %sub, i32* @glob, align 4
ret void ret void
} }

llvm/test/CodeGen/PowerPC/testComparesigesll.ll

Show All 12 Lines
; CHECK-NEXT: sradi r5, r3, 63 ; CHECK-NEXT: sradi r5, r3, 63
; CHECK-NEXT: rldicl r6, r4, 1, 63 ; CHECK-NEXT: rldicl r6, r4, 1, 63
; CHECK-NEXT: subfc r3, r4, r3 ; CHECK-NEXT: subfc r3, r4, r3
; CHECK-NEXT: adde r3, r5, r6 ; CHECK-NEXT: adde r3, r5, r6
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_igesll: ; CHECK-BE-LABEL: test_igesll:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r5, r3, 63 ; CHECK-BE-NEXT: sradi r5, r3, 63
; CHECK-BE-NEXT: rldicl r6, r4, 1, 63 ; CHECK-BE-NEXT: srdi r6, r4, 63
; CHECK-BE-NEXT: subc r3, r3, r4 ; CHECK-BE-NEXT: subc r3, r3, r4
; CHECK-BE-NEXT: adde r3, r5, r6 ; CHECK-BE-NEXT: adde r3, r5, r6
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_igesll: ; CHECK-LE-LABEL: test_igesll:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r5, r3, 63 ; CHECK-LE-NEXT: sradi r5, r3, 63
; CHECK-LE-NEXT: rldicl r6, r4, 1, 63 ; CHECK-LE-NEXT: srdi r6, r4, 63
; CHECK-LE-NEXT: subc r3, r3, r4 ; CHECK-LE-NEXT: subc r3, r3, r4
; CHECK-LE-NEXT: adde r3, r5, r6 ; CHECK-LE-NEXT: adde r3, r5, r6
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i64 %a, %b %cmp = icmp sge i64 %a, %b
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
define signext i32 @test_igesll_sext(i64 %a, i64 %b) { define signext i32 @test_igesll_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_igesll_sext: ; CHECK-LABEL: test_igesll_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r5, r3, 63 ; CHECK-NEXT: sradi r5, r3, 63
; CHECK-NEXT: rldicl r6, r4, 1, 63 ; CHECK-NEXT: rldicl r6, r4, 1, 63
; CHECK-NEXT: subfc r3, r4, r3 ; CHECK-NEXT: subfc r3, r4, r3
; CHECK-NEXT: adde r3, r5, r6 ; CHECK-NEXT: adde r3, r5, r6
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_igesll_sext: ; CHECK-BE-LABEL: test_igesll_sext:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r5, r3, 63 ; CHECK-BE-NEXT: sradi r5, r3, 63
; CHECK-BE-NEXT: rldicl r6, r4, 1, 63 ; CHECK-BE-NEXT: srdi r6, r4, 63
; CHECK-BE-NEXT: subc r3, r3, r4 ; CHECK-BE-NEXT: subc r3, r3, r4
; CHECK-BE-NEXT: adde r3, r5, r6 ; CHECK-BE-NEXT: adde r3, r5, r6
; CHECK-BE-NEXT: neg r3, r3 ; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_igesll_sext: ; CHECK-LE-LABEL: test_igesll_sext:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r5, r3, 63 ; CHECK-LE-NEXT: sradi r5, r3, 63
; CHECK-LE-NEXT: rldicl r6, r4, 1, 63 ; CHECK-LE-NEXT: srdi r6, r4, 63
; CHECK-LE-NEXT: subc r3, r3, r4 ; CHECK-LE-NEXT: subc r3, r3, r4
; CHECK-LE-NEXT: adde r3, r5, r6 ; CHECK-LE-NEXT: adde r3, r5, r6
; CHECK-LE-NEXT: neg r3, r3 ; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i64 %a, %b %cmp = icmp sge i64 %a, %b
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
ret i32 %sub ret i32 %sub
} }
define signext i32 @test_igesll_z(i64 %a) { define signext i32 @test_igesll_z(i64 %a) {
; CHECK-LABEL: test_igesll_z: ; CHECK-LABEL: test_igesll_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: not r3, r3 ; CHECK-NEXT: not r3, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_igesll_z: ; CHECK-BE-LABEL: test_igesll_z:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: not r3, r3 ; CHECK-BE-NEXT: not r3, r3
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-BE-NEXT: srdi r3, r3, 63
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_igesll_z: ; CHECK-LE-LABEL: test_igesll_z:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: not r3, r3 ; CHECK-LE-NEXT: not r3, r3
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-LE-NEXT: srdi r3, r3, 63
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sgt i64 %a, -1 %cmp = icmp sgt i64 %a, -1
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
define signext i32 @test_igesll_sext_z(i64 %a) { define signext i32 @test_igesll_sext_z(i64 %a) {
Show All 30 Lines
; CHECK-NEXT: std r3, glob@toc@l(r5) ; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_igesll_store: ; CHECK-BE-LABEL: test_igesll_store:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sradi r6, r3, 63 ; CHECK-BE-NEXT: sradi r6, r3, 63
; CHECK-BE-NEXT: ld r5, .LC0@toc@l(r5) ; CHECK-BE-NEXT: ld r5, .LC0@toc@l(r5)
; CHECK-BE-NEXT: subc r3, r3, r4 ; CHECK-BE-NEXT: subc r3, r3, r4
; CHECK-BE-NEXT: rldicl r3, r4, 1, 63 ; CHECK-BE-NEXT: srdi r3, r4, 63
; CHECK-BE-NEXT: adde r3, r6, r3 ; CHECK-BE-NEXT: adde r3, r6, r3
; CHECK-BE-NEXT: std r3, 0(r5) ; CHECK-BE-NEXT: std r3, 0(r5)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_igesll_store: ; CHECK-LE-LABEL: test_igesll_store:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r6, r3, 63 ; CHECK-LE-NEXT: sradi r6, r3, 63
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha ; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: subc r3, r3, r4 ; CHECK-LE-NEXT: subc r3, r3, r4
; CHECK-LE-NEXT: rldicl r3, r4, 1, 63 ; CHECK-LE-NEXT: srdi r3, r4, 63
; CHECK-LE-NEXT: adde r3, r6, r3 ; CHECK-LE-NEXT: adde r3, r6, r3
; CHECK-LE-NEXT: std r3, glob@toc@l(r5) ; CHECK-LE-NEXT: std r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i64 %a, %b %cmp = icmp sge i64 %a, %b
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
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; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: std r3, glob@toc@l(r5) ; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_igesll_sext_store: ; CHECK-BE-LABEL: test_igesll_sext_store:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r6, r3, 63 ; CHECK-BE-NEXT: sradi r6, r3, 63
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: subc r3, r3, r4 ; CHECK-BE-NEXT: subc r3, r3, r4
; CHECK-BE-NEXT: rldicl r3, r4, 1, 63 ; CHECK-BE-NEXT: srdi r3, r4, 63
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: adde r3, r6, r3 ; CHECK-BE-NEXT: adde r3, r6, r3
; CHECK-BE-NEXT: neg r3, r3 ; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: std r3, 0(r4) ; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_igesll_sext_store: ; CHECK-LE-LABEL: test_igesll_sext_store:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r6, r3, 63 ; CHECK-LE-NEXT: sradi r6, r3, 63
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha ; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: subc r3, r3, r4 ; CHECK-LE-NEXT: subc r3, r3, r4
; CHECK-LE-NEXT: rldicl r3, r4, 1, 63 ; CHECK-LE-NEXT: srdi r3, r4, 63
; CHECK-LE-NEXT: adde r3, r6, r3 ; CHECK-LE-NEXT: adde r3, r6, r3
; CHECK-LE-NEXT: neg r3, r3 ; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: std r3, glob@toc@l(r5) ; CHECK-LE-NEXT: std r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i64 %a, %b %cmp = icmp sge i64 %a, %b
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }
define void @test_igesll_z_store(i64 %a) { define void @test_igesll_z_store(i64 %a) {
; CHECK-LABEL: test_igesll_z_store: ; CHECK-LABEL: test_igesll_z_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: not r3, r3 ; CHECK-NEXT: not r3, r3
; CHECK-NEXT: addis r4, r2, glob@toc@ha ; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: std r3, glob@toc@l(r4) ; CHECK-NEXT: std r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_igesll_z_store: ; CHECK-BE-LABEL: test_igesll_z_store:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: not r3, r3 ; CHECK-BE-NEXT: not r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-BE-NEXT: srdi r3, r3, 63
; CHECK-BE-NEXT: std r3, 0(r4) ; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_igesll_z_store: ; CHECK-LE-LABEL: test_igesll_z_store:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: not r3, r3 ; CHECK-LE-NEXT: not r3, r3
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha ; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-LE-NEXT: srdi r3, r3, 63
; CHECK-LE-NEXT: std r3, glob@toc@l(r4) ; CHECK-LE-NEXT: std r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sgt i64 %a, -1 %cmp = icmp sgt i64 %a, -1
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }
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llvm/test/CodeGen/PowerPC/testComparesigess.ll

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; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_igess: ; CHECK-BE-LABEL: test_igess:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sub r3, r3, r4 ; CHECK-BE-NEXT: sub r3, r3, r4
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-BE-NEXT: srdi r3, r3, 63
; CHECK-BE-NEXT: xori r3, r3, 1 ; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_igess: ; CHECK-LE-LABEL: test_igess:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r3, r4 ; CHECK-LE-NEXT: sub r3, r3, r4
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-LE-NEXT: srdi r3, r3, 63
; CHECK-LE-NEXT: xori r3, r3, 1 ; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i16 %a, %b %cmp = icmp sge i16 %a, %b
%conv2 = zext i1 %cmp to i32 %conv2 = zext i1 %cmp to i32
ret i32 %conv2 ret i32 %conv2
} }
define signext i32 @test_igess_sext(i16 signext %a, i16 signext %b) { define signext i32 @test_igess_sext(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_igess_sext: ; CHECK-LABEL: test_igess_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_igess_sext: ; CHECK-BE-LABEL: test_igess_sext:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sub r3, r3, r4 ; CHECK-BE-NEXT: sub r3, r3, r4
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-BE-NEXT: srdi r3, r3, 63
; CHECK-BE-NEXT: addi r3, r3, -1 ; CHECK-BE-NEXT: addi r3, r3, -1
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_igess_sext: ; CHECK-LE-LABEL: test_igess_sext:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r3, r4 ; CHECK-LE-NEXT: sub r3, r3, r4
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-LE-NEXT: srdi r3, r3, 63
; CHECK-LE-NEXT: addi r3, r3, -1 ; CHECK-LE-NEXT: addi r3, r3, -1
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i16 %a, %b %cmp = icmp sge i16 %a, %b
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
ret i32 %sub ret i32 %sub
} }
define void @test_igess_store(i16 signext %a, i16 signext %b) { define void @test_igess_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_igess_store: ; CHECK-LABEL: test_igess_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: sth r3, glob@toc@l(r5) ; CHECK-NEXT: sth r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_igess_store: ; CHECK-BE-LABEL: test_igess_store:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sub r3, r3, r4 ; CHECK-BE-NEXT: sub r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-BE-NEXT: srdi r3, r3, 63
; CHECK-BE-NEXT: xori r3, r3, 1 ; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: sth r3, 0(r4) ; CHECK-BE-NEXT: sth r3, 0(r4)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_igess_store: ; CHECK-LE-LABEL: test_igess_store:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r3, r4 ; CHECK-LE-NEXT: sub r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha ; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-LE-NEXT: srdi r3, r3, 63
; CHECK-LE-NEXT: xori r3, r3, 1 ; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: sth r3, glob@toc@l(r5) ; CHECK-LE-NEXT: sth r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i16 %a, %b %cmp = icmp sge i16 %a, %b
%conv3 = zext i1 %cmp to i16 %conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2 store i16 %conv3, i16* @glob, align 2
ret void ret void
} }
define void @test_igess_sext_store(i16 signext %a, i16 signext %b) { define void @test_igess_sext_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_igess_sext_store: ; CHECK-LABEL: test_igess_sext_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: sth r3, glob@toc@l(r5) ; CHECK-NEXT: sth r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_igess_sext_store: ; CHECK-BE-LABEL: test_igess_sext_store:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sub r3, r3, r4 ; CHECK-BE-NEXT: sub r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-BE-NEXT: srdi r3, r3, 63
; CHECK-BE-NEXT: addi r3, r3, -1 ; CHECK-BE-NEXT: addi r3, r3, -1
; CHECK-BE-NEXT: sth r3, 0(r4) ; CHECK-BE-NEXT: sth r3, 0(r4)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_igess_sext_store: ; CHECK-LE-LABEL: test_igess_sext_store:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r3, r4 ; CHECK-LE-NEXT: sub r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha ; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-LE-NEXT: srdi r3, r3, 63
; CHECK-LE-NEXT: addi r3, r3, -1 ; CHECK-LE-NEXT: addi r3, r3, -1
; CHECK-LE-NEXT: sth r3, glob@toc@l(r5) ; CHECK-LE-NEXT: sth r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i16 %a, %b %cmp = icmp sge i16 %a, %b
%conv3 = sext i1 %cmp to i16 %conv3 = sext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2 store i16 %conv3, i16* @glob, align 2
ret void ret void
} }

llvm/test/CodeGen/PowerPC/testComparesigeuc.ll

Show All 10 Lines
@glob = local_unnamed_addr global i8 0, align 1 @glob = local_unnamed_addr global i8 0, align 1
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igeuc(i8 zeroext %a, i8 zeroext %b) { define signext i32 @test_igeuc(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_igeuc: ; CHECK-LABEL: test_igeuc:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: not r3, r3 ; CHECK-NEXT: not r3, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp uge i8 %a, %b %cmp = icmp uge i8 %a, %b
%conv2 = zext i1 %cmp to i32 %conv2 = zext i1 %cmp to i32
ret i32 %conv2 ret i32 %conv2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igeuc_sext(i8 zeroext %a, i8 zeroext %b) { define signext i32 @test_igeuc_sext(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_igeuc_sext: ; CHECK-LABEL: test_igeuc_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp uge i8 %a, %b %cmp = icmp uge i8 %a, %b
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
ret i32 %sub ret i32 %sub
} }
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; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_igeuc_store(i8 zeroext %a, i8 zeroext %b) { define void @test_igeuc_store(i8 zeroext %a, i8 zeroext %b) {
; BE-LABEL: test_igeuc_store: ; BE-LABEL: test_igeuc_store:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha ; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: sub r3, r3, r4 ; BE-NEXT: sub r3, r3, r4
; BE-NEXT: ld r4, .LC0@toc@l(r5) ; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: not r3, r3 ; BE-NEXT: not r3, r3
; BE-NEXT: rldicl r3, r3, 1, 63 ; BE-NEXT: srdi r3, r3, 63
; BE-NEXT: stb r3, 0(r4) ; BE-NEXT: stb r3, 0(r4)
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; LE-LABEL: test_igeuc_store: ; LE-LABEL: test_igeuc_store:
; LE: # %bb.0: # %entry ; LE: # %bb.0: # %entry
; LE-NEXT: sub r3, r3, r4 ; LE-NEXT: sub r3, r3, r4
; LE-NEXT: addis r5, r2, glob@toc@ha ; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: not r3, r3 ; LE-NEXT: not r3, r3
; LE-NEXT: rldicl r3, r3, 1, 63 ; LE-NEXT: srdi r3, r3, 63
; LE-NEXT: stb r3, glob@toc@l(r5) ; LE-NEXT: stb r3, glob@toc@l(r5)
; LE-NEXT: blr ; LE-NEXT: blr
entry: entry:
%cmp = icmp uge i8 %a, %b %cmp = icmp uge i8 %a, %b
%conv3 = zext i1 %cmp to i8 %conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob store i8 %conv3, i8* @glob
ret void ret void
; CHECK_LABEL: test_igeuc_store: ; CHECK_LABEL: test_igeuc_store:
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_igeuc_sext_store(i8 zeroext %a, i8 zeroext %b) { define void @test_igeuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
; BE-LABEL: test_igeuc_sext_store: ; BE-LABEL: test_igeuc_sext_store:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha ; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: sub r3, r3, r4 ; BE-NEXT: sub r3, r3, r4
; BE-NEXT: ld r4, .LC0@toc@l(r5) ; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: rldicl r3, r3, 1, 63 ; BE-NEXT: srdi r3, r3, 63
; BE-NEXT: addi r3, r3, -1 ; BE-NEXT: addi r3, r3, -1
; BE-NEXT: stb r3, 0(r4) ; BE-NEXT: stb r3, 0(r4)
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; LE-LABEL: test_igeuc_sext_store: ; LE-LABEL: test_igeuc_sext_store:
; LE: # %bb.0: # %entry ; LE: # %bb.0: # %entry
; LE-NEXT: sub r3, r3, r4 ; LE-NEXT: sub r3, r3, r4
; LE-NEXT: addis r5, r2, glob@toc@ha ; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: rldicl r3, r3, 1, 63 ; LE-NEXT: srdi r3, r3, 63
; LE-NEXT: addi r3, r3, -1 ; LE-NEXT: addi r3, r3, -1
; LE-NEXT: stb r3, glob@toc@l(r5) ; LE-NEXT: stb r3, glob@toc@l(r5)
; LE-NEXT: blr ; LE-NEXT: blr
entry: entry:
%cmp = icmp uge i8 %a, %b %cmp = icmp uge i8 %a, %b
%conv3 = sext i1 %cmp to i8 %conv3 = sext i1 %cmp to i8
store i8 %conv3, i8* @glob store i8 %conv3, i8* @glob
ret void ret void
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llvm/test/CodeGen/PowerPC/testComparesigeui.ll

Show All 10 Lines
@glob = local_unnamed_addr global i32 0, align 4 @glob = local_unnamed_addr global i32 0, align 4
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igeui(i32 zeroext %a, i32 zeroext %b) { define signext i32 @test_igeui(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_igeui: ; CHECK-LABEL: test_igeui:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: not r3, r3 ; CHECK-NEXT: not r3, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp uge i32 %a, %b %cmp = icmp uge i32 %a, %b
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igeui_sext(i32 zeroext %a, i32 zeroext %b) { define signext i32 @test_igeui_sext(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_igeui_sext: ; CHECK-LABEL: test_igeui_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp uge i32 %a, %b %cmp = icmp uge i32 %a, %b
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
ret i32 %sub ret i32 %sub
} }
Show All 24 Lines
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_igeui_store(i32 zeroext %a, i32 zeroext %b) { define void @test_igeui_store(i32 zeroext %a, i32 zeroext %b) {
; BE-LABEL: test_igeui_store: ; BE-LABEL: test_igeui_store:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha ; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: sub r3, r3, r4 ; BE-NEXT: sub r3, r3, r4
; BE-NEXT: ld r4, .LC0@toc@l(r5) ; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: not r3, r3 ; BE-NEXT: not r3, r3
; BE-NEXT: rldicl r3, r3, 1, 63 ; BE-NEXT: srdi r3, r3, 63
; BE-NEXT: stw r3, 0(r4) ; BE-NEXT: stw r3, 0(r4)
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; LE-LABEL: test_igeui_store: ; LE-LABEL: test_igeui_store:
; LE: # %bb.0: # %entry ; LE: # %bb.0: # %entry
; LE-NEXT: sub r3, r3, r4 ; LE-NEXT: sub r3, r3, r4
; LE-NEXT: addis r5, r2, glob@toc@ha ; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: not r3, r3 ; LE-NEXT: not r3, r3
; LE-NEXT: rldicl r3, r3, 1, 63 ; LE-NEXT: srdi r3, r3, 63
; LE-NEXT: stw r3, glob@toc@l(r5) ; LE-NEXT: stw r3, glob@toc@l(r5)
; LE-NEXT: blr ; LE-NEXT: blr
entry: entry:
%cmp = icmp uge i32 %a, %b %cmp = icmp uge i32 %a, %b
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob store i32 %conv, i32* @glob
ret void ret void
; CHECK_LABEL: test_igeuc_store: ; CHECK_LABEL: test_igeuc_store:
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_igeui_sext_store(i32 zeroext %a, i32 zeroext %b) { define void @test_igeui_sext_store(i32 zeroext %a, i32 zeroext %b) {
; BE-LABEL: test_igeui_sext_store: ; BE-LABEL: test_igeui_sext_store:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha ; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: sub r3, r3, r4 ; BE-NEXT: sub r3, r3, r4
; BE-NEXT: ld r4, .LC0@toc@l(r5) ; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: rldicl r3, r3, 1, 63 ; BE-NEXT: srdi r3, r3, 63
; BE-NEXT: addi r3, r3, -1 ; BE-NEXT: addi r3, r3, -1
; BE-NEXT: stw r3, 0(r4) ; BE-NEXT: stw r3, 0(r4)
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; LE-LABEL: test_igeui_sext_store: ; LE-LABEL: test_igeui_sext_store:
; LE: # %bb.0: # %entry ; LE: # %bb.0: # %entry
; LE-NEXT: sub r3, r3, r4 ; LE-NEXT: sub r3, r3, r4
; LE-NEXT: addis r5, r2, glob@toc@ha ; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: rldicl r3, r3, 1, 63 ; LE-NEXT: srdi r3, r3, 63
; LE-NEXT: addi r3, r3, -1 ; LE-NEXT: addi r3, r3, -1
; LE-NEXT: stw r3, glob@toc@l(r5) ; LE-NEXT: stw r3, glob@toc@l(r5)
; LE-NEXT: blr ; LE-NEXT: blr
entry: entry:
%cmp = icmp uge i32 %a, %b %cmp = icmp uge i32 %a, %b
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob store i32 %sub, i32* @glob
ret void ret void
▲ Show 20 Lines • Show All 48 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/testComparesigeus.ll

Show All 10 Lines
@glob = local_unnamed_addr global i16 0, align 2 @glob = local_unnamed_addr global i16 0, align 2
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igeus(i16 zeroext %a, i16 zeroext %b) { define signext i32 @test_igeus(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_igeus: ; CHECK-LABEL: test_igeus:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: not r3, r3 ; CHECK-NEXT: not r3, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp uge i16 %a, %b %cmp = icmp uge i16 %a, %b
%conv2 = zext i1 %cmp to i32 %conv2 = zext i1 %cmp to i32
ret i32 %conv2 ret i32 %conv2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igeus_sext(i16 zeroext %a, i16 zeroext %b) { define signext i32 @test_igeus_sext(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_igeus_sext: ; CHECK-LABEL: test_igeus_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp uge i16 %a, %b %cmp = icmp uge i16 %a, %b
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
ret i32 %sub ret i32 %sub
} }
Show All 24 Lines
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_igeus_store(i16 zeroext %a, i16 zeroext %b) { define void @test_igeus_store(i16 zeroext %a, i16 zeroext %b) {
; BE-LABEL: test_igeus_store: ; BE-LABEL: test_igeus_store:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha ; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: sub r3, r3, r4 ; BE-NEXT: sub r3, r3, r4
; BE-NEXT: ld r4, .LC0@toc@l(r5) ; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: not r3, r3 ; BE-NEXT: not r3, r3
; BE-NEXT: rldicl r3, r3, 1, 63 ; BE-NEXT: srdi r3, r3, 63
; BE-NEXT: sth r3, 0(r4) ; BE-NEXT: sth r3, 0(r4)
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; LE-LABEL: test_igeus_store: ; LE-LABEL: test_igeus_store:
; LE: # %bb.0: # %entry ; LE: # %bb.0: # %entry
; LE-NEXT: sub r3, r3, r4 ; LE-NEXT: sub r3, r3, r4
; LE-NEXT: addis r5, r2, glob@toc@ha ; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: not r3, r3 ; LE-NEXT: not r3, r3
; LE-NEXT: rldicl r3, r3, 1, 63 ; LE-NEXT: srdi r3, r3, 63
; LE-NEXT: sth r3, glob@toc@l(r5) ; LE-NEXT: sth r3, glob@toc@l(r5)
; LE-NEXT: blr ; LE-NEXT: blr
entry: entry:
%cmp = icmp uge i16 %a, %b %cmp = icmp uge i16 %a, %b
%conv3 = zext i1 %cmp to i16 %conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob store i16 %conv3, i16* @glob
ret void ret void
; CHECK_LABEL: test_igeus_store: ; CHECK_LABEL: test_igeus_store:
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_igeus_sext_store(i16 zeroext %a, i16 zeroext %b) { define void @test_igeus_sext_store(i16 zeroext %a, i16 zeroext %b) {
; BE-LABEL: test_igeus_sext_store: ; BE-LABEL: test_igeus_sext_store:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha ; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: sub r3, r3, r4 ; BE-NEXT: sub r3, r3, r4
; BE-NEXT: ld r4, .LC0@toc@l(r5) ; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: rldicl r3, r3, 1, 63 ; BE-NEXT: srdi r3, r3, 63
; BE-NEXT: addi r3, r3, -1 ; BE-NEXT: addi r3, r3, -1
; BE-NEXT: sth r3, 0(r4) ; BE-NEXT: sth r3, 0(r4)
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; LE-LABEL: test_igeus_sext_store: ; LE-LABEL: test_igeus_sext_store:
; LE: # %bb.0: # %entry ; LE: # %bb.0: # %entry
; LE-NEXT: sub r3, r3, r4 ; LE-NEXT: sub r3, r3, r4
; LE-NEXT: addis r5, r2, glob@toc@ha ; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: rldicl r3, r3, 1, 63 ; LE-NEXT: srdi r3, r3, 63
; LE-NEXT: addi r3, r3, -1 ; LE-NEXT: addi r3, r3, -1
; LE-NEXT: sth r3, glob@toc@l(r5) ; LE-NEXT: sth r3, glob@toc@l(r5)
; LE-NEXT: blr ; LE-NEXT: blr
entry: entry:
%cmp = icmp uge i16 %a, %b %cmp = icmp uge i16 %a, %b
%conv3 = sext i1 %cmp to i16 %conv3 = sext i1 %cmp to i16
store i16 %conv3, i16* @glob store i16 %conv3, i16* @glob
ret void ret void
▲ Show 20 Lines • Show All 48 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/testComparesigtsc.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = local_unnamed_addr global i8 0, align 1 @glob = local_unnamed_addr global i8 0, align 1
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtsc(i8 signext %a, i8 signext %b) { define signext i32 @test_igtsc(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_igtsc: ; CHECK-LABEL: test_igtsc:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp sgt i8 %a, %b %cmp = icmp sgt i8 %a, %b
%conv2 = zext i1 %cmp to i32 %conv2 = zext i1 %cmp to i32
ret i32 %conv2 ret i32 %conv2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
Show All 10 Lines
} }
; FIXME ; FIXME
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtsc_z(i8 signext %a) { define signext i32 @test_igtsc_z(i8 signext %a) {
; CHECK-LABEL: test_igtsc_z: ; CHECK-LABEL: test_igtsc_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp sgt i8 %a, 0 %cmp = icmp sgt i8 %a, 0
%conv1 = zext i1 %cmp to i32 %conv1 = zext i1 %cmp to i32
ret i32 %conv1 ret i32 %conv1
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
Show All 11 Lines
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_igtsc_store(i8 signext %a, i8 signext %b) { define void @test_igtsc_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_igtsc_store: ; CHECK-LABEL: test_igtsc_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: ld r5, .LC0@toc@l(r5) ; CHECK-NEXT: ld r5, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: stb r3, 0(r5) ; CHECK-NEXT: stb r3, 0(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp sgt i8 %a, %b %cmp = icmp sgt i8 %a, %b
%conv3 = zext i1 %cmp to i8 %conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1 store i8 %conv3, i8* @glob, align 1
ret void ret void
} }
Show All 18 Lines
; FIXME ; FIXME
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_igtsc_z_store(i8 signext %a) { define void @test_igtsc_z_store(i8 signext %a) {
; CHECK-LABEL: test_igtsc_z_store: ; CHECK-LABEL: test_igtsc_z_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: stb r3, 0(r4) ; CHECK-NEXT: stb r3, 0(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp sgt i8 %a, 0 %cmp = icmp sgt i8 %a, 0
%conv2 = zext i1 %cmp to i8 %conv2 = zext i1 %cmp to i8
store i8 %conv2, i8* @glob, align 1 store i8 %conv2, i8* @glob, align 1
ret void ret void
} }
Show All 17 Lines

llvm/test/CodeGen/PowerPC/testComparesigtsi.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = local_unnamed_addr global i32 0, align 4 @glob = local_unnamed_addr global i32 0, align 4
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtsi(i32 signext %a, i32 signext %b) { define signext i32 @test_igtsi(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_igtsi: ; CHECK-LABEL: test_igtsi:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp sgt i32 %a, %b %cmp = icmp sgt i32 %a, %b
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
Show All 10 Lines
} }
; FIXME ; FIXME
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtsi_z(i32 signext %a) { define signext i32 @test_igtsi_z(i32 signext %a) {
; CHECK-LABEL: test_igtsi_z: ; CHECK-LABEL: test_igtsi_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp sgt i32 %a, 0 %cmp = icmp sgt i32 %a, 0
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
Show All 11 Lines
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_igtsi_store(i32 signext %a, i32 signext %b) { define void @test_igtsi_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_igtsi_store: ; CHECK-LABEL: test_igtsi_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: ld r5, .LC0@toc@l(r5) ; CHECK-NEXT: ld r5, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: stw r3, 0(r5) ; CHECK-NEXT: stw r3, 0(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp sgt i32 %a, %b %cmp = icmp sgt i32 %a, %b
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4 store i32 %conv, i32* @glob, align 4
ret void ret void
} }
Show All 18 Lines
; FIXME ; FIXME
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_igtsi_z_store(i32 signext %a) { define void @test_igtsi_z_store(i32 signext %a) {
; CHECK-LABEL: test_igtsi_z_store: ; CHECK-LABEL: test_igtsi_z_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: stw r3, 0(r4) ; CHECK-NEXT: stw r3, 0(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp sgt i32 %a, 0 %cmp = icmp sgt i32 %a, 0
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4 store i32 %conv, i32* @glob, align 4
ret void ret void
} }
Show All 17 Lines

llvm/test/CodeGen/PowerPC/testComparesigtsll.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = local_unnamed_addr global i64 0, align 8 @glob = local_unnamed_addr global i64 0, align 8
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtsll(i64 %a, i64 %b) { define signext i32 @test_igtsll(i64 %a, i64 %b) {
; CHECK-LABEL: test_igtsll: ; CHECK-LABEL: test_igtsll:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r5, r4, 63 ; CHECK-NEXT: sradi r5, r4, 63
; CHECK-NEXT: rldicl r6, r3, 1, 63 ; CHECK-NEXT: srdi r6, r3, 63
; CHECK-NEXT: subc r3, r4, r3 ; CHECK-NEXT: subc r3, r4, r3
; CHECK-NEXT: adde r3, r6, r5 ; CHECK-NEXT: adde r3, r6, r5
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp sgt i64 %a, %b %cmp = icmp sgt i64 %a, %b
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtsll_sext(i64 %a, i64 %b) { define signext i32 @test_igtsll_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_igtsll_sext: ; CHECK-LABEL: test_igtsll_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r5, r4, 63 ; CHECK-NEXT: sradi r5, r4, 63
; CHECK-NEXT: rldicl r6, r3, 1, 63 ; CHECK-NEXT: srdi r6, r3, 63
; CHECK-NEXT: subc r3, r4, r3 ; CHECK-NEXT: subc r3, r4, r3
; CHECK-NEXT: adde r3, r6, r5 ; CHECK-NEXT: adde r3, r6, r5
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp sgt i64 %a, %b %cmp = icmp sgt i64 %a, %b
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
ret i32 %sub ret i32 %sub
} }
; FIXME ; FIXME
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtsll_z(i64 %a) { define signext i32 @test_igtsll_z(i64 %a) {
; CHECK-LABEL: test_igtsll_z: ; CHECK-LABEL: test_igtsll_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi r4, r3, -1 ; CHECK-NEXT: addi r4, r3, -1
; CHECK-NEXT: nor r3, r4, r3 ; CHECK-NEXT: nor r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp sgt i64 %a, 0 %cmp = icmp sgt i64 %a, 0
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
Show All 12 Lines
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_igtsll_store(i64 %a, i64 %b) { define void @test_igtsll_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_igtsll_store: ; CHECK-LABEL: test_igtsll_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r6, r4, 63 ; CHECK-NEXT: sradi r6, r4, 63
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subc r4, r4, r3 ; CHECK-NEXT: subc r4, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: adde r3, r3, r6 ; CHECK-NEXT: adde r3, r3, r6
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r3, r4 ; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r3, r4
entry: entry:
%cmp = icmp sgt i64 %a, %b %cmp = icmp sgt i64 %a, %b
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_igtsll_sext_store(i64 %a, i64 %b) { define void @test_igtsll_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_igtsll_sext_store: ; CHECK-LABEL: test_igtsll_sext_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r6, r4, 63 ; CHECK-NEXT: sradi r6, r4, 63
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subc r4, r4, r3 ; CHECK-NEXT: subc r4, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: adde r3, r3, r6 ; CHECK-NEXT: adde r3, r3, r6
; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r3, r4 ; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r3, r4
entry: entry:
%cmp = icmp sgt i64 %a, %b %cmp = icmp sgt i64 %a, %b
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }
; FIXME ; FIXME
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_igtsll_z_store(i64 %a) { define void @test_igtsll_z_store(i64 %a) {
; CHECK-LABEL: test_igtsll_z_store: ; CHECK-LABEL: test_igtsll_z_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: addi r5, r3, -1 ; CHECK-NEXT: addi r5, r3, -1
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: nor r3, r5, r3 ; CHECK-NEXT: nor r3, r5, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp sgt i64 %a, 0 %cmp = icmp sgt i64 %a, 0
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }
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llvm/test/CodeGen/PowerPC/testComparesigtss.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = local_unnamed_addr global i16 0, align 2 @glob = local_unnamed_addr global i16 0, align 2
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtss(i16 signext %a, i16 signext %b) { define signext i32 @test_igtss(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_igtss: ; CHECK-LABEL: test_igtss:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp sgt i16 %a, %b %cmp = icmp sgt i16 %a, %b
%conv2 = zext i1 %cmp to i32 %conv2 = zext i1 %cmp to i32
ret i32 %conv2 ret i32 %conv2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
Show All 10 Lines
} }
; FIXME ; FIXME
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtss_z(i16 signext %a) { define signext i32 @test_igtss_z(i16 signext %a) {
; CHECK-LABEL: test_igtss_z: ; CHECK-LABEL: test_igtss_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp sgt i16 %a, 0 %cmp = icmp sgt i16 %a, 0
%conv1 = zext i1 %cmp to i32 %conv1 = zext i1 %cmp to i32
ret i32 %conv1 ret i32 %conv1
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
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; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_igtss_store(i16 signext %a, i16 signext %b) { define void @test_igtss_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_igtss_store: ; CHECK-LABEL: test_igtss_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: ld r5, .LC0@toc@l(r5) ; CHECK-NEXT: ld r5, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: sth r3, 0(r5) ; CHECK-NEXT: sth r3, 0(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp sgt i16 %a, %b %cmp = icmp sgt i16 %a, %b
%conv3 = zext i1 %cmp to i16 %conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2 store i16 %conv3, i16* @glob, align 2
ret void ret void
} }
Show All 18 Lines
; FIXME ; FIXME
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_igtss_z_store(i16 signext %a) { define void @test_igtss_z_store(i16 signext %a) {
; CHECK-LABEL: test_igtss_z_store: ; CHECK-LABEL: test_igtss_z_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: sth r3, 0(r4) ; CHECK-NEXT: sth r3, 0(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp sgt i16 %a, 0 %cmp = icmp sgt i16 %a, 0
%conv2 = zext i1 %cmp to i16 %conv2 = zext i1 %cmp to i16
store i16 %conv2, i16* @glob, align 2 store i16 %conv2, i16* @glob, align 2
ret void ret void
} }
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llvm/test/CodeGen/PowerPC/testComparesigtuc.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = local_unnamed_addr global i8 0, align 1 @glob = local_unnamed_addr global i8 0, align 1
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtuc(i8 zeroext %a, i8 zeroext %b) { define signext i32 @test_igtuc(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_igtuc: ; CHECK-LABEL: test_igtuc:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp ugt i8 %a, %b %cmp = icmp ugt i8 %a, %b
%conv2 = zext i1 %cmp to i32 %conv2 = zext i1 %cmp to i32
ret i32 %conv2 ret i32 %conv2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
Show All 40 Lines
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_igtuc_store(i8 zeroext %a, i8 zeroext %b) { define void @test_igtuc_store(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_igtuc_store: ; CHECK-LABEL: test_igtuc_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: ld r5, .LC0@toc@l(r5) ; CHECK-NEXT: ld r5, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: stb r3, 0(r5) ; CHECK-NEXT: stb r3, 0(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp ugt i8 %a, %b %cmp = icmp ugt i8 %a, %b
%conv3 = zext i1 %cmp to i8 %conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1 store i8 %conv3, i8* @glob, align 1
ret void ret void
} }
▲ Show 20 Lines • Show All 54 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/testComparesigtui.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = local_unnamed_addr global i32 0, align 4 @glob = local_unnamed_addr global i32 0, align 4
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtui(i32 zeroext %a, i32 zeroext %b) { define signext i32 @test_igtui(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_igtui: ; CHECK-LABEL: test_igtui:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp ugt i32 %a, %b %cmp = icmp ugt i32 %a, %b
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
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; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_igtui_store(i32 zeroext %a, i32 zeroext %b) { define void @test_igtui_store(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_igtui_store: ; CHECK-LABEL: test_igtui_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: ld r5, .LC0@toc@l(r5) ; CHECK-NEXT: ld r5, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: stw r3, 0(r5) ; CHECK-NEXT: stw r3, 0(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp ugt i32 %a, %b %cmp = icmp ugt i32 %a, %b
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4 store i32 %conv, i32* @glob, align 4
ret void ret void
} }
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llvm/test/CodeGen/PowerPC/testComparesigtus.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = local_unnamed_addr global i16 0, align 2 @glob = local_unnamed_addr global i16 0, align 2
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtus(i16 zeroext %a, i16 zeroext %b) { define signext i32 @test_igtus(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_igtus: ; CHECK-LABEL: test_igtus:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp ugt i16 %a, %b %cmp = icmp ugt i16 %a, %b
%conv2 = zext i1 %cmp to i32 %conv2 = zext i1 %cmp to i32
ret i32 %conv2 ret i32 %conv2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
Show All 40 Lines
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_igtus_store(i16 zeroext %a, i16 zeroext %b) { define void @test_igtus_store(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_igtus_store: ; CHECK-LABEL: test_igtus_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: ld r5, .LC0@toc@l(r5) ; CHECK-NEXT: ld r5, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: sth r3, 0(r5) ; CHECK-NEXT: sth r3, 0(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp ugt i16 %a, %b %cmp = icmp ugt i16 %a, %b
%conv3 = zext i1 %cmp to i16 %conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2 store i16 %conv3, i16* @glob, align 2
ret void ret void
} }
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llvm/test/CodeGen/PowerPC/testComparesilesc.ll

Show All 11 Lines
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ilesc: ; CHECK-BE-LABEL: test_ilesc:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sub r3, r4, r3 ; CHECK-BE-NEXT: sub r3, r4, r3
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-BE-NEXT: srdi r3, r3, 63
; CHECK-BE-NEXT: xori r3, r3, 1 ; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_ilesc: ; CHECK-LE-LABEL: test_ilesc:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r4, r3 ; CHECK-LE-NEXT: sub r3, r4, r3
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-LE-NEXT: srdi r3, r3, 63
; CHECK-LE-NEXT: xori r3, r3, 1 ; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i8 %a, %b %cmp = icmp sle i8 %a, %b
%conv2 = zext i1 %cmp to i32 %conv2 = zext i1 %cmp to i32
ret i32 %conv2 ret i32 %conv2
} }
define signext i32 @test_ilesc_sext(i8 signext %a, i8 signext %b) { define signext i32 @test_ilesc_sext(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_ilesc_sext: ; CHECK-LABEL: test_ilesc_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ilesc_sext: ; CHECK-BE-LABEL: test_ilesc_sext:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sub r3, r4, r3 ; CHECK-BE-NEXT: sub r3, r4, r3
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-BE-NEXT: srdi r3, r3, 63
; CHECK-BE-NEXT: addi r3, r3, -1 ; CHECK-BE-NEXT: addi r3, r3, -1
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_ilesc_sext: ; CHECK-LE-LABEL: test_ilesc_sext:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r4, r3 ; CHECK-LE-NEXT: sub r3, r4, r3
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-LE-NEXT: srdi r3, r3, 63
; CHECK-LE-NEXT: addi r3, r3, -1 ; CHECK-LE-NEXT: addi r3, r3, -1
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i8 %a, %b %cmp = icmp sle i8 %a, %b
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
ret i32 %sub ret i32 %sub
} }
define void @test_ilesc_store(i8 signext %a, i8 signext %b) { define void @test_ilesc_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_ilesc_store: ; CHECK-LABEL: test_ilesc_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stb r3, glob@toc@l(r5) ; CHECK-NEXT: stb r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ilesc_store: ; CHECK-BE-LABEL: test_ilesc_store:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sub r3, r4, r3 ; CHECK-BE-NEXT: sub r3, r4, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-BE-NEXT: srdi r3, r3, 63
; CHECK-BE-NEXT: xori r3, r3, 1 ; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: stb r3, 0(r4) ; CHECK-BE-NEXT: stb r3, 0(r4)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_ilesc_store: ; CHECK-LE-LABEL: test_ilesc_store:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r4, r3 ; CHECK-LE-NEXT: sub r3, r4, r3
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha ; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-LE-NEXT: srdi r3, r3, 63
; CHECK-LE-NEXT: xori r3, r3, 1 ; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: stb r3, glob@toc@l(r5) ; CHECK-LE-NEXT: stb r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i8 %a, %b %cmp = icmp sle i8 %a, %b
%conv3 = zext i1 %cmp to i8 %conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1 store i8 %conv3, i8* @glob, align 1
ret void ret void
} }
define void @test_ilesc_sext_store(i8 signext %a, i8 signext %b) { define void @test_ilesc_sext_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_ilesc_sext_store: ; CHECK-LABEL: test_ilesc_sext_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: stb r3, glob@toc@l(r5) ; CHECK-NEXT: stb r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ilesc_sext_store: ; CHECK-BE-LABEL: test_ilesc_sext_store:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sub r3, r4, r3 ; CHECK-BE-NEXT: sub r3, r4, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-BE-NEXT: srdi r3, r3, 63
; CHECK-BE-NEXT: addi r3, r3, -1 ; CHECK-BE-NEXT: addi r3, r3, -1
; CHECK-BE-NEXT: stb r3, 0(r4) ; CHECK-BE-NEXT: stb r3, 0(r4)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_ilesc_sext_store: ; CHECK-LE-LABEL: test_ilesc_sext_store:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r4, r3 ; CHECK-LE-NEXT: sub r3, r4, r3
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha ; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-LE-NEXT: srdi r3, r3, 63
; CHECK-LE-NEXT: addi r3, r3, -1 ; CHECK-LE-NEXT: addi r3, r3, -1
; CHECK-LE-NEXT: stb r3, glob@toc@l(r5) ; CHECK-LE-NEXT: stb r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i8 %a, %b %cmp = icmp sle i8 %a, %b
%conv3 = sext i1 %cmp to i8 %conv3 = sext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1 store i8 %conv3, i8* @glob, align 1
ret void ret void
} }

llvm/test/CodeGen/PowerPC/testComparesilesi.ll

Show All 11 Lines
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ilesi: ; CHECK-BE-LABEL: test_ilesi:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sub r3, r4, r3 ; CHECK-BE-NEXT: sub r3, r4, r3
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-BE-NEXT: srdi r3, r3, 63
; CHECK-BE-NEXT: xori r3, r3, 1 ; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_ilesi: ; CHECK-LE-LABEL: test_ilesi:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r4, r3 ; CHECK-LE-NEXT: sub r3, r4, r3
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-LE-NEXT: srdi r3, r3, 63
; CHECK-LE-NEXT: xori r3, r3, 1 ; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i32 %a, %b %cmp = icmp sle i32 %a, %b
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
define signext i32 @test_ilesi_sext(i32 signext %a, i32 signext %b) { define signext i32 @test_ilesi_sext(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_ilesi_sext: ; CHECK-LABEL: test_ilesi_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ilesi_sext: ; CHECK-BE-LABEL: test_ilesi_sext:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sub r3, r4, r3 ; CHECK-BE-NEXT: sub r3, r4, r3
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-BE-NEXT: srdi r3, r3, 63
; CHECK-BE-NEXT: addi r3, r3, -1 ; CHECK-BE-NEXT: addi r3, r3, -1
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_ilesi_sext: ; CHECK-LE-LABEL: test_ilesi_sext:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r4, r3 ; CHECK-LE-NEXT: sub r3, r4, r3
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-LE-NEXT: srdi r3, r3, 63
; CHECK-LE-NEXT: addi r3, r3, -1 ; CHECK-LE-NEXT: addi r3, r3, -1
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i32 %a, %b %cmp = icmp sle i32 %a, %b
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
ret i32 %sub ret i32 %sub
} }
define void @test_ilesi_store(i32 signext %a, i32 signext %b) { define void @test_ilesi_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_ilesi_store: ; CHECK-LABEL: test_ilesi_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stw r3, glob@toc@l(r5) ; CHECK-NEXT: stw r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ilesi_store: ; CHECK-BE-LABEL: test_ilesi_store:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sub r3, r4, r3 ; CHECK-BE-NEXT: sub r3, r4, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-BE-NEXT: srdi r3, r3, 63
; CHECK-BE-NEXT: xori r3, r3, 1 ; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: stw r3, 0(r4) ; CHECK-BE-NEXT: stw r3, 0(r4)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_ilesi_store: ; CHECK-LE-LABEL: test_ilesi_store:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r4, r3 ; CHECK-LE-NEXT: sub r3, r4, r3
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha ; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-LE-NEXT: srdi r3, r3, 63
; CHECK-LE-NEXT: xori r3, r3, 1 ; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: stw r3, glob@toc@l(r5) ; CHECK-LE-NEXT: stw r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i32 %a, %b %cmp = icmp sle i32 %a, %b
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4 store i32 %conv, i32* @glob, align 4
ret void ret void
} }
define void @test_ilesi_sext_store(i32 signext %a, i32 signext %b) { define void @test_ilesi_sext_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_ilesi_sext_store: ; CHECK-LABEL: test_ilesi_sext_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: stw r3, glob@toc@l(r5) ; CHECK-NEXT: stw r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ilesi_sext_store: ; CHECK-BE-LABEL: test_ilesi_sext_store:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sub r3, r4, r3 ; CHECK-BE-NEXT: sub r3, r4, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-BE-NEXT: srdi r3, r3, 63
; CHECK-BE-NEXT: addi r3, r3, -1 ; CHECK-BE-NEXT: addi r3, r3, -1
; CHECK-BE-NEXT: stw r3, 0(r4) ; CHECK-BE-NEXT: stw r3, 0(r4)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_ilesi_sext_store: ; CHECK-LE-LABEL: test_ilesi_sext_store:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r4, r3 ; CHECK-LE-NEXT: sub r3, r4, r3
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha ; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-LE-NEXT: srdi r3, r3, 63
; CHECK-LE-NEXT: addi r3, r3, -1 ; CHECK-LE-NEXT: addi r3, r3, -1
; CHECK-LE-NEXT: stw r3, glob@toc@l(r5) ; CHECK-LE-NEXT: stw r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i32 %a, %b %cmp = icmp sle i32 %a, %b
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4 store i32 %sub, i32* @glob, align 4
ret void ret void
} }

llvm/test/CodeGen/PowerPC/testComparesilesll.ll

Show All 12 Lines
; CHECK-NEXT: sradi r5, r4, 63 ; CHECK-NEXT: sradi r5, r4, 63
; CHECK-NEXT: rldicl r6, r3, 1, 63 ; CHECK-NEXT: rldicl r6, r3, 1, 63
; CHECK-NEXT: subfc r3, r3, r4 ; CHECK-NEXT: subfc r3, r3, r4
; CHECK-NEXT: adde r3, r5, r6 ; CHECK-NEXT: adde r3, r5, r6
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ilesll: ; CHECK-BE-LABEL: test_ilesll:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r5, r4, 63 ; CHECK-BE-NEXT: sradi r5, r4, 63
; CHECK-BE-NEXT: rldicl r6, r3, 1, 63 ; CHECK-BE-NEXT: srdi r6, r3, 63
; CHECK-BE-NEXT: subc r3, r4, r3 ; CHECK-BE-NEXT: subc r3, r4, r3
; CHECK-BE-NEXT: adde r3, r5, r6 ; CHECK-BE-NEXT: adde r3, r5, r6
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_ilesll: ; CHECK-LE-LABEL: test_ilesll:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r5, r4, 63 ; CHECK-LE-NEXT: sradi r5, r4, 63
; CHECK-LE-NEXT: rldicl r6, r3, 1, 63 ; CHECK-LE-NEXT: srdi r6, r3, 63
; CHECK-LE-NEXT: subc r3, r4, r3 ; CHECK-LE-NEXT: subc r3, r4, r3
; CHECK-LE-NEXT: adde r3, r5, r6 ; CHECK-LE-NEXT: adde r3, r5, r6
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i64 %a, %b %cmp = icmp sle i64 %a, %b
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
define signext i32 @test_ilesll_sext(i64 %a, i64 %b) { define signext i32 @test_ilesll_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_ilesll_sext: ; CHECK-LABEL: test_ilesll_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r5, r4, 63 ; CHECK-NEXT: sradi r5, r4, 63
; CHECK-NEXT: rldicl r6, r3, 1, 63 ; CHECK-NEXT: rldicl r6, r3, 1, 63
; CHECK-NEXT: subfc r3, r3, r4 ; CHECK-NEXT: subfc r3, r3, r4
; CHECK-NEXT: adde r3, r5, r6 ; CHECK-NEXT: adde r3, r5, r6
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ilesll_sext: ; CHECK-BE-LABEL: test_ilesll_sext:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r5, r4, 63 ; CHECK-BE-NEXT: sradi r5, r4, 63
; CHECK-BE-NEXT: rldicl r6, r3, 1, 63 ; CHECK-BE-NEXT: srdi r6, r3, 63
; CHECK-BE-NEXT: subc r3, r4, r3 ; CHECK-BE-NEXT: subc r3, r4, r3
; CHECK-BE-NEXT: adde r3, r5, r6 ; CHECK-BE-NEXT: adde r3, r5, r6
; CHECK-BE-NEXT: neg r3, r3 ; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_ilesll_sext: ; CHECK-LE-LABEL: test_ilesll_sext:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r5, r4, 63 ; CHECK-LE-NEXT: sradi r5, r4, 63
; CHECK-LE-NEXT: rldicl r6, r3, 1, 63 ; CHECK-LE-NEXT: srdi r6, r3, 63
; CHECK-LE-NEXT: subc r3, r4, r3 ; CHECK-LE-NEXT: subc r3, r4, r3
; CHECK-LE-NEXT: adde r3, r5, r6 ; CHECK-LE-NEXT: adde r3, r5, r6
; CHECK-LE-NEXT: neg r3, r3 ; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i64 %a, %b %cmp = icmp sle i64 %a, %b
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
ret i32 %sub ret i32 %sub
} }
define signext i32 @test_ilesll_z(i64 %a) { define signext i32 @test_ilesll_z(i64 %a) {
; CHECK-LABEL: test_ilesll_z: ; CHECK-LABEL: test_ilesll_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi r4, r3, -1 ; CHECK-NEXT: addi r4, r3, -1
; CHECK-NEXT: or r3, r4, r3 ; CHECK-NEXT: or r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ilesll_z: ; CHECK-BE-LABEL: test_ilesll_z:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addi r4, r3, -1 ; CHECK-BE-NEXT: addi r4, r3, -1
; CHECK-BE-NEXT: or r3, r4, r3 ; CHECK-BE-NEXT: or r3, r4, r3
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-BE-NEXT: srdi r3, r3, 63
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_ilesll_z: ; CHECK-LE-LABEL: test_ilesll_z:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: addi r4, r3, -1 ; CHECK-LE-NEXT: addi r4, r3, -1
; CHECK-LE-NEXT: or r3, r4, r3 ; CHECK-LE-NEXT: or r3, r4, r3
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-LE-NEXT: srdi r3, r3, 63
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp slt i64 %a, 1 %cmp = icmp slt i64 %a, 1
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
define signext i32 @test_ilesll_sext_z(i64 %a) { define signext i32 @test_ilesll_sext_z(i64 %a) {
Show All 33 Lines
; CHECK-NEXT: std r3, glob@toc@l(r5) ; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ilesll_store: ; CHECK-BE-LABEL: test_ilesll_store:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sradi r6, r4, 63 ; CHECK-BE-NEXT: sradi r6, r4, 63
; CHECK-BE-NEXT: ld r5, .LC0@toc@l(r5) ; CHECK-BE-NEXT: ld r5, .LC0@toc@l(r5)
; CHECK-BE-NEXT: subc r4, r4, r3 ; CHECK-BE-NEXT: subc r4, r4, r3
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-BE-NEXT: srdi r3, r3, 63
; CHECK-BE-NEXT: adde r3, r6, r3 ; CHECK-BE-NEXT: adde r3, r6, r3
; CHECK-BE-NEXT: std r3, 0(r5) ; CHECK-BE-NEXT: std r3, 0(r5)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_ilesll_store: ; CHECK-LE-LABEL: test_ilesll_store:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r6, r4, 63 ; CHECK-LE-NEXT: sradi r6, r4, 63
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha ; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: subc r4, r4, r3 ; CHECK-LE-NEXT: subc r4, r4, r3
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-LE-NEXT: srdi r3, r3, 63
; CHECK-LE-NEXT: adde r3, r6, r3 ; CHECK-LE-NEXT: adde r3, r6, r3
; CHECK-LE-NEXT: std r3, glob@toc@l(r5) ; CHECK-LE-NEXT: std r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i64 %a, %b %cmp = icmp sle i64 %a, %b
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
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; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: std r3, glob@toc@l(r5) ; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ilesll_sext_store: ; CHECK-BE-LABEL: test_ilesll_sext_store:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r6, r4, 63 ; CHECK-BE-NEXT: sradi r6, r4, 63
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: subc r4, r4, r3 ; CHECK-BE-NEXT: subc r4, r4, r3
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-BE-NEXT: srdi r3, r3, 63
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: adde r3, r6, r3 ; CHECK-BE-NEXT: adde r3, r6, r3
; CHECK-BE-NEXT: neg r3, r3 ; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: std r3, 0(r4) ; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_ilesll_sext_store: ; CHECK-LE-LABEL: test_ilesll_sext_store:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r6, r4, 63 ; CHECK-LE-NEXT: sradi r6, r4, 63
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha ; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: subc r4, r4, r3 ; CHECK-LE-NEXT: subc r4, r4, r3
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-LE-NEXT: srdi r3, r3, 63
; CHECK-LE-NEXT: adde r3, r6, r3 ; CHECK-LE-NEXT: adde r3, r6, r3
; CHECK-LE-NEXT: neg r3, r3 ; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: std r3, glob@toc@l(r5) ; CHECK-LE-NEXT: std r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i64 %a, %b %cmp = icmp sle i64 %a, %b
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
Show All 10 Lines
; CHECK-NEXT: std r3, glob@toc@l(r4) ; CHECK-NEXT: std r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ilesll_z_store: ; CHECK-BE-LABEL: test_ilesll_z_store:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: addi r5, r3, -1 ; CHECK-BE-NEXT: addi r5, r3, -1
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: or r3, r5, r3 ; CHECK-BE-NEXT: or r3, r5, r3
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-BE-NEXT: srdi r3, r3, 63
; CHECK-BE-NEXT: std r3, 0(r4) ; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_ilesll_z_store: ; CHECK-LE-LABEL: test_ilesll_z_store:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: addi r5, r3, -1 ; CHECK-LE-NEXT: addi r5, r3, -1
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha ; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: or r3, r5, r3 ; CHECK-LE-NEXT: or r3, r5, r3
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-LE-NEXT: srdi r3, r3, 63
; CHECK-LE-NEXT: std r3, glob@toc@l(r4) ; CHECK-LE-NEXT: std r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp slt i64 %a, 1 %cmp = icmp slt i64 %a, 1
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }
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llvm/test/CodeGen/PowerPC/testComparesiless.ll

Show All 11 Lines
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iless: ; CHECK-BE-LABEL: test_iless:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sub r3, r4, r3 ; CHECK-BE-NEXT: sub r3, r4, r3
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-BE-NEXT: srdi r3, r3, 63
; CHECK-BE-NEXT: xori r3, r3, 1 ; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_iless: ; CHECK-LE-LABEL: test_iless:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r4, r3 ; CHECK-LE-NEXT: sub r3, r4, r3
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-LE-NEXT: srdi r3, r3, 63
; CHECK-LE-NEXT: xori r3, r3, 1 ; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i16 %a, %b %cmp = icmp sle i16 %a, %b
%conv2 = zext i1 %cmp to i32 %conv2 = zext i1 %cmp to i32
ret i32 %conv2 ret i32 %conv2
} }
define signext i32 @test_iless_sext(i16 signext %a, i16 signext %b) { define signext i32 @test_iless_sext(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_iless_sext: ; CHECK-LABEL: test_iless_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iless_sext: ; CHECK-BE-LABEL: test_iless_sext:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sub r3, r4, r3 ; CHECK-BE-NEXT: sub r3, r4, r3
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-BE-NEXT: srdi r3, r3, 63
; CHECK-BE-NEXT: addi r3, r3, -1 ; CHECK-BE-NEXT: addi r3, r3, -1
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_iless_sext: ; CHECK-LE-LABEL: test_iless_sext:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r4, r3 ; CHECK-LE-NEXT: sub r3, r4, r3
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-LE-NEXT: srdi r3, r3, 63
; CHECK-LE-NEXT: addi r3, r3, -1 ; CHECK-LE-NEXT: addi r3, r3, -1
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i16 %a, %b %cmp = icmp sle i16 %a, %b
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
ret i32 %sub ret i32 %sub
} }
define void @test_iless_store(i16 signext %a, i16 signext %b) { define void @test_iless_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_iless_store: ; CHECK-LABEL: test_iless_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: sth r3, glob@toc@l(r5) ; CHECK-NEXT: sth r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iless_store: ; CHECK-BE-LABEL: test_iless_store:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sub r3, r4, r3 ; CHECK-BE-NEXT: sub r3, r4, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-BE-NEXT: srdi r3, r3, 63
; CHECK-BE-NEXT: xori r3, r3, 1 ; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: sth r3, 0(r4) ; CHECK-BE-NEXT: sth r3, 0(r4)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_iless_store: ; CHECK-LE-LABEL: test_iless_store:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r4, r3 ; CHECK-LE-NEXT: sub r3, r4, r3
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha ; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-LE-NEXT: srdi r3, r3, 63
; CHECK-LE-NEXT: xori r3, r3, 1 ; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: sth r3, glob@toc@l(r5) ; CHECK-LE-NEXT: sth r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i16 %a, %b %cmp = icmp sle i16 %a, %b
%conv3 = zext i1 %cmp to i16 %conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2 store i16 %conv3, i16* @glob, align 2
ret void ret void
} }
define void @test_iless_sext_store(i16 signext %a, i16 signext %b) { define void @test_iless_sext_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_iless_sext_store: ; CHECK-LABEL: test_iless_sext_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: sth r3, glob@toc@l(r5) ; CHECK-NEXT: sth r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iless_sext_store: ; CHECK-BE-LABEL: test_iless_sext_store:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sub r3, r4, r3 ; CHECK-BE-NEXT: sub r3, r4, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-BE-NEXT: srdi r3, r3, 63
; CHECK-BE-NEXT: addi r3, r3, -1 ; CHECK-BE-NEXT: addi r3, r3, -1
; CHECK-BE-NEXT: sth r3, 0(r4) ; CHECK-BE-NEXT: sth r3, 0(r4)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_iless_sext_store: ; CHECK-LE-LABEL: test_iless_sext_store:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r4, r3 ; CHECK-LE-NEXT: sub r3, r4, r3
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha ; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-LE-NEXT: srdi r3, r3, 63
; CHECK-LE-NEXT: addi r3, r3, -1 ; CHECK-LE-NEXT: addi r3, r3, -1
; CHECK-LE-NEXT: sth r3, glob@toc@l(r5) ; CHECK-LE-NEXT: sth r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i16 %a, %b %cmp = icmp sle i16 %a, %b
%conv3 = sext i1 %cmp to i16 %conv3 = sext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2 store i16 %conv3, i16* @glob, align 2
ret void ret void
} }

llvm/test/CodeGen/PowerPC/testComparesileuc.ll

Show All 10 Lines
@glob = local_unnamed_addr global i8 0, align 1 @glob = local_unnamed_addr global i8 0, align 1
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ileuc(i8 zeroext %a, i8 zeroext %b) { define signext i32 @test_ileuc(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_ileuc: ; CHECK-LABEL: test_ileuc:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: not r3, r3 ; CHECK-NEXT: not r3, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp ule i8 %a, %b %cmp = icmp ule i8 %a, %b
%conv2 = zext i1 %cmp to i32 %conv2 = zext i1 %cmp to i32
ret i32 %conv2 ret i32 %conv2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ileuc_sext(i8 zeroext %a, i8 zeroext %b) { define signext i32 @test_ileuc_sext(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_ileuc_sext: ; CHECK-LABEL: test_ileuc_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp ule i8 %a, %b %cmp = icmp ule i8 %a, %b
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
ret i32 %sub ret i32 %sub
} }
Show All 27 Lines
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_ileuc_store(i8 zeroext %a, i8 zeroext %b) { define void @test_ileuc_store(i8 zeroext %a, i8 zeroext %b) {
; BE-LABEL: test_ileuc_store: ; BE-LABEL: test_ileuc_store:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha ; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: sub r3, r4, r3 ; BE-NEXT: sub r3, r4, r3
; BE-NEXT: ld r4, .LC0@toc@l(r5) ; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: not r3, r3 ; BE-NEXT: not r3, r3
; BE-NEXT: rldicl r3, r3, 1, 63 ; BE-NEXT: srdi r3, r3, 63
; BE-NEXT: stb r3, 0(r4) ; BE-NEXT: stb r3, 0(r4)
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; LE-LABEL: test_ileuc_store: ; LE-LABEL: test_ileuc_store:
; LE: # %bb.0: # %entry ; LE: # %bb.0: # %entry
; LE-NEXT: sub r3, r4, r3 ; LE-NEXT: sub r3, r4, r3
; LE-NEXT: addis r5, r2, glob@toc@ha ; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: not r3, r3 ; LE-NEXT: not r3, r3
; LE-NEXT: rldicl r3, r3, 1, 63 ; LE-NEXT: srdi r3, r3, 63
; LE-NEXT: stb r3, glob@toc@l(r5) ; LE-NEXT: stb r3, glob@toc@l(r5)
; LE-NEXT: blr ; LE-NEXT: blr
entry: entry:
%cmp = icmp ule i8 %a, %b %cmp = icmp ule i8 %a, %b
%conv3 = zext i1 %cmp to i8 %conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob store i8 %conv3, i8* @glob
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_ileuc_sext_store(i8 zeroext %a, i8 zeroext %b) { define void @test_ileuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
; BE-LABEL: test_ileuc_sext_store: ; BE-LABEL: test_ileuc_sext_store:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha ; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: sub r3, r4, r3 ; BE-NEXT: sub r3, r4, r3
; BE-NEXT: ld r4, .LC0@toc@l(r5) ; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: rldicl r3, r3, 1, 63 ; BE-NEXT: srdi r3, r3, 63
; BE-NEXT: addi r3, r3, -1 ; BE-NEXT: addi r3, r3, -1
; BE-NEXT: stb r3, 0(r4) ; BE-NEXT: stb r3, 0(r4)
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; LE-LABEL: test_ileuc_sext_store: ; LE-LABEL: test_ileuc_sext_store:
; LE: # %bb.0: # %entry ; LE: # %bb.0: # %entry
; LE-NEXT: sub r3, r4, r3 ; LE-NEXT: sub r3, r4, r3
; LE-NEXT: addis r5, r2, glob@toc@ha ; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: rldicl r3, r3, 1, 63 ; LE-NEXT: srdi r3, r3, 63
; LE-NEXT: addi r3, r3, -1 ; LE-NEXT: addi r3, r3, -1
; LE-NEXT: stb r3, glob@toc@l(r5) ; LE-NEXT: stb r3, glob@toc@l(r5)
; LE-NEXT: blr ; LE-NEXT: blr
entry: entry:
%cmp = icmp ule i8 %a, %b %cmp = icmp ule i8 %a, %b
%conv3 = sext i1 %cmp to i8 %conv3 = sext i1 %cmp to i8
store i8 %conv3, i8* @glob store i8 %conv3, i8* @glob
ret void ret void
▲ Show 20 Lines • Show All 54 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/testComparesileui.ll

Show All 10 Lines
@glob = local_unnamed_addr global i32 0, align 4 @glob = local_unnamed_addr global i32 0, align 4
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ileui(i32 zeroext %a, i32 zeroext %b) { define signext i32 @test_ileui(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_ileui: ; CHECK-LABEL: test_ileui:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: not r3, r3 ; CHECK-NEXT: not r3, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp ule i32 %a, %b %cmp = icmp ule i32 %a, %b
%sub = zext i1 %cmp to i32 %sub = zext i1 %cmp to i32
ret i32 %sub ret i32 %sub
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ileui_sext(i32 zeroext %a, i32 zeroext %b) { define signext i32 @test_ileui_sext(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_ileui_sext: ; CHECK-LABEL: test_ileui_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp ule i32 %a, %b %cmp = icmp ule i32 %a, %b
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
ret i32 %sub ret i32 %sub
} }
Show All 27 Lines
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_ileui_store(i32 zeroext %a, i32 zeroext %b) { define void @test_ileui_store(i32 zeroext %a, i32 zeroext %b) {
; BE-LABEL: test_ileui_store: ; BE-LABEL: test_ileui_store:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha ; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: sub r3, r4, r3 ; BE-NEXT: sub r3, r4, r3
; BE-NEXT: ld r4, .LC0@toc@l(r5) ; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: not r3, r3 ; BE-NEXT: not r3, r3
; BE-NEXT: rldicl r3, r3, 1, 63 ; BE-NEXT: srdi r3, r3, 63
; BE-NEXT: stw r3, 0(r4) ; BE-NEXT: stw r3, 0(r4)
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; LE-LABEL: test_ileui_store: ; LE-LABEL: test_ileui_store:
; LE: # %bb.0: # %entry ; LE: # %bb.0: # %entry
; LE-NEXT: sub r3, r4, r3 ; LE-NEXT: sub r3, r4, r3
; LE-NEXT: addis r5, r2, glob@toc@ha ; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: not r3, r3 ; LE-NEXT: not r3, r3
; LE-NEXT: rldicl r3, r3, 1, 63 ; LE-NEXT: srdi r3, r3, 63
; LE-NEXT: stw r3, glob@toc@l(r5) ; LE-NEXT: stw r3, glob@toc@l(r5)
; LE-NEXT: blr ; LE-NEXT: blr
entry: entry:
%cmp = icmp ule i32 %a, %b %cmp = icmp ule i32 %a, %b
%sub = zext i1 %cmp to i32 %sub = zext i1 %cmp to i32
store i32 %sub, i32* @glob store i32 %sub, i32* @glob
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_ileui_sext_store(i32 zeroext %a, i32 zeroext %b) { define void @test_ileui_sext_store(i32 zeroext %a, i32 zeroext %b) {
; BE-LABEL: test_ileui_sext_store: ; BE-LABEL: test_ileui_sext_store:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha ; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: sub r3, r4, r3 ; BE-NEXT: sub r3, r4, r3
; BE-NEXT: ld r4, .LC0@toc@l(r5) ; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: rldicl r3, r3, 1, 63 ; BE-NEXT: srdi r3, r3, 63
; BE-NEXT: addi r3, r3, -1 ; BE-NEXT: addi r3, r3, -1
; BE-NEXT: stw r3, 0(r4) ; BE-NEXT: stw r3, 0(r4)
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; LE-LABEL: test_ileui_sext_store: ; LE-LABEL: test_ileui_sext_store:
; LE: # %bb.0: # %entry ; LE: # %bb.0: # %entry
; LE-NEXT: sub r3, r4, r3 ; LE-NEXT: sub r3, r4, r3
; LE-NEXT: addis r5, r2, glob@toc@ha ; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: rldicl r3, r3, 1, 63 ; LE-NEXT: srdi r3, r3, 63
; LE-NEXT: addi r3, r3, -1 ; LE-NEXT: addi r3, r3, -1
; LE-NEXT: stw r3, glob@toc@l(r5) ; LE-NEXT: stw r3, glob@toc@l(r5)
; LE-NEXT: blr ; LE-NEXT: blr
entry: entry:
%cmp = icmp ule i32 %a, %b %cmp = icmp ule i32 %a, %b
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob store i32 %sub, i32* @glob
ret void ret void
▲ Show 20 Lines • Show All 54 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/testComparesileull.ll

Show All 37 Linesentry:
ret i32 %sub ret i32 %sub
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ileull_z(i64 %a) { define signext i32 @test_ileull_z(i64 %a) {
; CHECK-LABEL: test_ileull_z: ; CHECK-LABEL: test_ileull_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63 ; CHECK-NEXT: extrdi r3, r3, 1, 57
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp ule i64 %a, 0 %cmp = icmp ule i64 %a, 0
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Lines
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_ileull_z_store(i64 %a) { define void @test_ileull_z_store(i64 %a) {
; BE-LABEL: test_ileull_z_store: ; BE-LABEL: test_ileull_z_store:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
; BE-NEXT: addis r4, r2, .LC0@toc@ha ; BE-NEXT: addis r4, r2, .LC0@toc@ha
; BE-NEXT: cntlzd r3, r3 ; BE-NEXT: cntlzd r3, r3
; BE-NEXT: ld r4, .LC0@toc@l(r4) ; BE-NEXT: ld r4, .LC0@toc@l(r4)
; BE-NEXT: rldicl r3, r3, 58, 63 ; BE-NEXT: extrdi r3, r3, 1, 57
; BE-NEXT: std r3, 0(r4) ; BE-NEXT: std r3, 0(r4)
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; LE-LABEL: test_ileull_z_store: ; LE-LABEL: test_ileull_z_store:
; LE: # %bb.0: # %entry ; LE: # %bb.0: # %entry
; LE-NEXT: cntlzd r3, r3 ; LE-NEXT: cntlzd r3, r3
; LE-NEXT: addis r4, r2, glob@toc@ha ; LE-NEXT: addis r4, r2, glob@toc@ha
; LE-NEXT: rldicl r3, r3, 58, 63 ; LE-NEXT: extrdi r3, r3, 1, 57
; LE-NEXT: std r3, glob@toc@l(r4) ; LE-NEXT: std r3, glob@toc@l(r4)
; LE-NEXT: blr ; LE-NEXT: blr
entry: entry:
%cmp = icmp ule i64 %a, 0 %cmp = icmp ule i64 %a, 0
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob store i64 %conv1, i64* @glob
ret void ret void
} }
Show All 26 Lines

llvm/test/CodeGen/PowerPC/testComparesileus.ll

Show All 10 Lines
@glob = local_unnamed_addr global i16 0, align 2 @glob = local_unnamed_addr global i16 0, align 2
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ileus(i16 zeroext %a, i16 zeroext %b) { define signext i32 @test_ileus(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_ileus: ; CHECK-LABEL: test_ileus:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: not r3, r3 ; CHECK-NEXT: not r3, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp ule i16 %a, %b %cmp = icmp ule i16 %a, %b
%conv2 = zext i1 %cmp to i32 %conv2 = zext i1 %cmp to i32
ret i32 %conv2 ret i32 %conv2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ileus_sext(i16 zeroext %a, i16 zeroext %b) { define signext i32 @test_ileus_sext(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_ileus_sext: ; CHECK-LABEL: test_ileus_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp ule i16 %a, %b %cmp = icmp ule i16 %a, %b
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
ret i32 %sub ret i32 %sub
} }
Show All 27 Lines
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_ileus_store(i16 zeroext %a, i16 zeroext %b) { define void @test_ileus_store(i16 zeroext %a, i16 zeroext %b) {
; BE-LABEL: test_ileus_store: ; BE-LABEL: test_ileus_store:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha ; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: sub r3, r4, r3 ; BE-NEXT: sub r3, r4, r3
; BE-NEXT: ld r4, .LC0@toc@l(r5) ; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: not r3, r3 ; BE-NEXT: not r3, r3
; BE-NEXT: rldicl r3, r3, 1, 63 ; BE-NEXT: srdi r3, r3, 63
; BE-NEXT: sth r3, 0(r4) ; BE-NEXT: sth r3, 0(r4)
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; LE-LABEL: test_ileus_store: ; LE-LABEL: test_ileus_store:
; LE: # %bb.0: # %entry ; LE: # %bb.0: # %entry
; LE-NEXT: sub r3, r4, r3 ; LE-NEXT: sub r3, r4, r3
; LE-NEXT: addis r5, r2, glob@toc@ha ; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: not r3, r3 ; LE-NEXT: not r3, r3
; LE-NEXT: rldicl r3, r3, 1, 63 ; LE-NEXT: srdi r3, r3, 63
; LE-NEXT: sth r3, glob@toc@l(r5) ; LE-NEXT: sth r3, glob@toc@l(r5)
; LE-NEXT: blr ; LE-NEXT: blr
entry: entry:
%cmp = icmp ule i16 %a, %b %cmp = icmp ule i16 %a, %b
%conv3 = zext i1 %cmp to i16 %conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob store i16 %conv3, i16* @glob
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_ileus_sext_store(i16 zeroext %a, i16 zeroext %b) { define void @test_ileus_sext_store(i16 zeroext %a, i16 zeroext %b) {
; BE-LABEL: test_ileus_sext_store: ; BE-LABEL: test_ileus_sext_store:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha ; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: sub r3, r4, r3 ; BE-NEXT: sub r3, r4, r3
; BE-NEXT: ld r4, .LC0@toc@l(r5) ; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: rldicl r3, r3, 1, 63 ; BE-NEXT: srdi r3, r3, 63
; BE-NEXT: addi r3, r3, -1 ; BE-NEXT: addi r3, r3, -1
; BE-NEXT: sth r3, 0(r4) ; BE-NEXT: sth r3, 0(r4)
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; LE-LABEL: test_ileus_sext_store: ; LE-LABEL: test_ileus_sext_store:
; LE: # %bb.0: # %entry ; LE: # %bb.0: # %entry
; LE-NEXT: sub r3, r4, r3 ; LE-NEXT: sub r3, r4, r3
; LE-NEXT: addis r5, r2, glob@toc@ha ; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: rldicl r3, r3, 1, 63 ; LE-NEXT: srdi r3, r3, 63
; LE-NEXT: addi r3, r3, -1 ; LE-NEXT: addi r3, r3, -1
; LE-NEXT: sth r3, glob@toc@l(r5) ; LE-NEXT: sth r3, glob@toc@l(r5)
; LE-NEXT: blr ; LE-NEXT: blr
entry: entry:
%cmp = icmp ule i16 %a, %b %cmp = icmp ule i16 %a, %b
%conv3 = sext i1 %cmp to i16 %conv3 = sext i1 %cmp to i16
store i16 %conv3, i16* @glob store i16 %conv3, i16* @glob
ret void ret void
▲ Show 20 Lines • Show All 54 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/testComparesiltsc.ll

Show All 9 Lines
@glob = local_unnamed_addr global i8 0, align 1 @glob = local_unnamed_addr global i8 0, align 1
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iltsc(i8 signext %a, i8 signext %b) { define signext i32 @test_iltsc(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_iltsc: ; CHECK-LABEL: test_iltsc:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp slt i8 %a, %b %cmp = icmp slt i8 %a, %b
%conv2 = zext i1 %cmp to i32 %conv2 = zext i1 %cmp to i32
ret i32 %conv2 ret i32 %conv2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
Show All 23 Lines
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_iltsc_store(i8 signext %a, i8 signext %b) { define void @test_iltsc_store(i8 signext %a, i8 signext %b) {
; BE-LABEL: test_iltsc_store: ; BE-LABEL: test_iltsc_store:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha ; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: sub r3, r3, r4 ; BE-NEXT: sub r3, r3, r4
; BE-NEXT: ld r5, .LC0@toc@l(r5) ; BE-NEXT: ld r5, .LC0@toc@l(r5)
; BE-NEXT: rldicl r3, r3, 1, 63 ; BE-NEXT: srdi r3, r3, 63
; BE-NEXT: stb r3, 0(r5) ; BE-NEXT: stb r3, 0(r5)
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; LE-LABEL: test_iltsc_store: ; LE-LABEL: test_iltsc_store:
; LE: # %bb.0: # %entry ; LE: # %bb.0: # %entry
; LE-NEXT: sub r3, r3, r4 ; LE-NEXT: sub r3, r3, r4
; LE-NEXT: addis r5, r2, glob@toc@ha ; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: rldicl r3, r3, 1, 63 ; LE-NEXT: srdi r3, r3, 63
; LE-NEXT: stb r3, glob@toc@l(r5) ; LE-NEXT: stb r3, glob@toc@l(r5)
; LE-NEXT: blr ; LE-NEXT: blr
entry: entry:
%cmp = icmp slt i8 %a, %b %cmp = icmp slt i8 %a, %b
%conv3 = zext i1 %cmp to i8 %conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1 store i8 %conv3, i8* @glob, align 1
ret void ret void
} }
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llvm/test/CodeGen/PowerPC/testComparesiltsi.ll

Show All 9 Lines
@glob = local_unnamed_addr global i32 0, align 4 @glob = local_unnamed_addr global i32 0, align 4
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iltsi(i32 signext %a, i32 signext %b) { define signext i32 @test_iltsi(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_iltsi: ; CHECK-LABEL: test_iltsi:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp slt i32 %a, %b %cmp = icmp slt i32 %a, %b
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
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; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_iltsi_store(i32 signext %a, i32 signext %b) { define void @test_iltsi_store(i32 signext %a, i32 signext %b) {
; BE-LABEL: test_iltsi_store: ; BE-LABEL: test_iltsi_store:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha ; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: sub r3, r3, r4 ; BE-NEXT: sub r3, r3, r4
; BE-NEXT: ld r5, .LC0@toc@l(r5) ; BE-NEXT: ld r5, .LC0@toc@l(r5)
; BE-NEXT: rldicl r3, r3, 1, 63 ; BE-NEXT: srdi r3, r3, 63
; BE-NEXT: stw r3, 0(r5) ; BE-NEXT: stw r3, 0(r5)
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; LE-LABEL: test_iltsi_store: ; LE-LABEL: test_iltsi_store:
; LE: # %bb.0: # %entry ; LE: # %bb.0: # %entry
; LE-NEXT: sub r3, r3, r4 ; LE-NEXT: sub r3, r3, r4
; LE-NEXT: addis r5, r2, glob@toc@ha ; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: rldicl r3, r3, 1, 63 ; LE-NEXT: srdi r3, r3, 63
; LE-NEXT: stw r3, glob@toc@l(r5) ; LE-NEXT: stw r3, glob@toc@l(r5)
; LE-NEXT: blr ; LE-NEXT: blr
entry: entry:
%cmp = icmp slt i32 %a, %b %cmp = icmp slt i32 %a, %b
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4 store i32 %conv, i32* @glob, align 4
ret void ret void
} }
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llvm/test/CodeGen/PowerPC/testComparesiltsll.ll

Show All 9 Lines
@glob = local_unnamed_addr global i64 0, align 8 @glob = local_unnamed_addr global i64 0, align 8
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iltsll(i64 %a, i64 %b) { define signext i32 @test_iltsll(i64 %a, i64 %b) {
; CHECK-LABEL: test_iltsll: ; CHECK-LABEL: test_iltsll:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r5, r3, 63 ; CHECK-NEXT: sradi r5, r3, 63
; CHECK-NEXT: rldicl r6, r4, 1, 63 ; CHECK-NEXT: srdi r6, r4, 63
; CHECK-NEXT: subc r3, r3, r4 ; CHECK-NEXT: subc r3, r3, r4
; CHECK-NEXT: adde r3, r6, r5 ; CHECK-NEXT: adde r3, r6, r5
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp slt i64 %a, %b %cmp = icmp slt i64 %a, %b
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iltsll_sext(i64 %a, i64 %b) { define signext i32 @test_iltsll_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_iltsll_sext: ; CHECK-LABEL: test_iltsll_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r5, r3, 63 ; CHECK-NEXT: sradi r5, r3, 63
; CHECK-NEXT: rldicl r6, r4, 1, 63 ; CHECK-NEXT: srdi r6, r4, 63
; CHECK-NEXT: subc r3, r3, r4 ; CHECK-NEXT: subc r3, r3, r4
; CHECK-NEXT: adde r3, r6, r5 ; CHECK-NEXT: adde r3, r6, r5
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp slt i64 %a, %b %cmp = icmp slt i64 %a, %b
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
Show All 14 Lines
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_iltsll_store(i64 %a, i64 %b) { define void @test_iltsll_store(i64 %a, i64 %b) {
; BE-LABEL: test_iltsll_store: ; BE-LABEL: test_iltsll_store:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
; BE-NEXT: sradi r6, r3, 63 ; BE-NEXT: sradi r6, r3, 63
; BE-NEXT: addis r5, r2, .LC0@toc@ha ; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: subc r3, r3, r4 ; BE-NEXT: subc r3, r3, r4
; BE-NEXT: rldicl r3, r4, 1, 63 ; BE-NEXT: srdi r3, r4, 63
; BE-NEXT: ld r4, .LC0@toc@l(r5) ; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: adde r3, r3, r6 ; BE-NEXT: adde r3, r3, r6
; BE-NEXT: xori r3, r3, 1 ; BE-NEXT: xori r3, r3, 1
; BE-NEXT: std r3, 0(r4) ; BE-NEXT: std r3, 0(r4)
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; LE-LABEL: test_iltsll_store: ; LE-LABEL: test_iltsll_store:
; LE: # %bb.0: # %entry ; LE: # %bb.0: # %entry
; LE-NEXT: sradi r6, r3, 63 ; LE-NEXT: sradi r6, r3, 63
; LE-NEXT: addis r5, r2, glob@toc@ha ; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: subc r3, r3, r4 ; LE-NEXT: subc r3, r3, r4
; LE-NEXT: rldicl r3, r4, 1, 63 ; LE-NEXT: srdi r3, r4, 63
; LE-NEXT: adde r3, r3, r6 ; LE-NEXT: adde r3, r3, r6
; LE-NEXT: xori r3, r3, 1 ; LE-NEXT: xori r3, r3, 1
; LE-NEXT: std r3, glob@toc@l(r5) ; LE-NEXT: std r3, glob@toc@l(r5)
; LE-NEXT: blr ; LE-NEXT: blr
; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r4, r3 ; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r4, r3
entry: entry:
%cmp = icmp slt i64 %a, %b %cmp = icmp slt i64 %a, %b
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_iltsll_sext_store(i64 %a, i64 %b) { define void @test_iltsll_sext_store(i64 %a, i64 %b) {
; BE-LABEL: test_iltsll_sext_store: ; BE-LABEL: test_iltsll_sext_store:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
; BE-NEXT: sradi r6, r3, 63 ; BE-NEXT: sradi r6, r3, 63
; BE-NEXT: addis r5, r2, .LC0@toc@ha ; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: subc r3, r3, r4 ; BE-NEXT: subc r3, r3, r4
; BE-NEXT: rldicl r3, r4, 1, 63 ; BE-NEXT: srdi r3, r4, 63
; BE-NEXT: ld r4, .LC0@toc@l(r5) ; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: adde r3, r3, r6 ; BE-NEXT: adde r3, r3, r6
; BE-NEXT: xori r3, r3, 1 ; BE-NEXT: xori r3, r3, 1
; BE-NEXT: neg r3, r3 ; BE-NEXT: neg r3, r3
; BE-NEXT: std r3, 0(r4) ; BE-NEXT: std r3, 0(r4)
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; LE-LABEL: test_iltsll_sext_store: ; LE-LABEL: test_iltsll_sext_store:
; LE: # %bb.0: # %entry ; LE: # %bb.0: # %entry
; LE-NEXT: sradi r6, r3, 63 ; LE-NEXT: sradi r6, r3, 63
; LE-NEXT: addis r5, r2, glob@toc@ha ; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: subc r3, r3, r4 ; LE-NEXT: subc r3, r3, r4
; LE-NEXT: rldicl r3, r4, 1, 63 ; LE-NEXT: srdi r3, r4, 63
; LE-NEXT: adde r3, r3, r6 ; LE-NEXT: adde r3, r3, r6
; LE-NEXT: xori r3, r3, 1 ; LE-NEXT: xori r3, r3, 1
; LE-NEXT: neg r3, r3 ; LE-NEXT: neg r3, r3
; LE-NEXT: std r3, glob@toc@l(r5) ; LE-NEXT: std r3, glob@toc@l(r5)
; LE-NEXT: blr ; LE-NEXT: blr
; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r4, r3 ; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r4, r3
entry: entry:
%cmp = icmp slt i64 %a, %b %cmp = icmp slt i64 %a, %b
Show All 27 Lines

llvm/test/CodeGen/PowerPC/testComparesiltss.ll

Show All 9 Lines
@glob = local_unnamed_addr global i16 0, align 2 @glob = local_unnamed_addr global i16 0, align 2
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iltss(i16 signext %a, i16 signext %b) { define signext i32 @test_iltss(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_iltss: ; CHECK-LABEL: test_iltss:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp slt i16 %a, %b %cmp = icmp slt i16 %a, %b
%conv2 = zext i1 %cmp to i32 %conv2 = zext i1 %cmp to i32
ret i32 %conv2 ret i32 %conv2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
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; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_iltss_store(i16 signext %a, i16 signext %b) { define void @test_iltss_store(i16 signext %a, i16 signext %b) {
; BE-LABEL: test_iltss_store: ; BE-LABEL: test_iltss_store:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha ; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: sub r3, r3, r4 ; BE-NEXT: sub r3, r3, r4
; BE-NEXT: ld r5, .LC0@toc@l(r5) ; BE-NEXT: ld r5, .LC0@toc@l(r5)
; BE-NEXT: rldicl r3, r3, 1, 63 ; BE-NEXT: srdi r3, r3, 63
; BE-NEXT: sth r3, 0(r5) ; BE-NEXT: sth r3, 0(r5)
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; LE-LABEL: test_iltss_store: ; LE-LABEL: test_iltss_store:
; LE: # %bb.0: # %entry ; LE: # %bb.0: # %entry
; LE-NEXT: sub r3, r3, r4 ; LE-NEXT: sub r3, r3, r4
; LE-NEXT: addis r5, r2, glob@toc@ha ; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: rldicl r3, r3, 1, 63 ; LE-NEXT: srdi r3, r3, 63
; LE-NEXT: sth r3, glob@toc@l(r5) ; LE-NEXT: sth r3, glob@toc@l(r5)
; LE-NEXT: blr ; LE-NEXT: blr
entry: entry:
%cmp = icmp slt i16 %a, %b %cmp = icmp slt i16 %a, %b
%conv3 = zext i1 %cmp to i16 %conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2 store i16 %conv3, i16* @glob, align 2
ret void ret void
} }
▲ Show 20 Lines • Show All 48 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/testComparesiltuc.ll

Show All 9 Lines
@glob = local_unnamed_addr global i8 0, align 1 @glob = local_unnamed_addr global i8 0, align 1
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iltuc(i8 zeroext %a, i8 zeroext %b) { define signext i32 @test_iltuc(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_iltuc: ; CHECK-LABEL: test_iltuc:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp ult i8 %a, %b %cmp = icmp ult i8 %a, %b
%conv2 = zext i1 %cmp to i32 %conv2 = zext i1 %cmp to i32
ret i32 %conv2 ret i32 %conv2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
Show All 11 Lines
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_iltuc_store(i8 zeroext %a, i8 zeroext %b) { define void @test_iltuc_store(i8 zeroext %a, i8 zeroext %b) {
; BE-LABEL: test_iltuc_store: ; BE-LABEL: test_iltuc_store:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha ; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: sub r3, r3, r4 ; BE-NEXT: sub r3, r3, r4
; BE-NEXT: ld r5, .LC0@toc@l(r5) ; BE-NEXT: ld r5, .LC0@toc@l(r5)
; BE-NEXT: rldicl r3, r3, 1, 63 ; BE-NEXT: srdi r3, r3, 63
; BE-NEXT: stb r3, 0(r5) ; BE-NEXT: stb r3, 0(r5)
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; LE-LABEL: test_iltuc_store: ; LE-LABEL: test_iltuc_store:
; LE: # %bb.0: # %entry ; LE: # %bb.0: # %entry
; LE-NEXT: sub r3, r3, r4 ; LE-NEXT: sub r3, r3, r4
; LE-NEXT: addis r5, r2, glob@toc@ha ; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: rldicl r3, r3, 1, 63 ; LE-NEXT: srdi r3, r3, 63
; LE-NEXT: stb r3, glob@toc@l(r5) ; LE-NEXT: stb r3, glob@toc@l(r5)
; LE-NEXT: blr ; LE-NEXT: blr
entry: entry:
%cmp = icmp ult i8 %a, %b %cmp = icmp ult i8 %a, %b
%conv3 = zext i1 %cmp to i8 %conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1 store i8 %conv3, i8* @glob, align 1
ret void ret void
} }
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llvm/test/CodeGen/PowerPC/testComparesiltui.ll

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@glob = local_unnamed_addr global i32 0, align 4 @glob = local_unnamed_addr global i32 0, align 4
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iltui(i32 zeroext %a, i32 zeroext %b) { define signext i32 @test_iltui(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_iltui: ; CHECK-LABEL: test_iltui:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp ult i32 %a, %b %cmp = icmp ult i32 %a, %b
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
Show All 11 Lines
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_iltui_store(i32 zeroext %a, i32 zeroext %b) { define void @test_iltui_store(i32 zeroext %a, i32 zeroext %b) {
; BE-LABEL: test_iltui_store: ; BE-LABEL: test_iltui_store:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha ; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: sub r3, r3, r4 ; BE-NEXT: sub r3, r3, r4
; BE-NEXT: ld r5, .LC0@toc@l(r5) ; BE-NEXT: ld r5, .LC0@toc@l(r5)
; BE-NEXT: rldicl r3, r3, 1, 63 ; BE-NEXT: srdi r3, r3, 63
; BE-NEXT: stw r3, 0(r5) ; BE-NEXT: stw r3, 0(r5)
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; LE-LABEL: test_iltui_store: ; LE-LABEL: test_iltui_store:
; LE: # %bb.0: # %entry ; LE: # %bb.0: # %entry
; LE-NEXT: sub r3, r3, r4 ; LE-NEXT: sub r3, r3, r4
; LE-NEXT: addis r5, r2, glob@toc@ha ; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: rldicl r3, r3, 1, 63 ; LE-NEXT: srdi r3, r3, 63
; LE-NEXT: stw r3, glob@toc@l(r5) ; LE-NEXT: stw r3, glob@toc@l(r5)
; LE-NEXT: blr ; LE-NEXT: blr
entry: entry:
%cmp = icmp ult i32 %a, %b %cmp = icmp ult i32 %a, %b
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4 store i32 %conv, i32* @glob, align 4
ret void ret void
} }
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llvm/test/CodeGen/PowerPC/testComparesiltus.ll

Show All 9 Lines
@glob = local_unnamed_addr global i16 0, align 2 @glob = local_unnamed_addr global i16 0, align 2
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iltus(i16 zeroext %a, i16 zeroext %b) { define signext i32 @test_iltus(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_iltus: ; CHECK-LABEL: test_iltus:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp ult i16 %a, %b %cmp = icmp ult i16 %a, %b
%conv2 = zext i1 %cmp to i32 %conv2 = zext i1 %cmp to i32
ret i32 %conv2 ret i32 %conv2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
Show All 11 Lines
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_iltus_store(i16 zeroext %a, i16 zeroext %b) { define void @test_iltus_store(i16 zeroext %a, i16 zeroext %b) {
; BE-LABEL: test_iltus_store: ; BE-LABEL: test_iltus_store:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha ; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: sub r3, r3, r4 ; BE-NEXT: sub r3, r3, r4
; BE-NEXT: ld r5, .LC0@toc@l(r5) ; BE-NEXT: ld r5, .LC0@toc@l(r5)
; BE-NEXT: rldicl r3, r3, 1, 63 ; BE-NEXT: srdi r3, r3, 63
; BE-NEXT: sth r3, 0(r5) ; BE-NEXT: sth r3, 0(r5)
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; LE-LABEL: test_iltus_store: ; LE-LABEL: test_iltus_store:
; LE: # %bb.0: # %entry ; LE: # %bb.0: # %entry
; LE-NEXT: sub r3, r3, r4 ; LE-NEXT: sub r3, r3, r4
; LE-NEXT: addis r5, r2, glob@toc@ha ; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: rldicl r3, r3, 1, 63 ; LE-NEXT: srdi r3, r3, 63
; LE-NEXT: sth r3, glob@toc@l(r5) ; LE-NEXT: sth r3, glob@toc@l(r5)
; LE-NEXT: blr ; LE-NEXT: blr
entry: entry:
%cmp = icmp ult i16 %a, %b %cmp = icmp ult i16 %a, %b
%conv3 = zext i1 %cmp to i16 %conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2 store i16 %conv3, i16* @glob, align 2
ret void ret void
} }
Show All 25 Lines

llvm/test/CodeGen/PowerPC/testCompareslleqsll.ll

Show All 14 Lines
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63 ; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lleqsll: ; CHECK-BE-LABEL: test_lleqsll:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xor r3, r3, r4 ; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: cntlzd r3, r3 ; CHECK-BE-NEXT: cntlzd r3, r3
; CHECK-BE-NEXT: rldicl r3, r3, 58, 63 ; CHECK-BE-NEXT: extrdi r3, r3, 1, 57
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_lleqsll: ; CHECK-LE-LABEL: test_lleqsll:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4 ; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: cntlzd r3, r3 ; CHECK-LE-NEXT: cntlzd r3, r3
; CHECK-LE-NEXT: rldicl r3, r3, 58, 63 ; CHECK-LE-NEXT: extrdi r3, r3, 1, 57
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i64 %a, %b %cmp = icmp eq i64 %a, %b
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
Show All 28 Lines
; CHECK-LABEL: test_lleqsll_z: ; CHECK-LABEL: test_lleqsll_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63 ; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lleqsll_z: ; CHECK-BE-LABEL: test_lleqsll_z:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: cntlzd r3, r3 ; CHECK-BE-NEXT: cntlzd r3, r3
; CHECK-BE-NEXT: rldicl r3, r3, 58, 63 ; CHECK-BE-NEXT: extrdi r3, r3, 1, 57
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_lleqsll_z: ; CHECK-LE-LABEL: test_lleqsll_z:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzd r3, r3 ; CHECK-LE-NEXT: cntlzd r3, r3
; CHECK-LE-NEXT: rldicl r3, r3, 58, 63 ; CHECK-LE-NEXT: extrdi r3, r3, 1, 57
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i64 %a, 0 %cmp = icmp eq i64 %a, 0
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
Show All 31 Lines
; CHECK-NEXT: std r3, glob@toc@l(r5) ; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lleqsll_store: ; CHECK-BE-LABEL: test_lleqsll_store:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: xor r3, r3, r4 ; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: cntlzd r3, r3 ; CHECK-BE-NEXT: cntlzd r3, r3
; CHECK-BE-NEXT: rldicl r3, r3, 58, 63 ; CHECK-BE-NEXT: extrdi r3, r3, 1, 57
; CHECK-BE-NEXT: std r3, 0(r4) ; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_lleqsll_store: ; CHECK-LE-LABEL: test_lleqsll_store:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4 ; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha ; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: cntlzd r3, r3 ; CHECK-LE-NEXT: cntlzd r3, r3
; CHECK-LE-NEXT: rldicl r3, r3, 58, 63 ; CHECK-LE-NEXT: extrdi r3, r3, 1, 57
; CHECK-LE-NEXT: std r3, glob@toc@l(r5) ; CHECK-LE-NEXT: std r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i64 %a, %b %cmp = icmp eq i64 %a, %b
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
; CHECK-NEXT: rldicl r3, r3, 58, 63 ; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: std r3, glob@toc@l(r4) ; CHECK-NEXT: std r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lleqsll_z_store: ; CHECK-BE-LABEL: test_lleqsll_z_store:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: cntlzd r3, r3 ; CHECK-BE-NEXT: cntlzd r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: rldicl r3, r3, 58, 63 ; CHECK-BE-NEXT: extrdi r3, r3, 1, 57
; CHECK-BE-NEXT: std r3, 0(r4) ; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_lleqsll_z_store: ; CHECK-LE-LABEL: test_lleqsll_z_store:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzd r3, r3 ; CHECK-LE-NEXT: cntlzd r3, r3
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha ; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: rldicl r3, r3, 58, 63 ; CHECK-LE-NEXT: extrdi r3, r3, 1, 57
; CHECK-LE-NEXT: std r3, glob@toc@l(r4) ; CHECK-LE-NEXT: std r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i64 %a, 0 %cmp = icmp eq i64 %a, 0
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }
Show All 32 Lines

llvm/test/CodeGen/PowerPC/testComparesllequll.ll

Show All 14 Lines
; CHECK-NEXT: xor r3, r3, r4 ; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63 ; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llequll: ; CHECK-BE-LABEL: test_llequll:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xor r3, r3, r4 ; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: cntlzd r3, r3 ; CHECK-BE-NEXT: cntlzd r3, r3
; CHECK-BE-NEXT: rldicl r3, r3, 58, 63 ; CHECK-BE-NEXT: extrdi r3, r3, 1, 57
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_llequll: ; CHECK-LE-LABEL: test_llequll:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4 ; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: cntlzd r3, r3 ; CHECK-LE-NEXT: cntlzd r3, r3
; CHECK-LE-NEXT: rldicl r3, r3, 58, 63 ; CHECK-LE-NEXT: extrdi r3, r3, 1, 57
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i64 %a, %b %cmp = icmp eq i64 %a, %b
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
Show All 28 Lines
; CHECK-LABEL: test_llequll_z: ; CHECK-LABEL: test_llequll_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63 ; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llequll_z: ; CHECK-BE-LABEL: test_llequll_z:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: cntlzd r3, r3 ; CHECK-BE-NEXT: cntlzd r3, r3
; CHECK-BE-NEXT: rldicl r3, r3, 58, 63 ; CHECK-BE-NEXT: extrdi r3, r3, 1, 57
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_llequll_z: ; CHECK-LE-LABEL: test_llequll_z:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzd r3, r3 ; CHECK-LE-NEXT: cntlzd r3, r3
; CHECK-LE-NEXT: rldicl r3, r3, 58, 63 ; CHECK-LE-NEXT: extrdi r3, r3, 1, 57
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i64 %a, 0 %cmp = icmp eq i64 %a, 0
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
Show All 31 Lines
; CHECK-NEXT: std r3, glob@toc@l(r5) ; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llequll_store: ; CHECK-BE-LABEL: test_llequll_store:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: xor r3, r3, r4 ; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: cntlzd r3, r3 ; CHECK-BE-NEXT: cntlzd r3, r3
; CHECK-BE-NEXT: rldicl r3, r3, 58, 63 ; CHECK-BE-NEXT: extrdi r3, r3, 1, 57
; CHECK-BE-NEXT: std r3, 0(r4) ; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_llequll_store: ; CHECK-LE-LABEL: test_llequll_store:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xor r3, r3, r4 ; CHECK-LE-NEXT: xor r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha ; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: cntlzd r3, r3 ; CHECK-LE-NEXT: cntlzd r3, r3
; CHECK-LE-NEXT: rldicl r3, r3, 58, 63 ; CHECK-LE-NEXT: extrdi r3, r3, 1, 57
; CHECK-LE-NEXT: std r3, glob@toc@l(r5) ; CHECK-LE-NEXT: std r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i64 %a, %b %cmp = icmp eq i64 %a, %b
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
; CHECK-NEXT: rldicl r3, r3, 58, 63 ; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: std r3, glob@toc@l(r4) ; CHECK-NEXT: std r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llequll_z_store: ; CHECK-BE-LABEL: test_llequll_z_store:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: cntlzd r3, r3 ; CHECK-BE-NEXT: cntlzd r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: rldicl r3, r3, 58, 63 ; CHECK-BE-NEXT: extrdi r3, r3, 1, 57
; CHECK-BE-NEXT: std r3, 0(r4) ; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_llequll_z_store: ; CHECK-LE-LABEL: test_llequll_z_store:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: cntlzd r3, r3 ; CHECK-LE-NEXT: cntlzd r3, r3
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha ; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: rldicl r3, r3, 58, 63 ; CHECK-LE-NEXT: extrdi r3, r3, 1, 57
; CHECK-LE-NEXT: std r3, glob@toc@l(r4) ; CHECK-LE-NEXT: std r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp eq i64 %a, 0 %cmp = icmp eq i64 %a, 0
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }
Show All 32 Lines

llvm/test/CodeGen/PowerPC/testComparesllgesc.ll

Show All 11 Lines
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llgesc: ; CHECK-BE-LABEL: test_llgesc:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sub r3, r3, r4 ; CHECK-BE-NEXT: sub r3, r3, r4
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-BE-NEXT: srdi r3, r3, 63
; CHECK-BE-NEXT: xori r3, r3, 1 ; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_llgesc: ; CHECK-LE-LABEL: test_llgesc:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r3, r4 ; CHECK-LE-NEXT: sub r3, r3, r4
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-LE-NEXT: srdi r3, r3, 63
; CHECK-LE-NEXT: xori r3, r3, 1 ; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i8 %a, %b %cmp = icmp sge i8 %a, %b
%conv3 = zext i1 %cmp to i64 %conv3 = zext i1 %cmp to i64
ret i64 %conv3 ret i64 %conv3
} }
define i64 @test_llgesc_sext(i8 signext %a, i8 signext %b) { define i64 @test_llgesc_sext(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_llgesc_sext: ; CHECK-LABEL: test_llgesc_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llgesc_sext: ; CHECK-BE-LABEL: test_llgesc_sext:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sub r3, r3, r4 ; CHECK-BE-NEXT: sub r3, r3, r4
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-BE-NEXT: srdi r3, r3, 63
; CHECK-BE-NEXT: addi r3, r3, -1 ; CHECK-BE-NEXT: addi r3, r3, -1
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_llgesc_sext: ; CHECK-LE-LABEL: test_llgesc_sext:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r3, r4 ; CHECK-LE-NEXT: sub r3, r3, r4
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-LE-NEXT: srdi r3, r3, 63
; CHECK-LE-NEXT: addi r3, r3, -1 ; CHECK-LE-NEXT: addi r3, r3, -1
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i8 %a, %b %cmp = icmp sge i8 %a, %b
%conv3 = sext i1 %cmp to i64 %conv3 = sext i1 %cmp to i64
ret i64 %conv3 ret i64 %conv3
} }
define void @test_llgesc_store(i8 signext %a, i8 signext %b) { define void @test_llgesc_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_llgesc_store: ; CHECK-LABEL: test_llgesc_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stb r3, glob@toc@l(r5) ; CHECK-NEXT: stb r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llgesc_store: ; CHECK-BE-LABEL: test_llgesc_store:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sub r3, r3, r4 ; CHECK-BE-NEXT: sub r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-BE-NEXT: srdi r3, r3, 63
; CHECK-BE-NEXT: xori r3, r3, 1 ; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: stb r3, 0(r4) ; CHECK-BE-NEXT: stb r3, 0(r4)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_llgesc_store: ; CHECK-LE-LABEL: test_llgesc_store:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r3, r4 ; CHECK-LE-NEXT: sub r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha ; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-LE-NEXT: srdi r3, r3, 63
; CHECK-LE-NEXT: xori r3, r3, 1 ; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: stb r3, glob@toc@l(r5) ; CHECK-LE-NEXT: stb r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i8 %a, %b %cmp = icmp sge i8 %a, %b
%conv3 = zext i1 %cmp to i8 %conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1 store i8 %conv3, i8* @glob, align 1
ret void ret void
} }
define void @test_llgesc_sext_store(i8 signext %a, i8 signext %b) { define void @test_llgesc_sext_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_llgesc_sext_store: ; CHECK-LABEL: test_llgesc_sext_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: stb r3, glob@toc@l(r5) ; CHECK-NEXT: stb r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llgesc_sext_store: ; CHECK-BE-LABEL: test_llgesc_sext_store:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sub r3, r3, r4 ; CHECK-BE-NEXT: sub r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-BE-NEXT: srdi r3, r3, 63
; CHECK-BE-NEXT: addi r3, r3, -1 ; CHECK-BE-NEXT: addi r3, r3, -1
; CHECK-BE-NEXT: stb r3, 0(r4) ; CHECK-BE-NEXT: stb r3, 0(r4)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_llgesc_sext_store: ; CHECK-LE-LABEL: test_llgesc_sext_store:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r3, r4 ; CHECK-LE-NEXT: sub r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha ; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-LE-NEXT: srdi r3, r3, 63
; CHECK-LE-NEXT: addi r3, r3, -1 ; CHECK-LE-NEXT: addi r3, r3, -1
; CHECK-LE-NEXT: stb r3, glob@toc@l(r5) ; CHECK-LE-NEXT: stb r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i8 %a, %b %cmp = icmp sge i8 %a, %b
%conv3 = sext i1 %cmp to i8 %conv3 = sext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1 store i8 %conv3, i8* @glob, align 1
ret void ret void
} }

llvm/test/CodeGen/PowerPC/testComparesllgesi.ll

Show All 11 Lines
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llgesi: ; CHECK-BE-LABEL: test_llgesi:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sub r3, r3, r4 ; CHECK-BE-NEXT: sub r3, r3, r4
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-BE-NEXT: srdi r3, r3, 63
; CHECK-BE-NEXT: xori r3, r3, 1 ; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_llgesi: ; CHECK-LE-LABEL: test_llgesi:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r3, r4 ; CHECK-LE-NEXT: sub r3, r3, r4
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-LE-NEXT: srdi r3, r3, 63
; CHECK-LE-NEXT: xori r3, r3, 1 ; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i32 %a, %b %cmp = icmp sge i32 %a, %b
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
define i64 @test_llgesi_sext(i32 signext %a, i32 signext %b) { define i64 @test_llgesi_sext(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_llgesi_sext: ; CHECK-LABEL: test_llgesi_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llgesi_sext: ; CHECK-BE-LABEL: test_llgesi_sext:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sub r3, r3, r4 ; CHECK-BE-NEXT: sub r3, r3, r4
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-BE-NEXT: srdi r3, r3, 63
; CHECK-BE-NEXT: addi r3, r3, -1 ; CHECK-BE-NEXT: addi r3, r3, -1
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_llgesi_sext: ; CHECK-LE-LABEL: test_llgesi_sext:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r3, r4 ; CHECK-LE-NEXT: sub r3, r3, r4
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-LE-NEXT: srdi r3, r3, 63
; CHECK-LE-NEXT: addi r3, r3, -1 ; CHECK-LE-NEXT: addi r3, r3, -1
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i32 %a, %b %cmp = icmp sge i32 %a, %b
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
define void @test_llgesi_store(i32 signext %a, i32 signext %b) { define void @test_llgesi_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_llgesi_store: ; CHECK-LABEL: test_llgesi_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stw r3, glob@toc@l(r5) ; CHECK-NEXT: stw r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llgesi_store: ; CHECK-BE-LABEL: test_llgesi_store:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sub r3, r3, r4 ; CHECK-BE-NEXT: sub r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-BE-NEXT: srdi r3, r3, 63
; CHECK-BE-NEXT: xori r3, r3, 1 ; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: stw r3, 0(r4) ; CHECK-BE-NEXT: stw r3, 0(r4)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_llgesi_store: ; CHECK-LE-LABEL: test_llgesi_store:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r3, r4 ; CHECK-LE-NEXT: sub r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha ; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-LE-NEXT: srdi r3, r3, 63
; CHECK-LE-NEXT: xori r3, r3, 1 ; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: stw r3, glob@toc@l(r5) ; CHECK-LE-NEXT: stw r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i32 %a, %b %cmp = icmp sge i32 %a, %b
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4 store i32 %conv, i32* @glob, align 4
ret void ret void
} }
define void @test_llgesi_sext_store(i32 signext %a, i32 signext %b) { define void @test_llgesi_sext_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_llgesi_sext_store: ; CHECK-LABEL: test_llgesi_sext_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: stw r3, glob@toc@l(r5) ; CHECK-NEXT: stw r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llgesi_sext_store: ; CHECK-BE-LABEL: test_llgesi_sext_store:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sub r3, r3, r4 ; CHECK-BE-NEXT: sub r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-BE-NEXT: srdi r3, r3, 63
; CHECK-BE-NEXT: addi r3, r3, -1 ; CHECK-BE-NEXT: addi r3, r3, -1
; CHECK-BE-NEXT: stw r3, 0(r4) ; CHECK-BE-NEXT: stw r3, 0(r4)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_llgesi_sext_store: ; CHECK-LE-LABEL: test_llgesi_sext_store:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r3, r4 ; CHECK-LE-NEXT: sub r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha ; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-LE-NEXT: srdi r3, r3, 63
; CHECK-LE-NEXT: addi r3, r3, -1 ; CHECK-LE-NEXT: addi r3, r3, -1
; CHECK-LE-NEXT: stw r3, glob@toc@l(r5) ; CHECK-LE-NEXT: stw r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i32 %a, %b %cmp = icmp sge i32 %a, %b
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4 store i32 %sub, i32* @glob, align 4
ret void ret void
} }

llvm/test/CodeGen/PowerPC/testComparesllgesll.ll

Show All 12 Lines
; CHECK-NEXT: sradi r5, r3, 63 ; CHECK-NEXT: sradi r5, r3, 63
; CHECK-NEXT: rldicl r6, r4, 1, 63 ; CHECK-NEXT: rldicl r6, r4, 1, 63
; CHECK-NEXT: subfc r3, r4, r3 ; CHECK-NEXT: subfc r3, r4, r3
; CHECK-NEXT: adde r3, r5, r6 ; CHECK-NEXT: adde r3, r5, r6
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llgesll: ; CHECK-BE-LABEL: test_llgesll:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r5, r3, 63 ; CHECK-BE-NEXT: sradi r5, r3, 63
; CHECK-BE-NEXT: rldicl r6, r4, 1, 63 ; CHECK-BE-NEXT: srdi r6, r4, 63
; CHECK-BE-NEXT: subc r3, r3, r4 ; CHECK-BE-NEXT: subc r3, r3, r4
; CHECK-BE-NEXT: adde r3, r5, r6 ; CHECK-BE-NEXT: adde r3, r5, r6
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_llgesll: ; CHECK-LE-LABEL: test_llgesll:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r5, r3, 63 ; CHECK-LE-NEXT: sradi r5, r3, 63
; CHECK-LE-NEXT: rldicl r6, r4, 1, 63 ; CHECK-LE-NEXT: srdi r6, r4, 63
; CHECK-LE-NEXT: subc r3, r3, r4 ; CHECK-LE-NEXT: subc r3, r3, r4
; CHECK-LE-NEXT: adde r3, r5, r6 ; CHECK-LE-NEXT: adde r3, r5, r6
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i64 %a, %b %cmp = icmp sge i64 %a, %b
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
define i64 @test_llgesll_sext(i64 %a, i64 %b) { define i64 @test_llgesll_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_llgesll_sext: ; CHECK-LABEL: test_llgesll_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r5, r3, 63 ; CHECK-NEXT: sradi r5, r3, 63
; CHECK-NEXT: rldicl r6, r4, 1, 63 ; CHECK-NEXT: rldicl r6, r4, 1, 63
; CHECK-NEXT: subfc r3, r4, r3 ; CHECK-NEXT: subfc r3, r4, r3
; CHECK-NEXT: adde r3, r5, r6 ; CHECK-NEXT: adde r3, r5, r6
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llgesll_sext: ; CHECK-BE-LABEL: test_llgesll_sext:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r5, r3, 63 ; CHECK-BE-NEXT: sradi r5, r3, 63
; CHECK-BE-NEXT: rldicl r6, r4, 1, 63 ; CHECK-BE-NEXT: srdi r6, r4, 63
; CHECK-BE-NEXT: subc r3, r3, r4 ; CHECK-BE-NEXT: subc r3, r3, r4
; CHECK-BE-NEXT: adde r3, r5, r6 ; CHECK-BE-NEXT: adde r3, r5, r6
; CHECK-BE-NEXT: neg r3, r3 ; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_llgesll_sext: ; CHECK-LE-LABEL: test_llgesll_sext:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r5, r3, 63 ; CHECK-LE-NEXT: sradi r5, r3, 63
; CHECK-LE-NEXT: rldicl r6, r4, 1, 63 ; CHECK-LE-NEXT: srdi r6, r4, 63
; CHECK-LE-NEXT: subc r3, r3, r4 ; CHECK-LE-NEXT: subc r3, r3, r4
; CHECK-LE-NEXT: adde r3, r5, r6 ; CHECK-LE-NEXT: adde r3, r5, r6
; CHECK-LE-NEXT: neg r3, r3 ; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i64 %a, %b %cmp = icmp sge i64 %a, %b
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
define i64 @test_llgesll_z(i64 %a) { define i64 @test_llgesll_z(i64 %a) {
; CHECK-LABEL: test_llgesll_z: ; CHECK-LABEL: test_llgesll_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: not r3, r3 ; CHECK-NEXT: not r3, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llgesll_z: ; CHECK-BE-LABEL: test_llgesll_z:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: not r3, r3 ; CHECK-BE-NEXT: not r3, r3
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-BE-NEXT: srdi r3, r3, 63
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_llgesll_z: ; CHECK-LE-LABEL: test_llgesll_z:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: not r3, r3 ; CHECK-LE-NEXT: not r3, r3
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-LE-NEXT: srdi r3, r3, 63
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sgt i64 %a, -1 %cmp = icmp sgt i64 %a, -1
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
define i64 @test_llgesll_sext_z(i64 %a) { define i64 @test_llgesll_sext_z(i64 %a) {
Show All 30 Lines
; CHECK-NEXT: std r3, glob@toc@l(r5) ; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llgesll_store: ; CHECK-BE-LABEL: test_llgesll_store:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sradi r6, r3, 63 ; CHECK-BE-NEXT: sradi r6, r3, 63
; CHECK-BE-NEXT: ld r5, .LC0@toc@l(r5) ; CHECK-BE-NEXT: ld r5, .LC0@toc@l(r5)
; CHECK-BE-NEXT: subc r3, r3, r4 ; CHECK-BE-NEXT: subc r3, r3, r4
; CHECK-BE-NEXT: rldicl r3, r4, 1, 63 ; CHECK-BE-NEXT: srdi r3, r4, 63
; CHECK-BE-NEXT: adde r3, r6, r3 ; CHECK-BE-NEXT: adde r3, r6, r3
; CHECK-BE-NEXT: std r3, 0(r5) ; CHECK-BE-NEXT: std r3, 0(r5)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_llgesll_store: ; CHECK-LE-LABEL: test_llgesll_store:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r6, r3, 63 ; CHECK-LE-NEXT: sradi r6, r3, 63
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha ; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: subc r3, r3, r4 ; CHECK-LE-NEXT: subc r3, r3, r4
; CHECK-LE-NEXT: rldicl r3, r4, 1, 63 ; CHECK-LE-NEXT: srdi r3, r4, 63
; CHECK-LE-NEXT: adde r3, r6, r3 ; CHECK-LE-NEXT: adde r3, r6, r3
; CHECK-LE-NEXT: std r3, glob@toc@l(r5) ; CHECK-LE-NEXT: std r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i64 %a, %b %cmp = icmp sge i64 %a, %b
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
Show All 10 Lines
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: std r3, glob@toc@l(r5) ; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llgesll_sext_store: ; CHECK-BE-LABEL: test_llgesll_sext_store:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r6, r3, 63 ; CHECK-BE-NEXT: sradi r6, r3, 63
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: subc r3, r3, r4 ; CHECK-BE-NEXT: subc r3, r3, r4
; CHECK-BE-NEXT: rldicl r3, r4, 1, 63 ; CHECK-BE-NEXT: srdi r3, r4, 63
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: adde r3, r6, r3 ; CHECK-BE-NEXT: adde r3, r6, r3
; CHECK-BE-NEXT: neg r3, r3 ; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: std r3, 0(r4) ; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_llgesll_sext_store: ; CHECK-LE-LABEL: test_llgesll_sext_store:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r6, r3, 63 ; CHECK-LE-NEXT: sradi r6, r3, 63
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha ; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: subc r3, r3, r4 ; CHECK-LE-NEXT: subc r3, r3, r4
; CHECK-LE-NEXT: rldicl r3, r4, 1, 63 ; CHECK-LE-NEXT: srdi r3, r4, 63
; CHECK-LE-NEXT: adde r3, r6, r3 ; CHECK-LE-NEXT: adde r3, r6, r3
; CHECK-LE-NEXT: neg r3, r3 ; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: std r3, glob@toc@l(r5) ; CHECK-LE-NEXT: std r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i64 %a, %b %cmp = icmp sge i64 %a, %b
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }
define void @test_llgesll_z_store(i64 %a) { define void @test_llgesll_z_store(i64 %a) {
; CHECK-LABEL: test_llgesll_z_store: ; CHECK-LABEL: test_llgesll_z_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: not r3, r3 ; CHECK-NEXT: not r3, r3
; CHECK-NEXT: addis r4, r2, glob@toc@ha ; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: std r3, glob@toc@l(r4) ; CHECK-NEXT: std r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llgesll_z_store: ; CHECK-BE-LABEL: test_llgesll_z_store:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: not r3, r3 ; CHECK-BE-NEXT: not r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-BE-NEXT: srdi r3, r3, 63
; CHECK-BE-NEXT: std r3, 0(r4) ; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_llgesll_z_store: ; CHECK-LE-LABEL: test_llgesll_z_store:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: not r3, r3 ; CHECK-LE-NEXT: not r3, r3
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha ; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-LE-NEXT: srdi r3, r3, 63
; CHECK-LE-NEXT: std r3, glob@toc@l(r4) ; CHECK-LE-NEXT: std r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sgt i64 %a, -1 %cmp = icmp sgt i64 %a, -1
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }
Show All 31 Lines

llvm/test/CodeGen/PowerPC/testComparesllgess.ll

Show All 11 Lines
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llgess: ; CHECK-BE-LABEL: test_llgess:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sub r3, r3, r4 ; CHECK-BE-NEXT: sub r3, r3, r4
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-BE-NEXT: srdi r3, r3, 63
; CHECK-BE-NEXT: xori r3, r3, 1 ; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_llgess: ; CHECK-LE-LABEL: test_llgess:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r3, r4 ; CHECK-LE-NEXT: sub r3, r3, r4
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-LE-NEXT: srdi r3, r3, 63
; CHECK-LE-NEXT: xori r3, r3, 1 ; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i16 %a, %b %cmp = icmp sge i16 %a, %b
%conv3 = zext i1 %cmp to i64 %conv3 = zext i1 %cmp to i64
ret i64 %conv3 ret i64 %conv3
} }
define i64 @test_llgess_sext(i16 signext %a, i16 signext %b) { define i64 @test_llgess_sext(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_llgess_sext: ; CHECK-LABEL: test_llgess_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llgess_sext: ; CHECK-BE-LABEL: test_llgess_sext:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sub r3, r3, r4 ; CHECK-BE-NEXT: sub r3, r3, r4
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-BE-NEXT: srdi r3, r3, 63
; CHECK-BE-NEXT: addi r3, r3, -1 ; CHECK-BE-NEXT: addi r3, r3, -1
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_llgess_sext: ; CHECK-LE-LABEL: test_llgess_sext:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r3, r4 ; CHECK-LE-NEXT: sub r3, r3, r4
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-LE-NEXT: srdi r3, r3, 63
; CHECK-LE-NEXT: addi r3, r3, -1 ; CHECK-LE-NEXT: addi r3, r3, -1
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i16 %a, %b %cmp = icmp sge i16 %a, %b
%conv3 = sext i1 %cmp to i64 %conv3 = sext i1 %cmp to i64
ret i64 %conv3 ret i64 %conv3
} }
define void @test_llgess_store(i16 signext %a, i16 signext %b) { define void @test_llgess_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_llgess_store: ; CHECK-LABEL: test_llgess_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: sth r3, glob@toc@l(r5) ; CHECK-NEXT: sth r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llgess_store: ; CHECK-BE-LABEL: test_llgess_store:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sub r3, r3, r4 ; CHECK-BE-NEXT: sub r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-BE-NEXT: srdi r3, r3, 63
; CHECK-BE-NEXT: xori r3, r3, 1 ; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: sth r3, 0(r4) ; CHECK-BE-NEXT: sth r3, 0(r4)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_llgess_store: ; CHECK-LE-LABEL: test_llgess_store:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r3, r4 ; CHECK-LE-NEXT: sub r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha ; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-LE-NEXT: srdi r3, r3, 63
; CHECK-LE-NEXT: xori r3, r3, 1 ; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: sth r3, glob@toc@l(r5) ; CHECK-LE-NEXT: sth r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i16 %a, %b %cmp = icmp sge i16 %a, %b
%conv3 = zext i1 %cmp to i16 %conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2 store i16 %conv3, i16* @glob, align 2
ret void ret void
} }
define void @test_llgess_sext_store(i16 signext %a, i16 signext %b) { define void @test_llgess_sext_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_llgess_sext_store: ; CHECK-LABEL: test_llgess_sext_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: sth r3, glob@toc@l(r5) ; CHECK-NEXT: sth r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llgess_sext_store: ; CHECK-BE-LABEL: test_llgess_sext_store:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sub r3, r3, r4 ; CHECK-BE-NEXT: sub r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-BE-NEXT: srdi r3, r3, 63
; CHECK-BE-NEXT: addi r3, r3, -1 ; CHECK-BE-NEXT: addi r3, r3, -1
; CHECK-BE-NEXT: sth r3, 0(r4) ; CHECK-BE-NEXT: sth r3, 0(r4)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_llgess_sext_store: ; CHECK-LE-LABEL: test_llgess_sext_store:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r3, r4 ; CHECK-LE-NEXT: sub r3, r3, r4
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha ; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-LE-NEXT: srdi r3, r3, 63
; CHECK-LE-NEXT: addi r3, r3, -1 ; CHECK-LE-NEXT: addi r3, r3, -1
; CHECK-LE-NEXT: sth r3, glob@toc@l(r5) ; CHECK-LE-NEXT: sth r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i16 %a, %b %cmp = icmp sge i16 %a, %b
%conv3 = sext i1 %cmp to i16 %conv3 = sext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2 store i16 %conv3, i16* @glob, align 2
ret void ret void
} }

llvm/test/CodeGen/PowerPC/testComparesllgeuc.ll

Show All 10 Lines
@glob = local_unnamed_addr global i8 0, align 1 @glob = local_unnamed_addr global i8 0, align 1
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_llgeuc(i8 zeroext %a, i8 zeroext %b) { define i64 @test_llgeuc(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_llgeuc: ; CHECK-LABEL: test_llgeuc:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: not r3, r3 ; CHECK-NEXT: not r3, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp uge i8 %a, %b %cmp = icmp uge i8 %a, %b
%conv3 = zext i1 %cmp to i64 %conv3 = zext i1 %cmp to i64
ret i64 %conv3 ret i64 %conv3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_llgeuc_sext(i8 zeroext %a, i8 zeroext %b) { define i64 @test_llgeuc_sext(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_llgeuc_sext: ; CHECK-LABEL: test_llgeuc_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp uge i8 %a, %b %cmp = icmp uge i8 %a, %b
%conv3 = sext i1 %cmp to i64 %conv3 = sext i1 %cmp to i64
ret i64 %conv3 ret i64 %conv3
} }
Show All 24 Lines
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_llgeuc_store(i8 zeroext %a, i8 zeroext %b) { define void @test_llgeuc_store(i8 zeroext %a, i8 zeroext %b) {
; BE-LABEL: test_llgeuc_store: ; BE-LABEL: test_llgeuc_store:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha ; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: sub r3, r3, r4 ; BE-NEXT: sub r3, r3, r4
; BE-NEXT: ld r4, .LC0@toc@l(r5) ; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: not r3, r3 ; BE-NEXT: not r3, r3
; BE-NEXT: rldicl r3, r3, 1, 63 ; BE-NEXT: srdi r3, r3, 63
; BE-NEXT: stb r3, 0(r4) ; BE-NEXT: stb r3, 0(r4)
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; LE-LABEL: test_llgeuc_store: ; LE-LABEL: test_llgeuc_store:
; LE: # %bb.0: # %entry ; LE: # %bb.0: # %entry
; LE-NEXT: sub r3, r3, r4 ; LE-NEXT: sub r3, r3, r4
; LE-NEXT: addis r5, r2, glob@toc@ha ; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: not r3, r3 ; LE-NEXT: not r3, r3
; LE-NEXT: rldicl r3, r3, 1, 63 ; LE-NEXT: srdi r3, r3, 63
; LE-NEXT: stb r3, glob@toc@l(r5) ; LE-NEXT: stb r3, glob@toc@l(r5)
; LE-NEXT: blr ; LE-NEXT: blr
entry: entry:
%cmp = icmp uge i8 %a, %b %cmp = icmp uge i8 %a, %b
%conv3 = zext i1 %cmp to i8 %conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob store i8 %conv3, i8* @glob
ret void ret void
; CHECK_LABEL: test_llgeuc_store: ; CHECK_LABEL: test_llgeuc_store:
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_llgeuc_sext_store(i8 zeroext %a, i8 zeroext %b) { define void @test_llgeuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
; BE-LABEL: test_llgeuc_sext_store: ; BE-LABEL: test_llgeuc_sext_store:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha ; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: sub r3, r3, r4 ; BE-NEXT: sub r3, r3, r4
; BE-NEXT: ld r4, .LC0@toc@l(r5) ; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: rldicl r3, r3, 1, 63 ; BE-NEXT: srdi r3, r3, 63
; BE-NEXT: addi r3, r3, -1 ; BE-NEXT: addi r3, r3, -1
; BE-NEXT: stb r3, 0(r4) ; BE-NEXT: stb r3, 0(r4)
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; LE-LABEL: test_llgeuc_sext_store: ; LE-LABEL: test_llgeuc_sext_store:
; LE: # %bb.0: # %entry ; LE: # %bb.0: # %entry
; LE-NEXT: sub r3, r3, r4 ; LE-NEXT: sub r3, r3, r4
; LE-NEXT: addis r5, r2, glob@toc@ha ; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: rldicl r3, r3, 1, 63 ; LE-NEXT: srdi r3, r3, 63
; LE-NEXT: addi r3, r3, -1 ; LE-NEXT: addi r3, r3, -1
; LE-NEXT: stb r3, glob@toc@l(r5) ; LE-NEXT: stb r3, glob@toc@l(r5)
; LE-NEXT: blr ; LE-NEXT: blr
entry: entry:
%cmp = icmp uge i8 %a, %b %cmp = icmp uge i8 %a, %b
%conv3 = sext i1 %cmp to i8 %conv3 = sext i1 %cmp to i8
store i8 %conv3, i8* @glob store i8 %conv3, i8* @glob
ret void ret void
▲ Show 20 Lines • Show All 48 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/testComparesllgeui.ll

Show All 10 Lines
@glob = local_unnamed_addr global i32 0, align 4 @glob = local_unnamed_addr global i32 0, align 4
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_llgeui(i32 zeroext %a, i32 zeroext %b) { define i64 @test_llgeui(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_llgeui: ; CHECK-LABEL: test_llgeui:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: not r3, r3 ; CHECK-NEXT: not r3, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp uge i32 %a, %b %cmp = icmp uge i32 %a, %b
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_llgeui_sext(i32 zeroext %a, i32 zeroext %b) { define i64 @test_llgeui_sext(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_llgeui_sext: ; CHECK-LABEL: test_llgeui_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp uge i32 %a, %b %cmp = icmp uge i32 %a, %b
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
Show All 24 Lines
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_llgeui_store(i32 zeroext %a, i32 zeroext %b) { define void @test_llgeui_store(i32 zeroext %a, i32 zeroext %b) {
; BE-LABEL: test_llgeui_store: ; BE-LABEL: test_llgeui_store:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha ; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: sub r3, r3, r4 ; BE-NEXT: sub r3, r3, r4
; BE-NEXT: ld r4, .LC0@toc@l(r5) ; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: not r3, r3 ; BE-NEXT: not r3, r3
; BE-NEXT: rldicl r3, r3, 1, 63 ; BE-NEXT: srdi r3, r3, 63
; BE-NEXT: stw r3, 0(r4) ; BE-NEXT: stw r3, 0(r4)
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; LE-LABEL: test_llgeui_store: ; LE-LABEL: test_llgeui_store:
; LE: # %bb.0: # %entry ; LE: # %bb.0: # %entry
; LE-NEXT: sub r3, r3, r4 ; LE-NEXT: sub r3, r3, r4
; LE-NEXT: addis r5, r2, glob@toc@ha ; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: not r3, r3 ; LE-NEXT: not r3, r3
; LE-NEXT: rldicl r3, r3, 1, 63 ; LE-NEXT: srdi r3, r3, 63
; LE-NEXT: stw r3, glob@toc@l(r5) ; LE-NEXT: stw r3, glob@toc@l(r5)
; LE-NEXT: blr ; LE-NEXT: blr
entry: entry:
%cmp = icmp uge i32 %a, %b %cmp = icmp uge i32 %a, %b
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob store i32 %conv, i32* @glob
ret void ret void
; CHECK_LABEL: test_igeuc_store: ; CHECK_LABEL: test_igeuc_store:
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_llgeui_sext_store(i32 zeroext %a, i32 zeroext %b) { define void @test_llgeui_sext_store(i32 zeroext %a, i32 zeroext %b) {
; BE-LABEL: test_llgeui_sext_store: ; BE-LABEL: test_llgeui_sext_store:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha ; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: sub r3, r3, r4 ; BE-NEXT: sub r3, r3, r4
; BE-NEXT: ld r4, .LC0@toc@l(r5) ; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: rldicl r3, r3, 1, 63 ; BE-NEXT: srdi r3, r3, 63
; BE-NEXT: addi r3, r3, -1 ; BE-NEXT: addi r3, r3, -1
; BE-NEXT: stw r3, 0(r4) ; BE-NEXT: stw r3, 0(r4)
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; LE-LABEL: test_llgeui_sext_store: ; LE-LABEL: test_llgeui_sext_store:
; LE: # %bb.0: # %entry ; LE: # %bb.0: # %entry
; LE-NEXT: sub r3, r3, r4 ; LE-NEXT: sub r3, r3, r4
; LE-NEXT: addis r5, r2, glob@toc@ha ; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: rldicl r3, r3, 1, 63 ; LE-NEXT: srdi r3, r3, 63
; LE-NEXT: addi r3, r3, -1 ; LE-NEXT: addi r3, r3, -1
; LE-NEXT: stw r3, glob@toc@l(r5) ; LE-NEXT: stw r3, glob@toc@l(r5)
; LE-NEXT: blr ; LE-NEXT: blr
entry: entry:
%cmp = icmp uge i32 %a, %b %cmp = icmp uge i32 %a, %b
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob store i32 %sub, i32* @glob
ret void ret void
▲ Show 20 Lines • Show All 48 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/testComparesllgeus.ll

Show All 10 Lines
@glob = local_unnamed_addr global i16 0, align 2 @glob = local_unnamed_addr global i16 0, align 2
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_llgeus(i16 zeroext %a, i16 zeroext %b) { define i64 @test_llgeus(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_llgeus: ; CHECK-LABEL: test_llgeus:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: not r3, r3 ; CHECK-NEXT: not r3, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp uge i16 %a, %b %cmp = icmp uge i16 %a, %b
%conv3 = zext i1 %cmp to i64 %conv3 = zext i1 %cmp to i64
ret i64 %conv3 ret i64 %conv3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_llgeus_sext(i16 zeroext %a, i16 zeroext %b) { define i64 @test_llgeus_sext(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_llgeus_sext: ; CHECK-LABEL: test_llgeus_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp uge i16 %a, %b %cmp = icmp uge i16 %a, %b
%conv3 = sext i1 %cmp to i64 %conv3 = sext i1 %cmp to i64
ret i64 %conv3 ret i64 %conv3
} }
Show All 24 Lines
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_llgeus_store(i16 zeroext %a, i16 zeroext %b) { define void @test_llgeus_store(i16 zeroext %a, i16 zeroext %b) {
; BE-LABEL: test_llgeus_store: ; BE-LABEL: test_llgeus_store:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha ; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: sub r3, r3, r4 ; BE-NEXT: sub r3, r3, r4
; BE-NEXT: ld r4, .LC0@toc@l(r5) ; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: not r3, r3 ; BE-NEXT: not r3, r3
; BE-NEXT: rldicl r3, r3, 1, 63 ; BE-NEXT: srdi r3, r3, 63
; BE-NEXT: sth r3, 0(r4) ; BE-NEXT: sth r3, 0(r4)
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; LE-LABEL: test_llgeus_store: ; LE-LABEL: test_llgeus_store:
; LE: # %bb.0: # %entry ; LE: # %bb.0: # %entry
; LE-NEXT: sub r3, r3, r4 ; LE-NEXT: sub r3, r3, r4
; LE-NEXT: addis r5, r2, glob@toc@ha ; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: not r3, r3 ; LE-NEXT: not r3, r3
; LE-NEXT: rldicl r3, r3, 1, 63 ; LE-NEXT: srdi r3, r3, 63
; LE-NEXT: sth r3, glob@toc@l(r5) ; LE-NEXT: sth r3, glob@toc@l(r5)
; LE-NEXT: blr ; LE-NEXT: blr
entry: entry:
%cmp = icmp uge i16 %a, %b %cmp = icmp uge i16 %a, %b
%conv3 = zext i1 %cmp to i16 %conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob store i16 %conv3, i16* @glob
ret void ret void
; CHECK_LABEL: test_llgeus_store: ; CHECK_LABEL: test_llgeus_store:
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_llgeus_sext_store(i16 zeroext %a, i16 zeroext %b) { define void @test_llgeus_sext_store(i16 zeroext %a, i16 zeroext %b) {
; BE-LABEL: test_llgeus_sext_store: ; BE-LABEL: test_llgeus_sext_store:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha ; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: sub r3, r3, r4 ; BE-NEXT: sub r3, r3, r4
; BE-NEXT: ld r4, .LC0@toc@l(r5) ; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: rldicl r3, r3, 1, 63 ; BE-NEXT: srdi r3, r3, 63
; BE-NEXT: addi r3, r3, -1 ; BE-NEXT: addi r3, r3, -1
; BE-NEXT: sth r3, 0(r4) ; BE-NEXT: sth r3, 0(r4)
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; LE-LABEL: test_llgeus_sext_store: ; LE-LABEL: test_llgeus_sext_store:
; LE: # %bb.0: # %entry ; LE: # %bb.0: # %entry
; LE-NEXT: sub r3, r3, r4 ; LE-NEXT: sub r3, r3, r4
; LE-NEXT: addis r5, r2, glob@toc@ha ; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: rldicl r3, r3, 1, 63 ; LE-NEXT: srdi r3, r3, 63
; LE-NEXT: addi r3, r3, -1 ; LE-NEXT: addi r3, r3, -1
; LE-NEXT: sth r3, glob@toc@l(r5) ; LE-NEXT: sth r3, glob@toc@l(r5)
; LE-NEXT: blr ; LE-NEXT: blr
entry: entry:
%cmp = icmp uge i16 %a, %b %cmp = icmp uge i16 %a, %b
%conv3 = sext i1 %cmp to i16 %conv3 = sext i1 %cmp to i16
store i16 %conv3, i16* @glob store i16 %conv3, i16* @glob
ret void ret void
▲ Show 20 Lines • Show All 48 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/testComparesllgtsll.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = local_unnamed_addr global i64 0, align 8 @glob = local_unnamed_addr global i64 0, align 8
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_llgtsll(i64 %a, i64 %b) { define i64 @test_llgtsll(i64 %a, i64 %b) {
; CHECK-LABEL: test_llgtsll: ; CHECK-LABEL: test_llgtsll:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r5, r4, 63 ; CHECK-NEXT: sradi r5, r4, 63
; CHECK-NEXT: rldicl r6, r3, 1, 63 ; CHECK-NEXT: srdi r6, r3, 63
; CHECK-NEXT: subc r3, r4, r3 ; CHECK-NEXT: subc r3, r4, r3
; CHECK-NEXT: adde r3, r6, r5 ; CHECK-NEXT: adde r3, r6, r5
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp sgt i64 %a, %b %cmp = icmp sgt i64 %a, %b
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_llgtsll_sext(i64 %a, i64 %b) { define i64 @test_llgtsll_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_llgtsll_sext: ; CHECK-LABEL: test_llgtsll_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r5, r4, 63 ; CHECK-NEXT: sradi r5, r4, 63
; CHECK-NEXT: rldicl r6, r3, 1, 63 ; CHECK-NEXT: srdi r6, r3, 63
; CHECK-NEXT: subc r3, r4, r3 ; CHECK-NEXT: subc r3, r4, r3
; CHECK-NEXT: adde r3, r6, r5 ; CHECK-NEXT: adde r3, r6, r5
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp sgt i64 %a, %b %cmp = icmp sgt i64 %a, %b
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
; FIXME ; FIXME
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_llgtsll_z(i64 %a) { define i64 @test_llgtsll_z(i64 %a) {
; CHECK-LABEL: test_llgtsll_z: ; CHECK-LABEL: test_llgtsll_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi r4, r3, -1 ; CHECK-NEXT: addi r4, r3, -1
; CHECK-NEXT: nor r3, r4, r3 ; CHECK-NEXT: nor r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp sgt i64 %a, 0 %cmp = icmp sgt i64 %a, 0
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
Show All 12 Lines
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_llgtsll_store(i64 %a, i64 %b) { define void @test_llgtsll_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_llgtsll_store: ; CHECK-LABEL: test_llgtsll_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r6, r4, 63 ; CHECK-NEXT: sradi r6, r4, 63
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subc r4, r4, r3 ; CHECK-NEXT: subc r4, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: adde r3, r3, r6 ; CHECK-NEXT: adde r3, r3, r6
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r3, r4 ; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r3, r4
entry: entry:
%cmp = icmp sgt i64 %a, %b %cmp = icmp sgt i64 %a, %b
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_llgtsll_sext_store(i64 %a, i64 %b) { define void @test_llgtsll_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_llgtsll_sext_store: ; CHECK-LABEL: test_llgtsll_sext_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r6, r4, 63 ; CHECK-NEXT: sradi r6, r4, 63
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subc r4, r4, r3 ; CHECK-NEXT: subc r4, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: adde r3, r3, r6 ; CHECK-NEXT: adde r3, r3, r6
; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r3, r4 ; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r3, r4
entry: entry:
%cmp = icmp sgt i64 %a, %b %cmp = icmp sgt i64 %a, %b
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }
; FIXME ; FIXME
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_llgtsll_z_store(i64 %a) { define void @test_llgtsll_z_store(i64 %a) {
; CHECK-LABEL: test_llgtsll_z_store: ; CHECK-LABEL: test_llgtsll_z_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: addi r5, r3, -1 ; CHECK-NEXT: addi r5, r3, -1
; CHECK-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: nor r3, r5, r3 ; CHECK-NEXT: nor r3, r5, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp sgt i64 %a, 0 %cmp = icmp sgt i64 %a, 0
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }
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llvm/test/CodeGen/PowerPC/testComparesllgtuc.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = local_unnamed_addr global i8 0, align 1 @glob = local_unnamed_addr global i8 0, align 1
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_llgtuc(i8 zeroext %a, i8 zeroext %b) { define i64 @test_llgtuc(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_llgtuc: ; CHECK-LABEL: test_llgtuc:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp ugt i8 %a, %b %cmp = icmp ugt i8 %a, %b
%conv3 = zext i1 %cmp to i64 %conv3 = zext i1 %cmp to i64
ret i64 %conv3 ret i64 %conv3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
Show All 40 Lines
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_llgtuc_store(i8 zeroext %a, i8 zeroext %b) { define void @test_llgtuc_store(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_llgtuc_store: ; CHECK-LABEL: test_llgtuc_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: ld r5, .LC0@toc@l(r5) ; CHECK-NEXT: ld r5, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: stb r3, 0(r5) ; CHECK-NEXT: stb r3, 0(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp ugt i8 %a, %b %cmp = icmp ugt i8 %a, %b
%conv3 = zext i1 %cmp to i8 %conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1 store i8 %conv3, i8* @glob, align 1
ret void ret void
} }
▲ Show 20 Lines • Show All 54 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/testComparesllgtui.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = local_unnamed_addr global i32 0, align 4 @glob = local_unnamed_addr global i32 0, align 4
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_llgtui(i32 zeroext %a, i32 zeroext %b) { define i64 @test_llgtui(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_llgtui: ; CHECK-LABEL: test_llgtui:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp ugt i32 %a, %b %cmp = icmp ugt i32 %a, %b
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
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; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_llgtui_store(i32 zeroext %a, i32 zeroext %b) { define void @test_llgtui_store(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_llgtui_store: ; CHECK-LABEL: test_llgtui_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: ld r5, .LC0@toc@l(r5) ; CHECK-NEXT: ld r5, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: stw r3, 0(r5) ; CHECK-NEXT: stw r3, 0(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp ugt i32 %a, %b %cmp = icmp ugt i32 %a, %b
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4 store i32 %conv, i32* @glob, align 4
ret void ret void
} }
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llvm/test/CodeGen/PowerPC/testComparesllgtus.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = local_unnamed_addr global i16 0, align 2 @glob = local_unnamed_addr global i16 0, align 2
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_llgtus(i16 zeroext %a, i16 zeroext %b) { define i64 @test_llgtus(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_llgtus: ; CHECK-LABEL: test_llgtus:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp ugt i16 %a, %b %cmp = icmp ugt i16 %a, %b
%conv3 = zext i1 %cmp to i64 %conv3 = zext i1 %cmp to i64
ret i64 %conv3 ret i64 %conv3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
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; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_llgtus_store(i16 zeroext %a, i16 zeroext %b) { define void @test_llgtus_store(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_llgtus_store: ; CHECK-LABEL: test_llgtus_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: ld r5, .LC0@toc@l(r5) ; CHECK-NEXT: ld r5, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: sth r3, 0(r5) ; CHECK-NEXT: sth r3, 0(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp ugt i16 %a, %b %cmp = icmp ugt i16 %a, %b
%conv3 = zext i1 %cmp to i16 %conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2 store i16 %conv3, i16* @glob, align 2
ret void ret void
} }
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llvm/test/CodeGen/PowerPC/testCompareslllesc.ll

Show All 12 Lines
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lllesc: ; CHECK-BE-LABEL: test_lllesc:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sub r3, r4, r3 ; CHECK-BE-NEXT: sub r3, r4, r3
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-BE-NEXT: srdi r3, r3, 63
; CHECK-BE-NEXT: xori r3, r3, 1 ; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_lllesc: ; CHECK-LE-LABEL: test_lllesc:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r4, r3 ; CHECK-LE-NEXT: sub r3, r4, r3
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-LE-NEXT: srdi r3, r3, 63
; CHECK-LE-NEXT: xori r3, r3, 1 ; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i8 %a, %b %cmp = icmp sle i8 %a, %b
%conv3 = zext i1 %cmp to i64 %conv3 = zext i1 %cmp to i64
ret i64 %conv3 ret i64 %conv3
} }
define i64 @test_lllesc_sext(i8 signext %a, i8 signext %b) { define i64 @test_lllesc_sext(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_lllesc_sext: ; CHECK-LABEL: test_lllesc_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lllesc_sext: ; CHECK-BE-LABEL: test_lllesc_sext:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sub r3, r4, r3 ; CHECK-BE-NEXT: sub r3, r4, r3
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-BE-NEXT: srdi r3, r3, 63
; CHECK-BE-NEXT: addi r3, r3, -1 ; CHECK-BE-NEXT: addi r3, r3, -1
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_lllesc_sext: ; CHECK-LE-LABEL: test_lllesc_sext:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r4, r3 ; CHECK-LE-NEXT: sub r3, r4, r3
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-LE-NEXT: srdi r3, r3, 63
; CHECK-LE-NEXT: addi r3, r3, -1 ; CHECK-LE-NEXT: addi r3, r3, -1
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i8 %a, %b %cmp = icmp sle i8 %a, %b
%conv3 = sext i1 %cmp to i64 %conv3 = sext i1 %cmp to i64
ret i64 %conv3 ret i64 %conv3
} }
define void @test_lllesc_store(i8 signext %a, i8 signext %b) { define void @test_lllesc_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_lllesc_store: ; CHECK-LABEL: test_lllesc_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stb r3, glob@toc@l(r5) ; CHECK-NEXT: stb r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lllesc_store: ; CHECK-BE-LABEL: test_lllesc_store:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sub r3, r4, r3 ; CHECK-BE-NEXT: sub r3, r4, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-BE-NEXT: srdi r3, r3, 63
; CHECK-BE-NEXT: xori r3, r3, 1 ; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: stb r3, 0(r4) ; CHECK-BE-NEXT: stb r3, 0(r4)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_lllesc_store: ; CHECK-LE-LABEL: test_lllesc_store:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r4, r3 ; CHECK-LE-NEXT: sub r3, r4, r3
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha ; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-LE-NEXT: srdi r3, r3, 63
; CHECK-LE-NEXT: xori r3, r3, 1 ; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: stb r3, glob@toc@l(r5) ; CHECK-LE-NEXT: stb r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i8 %a, %b %cmp = icmp sle i8 %a, %b
%conv3 = zext i1 %cmp to i8 %conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1 store i8 %conv3, i8* @glob, align 1
ret void ret void
} }
define void @test_lllesc_sext_store(i8 signext %a, i8 signext %b) { define void @test_lllesc_sext_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_lllesc_sext_store: ; CHECK-LABEL: test_lllesc_sext_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: stb r3, glob@toc@l(r5) ; CHECK-NEXT: stb r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lllesc_sext_store: ; CHECK-BE-LABEL: test_lllesc_sext_store:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sub r3, r4, r3 ; CHECK-BE-NEXT: sub r3, r4, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-BE-NEXT: srdi r3, r3, 63
; CHECK-BE-NEXT: addi r3, r3, -1 ; CHECK-BE-NEXT: addi r3, r3, -1
; CHECK-BE-NEXT: stb r3, 0(r4) ; CHECK-BE-NEXT: stb r3, 0(r4)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_lllesc_sext_store: ; CHECK-LE-LABEL: test_lllesc_sext_store:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r4, r3 ; CHECK-LE-NEXT: sub r3, r4, r3
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha ; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-LE-NEXT: srdi r3, r3, 63
; CHECK-LE-NEXT: addi r3, r3, -1 ; CHECK-LE-NEXT: addi r3, r3, -1
; CHECK-LE-NEXT: stb r3, glob@toc@l(r5) ; CHECK-LE-NEXT: stb r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i8 %a, %b %cmp = icmp sle i8 %a, %b
%conv3 = sext i1 %cmp to i8 %conv3 = sext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1 store i8 %conv3, i8* @glob, align 1
ret void ret void
} }

llvm/test/CodeGen/PowerPC/testCompareslllesi.ll

Show All 12 Lines
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lllesi: ; CHECK-BE-LABEL: test_lllesi:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sub r3, r4, r3 ; CHECK-BE-NEXT: sub r3, r4, r3
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-BE-NEXT: srdi r3, r3, 63
; CHECK-BE-NEXT: xori r3, r3, 1 ; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_lllesi: ; CHECK-LE-LABEL: test_lllesi:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r4, r3 ; CHECK-LE-NEXT: sub r3, r4, r3
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-LE-NEXT: srdi r3, r3, 63
; CHECK-LE-NEXT: xori r3, r3, 1 ; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i32 %a, %b %cmp = icmp sle i32 %a, %b
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
define i64 @test_lllesi_sext(i32 signext %a, i32 signext %b) { define i64 @test_lllesi_sext(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_lllesi_sext: ; CHECK-LABEL: test_lllesi_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lllesi_sext: ; CHECK-BE-LABEL: test_lllesi_sext:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sub r3, r4, r3 ; CHECK-BE-NEXT: sub r3, r4, r3
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-BE-NEXT: srdi r3, r3, 63
; CHECK-BE-NEXT: addi r3, r3, -1 ; CHECK-BE-NEXT: addi r3, r3, -1
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_lllesi_sext: ; CHECK-LE-LABEL: test_lllesi_sext:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r4, r3 ; CHECK-LE-NEXT: sub r3, r4, r3
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-LE-NEXT: srdi r3, r3, 63
; CHECK-LE-NEXT: addi r3, r3, -1 ; CHECK-LE-NEXT: addi r3, r3, -1
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i32 %a, %b %cmp = icmp sle i32 %a, %b
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
define void @test_lllesi_store(i32 signext %a, i32 signext %b) { define void @test_lllesi_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_lllesi_store: ; CHECK-LABEL: test_lllesi_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: stw r3, glob@toc@l(r5) ; CHECK-NEXT: stw r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lllesi_store: ; CHECK-BE-LABEL: test_lllesi_store:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sub r3, r4, r3 ; CHECK-BE-NEXT: sub r3, r4, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-BE-NEXT: srdi r3, r3, 63
; CHECK-BE-NEXT: xori r3, r3, 1 ; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: stw r3, 0(r4) ; CHECK-BE-NEXT: stw r3, 0(r4)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_lllesi_store: ; CHECK-LE-LABEL: test_lllesi_store:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r4, r3 ; CHECK-LE-NEXT: sub r3, r4, r3
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha ; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-LE-NEXT: srdi r3, r3, 63
; CHECK-LE-NEXT: xori r3, r3, 1 ; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: stw r3, glob@toc@l(r5) ; CHECK-LE-NEXT: stw r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i32 %a, %b %cmp = icmp sle i32 %a, %b
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4 store i32 %conv, i32* @glob, align 4
ret void ret void
} }
define void @test_lllesi_sext_store(i32 signext %a, i32 signext %b) { define void @test_lllesi_sext_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_lllesi_sext_store: ; CHECK-LABEL: test_lllesi_sext_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: stw r3, glob@toc@l(r5) ; CHECK-NEXT: stw r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lllesi_sext_store: ; CHECK-BE-LABEL: test_lllesi_sext_store:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sub r3, r4, r3 ; CHECK-BE-NEXT: sub r3, r4, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-BE-NEXT: srdi r3, r3, 63
; CHECK-BE-NEXT: addi r3, r3, -1 ; CHECK-BE-NEXT: addi r3, r3, -1
; CHECK-BE-NEXT: stw r3, 0(r4) ; CHECK-BE-NEXT: stw r3, 0(r4)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_lllesi_sext_store: ; CHECK-LE-LABEL: test_lllesi_sext_store:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r4, r3 ; CHECK-LE-NEXT: sub r3, r4, r3
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha ; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-LE-NEXT: srdi r3, r3, 63
; CHECK-LE-NEXT: addi r3, r3, -1 ; CHECK-LE-NEXT: addi r3, r3, -1
; CHECK-LE-NEXT: stw r3, glob@toc@l(r5) ; CHECK-LE-NEXT: stw r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i32 %a, %b %cmp = icmp sle i32 %a, %b
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob, align 4 store i32 %sub, i32* @glob, align 4
ret void ret void
} }

llvm/test/CodeGen/PowerPC/testCompareslllesll.ll

Show All 13 Lines
; CHECK-NEXT: sradi r5, r4, 63 ; CHECK-NEXT: sradi r5, r4, 63
; CHECK-NEXT: rldicl r6, r3, 1, 63 ; CHECK-NEXT: rldicl r6, r3, 1, 63
; CHECK-NEXT: subfc r3, r3, r4 ; CHECK-NEXT: subfc r3, r3, r4
; CHECK-NEXT: adde r3, r5, r6 ; CHECK-NEXT: adde r3, r5, r6
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lllesll: ; CHECK-BE-LABEL: test_lllesll:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r5, r4, 63 ; CHECK-BE-NEXT: sradi r5, r4, 63
; CHECK-BE-NEXT: rldicl r6, r3, 1, 63 ; CHECK-BE-NEXT: srdi r6, r3, 63
; CHECK-BE-NEXT: subc r3, r4, r3 ; CHECK-BE-NEXT: subc r3, r4, r3
; CHECK-BE-NEXT: adde r3, r5, r6 ; CHECK-BE-NEXT: adde r3, r5, r6
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_lllesll: ; CHECK-LE-LABEL: test_lllesll:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r5, r4, 63 ; CHECK-LE-NEXT: sradi r5, r4, 63
; CHECK-LE-NEXT: rldicl r6, r3, 1, 63 ; CHECK-LE-NEXT: srdi r6, r3, 63
; CHECK-LE-NEXT: subc r3, r4, r3 ; CHECK-LE-NEXT: subc r3, r4, r3
; CHECK-LE-NEXT: adde r3, r5, r6 ; CHECK-LE-NEXT: adde r3, r5, r6
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i64 %a, %b %cmp = icmp sle i64 %a, %b
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_lllesll_sext(i64 %a, i64 %b) { define i64 @test_lllesll_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_lllesll_sext: ; CHECK-LABEL: test_lllesll_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r5, r4, 63 ; CHECK-NEXT: sradi r5, r4, 63
; CHECK-NEXT: rldicl r6, r3, 1, 63 ; CHECK-NEXT: rldicl r6, r3, 1, 63
; CHECK-NEXT: subfc r3, r3, r4 ; CHECK-NEXT: subfc r3, r3, r4
; CHECK-NEXT: adde r3, r5, r6 ; CHECK-NEXT: adde r3, r5, r6
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lllesll_sext: ; CHECK-BE-LABEL: test_lllesll_sext:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r5, r4, 63 ; CHECK-BE-NEXT: sradi r5, r4, 63
; CHECK-BE-NEXT: rldicl r6, r3, 1, 63 ; CHECK-BE-NEXT: srdi r6, r3, 63
; CHECK-BE-NEXT: subc r3, r4, r3 ; CHECK-BE-NEXT: subc r3, r4, r3
; CHECK-BE-NEXT: adde r3, r5, r6 ; CHECK-BE-NEXT: adde r3, r5, r6
; CHECK-BE-NEXT: neg r3, r3 ; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_lllesll_sext: ; CHECK-LE-LABEL: test_lllesll_sext:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r5, r4, 63 ; CHECK-LE-NEXT: sradi r5, r4, 63
; CHECK-LE-NEXT: rldicl r6, r3, 1, 63 ; CHECK-LE-NEXT: srdi r6, r3, 63
; CHECK-LE-NEXT: subc r3, r4, r3 ; CHECK-LE-NEXT: subc r3, r4, r3
; CHECK-LE-NEXT: adde r3, r5, r6 ; CHECK-LE-NEXT: adde r3, r5, r6
; CHECK-LE-NEXT: neg r3, r3 ; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i64 %a, %b %cmp = icmp sle i64 %a, %b
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_lllesll_z(i64 %a) { define i64 @test_lllesll_z(i64 %a) {
; CHECK-LABEL: test_lllesll_z: ; CHECK-LABEL: test_lllesll_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi r4, r3, -1 ; CHECK-NEXT: addi r4, r3, -1
; CHECK-NEXT: or r3, r4, r3 ; CHECK-NEXT: or r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lllesll_z: ; CHECK-BE-LABEL: test_lllesll_z:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addi r4, r3, -1 ; CHECK-BE-NEXT: addi r4, r3, -1
; CHECK-BE-NEXT: or r3, r4, r3 ; CHECK-BE-NEXT: or r3, r4, r3
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-BE-NEXT: srdi r3, r3, 63
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_lllesll_z: ; CHECK-LE-LABEL: test_lllesll_z:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: addi r4, r3, -1 ; CHECK-LE-NEXT: addi r4, r3, -1
; CHECK-LE-NEXT: or r3, r4, r3 ; CHECK-LE-NEXT: or r3, r4, r3
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-LE-NEXT: srdi r3, r3, 63
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp slt i64 %a, 1 %cmp = icmp slt i64 %a, 1
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
Show All 35 Lines
; CHECK-NEXT: std r3, glob@toc@l(r5) ; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lllesll_store: ; CHECK-BE-LABEL: test_lllesll_store:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sradi r6, r4, 63 ; CHECK-BE-NEXT: sradi r6, r4, 63
; CHECK-BE-NEXT: ld r5, .LC0@toc@l(r5) ; CHECK-BE-NEXT: ld r5, .LC0@toc@l(r5)
; CHECK-BE-NEXT: subc r4, r4, r3 ; CHECK-BE-NEXT: subc r4, r4, r3
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-BE-NEXT: srdi r3, r3, 63
; CHECK-BE-NEXT: adde r3, r6, r3 ; CHECK-BE-NEXT: adde r3, r6, r3
; CHECK-BE-NEXT: std r3, 0(r5) ; CHECK-BE-NEXT: std r3, 0(r5)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_lllesll_store: ; CHECK-LE-LABEL: test_lllesll_store:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r6, r4, 63 ; CHECK-LE-NEXT: sradi r6, r4, 63
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha ; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: subc r4, r4, r3 ; CHECK-LE-NEXT: subc r4, r4, r3
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-LE-NEXT: srdi r3, r3, 63
; CHECK-LE-NEXT: adde r3, r6, r3 ; CHECK-LE-NEXT: adde r3, r6, r3
; CHECK-LE-NEXT: std r3, glob@toc@l(r5) ; CHECK-LE-NEXT: std r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i64 %a, %b %cmp = icmp sle i64 %a, %b
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
Show All 11 Lines
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: std r3, glob@toc@l(r5) ; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lllesll_sext_store: ; CHECK-BE-LABEL: test_lllesll_sext_store:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r6, r4, 63 ; CHECK-BE-NEXT: sradi r6, r4, 63
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: subc r4, r4, r3 ; CHECK-BE-NEXT: subc r4, r4, r3
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-BE-NEXT: srdi r3, r3, 63
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: adde r3, r6, r3 ; CHECK-BE-NEXT: adde r3, r6, r3
; CHECK-BE-NEXT: neg r3, r3 ; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: std r3, 0(r4) ; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_lllesll_sext_store: ; CHECK-LE-LABEL: test_lllesll_sext_store:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r6, r4, 63 ; CHECK-LE-NEXT: sradi r6, r4, 63
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha ; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: subc r4, r4, r3 ; CHECK-LE-NEXT: subc r4, r4, r3
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-LE-NEXT: srdi r3, r3, 63
; CHECK-LE-NEXT: adde r3, r6, r3 ; CHECK-LE-NEXT: adde r3, r6, r3
; CHECK-LE-NEXT: neg r3, r3 ; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: std r3, glob@toc@l(r5) ; CHECK-LE-NEXT: std r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i64 %a, %b %cmp = icmp sle i64 %a, %b
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
Show All 11 Lines
; CHECK-NEXT: std r3, glob@toc@l(r4) ; CHECK-NEXT: std r3, glob@toc@l(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lllesll_z_store: ; CHECK-BE-LABEL: test_lllesll_z_store:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: addi r5, r3, -1 ; CHECK-BE-NEXT: addi r5, r3, -1
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4) ; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: or r3, r5, r3 ; CHECK-BE-NEXT: or r3, r5, r3
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-BE-NEXT: srdi r3, r3, 63
; CHECK-BE-NEXT: std r3, 0(r4) ; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_lllesll_z_store: ; CHECK-LE-LABEL: test_lllesll_z_store:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: addi r5, r3, -1 ; CHECK-LE-NEXT: addi r5, r3, -1
; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha ; CHECK-LE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-LE-NEXT: or r3, r5, r3 ; CHECK-LE-NEXT: or r3, r5, r3
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-LE-NEXT: srdi r3, r3, 63
; CHECK-LE-NEXT: std r3, glob@toc@l(r4) ; CHECK-LE-NEXT: std r3, glob@toc@l(r4)
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp slt i64 %a, 1 %cmp = icmp slt i64 %a, 1
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }
Show All 35 Lines

llvm/test/CodeGen/PowerPC/testComparesllless.ll

Show All 12 Lines
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llless: ; CHECK-BE-LABEL: test_llless:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sub r3, r4, r3 ; CHECK-BE-NEXT: sub r3, r4, r3
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-BE-NEXT: srdi r3, r3, 63
; CHECK-BE-NEXT: xori r3, r3, 1 ; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_llless: ; CHECK-LE-LABEL: test_llless:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r4, r3 ; CHECK-LE-NEXT: sub r3, r4, r3
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-LE-NEXT: srdi r3, r3, 63
; CHECK-LE-NEXT: xori r3, r3, 1 ; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i16 %a, %b %cmp = icmp sle i16 %a, %b
%conv3 = zext i1 %cmp to i64 %conv3 = zext i1 %cmp to i64
ret i64 %conv3 ret i64 %conv3
} }
define i64 @test_llless_sext(i16 signext %a, i16 signext %b) { define i64 @test_llless_sext(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_llless_sext: ; CHECK-LABEL: test_llless_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llless_sext: ; CHECK-BE-LABEL: test_llless_sext:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sub r3, r4, r3 ; CHECK-BE-NEXT: sub r3, r4, r3
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-BE-NEXT: srdi r3, r3, 63
; CHECK-BE-NEXT: addi r3, r3, -1 ; CHECK-BE-NEXT: addi r3, r3, -1
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_llless_sext: ; CHECK-LE-LABEL: test_llless_sext:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r4, r3 ; CHECK-LE-NEXT: sub r3, r4, r3
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-LE-NEXT: srdi r3, r3, 63
; CHECK-LE-NEXT: addi r3, r3, -1 ; CHECK-LE-NEXT: addi r3, r3, -1
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i16 %a, %b %cmp = icmp sle i16 %a, %b
%conv3 = sext i1 %cmp to i64 %conv3 = sext i1 %cmp to i64
ret i64 %conv3 ret i64 %conv3
} }
define void @test_llless_store(i16 signext %a, i16 signext %b) { define void @test_llless_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_llless_store: ; CHECK-LABEL: test_llless_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: sth r3, glob@toc@l(r5) ; CHECK-NEXT: sth r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llless_store: ; CHECK-BE-LABEL: test_llless_store:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sub r3, r4, r3 ; CHECK-BE-NEXT: sub r3, r4, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-BE-NEXT: srdi r3, r3, 63
; CHECK-BE-NEXT: xori r3, r3, 1 ; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: sth r3, 0(r4) ; CHECK-BE-NEXT: sth r3, 0(r4)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_llless_store: ; CHECK-LE-LABEL: test_llless_store:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r4, r3 ; CHECK-LE-NEXT: sub r3, r4, r3
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha ; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-LE-NEXT: srdi r3, r3, 63
; CHECK-LE-NEXT: xori r3, r3, 1 ; CHECK-LE-NEXT: xori r3, r3, 1
; CHECK-LE-NEXT: sth r3, glob@toc@l(r5) ; CHECK-LE-NEXT: sth r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i16 %a, %b %cmp = icmp sle i16 %a, %b
%conv3 = zext i1 %cmp to i16 %conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2 store i16 %conv3, i16* @glob, align 2
ret void ret void
} }
define void @test_llless_sext_store(i16 signext %a, i16 signext %b) { define void @test_llless_sext_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_llless_sext_store: ; CHECK-LABEL: test_llless_sext_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: addis r5, r2, glob@toc@ha ; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: sth r3, glob@toc@l(r5) ; CHECK-NEXT: sth r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llless_sext_store: ; CHECK-BE-LABEL: test_llless_sext_store:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sub r3, r4, r3 ; CHECK-BE-NEXT: sub r3, r4, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-BE-NEXT: srdi r3, r3, 63
; CHECK-BE-NEXT: addi r3, r3, -1 ; CHECK-BE-NEXT: addi r3, r3, -1
; CHECK-BE-NEXT: sth r3, 0(r4) ; CHECK-BE-NEXT: sth r3, 0(r4)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_llless_sext_store: ; CHECK-LE-LABEL: test_llless_sext_store:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sub r3, r4, r3 ; CHECK-LE-NEXT: sub r3, r4, r3
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha ; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-LE-NEXT: srdi r3, r3, 63
; CHECK-LE-NEXT: addi r3, r3, -1 ; CHECK-LE-NEXT: addi r3, r3, -1
; CHECK-LE-NEXT: sth r3, glob@toc@l(r5) ; CHECK-LE-NEXT: sth r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i16 %a, %b %cmp = icmp sle i16 %a, %b
%conv3 = sext i1 %cmp to i16 %conv3 = sext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2 store i16 %conv3, i16* @glob, align 2
ret void ret void
} }

llvm/test/CodeGen/PowerPC/testComparesllleuc.ll

Show All 10 Lines
@glob = local_unnamed_addr global i8 0, align 1 @glob = local_unnamed_addr global i8 0, align 1
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_llleuc(i8 zeroext %a, i8 zeroext %b) { define i64 @test_llleuc(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_llleuc: ; CHECK-LABEL: test_llleuc:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: not r3, r3 ; CHECK-NEXT: not r3, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp ule i8 %a, %b %cmp = icmp ule i8 %a, %b
%conv3 = zext i1 %cmp to i64 %conv3 = zext i1 %cmp to i64
ret i64 %conv3 ret i64 %conv3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_llleuc_sext(i8 zeroext %a, i8 zeroext %b) { define i64 @test_llleuc_sext(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_llleuc_sext: ; CHECK-LABEL: test_llleuc_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp ule i8 %a, %b %cmp = icmp ule i8 %a, %b
%conv3 = sext i1 %cmp to i64 %conv3 = sext i1 %cmp to i64
ret i64 %conv3 ret i64 %conv3
} }
Show All 27 Lines
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_llleuc_store(i8 zeroext %a, i8 zeroext %b) { define void @test_llleuc_store(i8 zeroext %a, i8 zeroext %b) {
; BE-LABEL: test_llleuc_store: ; BE-LABEL: test_llleuc_store:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha ; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: sub r3, r4, r3 ; BE-NEXT: sub r3, r4, r3
; BE-NEXT: ld r4, .LC0@toc@l(r5) ; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: not r3, r3 ; BE-NEXT: not r3, r3
; BE-NEXT: rldicl r3, r3, 1, 63 ; BE-NEXT: srdi r3, r3, 63
; BE-NEXT: stb r3, 0(r4) ; BE-NEXT: stb r3, 0(r4)
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; LE-LABEL: test_llleuc_store: ; LE-LABEL: test_llleuc_store:
; LE: # %bb.0: # %entry ; LE: # %bb.0: # %entry
; LE-NEXT: sub r3, r4, r3 ; LE-NEXT: sub r3, r4, r3
; LE-NEXT: addis r5, r2, glob@toc@ha ; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: not r3, r3 ; LE-NEXT: not r3, r3
; LE-NEXT: rldicl r3, r3, 1, 63 ; LE-NEXT: srdi r3, r3, 63
; LE-NEXT: stb r3, glob@toc@l(r5) ; LE-NEXT: stb r3, glob@toc@l(r5)
; LE-NEXT: blr ; LE-NEXT: blr
entry: entry:
%cmp = icmp ule i8 %a, %b %cmp = icmp ule i8 %a, %b
%conv3 = zext i1 %cmp to i8 %conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob store i8 %conv3, i8* @glob
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_llleuc_sext_store(i8 zeroext %a, i8 zeroext %b) { define void @test_llleuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
; BE-LABEL: test_llleuc_sext_store: ; BE-LABEL: test_llleuc_sext_store:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha ; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: sub r3, r4, r3 ; BE-NEXT: sub r3, r4, r3
; BE-NEXT: ld r4, .LC0@toc@l(r5) ; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: rldicl r3, r3, 1, 63 ; BE-NEXT: srdi r3, r3, 63
; BE-NEXT: addi r3, r3, -1 ; BE-NEXT: addi r3, r3, -1
; BE-NEXT: stb r3, 0(r4) ; BE-NEXT: stb r3, 0(r4)
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; LE-LABEL: test_llleuc_sext_store: ; LE-LABEL: test_llleuc_sext_store:
; LE: # %bb.0: # %entry ; LE: # %bb.0: # %entry
; LE-NEXT: sub r3, r4, r3 ; LE-NEXT: sub r3, r4, r3
; LE-NEXT: addis r5, r2, glob@toc@ha ; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: rldicl r3, r3, 1, 63 ; LE-NEXT: srdi r3, r3, 63
; LE-NEXT: addi r3, r3, -1 ; LE-NEXT: addi r3, r3, -1
; LE-NEXT: stb r3, glob@toc@l(r5) ; LE-NEXT: stb r3, glob@toc@l(r5)
; LE-NEXT: blr ; LE-NEXT: blr
entry: entry:
%cmp = icmp ule i8 %a, %b %cmp = icmp ule i8 %a, %b
%conv3 = sext i1 %cmp to i8 %conv3 = sext i1 %cmp to i8
store i8 %conv3, i8* @glob store i8 %conv3, i8* @glob
ret void ret void
▲ Show 20 Lines • Show All 53 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/testComparesllleui.ll

Show All 10 Lines
@glob = local_unnamed_addr global i32 0, align 4 @glob = local_unnamed_addr global i32 0, align 4
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_llleui(i32 zeroext %a, i32 zeroext %b) { define i64 @test_llleui(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_llleui: ; CHECK-LABEL: test_llleui:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: not r3, r3 ; CHECK-NEXT: not r3, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp ule i32 %a, %b %cmp = icmp ule i32 %a, %b
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_llleui_sext(i32 zeroext %a, i32 zeroext %b) { define i64 @test_llleui_sext(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_llleui_sext: ; CHECK-LABEL: test_llleui_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp ule i32 %a, %b %cmp = icmp ule i32 %a, %b
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
Show All 27 Lines
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_llleui_store(i32 zeroext %a, i32 zeroext %b) { define void @test_llleui_store(i32 zeroext %a, i32 zeroext %b) {
; BE-LABEL: test_llleui_store: ; BE-LABEL: test_llleui_store:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha ; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: sub r3, r4, r3 ; BE-NEXT: sub r3, r4, r3
; BE-NEXT: ld r4, .LC0@toc@l(r5) ; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: not r3, r3 ; BE-NEXT: not r3, r3
; BE-NEXT: rldicl r3, r3, 1, 63 ; BE-NEXT: srdi r3, r3, 63
; BE-NEXT: stw r3, 0(r4) ; BE-NEXT: stw r3, 0(r4)
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; LE-LABEL: test_llleui_store: ; LE-LABEL: test_llleui_store:
; LE: # %bb.0: # %entry ; LE: # %bb.0: # %entry
; LE-NEXT: sub r3, r4, r3 ; LE-NEXT: sub r3, r4, r3
; LE-NEXT: addis r5, r2, glob@toc@ha ; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: not r3, r3 ; LE-NEXT: not r3, r3
; LE-NEXT: rldicl r3, r3, 1, 63 ; LE-NEXT: srdi r3, r3, 63
; LE-NEXT: stw r3, glob@toc@l(r5) ; LE-NEXT: stw r3, glob@toc@l(r5)
; LE-NEXT: blr ; LE-NEXT: blr
entry: entry:
%cmp = icmp ule i32 %a, %b %cmp = icmp ule i32 %a, %b
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob store i32 %conv, i32* @glob
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_llleui_sext_store(i32 zeroext %a, i32 zeroext %b) { define void @test_llleui_sext_store(i32 zeroext %a, i32 zeroext %b) {
; BE-LABEL: test_llleui_sext_store: ; BE-LABEL: test_llleui_sext_store:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha ; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: sub r3, r4, r3 ; BE-NEXT: sub r3, r4, r3
; BE-NEXT: ld r4, .LC0@toc@l(r5) ; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: rldicl r3, r3, 1, 63 ; BE-NEXT: srdi r3, r3, 63
; BE-NEXT: addi r3, r3, -1 ; BE-NEXT: addi r3, r3, -1
; BE-NEXT: stw r3, 0(r4) ; BE-NEXT: stw r3, 0(r4)
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; LE-LABEL: test_llleui_sext_store: ; LE-LABEL: test_llleui_sext_store:
; LE: # %bb.0: # %entry ; LE: # %bb.0: # %entry
; LE-NEXT: sub r3, r4, r3 ; LE-NEXT: sub r3, r4, r3
; LE-NEXT: addis r5, r2, glob@toc@ha ; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: rldicl r3, r3, 1, 63 ; LE-NEXT: srdi r3, r3, 63
; LE-NEXT: addi r3, r3, -1 ; LE-NEXT: addi r3, r3, -1
; LE-NEXT: stw r3, glob@toc@l(r5) ; LE-NEXT: stw r3, glob@toc@l(r5)
; LE-NEXT: blr ; LE-NEXT: blr
entry: entry:
%cmp = icmp ule i32 %a, %b %cmp = icmp ule i32 %a, %b
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
store i32 %sub, i32* @glob store i32 %sub, i32* @glob
ret void ret void
▲ Show 20 Lines • Show All 54 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/testComparesllleull.ll

Show All 37 Linesentry:
ret i64 %conv1 ret i64 %conv1
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_llleull_z(i64 %a) { define i64 @test_llleull_z(i64 %a) {
; CHECK-LABEL: test_llleull_z: ; CHECK-LABEL: test_llleull_z:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzd r3, r3 ; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63 ; CHECK-NEXT: extrdi r3, r3, 1, 57
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp ule i64 %a, 0 %cmp = icmp ule i64 %a, 0
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Lines
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_llleull_z_store(i64 %a) { define void @test_llleull_z_store(i64 %a) {
; BE-LABEL: test_llleull_z_store: ; BE-LABEL: test_llleull_z_store:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
; BE-NEXT: addis r4, r2, .LC0@toc@ha ; BE-NEXT: addis r4, r2, .LC0@toc@ha
; BE-NEXT: cntlzd r3, r3 ; BE-NEXT: cntlzd r3, r3
; BE-NEXT: ld r4, .LC0@toc@l(r4) ; BE-NEXT: ld r4, .LC0@toc@l(r4)
; BE-NEXT: rldicl r3, r3, 58, 63 ; BE-NEXT: extrdi r3, r3, 1, 57
; BE-NEXT: std r3, 0(r4) ; BE-NEXT: std r3, 0(r4)
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; LE-LABEL: test_llleull_z_store: ; LE-LABEL: test_llleull_z_store:
; LE: # %bb.0: # %entry ; LE: # %bb.0: # %entry
; LE-NEXT: cntlzd r3, r3 ; LE-NEXT: cntlzd r3, r3
; LE-NEXT: addis r4, r2, glob@toc@ha ; LE-NEXT: addis r4, r2, glob@toc@ha
; LE-NEXT: rldicl r3, r3, 58, 63 ; LE-NEXT: extrdi r3, r3, 1, 57
; LE-NEXT: std r3, glob@toc@l(r4) ; LE-NEXT: std r3, glob@toc@l(r4)
; LE-NEXT: blr ; LE-NEXT: blr
entry: entry:
%cmp = icmp ule i64 %a, 0 %cmp = icmp ule i64 %a, 0
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob store i64 %conv1, i64* @glob
ret void ret void
} }
Show All 26 Lines

llvm/test/CodeGen/PowerPC/testComparesllleus.ll

Show All 10 Lines
@glob = local_unnamed_addr global i16 0, align 2 @glob = local_unnamed_addr global i16 0, align 2
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_llleus(i16 zeroext %a, i16 zeroext %b) { define i64 @test_llleus(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_llleus: ; CHECK-LABEL: test_llleus:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: not r3, r3 ; CHECK-NEXT: not r3, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp ule i16 %a, %b %cmp = icmp ule i16 %a, %b
%conv3 = zext i1 %cmp to i64 %conv3 = zext i1 %cmp to i64
ret i64 %conv3 ret i64 %conv3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_llleus_sext(i16 zeroext %a, i16 zeroext %b) { define i64 @test_llleus_sext(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_llleus_sext: ; CHECK-LABEL: test_llleus_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: addi r3, r3, -1 ; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp ule i16 %a, %b %cmp = icmp ule i16 %a, %b
%conv3 = sext i1 %cmp to i64 %conv3 = sext i1 %cmp to i64
ret i64 %conv3 ret i64 %conv3
} }
Show All 27 Lines
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_llleus_store(i16 zeroext %a, i16 zeroext %b) { define void @test_llleus_store(i16 zeroext %a, i16 zeroext %b) {
; BE-LABEL: test_llleus_store: ; BE-LABEL: test_llleus_store:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha ; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: sub r3, r4, r3 ; BE-NEXT: sub r3, r4, r3
; BE-NEXT: ld r4, .LC0@toc@l(r5) ; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: not r3, r3 ; BE-NEXT: not r3, r3
; BE-NEXT: rldicl r3, r3, 1, 63 ; BE-NEXT: srdi r3, r3, 63
; BE-NEXT: sth r3, 0(r4) ; BE-NEXT: sth r3, 0(r4)
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; LE-LABEL: test_llleus_store: ; LE-LABEL: test_llleus_store:
; LE: # %bb.0: # %entry ; LE: # %bb.0: # %entry
; LE-NEXT: sub r3, r4, r3 ; LE-NEXT: sub r3, r4, r3
; LE-NEXT: addis r5, r2, glob@toc@ha ; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: not r3, r3 ; LE-NEXT: not r3, r3
; LE-NEXT: rldicl r3, r3, 1, 63 ; LE-NEXT: srdi r3, r3, 63
; LE-NEXT: sth r3, glob@toc@l(r5) ; LE-NEXT: sth r3, glob@toc@l(r5)
; LE-NEXT: blr ; LE-NEXT: blr
entry: entry:
%cmp = icmp ule i16 %a, %b %cmp = icmp ule i16 %a, %b
%conv3 = zext i1 %cmp to i16 %conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob store i16 %conv3, i16* @glob
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_llleus_sext_store(i16 zeroext %a, i16 zeroext %b) { define void @test_llleus_sext_store(i16 zeroext %a, i16 zeroext %b) {
; BE-LABEL: test_llleus_sext_store: ; BE-LABEL: test_llleus_sext_store:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha ; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: sub r3, r4, r3 ; BE-NEXT: sub r3, r4, r3
; BE-NEXT: ld r4, .LC0@toc@l(r5) ; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: rldicl r3, r3, 1, 63 ; BE-NEXT: srdi r3, r3, 63
; BE-NEXT: addi r3, r3, -1 ; BE-NEXT: addi r3, r3, -1
; BE-NEXT: sth r3, 0(r4) ; BE-NEXT: sth r3, 0(r4)
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; LE-LABEL: test_llleus_sext_store: ; LE-LABEL: test_llleus_sext_store:
; LE: # %bb.0: # %entry ; LE: # %bb.0: # %entry
; LE-NEXT: sub r3, r4, r3 ; LE-NEXT: sub r3, r4, r3
; LE-NEXT: addis r5, r2, glob@toc@ha ; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: rldicl r3, r3, 1, 63 ; LE-NEXT: srdi r3, r3, 63
; LE-NEXT: addi r3, r3, -1 ; LE-NEXT: addi r3, r3, -1
; LE-NEXT: sth r3, glob@toc@l(r5) ; LE-NEXT: sth r3, glob@toc@l(r5)
; LE-NEXT: blr ; LE-NEXT: blr
entry: entry:
%cmp = icmp ule i16 %a, %b %cmp = icmp ule i16 %a, %b
%conv3 = sext i1 %cmp to i16 %conv3 = sext i1 %cmp to i16
store i16 %conv3, i16* @glob store i16 %conv3, i16* @glob
ret void ret void
▲ Show 20 Lines • Show All 54 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/testComparesllltsll.ll

Show All 9 Lines
@glob = local_unnamed_addr global i64 0, align 8 @glob = local_unnamed_addr global i64 0, align 8
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_llltsll(i64 %a, i64 %b) { define i64 @test_llltsll(i64 %a, i64 %b) {
; CHECK-LABEL: test_llltsll: ; CHECK-LABEL: test_llltsll:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r5, r3, 63 ; CHECK-NEXT: sradi r5, r3, 63
; CHECK-NEXT: rldicl r6, r4, 1, 63 ; CHECK-NEXT: srdi r6, r4, 63
; CHECK-NEXT: subc r3, r3, r4 ; CHECK-NEXT: subc r3, r3, r4
; CHECK-NEXT: adde r3, r6, r5 ; CHECK-NEXT: adde r3, r6, r5
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp slt i64 %a, %b %cmp = icmp slt i64 %a, %b
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_llltsll_sext(i64 %a, i64 %b) { define i64 @test_llltsll_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_llltsll_sext: ; CHECK-LABEL: test_llltsll_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r5, r3, 63 ; CHECK-NEXT: sradi r5, r3, 63
; CHECK-NEXT: rldicl r6, r4, 1, 63 ; CHECK-NEXT: srdi r6, r4, 63
; CHECK-NEXT: subc r3, r3, r4 ; CHECK-NEXT: subc r3, r3, r4
; CHECK-NEXT: adde r3, r6, r5 ; CHECK-NEXT: adde r3, r6, r5
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp slt i64 %a, %b %cmp = icmp slt i64 %a, %b
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
Show All 14 Lines
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_llltsll_store(i64 %a, i64 %b) { define void @test_llltsll_store(i64 %a, i64 %b) {
; BE-LABEL: test_llltsll_store: ; BE-LABEL: test_llltsll_store:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
; BE-NEXT: sradi r6, r3, 63 ; BE-NEXT: sradi r6, r3, 63
; BE-NEXT: addis r5, r2, .LC0@toc@ha ; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: subc r3, r3, r4 ; BE-NEXT: subc r3, r3, r4
; BE-NEXT: rldicl r3, r4, 1, 63 ; BE-NEXT: srdi r3, r4, 63
; BE-NEXT: ld r4, .LC0@toc@l(r5) ; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: adde r3, r3, r6 ; BE-NEXT: adde r3, r3, r6
; BE-NEXT: xori r3, r3, 1 ; BE-NEXT: xori r3, r3, 1
; BE-NEXT: std r3, 0(r4) ; BE-NEXT: std r3, 0(r4)
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; LE-LABEL: test_llltsll_store: ; LE-LABEL: test_llltsll_store:
; LE: # %bb.0: # %entry ; LE: # %bb.0: # %entry
; LE-NEXT: sradi r6, r3, 63 ; LE-NEXT: sradi r6, r3, 63
; LE-NEXT: addis r5, r2, glob@toc@ha ; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: subc r3, r3, r4 ; LE-NEXT: subc r3, r3, r4
; LE-NEXT: rldicl r3, r4, 1, 63 ; LE-NEXT: srdi r3, r4, 63
; LE-NEXT: adde r3, r3, r6 ; LE-NEXT: adde r3, r3, r6
; LE-NEXT: xori r3, r3, 1 ; LE-NEXT: xori r3, r3, 1
; LE-NEXT: std r3, glob@toc@l(r5) ; LE-NEXT: std r3, glob@toc@l(r5)
; LE-NEXT: blr ; LE-NEXT: blr
; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r4, r3 ; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r4, r3
entry: entry:
%cmp = icmp slt i64 %a, %b %cmp = icmp slt i64 %a, %b
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_llltsll_sext_store(i64 %a, i64 %b) { define void @test_llltsll_sext_store(i64 %a, i64 %b) {
; BE-LABEL: test_llltsll_sext_store: ; BE-LABEL: test_llltsll_sext_store:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
; BE-NEXT: sradi r6, r3, 63 ; BE-NEXT: sradi r6, r3, 63
; BE-NEXT: addis r5, r2, .LC0@toc@ha ; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: subc r3, r3, r4 ; BE-NEXT: subc r3, r3, r4
; BE-NEXT: rldicl r3, r4, 1, 63 ; BE-NEXT: srdi r3, r4, 63
; BE-NEXT: ld r4, .LC0@toc@l(r5) ; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: adde r3, r3, r6 ; BE-NEXT: adde r3, r3, r6
; BE-NEXT: xori r3, r3, 1 ; BE-NEXT: xori r3, r3, 1
; BE-NEXT: neg r3, r3 ; BE-NEXT: neg r3, r3
; BE-NEXT: std r3, 0(r4) ; BE-NEXT: std r3, 0(r4)
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; LE-LABEL: test_llltsll_sext_store: ; LE-LABEL: test_llltsll_sext_store:
; LE: # %bb.0: # %entry ; LE: # %bb.0: # %entry
; LE-NEXT: sradi r6, r3, 63 ; LE-NEXT: sradi r6, r3, 63
; LE-NEXT: addis r5, r2, glob@toc@ha ; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: subc r3, r3, r4 ; LE-NEXT: subc r3, r3, r4
; LE-NEXT: rldicl r3, r4, 1, 63 ; LE-NEXT: srdi r3, r4, 63
; LE-NEXT: adde r3, r3, r6 ; LE-NEXT: adde r3, r3, r6
; LE-NEXT: xori r3, r3, 1 ; LE-NEXT: xori r3, r3, 1
; LE-NEXT: neg r3, r3 ; LE-NEXT: neg r3, r3
; LE-NEXT: std r3, glob@toc@l(r5) ; LE-NEXT: std r3, glob@toc@l(r5)
; LE-NEXT: blr ; LE-NEXT: blr
; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r4, r3 ; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r4, r3
entry: entry:
%cmp = icmp slt i64 %a, %b %cmp = icmp slt i64 %a, %b
Show All 27 Lines

llvm/test/CodeGen/PowerPC/testComparesllltuc.ll

Show All 9 Lines
@glob = local_unnamed_addr global i8 0, align 1 @glob = local_unnamed_addr global i8 0, align 1
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_llltuc(i8 zeroext %a, i8 zeroext %b) { define i64 @test_llltuc(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_llltuc: ; CHECK-LABEL: test_llltuc:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp ult i8 %a, %b %cmp = icmp ult i8 %a, %b
%conv3 = zext i1 %cmp to i64 %conv3 = zext i1 %cmp to i64
ret i64 %conv3 ret i64 %conv3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
Show All 11 Lines
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_llltuc_store(i8 zeroext %a, i8 zeroext %b) { define void @test_llltuc_store(i8 zeroext %a, i8 zeroext %b) {
; BE-LABEL: test_llltuc_store: ; BE-LABEL: test_llltuc_store:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha ; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: sub r3, r3, r4 ; BE-NEXT: sub r3, r3, r4
; BE-NEXT: ld r5, .LC0@toc@l(r5) ; BE-NEXT: ld r5, .LC0@toc@l(r5)
; BE-NEXT: rldicl r3, r3, 1, 63 ; BE-NEXT: srdi r3, r3, 63
; BE-NEXT: stb r3, 0(r5) ; BE-NEXT: stb r3, 0(r5)
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; LE-LABEL: test_llltuc_store: ; LE-LABEL: test_llltuc_store:
; LE: # %bb.0: # %entry ; LE: # %bb.0: # %entry
; LE-NEXT: sub r3, r3, r4 ; LE-NEXT: sub r3, r3, r4
; LE-NEXT: addis r5, r2, glob@toc@ha ; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: rldicl r3, r3, 1, 63 ; LE-NEXT: srdi r3, r3, 63
; LE-NEXT: stb r3, glob@toc@l(r5) ; LE-NEXT: stb r3, glob@toc@l(r5)
; LE-NEXT: blr ; LE-NEXT: blr
entry: entry:
%cmp = icmp ult i8 %a, %b %cmp = icmp ult i8 %a, %b
%conv3 = zext i1 %cmp to i8 %conv3 = zext i1 %cmp to i8
store i8 %conv3, i8* @glob, align 1 store i8 %conv3, i8* @glob, align 1
ret void ret void
} }
Show All 25 Lines

llvm/test/CodeGen/PowerPC/testComparesllltui.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc --relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc --relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = local_unnamed_addr global i32 0, align 4 @glob = local_unnamed_addr global i32 0, align 4
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_llltui(i32 zeroext %a, i32 zeroext %b) { define i64 @test_llltui(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_llltui: ; CHECK-LABEL: test_llltui:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp ult i32 %a, %b %cmp = icmp ult i32 %a, %b
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
Show All 31 Lines
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_llltui_store(i32 zeroext %a, i32 zeroext %b) { define void @test_llltui_store(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_llltui_store: ; CHECK-LABEL: test_llltui_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: ld r5, .LC0@toc@l(r5) ; CHECK-NEXT: ld r5, .LC0@toc@l(r5)
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: stw r3, 0(r5) ; CHECK-NEXT: stw r3, 0(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp ult i32 %a, %b %cmp = icmp ult i32 %a, %b
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
store i32 %conv, i32* @glob, align 4 store i32 %conv, i32* @glob, align 4
ret void ret void
} }
▲ Show 20 Lines • Show All 46 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/testComparesllltus.ll

Show All 9 Lines
@glob = local_unnamed_addr global i16 0, align 2 @glob = local_unnamed_addr global i16 0, align 2
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_llltus(i16 zeroext %a, i16 zeroext %b) { define i64 @test_llltus(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_llltus: ; CHECK-LABEL: test_llltus:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: srdi r3, r3, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp ult i16 %a, %b %cmp = icmp ult i16 %a, %b
%conv3 = zext i1 %cmp to i64 %conv3 = zext i1 %cmp to i64
ret i64 %conv3 ret i64 %conv3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
Show All 11 Lines
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_llltus_store(i16 zeroext %a, i16 zeroext %b) { define void @test_llltus_store(i16 zeroext %a, i16 zeroext %b) {
; BE-LABEL: test_llltus_store: ; BE-LABEL: test_llltus_store:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha ; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: sub r3, r3, r4 ; BE-NEXT: sub r3, r3, r4
; BE-NEXT: ld r5, .LC0@toc@l(r5) ; BE-NEXT: ld r5, .LC0@toc@l(r5)
; BE-NEXT: rldicl r3, r3, 1, 63 ; BE-NEXT: srdi r3, r3, 63
; BE-NEXT: sth r3, 0(r5) ; BE-NEXT: sth r3, 0(r5)
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; LE-LABEL: test_llltus_store: ; LE-LABEL: test_llltus_store:
; LE: # %bb.0: # %entry ; LE: # %bb.0: # %entry
; LE-NEXT: sub r3, r3, r4 ; LE-NEXT: sub r3, r3, r4
; LE-NEXT: addis r5, r2, glob@toc@ha ; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: rldicl r3, r3, 1, 63 ; LE-NEXT: srdi r3, r3, 63
; LE-NEXT: sth r3, glob@toc@l(r5) ; LE-NEXT: sth r3, glob@toc@l(r5)
; LE-NEXT: blr ; LE-NEXT: blr
entry: entry:
%cmp = icmp ult i16 %a, %b %cmp = icmp ult i16 %a, %b
%conv3 = zext i1 %cmp to i16 %conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob, align 2 store i16 %conv3, i16* @glob, align 2
ret void ret void
} }
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llvm/test/CodeGen/PowerPC/trunc-srl-load.ll

Show All 19 Linesexit: ; preds = %entry
unreachable unreachable
cond.false: ; preds = %entry cond.false: ; preds = %entry
unreachable unreachable
} }
define i32 @sh_trunc_sh(i64 %x) { define i32 @sh_trunc_sh(i64 %x) {
; CHECK-LABEL: sh_trunc_sh: ; CHECK-LABEL: sh_trunc_sh:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: rldicl 3, 3, 47, 36 ; CHECK-NEXT: extrdi 3, 3, 28, 19
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%s = lshr i64 %x, 13 %s = lshr i64 %x, 13
%t = trunc i64 %s to i32 %t = trunc i64 %s to i32
%r = lshr i32 %t, 4 %r = lshr i32 %t, 4
ret i32 %r ret i32 %r
} }

llvm/test/CodeGen/PowerPC/uint-to-fp-v4i32.ll

Show All 39 Lines
; P9LE-NEXT: xscvuxddp f0, f0 ; P9LE-NEXT: xscvuxddp f0, f0
; P9LE-NEXT: xscvuxddp f1, f1 ; P9LE-NEXT: xscvuxddp f1, f1
; P9LE-NEXT: xxmrghd v2, vs1, vs0 ; P9LE-NEXT: xxmrghd v2, vs1, vs0
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P8BE-LABEL: test1: ; P8BE-LABEL: test1:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: mfvsrd r3, v2 ; P8BE-NEXT: mfvsrd r3, v2
; P8BE-NEXT: rldicl r4, r3, 16, 48 ; P8BE-NEXT: srdi r4, r3, 48
; P8BE-NEXT: rldicl r3, r3, 32, 48 ; P8BE-NEXT: extrdi r3, r3, 16, 16
; P8BE-NEXT: clrlwi r4, r4, 16 ; P8BE-NEXT: clrlwi r4, r4, 16
; P8BE-NEXT: clrlwi r3, r3, 16 ; P8BE-NEXT: clrlwi r3, r3, 16
; P8BE-NEXT: mtfprwz f0, r4 ; P8BE-NEXT: mtfprwz f0, r4
; P8BE-NEXT: mtfprwz f1, r3 ; P8BE-NEXT: mtfprwz f1, r3
; P8BE-NEXT: xscvuxddp f0, f0 ; P8BE-NEXT: xscvuxddp f0, f0
; P8BE-NEXT: xscvuxddp f1, f1 ; P8BE-NEXT: xscvuxddp f1, f1
; P8BE-NEXT: xxmrghd v2, vs0, vs1 ; P8BE-NEXT: xxmrghd v2, vs0, vs1
; P8BE-NEXT: blr ; P8BE-NEXT: blr
; ;
; P8LE-LABEL: test1: ; P8LE-LABEL: test1:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: xxswapd vs0, v2 ; P8LE-NEXT: xxswapd vs0, v2
; P8LE-NEXT: mffprd r3, f0 ; P8LE-NEXT: mffprd r3, f0
; P8LE-NEXT: clrldi r4, r3, 48 ; P8LE-NEXT: clrldi r4, r3, 48
; P8LE-NEXT: rldicl r3, r3, 48, 48 ; P8LE-NEXT: extrdi r3, r3, 16, 32
; P8LE-NEXT: clrlwi r4, r4, 16 ; P8LE-NEXT: clrlwi r4, r4, 16
; P8LE-NEXT: clrlwi r3, r3, 16 ; P8LE-NEXT: clrlwi r3, r3, 16
; P8LE-NEXT: mtfprwz f0, r4 ; P8LE-NEXT: mtfprwz f0, r4
; P8LE-NEXT: mtfprwz f1, r3 ; P8LE-NEXT: mtfprwz f1, r3
; P8LE-NEXT: xscvuxddp f0, f0 ; P8LE-NEXT: xscvuxddp f0, f0
; P8LE-NEXT: xscvuxddp f1, f1 ; P8LE-NEXT: xscvuxddp f1, f1
; P8LE-NEXT: xxmrghd v2, vs1, vs0 ; P8LE-NEXT: xxmrghd v2, vs1, vs0
; P8LE-NEXT: blr ; P8LE-NEXT: blr
▲ Show 20 Lines • Show All 62 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/umulfixsat.ll

Show All 19 Lines
define i32 @func2(i32 %x, i32 %y) nounwind { define i32 @func2(i32 %x, i32 %y) nounwind {
; CHECK-LABEL: func2: ; CHECK-LABEL: func2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: mulhwu 6, 3, 4 ; CHECK-NEXT: mulhwu 6, 3, 4
; CHECK-NEXT: li 5, -1 ; CHECK-NEXT: li 5, -1
; CHECK-NEXT: cmplwi 6, 1 ; CHECK-NEXT: cmplwi 6, 1
; CHECK-NEXT: mullw 3, 3, 4 ; CHECK-NEXT: mullw 3, 3, 4
; CHECK-NEXT: rotlwi 3, 3, 31 ; CHECK-NEXT: rotlwi 3, 3, 31
; CHECK-NEXT: rlwimi 3, 6, 31, 0, 0 ; CHECK-NEXT: insrwi 3, 6, 1, 0
; CHECK-NEXT: bc 12, 1, .LBB1_1 ; CHECK-NEXT: bc 12, 1, .LBB1_1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-NEXT: .LBB1_1: ; CHECK-NEXT: .LBB1_1:
; CHECK-NEXT: addi 3, 5, 0 ; CHECK-NEXT: addi 3, 5, 0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%tmp = call i32 @llvm.umul.fix.sat.i32(i32 %x, i32 %y, i32 1) %tmp = call i32 @llvm.umul.fix.sat.i32(i32 %x, i32 %y, i32 1)
ret i32 %tmp ret i32 %tmp
} }

llvm/test/CodeGen/PowerPC/urem-vector-lkk.ll

Show All 30 Lines
; P9LE-NEXT: ori r5, r5, 16913 ; P9LE-NEXT: ori r5, r5, 16913
; P9LE-NEXT: srwi r4, r4, 8 ; P9LE-NEXT: srwi r4, r4, 8
; P9LE-NEXT: mulli r4, r4, 1003 ; P9LE-NEXT: mulli r4, r4, 1003
; P9LE-NEXT: sub r3, r3, r4 ; P9LE-NEXT: sub r3, r3, r4
; P9LE-NEXT: xxswapd v3, vs0 ; P9LE-NEXT: xxswapd v3, vs0
; P9LE-NEXT: mtfprd f0, r3 ; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 2 ; P9LE-NEXT: li r3, 2
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: rlwinm r4, r3, 30, 18, 31 ; P9LE-NEXT: extrwi r4, r3, 14, 16
; P9LE-NEXT: mulhwu r4, r4, r5 ; P9LE-NEXT: mulhwu r4, r4, r5
; P9LE-NEXT: lis r5, 22765 ; P9LE-NEXT: lis r5, 22765
; P9LE-NEXT: ori r5, r5, 8969 ; P9LE-NEXT: ori r5, r5, 8969
; P9LE-NEXT: srwi r4, r4, 2 ; P9LE-NEXT: srwi r4, r4, 2
; P9LE-NEXT: mulli r4, r4, 124 ; P9LE-NEXT: mulli r4, r4, 124
; P9LE-NEXT: sub r3, r3, r4 ; P9LE-NEXT: sub r3, r3, r4
; P9LE-NEXT: xxswapd v4, vs0 ; P9LE-NEXT: xxswapd v4, vs0
; P9LE-NEXT: mtfprd f0, r3 ; P9LE-NEXT: mtfprd f0, r3
Show All 40 Lines
; P9BE-NEXT: sldi r3, r3, 48 ; P9BE-NEXT: sldi r3, r3, 48
; P9BE-NEXT: mtvsrd v4, r3 ; P9BE-NEXT: mtvsrd v4, r3
; P9BE-NEXT: li r3, 2 ; P9BE-NEXT: li r3, 2
; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: lis r5, 8456 ; P9BE-NEXT: lis r5, 8456
; P9BE-NEXT: ori r5, r5, 16913 ; P9BE-NEXT: ori r5, r5, 16913
; P9BE-NEXT: vmrghh v3, v4, v3 ; P9BE-NEXT: vmrghh v3, v4, v3
; P9BE-NEXT: clrlwi r4, r3, 16 ; P9BE-NEXT: clrlwi r4, r3, 16
; P9BE-NEXT: rlwinm r3, r3, 30, 18, 31 ; P9BE-NEXT: extrwi r3, r3, 14, 16
; P9BE-NEXT: mulhwu r3, r3, r5 ; P9BE-NEXT: mulhwu r3, r3, r5
; P9BE-NEXT: srwi r3, r3, 2 ; P9BE-NEXT: srwi r3, r3, 2
; P9BE-NEXT: mulli r3, r3, 124 ; P9BE-NEXT: mulli r3, r3, 124
; P9BE-NEXT: sub r3, r4, r3 ; P9BE-NEXT: sub r3, r4, r3
; P9BE-NEXT: lis r4, 22765 ; P9BE-NEXT: lis r4, 22765
; P9BE-NEXT: sldi r3, r3, 48 ; P9BE-NEXT: sldi r3, r3, 48
; P9BE-NEXT: mtvsrd v4, r3 ; P9BE-NEXT: mtvsrd v4, r3
; P9BE-NEXT: li r3, 0 ; P9BE-NEXT: li r3, 0
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; P8LE-NEXT: lis r3, 22765 ; P8LE-NEXT: lis r3, 22765
; P8LE-NEXT: lis r7, 21399 ; P8LE-NEXT: lis r7, 21399
; P8LE-NEXT: lis r10, 16727 ; P8LE-NEXT: lis r10, 16727
; P8LE-NEXT: ori r3, r3, 8969 ; P8LE-NEXT: ori r3, r3, 8969
; P8LE-NEXT: ori r7, r7, 33437 ; P8LE-NEXT: ori r7, r7, 33437
; P8LE-NEXT: ori r10, r10, 2287 ; P8LE-NEXT: ori r10, r10, 2287
; P8LE-NEXT: mffprd r4, f0 ; P8LE-NEXT: mffprd r4, f0
; P8LE-NEXT: clrldi r6, r4, 48 ; P8LE-NEXT: clrldi r6, r4, 48
; P8LE-NEXT: rldicl r5, r4, 32, 48 ; P8LE-NEXT: extrdi r5, r4, 16, 16
; P8LE-NEXT: clrlwi r9, r6, 16 ; P8LE-NEXT: clrlwi r9, r6, 16
; P8LE-NEXT: rldicl r8, r4, 16, 48 ; P8LE-NEXT: srdi r8, r4, 48
; P8LE-NEXT: clrlwi r11, r5, 16 ; P8LE-NEXT: clrlwi r11, r5, 16
; P8LE-NEXT: mulhwu r3, r9, r3 ; P8LE-NEXT: mulhwu r3, r9, r3
; P8LE-NEXT: clrlwi r12, r8, 16 ; P8LE-NEXT: clrlwi r12, r8, 16
; P8LE-NEXT: mulhwu r7, r11, r7 ; P8LE-NEXT: mulhwu r7, r11, r7
; P8LE-NEXT: lis r11, 8456 ; P8LE-NEXT: lis r11, 8456
; P8LE-NEXT: rldicl r4, r4, 48, 48 ; P8LE-NEXT: extrdi r4, r4, 16, 32
; P8LE-NEXT: mulhwu r10, r12, r10 ; P8LE-NEXT: mulhwu r10, r12, r10
; P8LE-NEXT: ori r11, r11, 16913 ; P8LE-NEXT: ori r11, r11, 16913
; P8LE-NEXT: rlwinm r12, r4, 30, 18, 31 ; P8LE-NEXT: extrwi r12, r4, 14, 16
; P8LE-NEXT: mulhwu r11, r12, r11 ; P8LE-NEXT: mulhwu r11, r12, r11
; P8LE-NEXT: sub r9, r9, r3 ; P8LE-NEXT: sub r9, r9, r3
; P8LE-NEXT: srwi r9, r9, 1 ; P8LE-NEXT: srwi r9, r9, 1
; P8LE-NEXT: srwi r7, r7, 5 ; P8LE-NEXT: srwi r7, r7, 5
; P8LE-NEXT: add r3, r9, r3 ; P8LE-NEXT: add r3, r9, r3
; P8LE-NEXT: srwi r9, r10, 8 ; P8LE-NEXT: srwi r9, r10, 8
; P8LE-NEXT: srwi r3, r3, 6 ; P8LE-NEXT: srwi r3, r3, 6
; P8LE-NEXT: mulli r7, r7, 98 ; P8LE-NEXT: mulli r7, r7, 98
Show All 24 Lines
; P8BE-NEXT: lis r3, 22765 ; P8BE-NEXT: lis r3, 22765
; P8BE-NEXT: lis r7, 16727 ; P8BE-NEXT: lis r7, 16727
; P8BE-NEXT: lis r9, 21399 ; P8BE-NEXT: lis r9, 21399
; P8BE-NEXT: lis r10, 8456 ; P8BE-NEXT: lis r10, 8456
; P8BE-NEXT: ori r3, r3, 8969 ; P8BE-NEXT: ori r3, r3, 8969
; P8BE-NEXT: ori r7, r7, 2287 ; P8BE-NEXT: ori r7, r7, 2287
; P8BE-NEXT: ori r9, r9, 33437 ; P8BE-NEXT: ori r9, r9, 33437
; P8BE-NEXT: ori r10, r10, 16913 ; P8BE-NEXT: ori r10, r10, 16913
; P8BE-NEXT: rldicl r6, r4, 16, 48 ; P8BE-NEXT: srdi r6, r4, 48
; P8BE-NEXT: clrldi r5, r4, 48 ; P8BE-NEXT: clrldi r5, r4, 48
; P8BE-NEXT: clrlwi r6, r6, 16 ; P8BE-NEXT: clrlwi r6, r6, 16
; P8BE-NEXT: rldicl r8, r4, 48, 48 ; P8BE-NEXT: extrdi r8, r4, 16, 32
; P8BE-NEXT: clrlwi r5, r5, 16 ; P8BE-NEXT: clrlwi r5, r5, 16
; P8BE-NEXT: mulhwu r3, r6, r3 ; P8BE-NEXT: mulhwu r3, r6, r3
; P8BE-NEXT: rldicl r4, r4, 32, 48 ; P8BE-NEXT: extrdi r4, r4, 16, 16
; P8BE-NEXT: clrlwi r8, r8, 16 ; P8BE-NEXT: clrlwi r8, r8, 16
; P8BE-NEXT: mulhwu r7, r5, r7 ; P8BE-NEXT: mulhwu r7, r5, r7
; P8BE-NEXT: rlwinm r11, r4, 30, 18, 31 ; P8BE-NEXT: extrwi r11, r4, 14, 16
; P8BE-NEXT: clrlwi r4, r4, 16 ; P8BE-NEXT: clrlwi r4, r4, 16
; P8BE-NEXT: mulhwu r9, r8, r9 ; P8BE-NEXT: mulhwu r9, r8, r9
; P8BE-NEXT: mulhwu r10, r11, r10 ; P8BE-NEXT: mulhwu r10, r11, r10
; P8BE-NEXT: sub r11, r6, r3 ; P8BE-NEXT: sub r11, r6, r3
; P8BE-NEXT: srwi r11, r11, 1 ; P8BE-NEXT: srwi r11, r11, 1
; P8BE-NEXT: srwi r7, r7, 8 ; P8BE-NEXT: srwi r7, r7, 8
; P8BE-NEXT: add r3, r11, r3 ; P8BE-NEXT: add r3, r11, r3
; P8BE-NEXT: srwi r9, r9, 5 ; P8BE-NEXT: srwi r9, r9, 5
▲ Show 20 Lines • Show All 141 Lines • ▼ Show 20 Lines
; P8LE-LABEL: fold_urem_vec_2: ; P8LE-LABEL: fold_urem_vec_2:
; P8LE: # %bb.0: ; P8LE: # %bb.0:
; P8LE-NEXT: xxswapd vs0, v2 ; P8LE-NEXT: xxswapd vs0, v2
; P8LE-NEXT: lis r3, 22765 ; P8LE-NEXT: lis r3, 22765
; P8LE-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; P8LE-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; P8LE-NEXT: ori r3, r3, 8969 ; P8LE-NEXT: ori r3, r3, 8969
; P8LE-NEXT: mffprd r4, f0 ; P8LE-NEXT: mffprd r4, f0
; P8LE-NEXT: clrldi r5, r4, 48 ; P8LE-NEXT: clrldi r5, r4, 48
; P8LE-NEXT: rldicl r6, r4, 48, 48 ; P8LE-NEXT: extrdi r6, r4, 16, 32
; P8LE-NEXT: clrlwi r8, r5, 16 ; P8LE-NEXT: clrlwi r8, r5, 16
; P8LE-NEXT: rldicl r7, r4, 32, 48 ; P8LE-NEXT: extrdi r7, r4, 16, 16
; P8LE-NEXT: clrlwi r9, r6, 16 ; P8LE-NEXT: clrlwi r9, r6, 16
; P8LE-NEXT: rldicl r4, r4, 16, 48 ; P8LE-NEXT: srdi r4, r4, 48
; P8LE-NEXT: mulhwu r10, r8, r3 ; P8LE-NEXT: mulhwu r10, r8, r3
; P8LE-NEXT: clrlwi r11, r7, 16 ; P8LE-NEXT: clrlwi r11, r7, 16
; P8LE-NEXT: clrlwi r0, r4, 16 ; P8LE-NEXT: clrlwi r0, r4, 16
; P8LE-NEXT: mulhwu r12, r9, r3 ; P8LE-NEXT: mulhwu r12, r9, r3
; P8LE-NEXT: mulhwu r30, r11, r3 ; P8LE-NEXT: mulhwu r30, r11, r3
; P8LE-NEXT: mulhwu r3, r0, r3 ; P8LE-NEXT: mulhwu r3, r0, r3
; P8LE-NEXT: sub r8, r8, r10 ; P8LE-NEXT: sub r8, r8, r10
; P8LE-NEXT: srwi r8, r8, 1 ; P8LE-NEXT: srwi r8, r8, 1
Show All 34 Lines
; P8LE-NEXT: blr ; P8LE-NEXT: blr
; ;
; P8BE-LABEL: fold_urem_vec_2: ; P8BE-LABEL: fold_urem_vec_2:
; P8BE: # %bb.0: ; P8BE: # %bb.0:
; P8BE-NEXT: mfvsrd r4, v2 ; P8BE-NEXT: mfvsrd r4, v2
; P8BE-NEXT: lis r3, 22765 ; P8BE-NEXT: lis r3, 22765
; P8BE-NEXT: ori r3, r3, 8969 ; P8BE-NEXT: ori r3, r3, 8969
; P8BE-NEXT: clrldi r5, r4, 48 ; P8BE-NEXT: clrldi r5, r4, 48
; P8BE-NEXT: rldicl r6, r4, 48, 48 ; P8BE-NEXT: extrdi r6, r4, 16, 32
; P8BE-NEXT: clrlwi r5, r5, 16 ; P8BE-NEXT: clrlwi r5, r5, 16
; P8BE-NEXT: rldicl r7, r4, 32, 48 ; P8BE-NEXT: extrdi r7, r4, 16, 16
; P8BE-NEXT: clrlwi r6, r6, 16 ; P8BE-NEXT: clrlwi r6, r6, 16
; P8BE-NEXT: mulhwu r8, r5, r3 ; P8BE-NEXT: mulhwu r8, r5, r3
; P8BE-NEXT: rldicl r4, r4, 16, 48 ; P8BE-NEXT: srdi r4, r4, 48
; P8BE-NEXT: clrlwi r7, r7, 16 ; P8BE-NEXT: clrlwi r7, r7, 16
; P8BE-NEXT: mulhwu r9, r6, r3 ; P8BE-NEXT: mulhwu r9, r6, r3
; P8BE-NEXT: clrlwi r4, r4, 16 ; P8BE-NEXT: clrlwi r4, r4, 16
; P8BE-NEXT: mulhwu r10, r7, r3 ; P8BE-NEXT: mulhwu r10, r7, r3
; P8BE-NEXT: mulhwu r3, r4, r3 ; P8BE-NEXT: mulhwu r3, r4, r3
; P8BE-NEXT: sub r11, r5, r8 ; P8BE-NEXT: sub r11, r5, r8
; P8BE-NEXT: sub r12, r6, r9 ; P8BE-NEXT: sub r12, r6, r9
; P8BE-NEXT: srwi r11, r11, 1 ; P8BE-NEXT: srwi r11, r11, 1
▲ Show 20 Lines • Show All 178 Lines • ▼ Show 20 Lines
; P8LE-LABEL: combine_urem_udiv: ; P8LE-LABEL: combine_urem_udiv:
; P8LE: # %bb.0: ; P8LE: # %bb.0:
; P8LE-NEXT: xxswapd vs0, v2 ; P8LE-NEXT: xxswapd vs0, v2
; P8LE-NEXT: lis r4, 22765 ; P8LE-NEXT: lis r4, 22765
; P8LE-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; P8LE-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; P8LE-NEXT: ori r4, r4, 8969 ; P8LE-NEXT: ori r4, r4, 8969
; P8LE-NEXT: mffprd r5, f0 ; P8LE-NEXT: mffprd r5, f0
; P8LE-NEXT: clrldi r3, r5, 48 ; P8LE-NEXT: clrldi r3, r5, 48
; P8LE-NEXT: rldicl r6, r5, 48, 48 ; P8LE-NEXT: extrdi r6, r5, 16, 32
; P8LE-NEXT: clrlwi r8, r3, 16 ; P8LE-NEXT: clrlwi r8, r3, 16
; P8LE-NEXT: rldicl r7, r5, 32, 48 ; P8LE-NEXT: extrdi r7, r5, 16, 16
; P8LE-NEXT: clrlwi r9, r6, 16 ; P8LE-NEXT: clrlwi r9, r6, 16
; P8LE-NEXT: mulhwu r10, r8, r4 ; P8LE-NEXT: mulhwu r10, r8, r4
; P8LE-NEXT: clrlwi r11, r7, 16 ; P8LE-NEXT: clrlwi r11, r7, 16
; P8LE-NEXT: rldicl r5, r5, 16, 48 ; P8LE-NEXT: srdi r5, r5, 48
; P8LE-NEXT: mulhwu r12, r9, r4 ; P8LE-NEXT: mulhwu r12, r9, r4
; P8LE-NEXT: mulhwu r0, r11, r4 ; P8LE-NEXT: mulhwu r0, r11, r4
; P8LE-NEXT: clrlwi r30, r5, 16 ; P8LE-NEXT: clrlwi r30, r5, 16
; P8LE-NEXT: mulhwu r4, r30, r4 ; P8LE-NEXT: mulhwu r4, r30, r4
; P8LE-NEXT: sub r8, r8, r10 ; P8LE-NEXT: sub r8, r8, r10
; P8LE-NEXT: srwi r8, r8, 1 ; P8LE-NEXT: srwi r8, r8, 1
; P8LE-NEXT: sub r9, r9, r12 ; P8LE-NEXT: sub r9, r9, r12
; P8LE-NEXT: add r8, r8, r10 ; P8LE-NEXT: add r8, r8, r10
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
; P8LE-NEXT: blr ; P8LE-NEXT: blr
; ;
; P8BE-LABEL: combine_urem_udiv: ; P8BE-LABEL: combine_urem_udiv:
; P8BE: # %bb.0: ; P8BE: # %bb.0:
; P8BE-NEXT: mfvsrd r5, v2 ; P8BE-NEXT: mfvsrd r5, v2
; P8BE-NEXT: lis r4, 22765 ; P8BE-NEXT: lis r4, 22765
; P8BE-NEXT: ori r4, r4, 8969 ; P8BE-NEXT: ori r4, r4, 8969
; P8BE-NEXT: clrldi r3, r5, 48 ; P8BE-NEXT: clrldi r3, r5, 48
; P8BE-NEXT: rldicl r6, r5, 48, 48 ; P8BE-NEXT: extrdi r6, r5, 16, 32
; P8BE-NEXT: clrlwi r8, r3, 16 ; P8BE-NEXT: clrlwi r8, r3, 16
; P8BE-NEXT: rldicl r7, r5, 32, 48 ; P8BE-NEXT: extrdi r7, r5, 16, 16
; P8BE-NEXT: clrlwi r9, r6, 16 ; P8BE-NEXT: clrlwi r9, r6, 16
; P8BE-NEXT: rldicl r5, r5, 16, 48 ; P8BE-NEXT: srdi r5, r5, 48
; P8BE-NEXT: mulhwu r10, r8, r4 ; P8BE-NEXT: mulhwu r10, r8, r4
; P8BE-NEXT: clrlwi r11, r7, 16 ; P8BE-NEXT: clrlwi r11, r7, 16
; P8BE-NEXT: mulhwu r12, r9, r4 ; P8BE-NEXT: mulhwu r12, r9, r4
; P8BE-NEXT: clrlwi r5, r5, 16 ; P8BE-NEXT: clrlwi r5, r5, 16
; P8BE-NEXT: mulhwu r0, r11, r4 ; P8BE-NEXT: mulhwu r0, r11, r4
; P8BE-NEXT: mulhwu r4, r5, r4 ; P8BE-NEXT: mulhwu r4, r5, r4
; P8BE-NEXT: sub r8, r8, r10 ; P8BE-NEXT: sub r8, r8, r10
; P8BE-NEXT: sub r9, r9, r12 ; P8BE-NEXT: sub r9, r9, r12
▲ Show 20 Lines • Show All 124 Lines • ▼ Show 20 Lines
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; ;
; P8LE-LABEL: dont_fold_urem_power_of_two: ; P8LE-LABEL: dont_fold_urem_power_of_two:
; P8LE: # %bb.0: ; P8LE: # %bb.0:
; P8LE-NEXT: xxswapd vs0, v2 ; P8LE-NEXT: xxswapd vs0, v2
; P8LE-NEXT: lis r3, 22765 ; P8LE-NEXT: lis r3, 22765
; P8LE-NEXT: ori r3, r3, 8969 ; P8LE-NEXT: ori r3, r3, 8969
; P8LE-NEXT: mffprd r4, f0 ; P8LE-NEXT: mffprd r4, f0
; P8LE-NEXT: rldicl r5, r4, 16, 48 ; P8LE-NEXT: srdi r5, r4, 48
; P8LE-NEXT: rldicl r7, r4, 48, 48 ; P8LE-NEXT: extrdi r7, r4, 16, 32
; P8LE-NEXT: clrlwi r6, r5, 16 ; P8LE-NEXT: clrlwi r6, r5, 16
; P8LE-NEXT: mulhwu r3, r6, r3 ; P8LE-NEXT: mulhwu r3, r6, r3
; P8LE-NEXT: sub r6, r6, r3 ; P8LE-NEXT: sub r6, r6, r3
; P8LE-NEXT: srwi r6, r6, 1 ; P8LE-NEXT: srwi r6, r6, 1
; P8LE-NEXT: add r3, r6, r3 ; P8LE-NEXT: add r3, r6, r3
; P8LE-NEXT: clrldi r6, r4, 48 ; P8LE-NEXT: clrldi r6, r4, 48
; P8LE-NEXT: srwi r3, r3, 6 ; P8LE-NEXT: srwi r3, r3, 6
; P8LE-NEXT: clrlwi r6, r6, 26 ; P8LE-NEXT: clrlwi r6, r6, 26
; P8LE-NEXT: mulli r3, r3, 95 ; P8LE-NEXT: mulli r3, r3, 95
; P8LE-NEXT: rldicl r4, r4, 32, 48 ; P8LE-NEXT: extrdi r4, r4, 16, 16
; P8LE-NEXT: mtfprd f0, r6 ; P8LE-NEXT: mtfprd f0, r6
; P8LE-NEXT: clrlwi r6, r7, 27 ; P8LE-NEXT: clrlwi r6, r7, 27
; P8LE-NEXT: clrlwi r4, r4, 29 ; P8LE-NEXT: clrlwi r4, r4, 29
; P8LE-NEXT: mtfprd f1, r6 ; P8LE-NEXT: mtfprd f1, r6
; P8LE-NEXT: mtfprd f3, r4 ; P8LE-NEXT: mtfprd f3, r4
; P8LE-NEXT: xxswapd v2, vs0 ; P8LE-NEXT: xxswapd v2, vs0
; P8LE-NEXT: xxswapd v3, vs1 ; P8LE-NEXT: xxswapd v3, vs1
; P8LE-NEXT: sub r3, r5, r3 ; P8LE-NEXT: sub r3, r5, r3
; P8LE-NEXT: xxswapd v5, vs3 ; P8LE-NEXT: xxswapd v5, vs3
; P8LE-NEXT: mtfprd f2, r3 ; P8LE-NEXT: mtfprd f2, r3
; P8LE-NEXT: vmrglh v2, v3, v2 ; P8LE-NEXT: vmrglh v2, v3, v2
; P8LE-NEXT: xxswapd v4, vs2 ; P8LE-NEXT: xxswapd v4, vs2
; P8LE-NEXT: vmrglh v3, v4, v5 ; P8LE-NEXT: vmrglh v3, v4, v5
; P8LE-NEXT: vmrglw v2, v3, v2 ; P8LE-NEXT: vmrglw v2, v3, v2
; P8LE-NEXT: blr ; P8LE-NEXT: blr
; ;
; P8BE-LABEL: dont_fold_urem_power_of_two: ; P8BE-LABEL: dont_fold_urem_power_of_two:
; P8BE: # %bb.0: ; P8BE: # %bb.0:
; P8BE-NEXT: mfvsrd r4, v2 ; P8BE-NEXT: mfvsrd r4, v2
; P8BE-NEXT: lis r3, 22765 ; P8BE-NEXT: lis r3, 22765
; P8BE-NEXT: ori r3, r3, 8969 ; P8BE-NEXT: ori r3, r3, 8969
; P8BE-NEXT: clrldi r5, r4, 48 ; P8BE-NEXT: clrldi r5, r4, 48
; P8BE-NEXT: rldicl r7, r4, 16, 48 ; P8BE-NEXT: srdi r7, r4, 48
; P8BE-NEXT: clrlwi r5, r5, 16 ; P8BE-NEXT: clrlwi r5, r5, 16
; P8BE-NEXT: clrlwi r7, r7, 26 ; P8BE-NEXT: clrlwi r7, r7, 26
; P8BE-NEXT: mulhwu r3, r5, r3 ; P8BE-NEXT: mulhwu r3, r5, r3
; P8BE-NEXT: sub r6, r5, r3 ; P8BE-NEXT: sub r6, r5, r3
; P8BE-NEXT: srwi r6, r6, 1 ; P8BE-NEXT: srwi r6, r6, 1
; P8BE-NEXT: add r3, r6, r3 ; P8BE-NEXT: add r3, r6, r3
; P8BE-NEXT: rldicl r6, r4, 32, 48 ; P8BE-NEXT: extrdi r6, r4, 16, 16
; P8BE-NEXT: srwi r3, r3, 6 ; P8BE-NEXT: srwi r3, r3, 6
; P8BE-NEXT: rldicl r4, r4, 48, 48 ; P8BE-NEXT: extrdi r4, r4, 16, 32
; P8BE-NEXT: clrlwi r6, r6, 27 ; P8BE-NEXT: clrlwi r6, r6, 27
; P8BE-NEXT: mulli r3, r3, 95 ; P8BE-NEXT: mulli r3, r3, 95
; P8BE-NEXT: sldi r6, r6, 48 ; P8BE-NEXT: sldi r6, r6, 48
; P8BE-NEXT: clrlwi r4, r4, 29 ; P8BE-NEXT: clrlwi r4, r4, 29
; P8BE-NEXT: mtvsrd v2, r6 ; P8BE-NEXT: mtvsrd v2, r6
; P8BE-NEXT: sldi r6, r7, 48 ; P8BE-NEXT: sldi r6, r7, 48
; P8BE-NEXT: sldi r4, r4, 48 ; P8BE-NEXT: sldi r4, r4, 48
; P8BE-NEXT: mtvsrd v3, r6 ; P8BE-NEXT: mtvsrd v3, r6
Show All 33 Lines
; P9LE-NEXT: ori r5, r5, 30865 ; P9LE-NEXT: ori r5, r5, 30865
; P9LE-NEXT: srwi r4, r4, 11 ; P9LE-NEXT: srwi r4, r4, 11
; P9LE-NEXT: mulli r4, r4, 5423 ; P9LE-NEXT: mulli r4, r4, 5423
; P9LE-NEXT: sub r3, r3, r4 ; P9LE-NEXT: sub r3, r3, r4
; P9LE-NEXT: xxswapd v3, vs0 ; P9LE-NEXT: xxswapd v3, vs0
; P9LE-NEXT: mtfprd f0, r3 ; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 2 ; P9LE-NEXT: li r3, 2
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: rlwinm r4, r3, 31, 17, 31 ; P9LE-NEXT: extrwi r4, r3, 15, 16
; P9LE-NEXT: mulhwu r4, r4, r5 ; P9LE-NEXT: mulhwu r4, r4, r5
; P9LE-NEXT: srwi r4, r4, 8 ; P9LE-NEXT: srwi r4, r4, 8
; P9LE-NEXT: mulli r4, r4, 654 ; P9LE-NEXT: mulli r4, r4, 654
; P9LE-NEXT: sub r3, r3, r4 ; P9LE-NEXT: sub r3, r3, r4
; P9LE-NEXT: xxswapd v4, vs0 ; P9LE-NEXT: xxswapd v4, vs0
; P9LE-NEXT: mtfprd f0, r3 ; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: xxswapd v2, vs0 ; P9LE-NEXT: xxswapd v2, vs0
; P9LE-NEXT: vmrglh v3, v4, v3 ; P9LE-NEXT: vmrglh v3, v4, v3
Show All 27 Lines
; P9BE-NEXT: sldi r3, r3, 48 ; P9BE-NEXT: sldi r3, r3, 48
; P9BE-NEXT: mtvsrd v4, r3 ; P9BE-NEXT: mtvsrd v4, r3
; P9BE-NEXT: li r3, 2 ; P9BE-NEXT: li r3, 2
; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: lis r5, -14230 ; P9BE-NEXT: lis r5, -14230
; P9BE-NEXT: ori r5, r5, 30865 ; P9BE-NEXT: ori r5, r5, 30865
; P9BE-NEXT: vmrghh v3, v4, v3 ; P9BE-NEXT: vmrghh v3, v4, v3
; P9BE-NEXT: clrlwi r4, r3, 16 ; P9BE-NEXT: clrlwi r4, r3, 16
; P9BE-NEXT: rlwinm r3, r3, 31, 17, 31 ; P9BE-NEXT: extrwi r3, r3, 15, 16
; P9BE-NEXT: mulhwu r3, r3, r5 ; P9BE-NEXT: mulhwu r3, r3, r5
; P9BE-NEXT: srwi r3, r3, 8 ; P9BE-NEXT: srwi r3, r3, 8
; P9BE-NEXT: mulli r3, r3, 654 ; P9BE-NEXT: mulli r3, r3, 654
; P9BE-NEXT: sub r3, r4, r3 ; P9BE-NEXT: sub r3, r4, r3
; P9BE-NEXT: sldi r3, r3, 48 ; P9BE-NEXT: sldi r3, r3, 48
; P9BE-NEXT: mtvsrd v2, r3 ; P9BE-NEXT: mtvsrd v2, r3
; P9BE-NEXT: li r3, 0 ; P9BE-NEXT: li r3, 0
; P9BE-NEXT: sldi r3, r3, 48 ; P9BE-NEXT: sldi r3, r3, 48
; P9BE-NEXT: mtvsrd v4, r3 ; P9BE-NEXT: mtvsrd v4, r3
; P9BE-NEXT: vmrghh v2, v4, v2 ; P9BE-NEXT: vmrghh v2, v4, v2
; P9BE-NEXT: vmrghw v2, v2, v3 ; P9BE-NEXT: vmrghw v2, v2, v3
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; ;
; P8LE-LABEL: dont_fold_urem_one: ; P8LE-LABEL: dont_fold_urem_one:
; P8LE: # %bb.0: ; P8LE: # %bb.0:
; P8LE-NEXT: xxswapd vs0, v2 ; P8LE-NEXT: xxswapd vs0, v2
; P8LE-NEXT: lis r3, -19946 ; P8LE-NEXT: lis r3, -19946
; P8LE-NEXT: lis r7, 24749 ; P8LE-NEXT: lis r7, 24749
; P8LE-NEXT: lis r9, -14230 ; P8LE-NEXT: lis r9, -14230
; P8LE-NEXT: xxlxor v5, v5, v5 ; P8LE-NEXT: xxlxor v5, v5, v5
; P8LE-NEXT: ori r3, r3, 17097 ; P8LE-NEXT: ori r3, r3, 17097
; P8LE-NEXT: ori r7, r7, 47143 ; P8LE-NEXT: ori r7, r7, 47143
; P8LE-NEXT: ori r9, r9, 30865 ; P8LE-NEXT: ori r9, r9, 30865
; P8LE-NEXT: mffprd r4, f0 ; P8LE-NEXT: mffprd r4, f0
; P8LE-NEXT: rldicl r5, r4, 32, 48 ; P8LE-NEXT: extrdi r5, r4, 16, 16
; P8LE-NEXT: rldicl r6, r4, 16, 48 ; P8LE-NEXT: srdi r6, r4, 48
; P8LE-NEXT: clrlwi r8, r5, 16 ; P8LE-NEXT: clrlwi r8, r5, 16
; P8LE-NEXT: rldicl r4, r4, 48, 48 ; P8LE-NEXT: extrdi r4, r4, 16, 32
; P8LE-NEXT: mulhwu r3, r8, r3 ; P8LE-NEXT: mulhwu r3, r8, r3
; P8LE-NEXT: clrlwi r8, r6, 16 ; P8LE-NEXT: clrlwi r8, r6, 16
; P8LE-NEXT: mulhwu r7, r8, r7 ; P8LE-NEXT: mulhwu r7, r8, r7
; P8LE-NEXT: rlwinm r8, r4, 31, 17, 31 ; P8LE-NEXT: extrwi r8, r4, 15, 16
; P8LE-NEXT: mulhwu r8, r8, r9 ; P8LE-NEXT: mulhwu r8, r8, r9
; P8LE-NEXT: srwi r3, r3, 4 ; P8LE-NEXT: srwi r3, r3, 4
; P8LE-NEXT: srwi r7, r7, 11 ; P8LE-NEXT: srwi r7, r7, 11
; P8LE-NEXT: mulli r3, r3, 23 ; P8LE-NEXT: mulli r3, r3, 23
; P8LE-NEXT: srwi r8, r8, 8 ; P8LE-NEXT: srwi r8, r8, 8
; P8LE-NEXT: mulli r7, r7, 5423 ; P8LE-NEXT: mulli r7, r7, 5423
; P8LE-NEXT: mulli r8, r8, 654 ; P8LE-NEXT: mulli r8, r8, 654
; P8LE-NEXT: sub r3, r5, r3 ; P8LE-NEXT: sub r3, r5, r3
Show All 15 Lines
; P8BE-NEXT: mfvsrd r4, v2 ; P8BE-NEXT: mfvsrd r4, v2
; P8BE-NEXT: lis r3, 24749 ; P8BE-NEXT: lis r3, 24749
; P8BE-NEXT: lis r7, -19946 ; P8BE-NEXT: lis r7, -19946
; P8BE-NEXT: lis r8, -14230 ; P8BE-NEXT: lis r8, -14230
; P8BE-NEXT: ori r3, r3, 47143 ; P8BE-NEXT: ori r3, r3, 47143
; P8BE-NEXT: ori r7, r7, 17097 ; P8BE-NEXT: ori r7, r7, 17097
; P8BE-NEXT: ori r8, r8, 30865 ; P8BE-NEXT: ori r8, r8, 30865
; P8BE-NEXT: clrldi r5, r4, 48 ; P8BE-NEXT: clrldi r5, r4, 48
; P8BE-NEXT: rldicl r6, r4, 48, 48 ; P8BE-NEXT: extrdi r6, r4, 16, 32
; P8BE-NEXT: rldicl r4, r4, 32, 48 ; P8BE-NEXT: extrdi r4, r4, 16, 16
; P8BE-NEXT: clrlwi r5, r5, 16 ; P8BE-NEXT: clrlwi r5, r5, 16
; P8BE-NEXT: clrlwi r6, r6, 16 ; P8BE-NEXT: clrlwi r6, r6, 16
; P8BE-NEXT: mulhwu r3, r5, r3 ; P8BE-NEXT: mulhwu r3, r5, r3
; P8BE-NEXT: rlwinm r9, r4, 31, 17, 31 ; P8BE-NEXT: extrwi r9, r4, 15, 16
; P8BE-NEXT: clrlwi r4, r4, 16 ; P8BE-NEXT: clrlwi r4, r4, 16
; P8BE-NEXT: mulhwu r7, r6, r7 ; P8BE-NEXT: mulhwu r7, r6, r7
; P8BE-NEXT: mulhwu r8, r9, r8 ; P8BE-NEXT: mulhwu r8, r9, r8
; P8BE-NEXT: li r9, 0 ; P8BE-NEXT: li r9, 0
; P8BE-NEXT: srwi r3, r3, 11 ; P8BE-NEXT: srwi r3, r3, 11
; P8BE-NEXT: srwi r7, r7, 4 ; P8BE-NEXT: srwi r7, r7, 4
; P8BE-NEXT: mulli r3, r3, 5423 ; P8BE-NEXT: mulli r3, r3, 5423
; P8BE-NEXT: srwi r8, r8, 8 ; P8BE-NEXT: srwi r8, r8, 8
Show All 34 Lines
; P9LE-NEXT: lis r4, 25644 ; P9LE-NEXT: lis r4, 25644
; P9LE-NEXT: ori r4, r4, 34192 ; P9LE-NEXT: ori r4, r4, 34192
; P9LE-NEXT: sldi r4, r4, 32 ; P9LE-NEXT: sldi r4, r4, 32
; P9LE-NEXT: oris r4, r4, 45590 ; P9LE-NEXT: oris r4, r4, 45590
; P9LE-NEXT: mfvsrld r3, v3 ; P9LE-NEXT: mfvsrld r3, v3
; P9LE-NEXT: ori r4, r4, 17097 ; P9LE-NEXT: ori r4, r4, 17097
; P9LE-NEXT: mulhdu r4, r3, r4 ; P9LE-NEXT: mulhdu r4, r3, r4
; P9LE-NEXT: sub r5, r3, r4 ; P9LE-NEXT: sub r5, r3, r4
; P9LE-NEXT: rldicl r5, r5, 63, 1 ; P9LE-NEXT: srdi r5, r5, 1
; P9LE-NEXT: add r4, r5, r4 ; P9LE-NEXT: add r4, r5, r4
; P9LE-NEXT: lis r5, -16037 ; P9LE-NEXT: lis r5, -16037
; P9LE-NEXT: rldicl r4, r4, 60, 4 ; P9LE-NEXT: srdi r4, r4, 4
; P9LE-NEXT: ori r5, r5, 28749 ; P9LE-NEXT: ori r5, r5, 28749
; P9LE-NEXT: mulli r4, r4, 23 ; P9LE-NEXT: mulli r4, r4, 23
; P9LE-NEXT: sldi r5, r5, 32 ; P9LE-NEXT: sldi r5, r5, 32
; P9LE-NEXT: oris r5, r5, 52170 ; P9LE-NEXT: oris r5, r5, 52170
; P9LE-NEXT: ori r5, r5, 12109 ; P9LE-NEXT: ori r5, r5, 12109
; P9LE-NEXT: sub r3, r3, r4 ; P9LE-NEXT: sub r3, r3, r4
; P9LE-NEXT: mfvsrd r4, v3 ; P9LE-NEXT: mfvsrd r4, v3
; P9LE-NEXT: mulhdu r5, r4, r5 ; P9LE-NEXT: mulhdu r5, r4, r5
; P9LE-NEXT: rldicl r5, r5, 52, 12 ; P9LE-NEXT: srdi r5, r5, 12
; P9LE-NEXT: mulli r5, r5, 5423 ; P9LE-NEXT: mulli r5, r5, 5423
; P9LE-NEXT: sub r4, r4, r5 ; P9LE-NEXT: sub r4, r4, r5
; P9LE-NEXT: lis r5, 25653 ; P9LE-NEXT: lis r5, 25653
; P9LE-NEXT: ori r5, r5, 15432 ; P9LE-NEXT: ori r5, r5, 15432
; P9LE-NEXT: sldi r5, r5, 32 ; P9LE-NEXT: sldi r5, r5, 32
; P9LE-NEXT: mtvsrdd v3, r4, r3 ; P9LE-NEXT: mtvsrdd v3, r4, r3
; P9LE-NEXT: mfvsrd r3, v2 ; P9LE-NEXT: mfvsrd r3, v2
; P9LE-NEXT: rldicl r4, r3, 63, 1 ; P9LE-NEXT: srdi r4, r3, 1
; P9LE-NEXT: oris r5, r5, 1603 ; P9LE-NEXT: oris r5, r5, 1603
; P9LE-NEXT: ori r5, r5, 21445 ; P9LE-NEXT: ori r5, r5, 21445
; P9LE-NEXT: mulhdu r4, r4, r5 ; P9LE-NEXT: mulhdu r4, r4, r5
; P9LE-NEXT: rldicl r4, r4, 57, 7 ; P9LE-NEXT: srdi r4, r4, 7
; P9LE-NEXT: mulli r4, r4, 654 ; P9LE-NEXT: mulli r4, r4, 654
; P9LE-NEXT: sub r3, r3, r4 ; P9LE-NEXT: sub r3, r3, r4
; P9LE-NEXT: li r4, 0 ; P9LE-NEXT: li r4, 0
; P9LE-NEXT: mtvsrdd v2, r3, r4 ; P9LE-NEXT: mtvsrdd v2, r3, r4
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P9BE-LABEL: dont_fold_urem_i64: ; P9BE-LABEL: dont_fold_urem_i64:
; P9BE: # %bb.0: ; P9BE: # %bb.0:
; P9BE-NEXT: lis r4, 25644 ; P9BE-NEXT: lis r4, 25644
; P9BE-NEXT: ori r4, r4, 34192 ; P9BE-NEXT: ori r4, r4, 34192
; P9BE-NEXT: sldi r4, r4, 32 ; P9BE-NEXT: sldi r4, r4, 32
; P9BE-NEXT: oris r4, r4, 45590 ; P9BE-NEXT: oris r4, r4, 45590
; P9BE-NEXT: mfvsrd r3, v3 ; P9BE-NEXT: mfvsrd r3, v3
; P9BE-NEXT: ori r4, r4, 17097 ; P9BE-NEXT: ori r4, r4, 17097
; P9BE-NEXT: mulhdu r4, r3, r4 ; P9BE-NEXT: mulhdu r4, r3, r4
; P9BE-NEXT: sub r5, r3, r4 ; P9BE-NEXT: sub r5, r3, r4
; P9BE-NEXT: rldicl r5, r5, 63, 1 ; P9BE-NEXT: srdi r5, r5, 1
; P9BE-NEXT: add r4, r5, r4 ; P9BE-NEXT: add r4, r5, r4
; P9BE-NEXT: lis r5, -16037 ; P9BE-NEXT: lis r5, -16037
; P9BE-NEXT: rldicl r4, r4, 60, 4 ; P9BE-NEXT: srdi r4, r4, 4
; P9BE-NEXT: mulli r4, r4, 23 ; P9BE-NEXT: mulli r4, r4, 23
; P9BE-NEXT: ori r5, r5, 28749 ; P9BE-NEXT: ori r5, r5, 28749
; P9BE-NEXT: sldi r5, r5, 32 ; P9BE-NEXT: sldi r5, r5, 32
; P9BE-NEXT: oris r5, r5, 52170 ; P9BE-NEXT: oris r5, r5, 52170
; P9BE-NEXT: ori r5, r5, 12109 ; P9BE-NEXT: ori r5, r5, 12109
; P9BE-NEXT: sub r3, r3, r4 ; P9BE-NEXT: sub r3, r3, r4
; P9BE-NEXT: mfvsrld r4, v3 ; P9BE-NEXT: mfvsrld r4, v3
; P9BE-NEXT: mulhdu r5, r4, r5 ; P9BE-NEXT: mulhdu r5, r4, r5
; P9BE-NEXT: rldicl r5, r5, 52, 12 ; P9BE-NEXT: srdi r5, r5, 12
; P9BE-NEXT: mulli r5, r5, 5423 ; P9BE-NEXT: mulli r5, r5, 5423
; P9BE-NEXT: sub r4, r4, r5 ; P9BE-NEXT: sub r4, r4, r5
; P9BE-NEXT: lis r5, 25653 ; P9BE-NEXT: lis r5, 25653
; P9BE-NEXT: ori r5, r5, 15432 ; P9BE-NEXT: ori r5, r5, 15432
; P9BE-NEXT: sldi r5, r5, 32 ; P9BE-NEXT: sldi r5, r5, 32
; P9BE-NEXT: mtvsrdd v3, r3, r4 ; P9BE-NEXT: mtvsrdd v3, r3, r4
; P9BE-NEXT: mfvsrld r3, v2 ; P9BE-NEXT: mfvsrld r3, v2
; P9BE-NEXT: rldicl r4, r3, 63, 1 ; P9BE-NEXT: srdi r4, r3, 1
; P9BE-NEXT: oris r5, r5, 1603 ; P9BE-NEXT: oris r5, r5, 1603
; P9BE-NEXT: ori r5, r5, 21445 ; P9BE-NEXT: ori r5, r5, 21445
; P9BE-NEXT: mulhdu r4, r4, r5 ; P9BE-NEXT: mulhdu r4, r4, r5
; P9BE-NEXT: rldicl r4, r4, 57, 7 ; P9BE-NEXT: srdi r4, r4, 7
; P9BE-NEXT: mulli r4, r4, 654 ; P9BE-NEXT: mulli r4, r4, 654
; P9BE-NEXT: sub r3, r3, r4 ; P9BE-NEXT: sub r3, r3, r4
; P9BE-NEXT: mtvsrdd v2, 0, r3 ; P9BE-NEXT: mtvsrdd v2, 0, r3
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; ;
; P8LE-LABEL: dont_fold_urem_i64: ; P8LE-LABEL: dont_fold_urem_i64:
; P8LE: # %bb.0: ; P8LE: # %bb.0:
; P8LE-NEXT: lis r3, 25644 ; P8LE-NEXT: lis r3, 25644
Show All 10 Lines
; P8LE-NEXT: oris r3, r3, 45590 ; P8LE-NEXT: oris r3, r3, 45590
; P8LE-NEXT: mffprd r7, f0 ; P8LE-NEXT: mffprd r7, f0
; P8LE-NEXT: sldi r5, r5, 32 ; P8LE-NEXT: sldi r5, r5, 32
; P8LE-NEXT: oris r4, r4, 52170 ; P8LE-NEXT: oris r4, r4, 52170
; P8LE-NEXT: ori r3, r3, 17097 ; P8LE-NEXT: ori r3, r3, 17097
; P8LE-NEXT: oris r5, r5, 1603 ; P8LE-NEXT: oris r5, r5, 1603
; P8LE-NEXT: ori r4, r4, 12109 ; P8LE-NEXT: ori r4, r4, 12109
; P8LE-NEXT: mulhdu r3, r7, r3 ; P8LE-NEXT: mulhdu r3, r7, r3
; P8LE-NEXT: rldicl r9, r6, 63, 1 ; P8LE-NEXT: srdi r9, r6, 1
; P8LE-NEXT: ori r5, r5, 21445 ; P8LE-NEXT: ori r5, r5, 21445
; P8LE-NEXT: mulhdu r4, r8, r4 ; P8LE-NEXT: mulhdu r4, r8, r4
; P8LE-NEXT: mulhdu r5, r9, r5 ; P8LE-NEXT: mulhdu r5, r9, r5
; P8LE-NEXT: sub r9, r7, r3 ; P8LE-NEXT: sub r9, r7, r3
; P8LE-NEXT: rldicl r9, r9, 63, 1 ; P8LE-NEXT: srdi r9, r9, 1
; P8LE-NEXT: rldicl r4, r4, 52, 12 ; P8LE-NEXT: srdi r4, r4, 12
; P8LE-NEXT: add r3, r9, r3 ; P8LE-NEXT: add r3, r9, r3
; P8LE-NEXT: rldicl r5, r5, 57, 7 ; P8LE-NEXT: srdi r5, r5, 7
; P8LE-NEXT: mulli r4, r4, 5423 ; P8LE-NEXT: mulli r4, r4, 5423
; P8LE-NEXT: rldicl r3, r3, 60, 4 ; P8LE-NEXT: srdi r3, r3, 4
; P8LE-NEXT: mulli r5, r5, 654 ; P8LE-NEXT: mulli r5, r5, 654
; P8LE-NEXT: mulli r3, r3, 23 ; P8LE-NEXT: mulli r3, r3, 23
; P8LE-NEXT: sub r4, r8, r4 ; P8LE-NEXT: sub r4, r8, r4
; P8LE-NEXT: sub r5, r6, r5 ; P8LE-NEXT: sub r5, r6, r5
; P8LE-NEXT: mtfprd f0, r4 ; P8LE-NEXT: mtfprd f0, r4
; P8LE-NEXT: sub r3, r7, r3 ; P8LE-NEXT: sub r3, r7, r3
; P8LE-NEXT: li r4, 0 ; P8LE-NEXT: li r4, 0
; P8LE-NEXT: mtfprd f1, r5 ; P8LE-NEXT: mtfprd f1, r5
Show All 22 Lines
; P8BE-NEXT: oris r4, r4, 52170 ; P8BE-NEXT: oris r4, r4, 52170
; P8BE-NEXT: ori r3, r3, 17097 ; P8BE-NEXT: ori r3, r3, 17097
; P8BE-NEXT: mffprd r8, f1 ; P8BE-NEXT: mffprd r8, f1
; P8BE-NEXT: oris r5, r5, 1603 ; P8BE-NEXT: oris r5, r5, 1603
; P8BE-NEXT: ori r4, r4, 12109 ; P8BE-NEXT: ori r4, r4, 12109
; P8BE-NEXT: mulhdu r3, r6, r3 ; P8BE-NEXT: mulhdu r3, r6, r3
; P8BE-NEXT: ori r5, r5, 21445 ; P8BE-NEXT: ori r5, r5, 21445
; P8BE-NEXT: mulhdu r4, r7, r4 ; P8BE-NEXT: mulhdu r4, r7, r4
; P8BE-NEXT: rldicl r9, r8, 63, 1 ; P8BE-NEXT: srdi r9, r8, 1
; P8BE-NEXT: mulhdu r5, r9, r5 ; P8BE-NEXT: mulhdu r5, r9, r5
; P8BE-NEXT: sub r9, r6, r3 ; P8BE-NEXT: sub r9, r6, r3
; P8BE-NEXT: rldicl r9, r9, 63, 1 ; P8BE-NEXT: srdi r9, r9, 1
; P8BE-NEXT: rldicl r4, r4, 52, 12 ; P8BE-NEXT: srdi r4, r4, 12
; P8BE-NEXT: add r3, r9, r3 ; P8BE-NEXT: add r3, r9, r3
; P8BE-NEXT: mulli r4, r4, 5423 ; P8BE-NEXT: mulli r4, r4, 5423
; P8BE-NEXT: rldicl r5, r5, 57, 7 ; P8BE-NEXT: srdi r5, r5, 7
; P8BE-NEXT: rldicl r3, r3, 60, 4 ; P8BE-NEXT: srdi r3, r3, 4
; P8BE-NEXT: mulli r5, r5, 654 ; P8BE-NEXT: mulli r5, r5, 654
; P8BE-NEXT: mulli r3, r3, 23 ; P8BE-NEXT: mulli r3, r3, 23
; P8BE-NEXT: sub r4, r7, r4 ; P8BE-NEXT: sub r4, r7, r4
; P8BE-NEXT: mtfprd f0, r4 ; P8BE-NEXT: mtfprd f0, r4
; P8BE-NEXT: sub r4, r8, r5 ; P8BE-NEXT: sub r4, r8, r5
; P8BE-NEXT: sub r3, r6, r3 ; P8BE-NEXT: sub r3, r6, r3
; P8BE-NEXT: mtfprd f1, r4 ; P8BE-NEXT: mtfprd f1, r4
; P8BE-NEXT: li r4, 0 ; P8BE-NEXT: li r4, 0
; P8BE-NEXT: mtfprd f2, r3 ; P8BE-NEXT: mtfprd f2, r3
; P8BE-NEXT: mtfprd f3, r4 ; P8BE-NEXT: mtfprd f3, r4
; P8BE-NEXT: xxmrghd v3, vs2, vs0 ; P8BE-NEXT: xxmrghd v3, vs2, vs0
; P8BE-NEXT: xxmrghd v2, vs3, vs1 ; P8BE-NEXT: xxmrghd v2, vs3, vs1
; P8BE-NEXT: blr ; P8BE-NEXT: blr
%1 = urem <4 x i64> %x, <i64 1, i64 654, i64 23, i64 5423> %1 = urem <4 x i64> %x, <i64 1, i64 654, i64 23, i64 5423>
ret <4 x i64> %1 ret <4 x i64> %1
} }

llvm/test/CodeGen/PowerPC/variable_elem_vec_extracts.ll

Show All 17 Lines
; CHECK-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] ; CHECK-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]]
; CHECK-DAG: vperm [[PERMVEC:[0-9]+]], 2, 2, [[SHMSKREG]] ; CHECK-DAG: vperm [[PERMVEC:[0-9]+]], 2, 2, [[SHMSKREG]]
; CHECK-DAG: li [[ONEREG:[0-9]+]], 1 ; CHECK-DAG: li [[ONEREG:[0-9]+]], 1
; CHECK-DAG: and [[ELEMSREG:[0-9]+]], [[ONEREG]], 5 ; CHECK-DAG: and [[ELEMSREG:[0-9]+]], [[ONEREG]], 5
; CHECK-DAG: sldi [[SHAMREG:[0-9]+]], [[ELEMSREG]], 5 ; CHECK-DAG: sldi [[SHAMREG:[0-9]+]], [[ELEMSREG]], 5
; CHECK: mfvsrd [[TOGPR:[0-9]+]], ; CHECK: mfvsrd [[TOGPR:[0-9]+]],
; CHECK: srd [[RSHREG:[0-9]+]], [[TOGPR]], [[SHAMREG]] ; CHECK: srd [[RSHREG:[0-9]+]], [[TOGPR]], [[SHAMREG]]
; CHECK: extsw 3, [[RSHREG]] ; CHECK: extsw 3, [[RSHREG]]
; CHECK-P7-DAG: rlwinm [[ELEMOFFREG:[0-9]+]], 5, 2, 28, 29 ; CHECK-P7-DAG: clrlslwi [[ELEMOFFREG:[0-9]+]], 5, 30, 2
; CHECK-P7-DAG: stxvw4x 34, ; CHECK-P7-DAG: stxvw4x 34,
; CHECK-P7: lwax 3, 3, [[ELEMOFFREG]] ; CHECK-P7: lwax 3, 3, [[ELEMOFFREG]]
; CHECK-BE-DAG: andi. [[ANDREG:[0-9]+]], 5, 2 ; CHECK-BE-DAG: andi. [[ANDREG:[0-9]+]], 5, 2
; CHECK-BE-DAG: sldi [[SLREG:[0-9]+]], [[ANDREG]], 2 ; CHECK-BE-DAG: sldi [[SLREG:[0-9]+]], [[ANDREG]], 2
; CHECK-BE-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]] ; CHECK-BE-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]]
; CHECK-BE-DAG: vperm {{[0-9]+}}, 2, 2, [[SHMSKREG]] ; CHECK-BE-DAG: vperm {{[0-9]+}}, 2, 2, [[SHMSKREG]]
; CHECK-BE-DAG: li [[IMMREG:[0-9]+]], 1 ; CHECK-BE-DAG: li [[IMMREG:[0-9]+]], 1
; CHECK-BE-DAG: andc [[ANDCREG:[0-9]+]], [[IMMREG]], 5 ; CHECK-BE-DAG: andc [[ANDCREG:[0-9]+]], [[IMMREG]], 5
Show All 12 Lines
; CHECK-P7-LABEL: @getl ; CHECK-P7-LABEL: @getl
; CHECK-BE-LABEL: @getl ; CHECK-BE-LABEL: @getl
; CHECK-DAG: li [[TRUNCREG:[0-9]+]], 1 ; CHECK-DAG: li [[TRUNCREG:[0-9]+]], 1
; CHECK-DAG: andc [[MASKREG:[0-9]+]], [[TRUNCREG]], 5 ; CHECK-DAG: andc [[MASKREG:[0-9]+]], [[TRUNCREG]], 5
; CHECK-DAG: sldi [[SHIFTREG:[0-9]+]], [[MASKREG]], 3 ; CHECK-DAG: sldi [[SHIFTREG:[0-9]+]], [[MASKREG]], 3
; CHECK-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] ; CHECK-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]]
; CHECK-DAG: vperm [[PERMVEC:[0-9]+]], 2, 2, [[SHMSKREG]] ; CHECK-DAG: vperm [[PERMVEC:[0-9]+]], 2, 2, [[SHMSKREG]]
; CHECK: mfvsrd 3, ; CHECK: mfvsrd 3,
; CHECK-P7-DAG: rlwinm [[ELEMOFFREG:[0-9]+]], 5, 3, 28, 28 ; CHECK-P7-DAG: clrlslwi [[ELEMOFFREG:[0-9]+]], 5, 31
; CHECK-P7-DAG: stxvd2x 34, ; CHECK-P7-DAG: stxvd2x 34,
; CHECK-P7: ldx 3, 3, [[ELEMOFFREG]] ; CHECK-P7: ldx 3, 3, [[ELEMOFFREG]]
; CHECK-BE-DAG: andi. [[ANDREG:[0-9]+]], 5, 1 ; CHECK-BE-DAG: andi. [[ANDREG:[0-9]+]], 5, 1
; CHECK-BE-DAG: sldi [[SLREG:[0-9]+]], [[ANDREG]], 3 ; CHECK-BE-DAG: sldi [[SLREG:[0-9]+]], [[ANDREG]], 3
; CHECK-BE-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]] ; CHECK-BE-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]]
; CHECK-BE-DAG: vperm {{[0-9]+}}, 2, 2, [[SHMSKREG]] ; CHECK-BE-DAG: vperm {{[0-9]+}}, 2, 2, [[SHMSKREG]]
; CHECK-BE: mfvsrd 3, ; CHECK-BE: mfvsrd 3,
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define float @getf(<4 x float> %a, i32 signext %b) { define float @getf(<4 x float> %a, i32 signext %b) {
entry: entry:
%vecext = extractelement <4 x float> %a, i32 %b %vecext = extractelement <4 x float> %a, i32 %b
ret float %vecext ret float %vecext
; CHECK-LABEL: @getf ; CHECK-LABEL: @getf
; CHECK-P7-LABEL: @getf ; CHECK-P7-LABEL: @getf
; CHECK-BE-LABEL: @getf ; CHECK-BE-LABEL: @getf
; CHECK: xori [[TRUNCREG:[0-9]+]], 5, 3 ; CHECK: xori [[TRUNCREG:[0-9]+]], 5, 3
; CHECK: sldi [[SHIFTREG:[0-9]+]], [[TRUNCREG]], 2 ; CHECK: sldi [[SHIFTREG:[0-9]+]], [[TRUNCREG]], 2
; CHECK: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] ; CHECK: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]]
; CHECK: vperm {{[0-9]+}}, 2, 2, [[SHMSKREG]] ; CHECK: vperm {{[0-9]+}}, 2, 2, [[SHMSKREG]]
; CHECK: xscvspdpn 1, ; CHECK: xscvspdpn 1,
; CHECK-P7-DAG: rlwinm [[ELEMOFFREG:[0-9]+]], 5, 2, 28, 29 ; CHECK-P7-DAG: clrlslwi [[ELEMOFFREG:[0-9]+]], 5, 30, 2
; CHECK-P7-DAG: stxvw4x 34, ; CHECK-P7-DAG: stxvw4x 34,
; CHECK-P7: lfsx 1, 3, [[ELEMOFFREG]] ; CHECK-P7: lfsx 1, 3, [[ELEMOFFREG]]
; CHECK-BE: sldi [[ELNOREG:[0-9]+]], 5, 2 ; CHECK-BE: sldi [[ELNOREG:[0-9]+]], 5, 2
; CHECK-BE: lvsl [[SHMSKREG:[0-9]+]], 0, [[ELNOREG]] ; CHECK-BE: lvsl [[SHMSKREG:[0-9]+]], 0, [[ELNOREG]]
; CHECK-BE: vperm {{[0-9]+}}, 2, 2, [[SHMSKREG]] ; CHECK-BE: vperm {{[0-9]+}}, 2, 2, [[SHMSKREG]]
; CHECK-BE: xscvspdpn 1, ; CHECK-BE: xscvspdpn 1,
} }
Show All 28 Lines

llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll

Show All 9 Lines
; RUN: FileCheck %s --check-prefix=CHECK-BE ; RUN: FileCheck %s --check-prefix=CHECK-BE
define i64 @test2elt(i32 %a.coerce) local_unnamed_addr #0 { define i64 @test2elt(i32 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt: ; CHECK-P8-LABEL: test2elt:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: mffprd r3, f0 ; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: clrldi r4, r3, 48 ; CHECK-P8-NEXT: clrldi r4, r3, 48
; CHECK-P8-NEXT: rldicl r3, r3, 48, 48 ; CHECK-P8-NEXT: extrdi r3, r3, 16, 32
; CHECK-P8-NEXT: clrlwi r4, r4, 16 ; CHECK-P8-NEXT: clrlwi r4, r4, 16
; CHECK-P8-NEXT: clrlwi r3, r3, 16 ; CHECK-P8-NEXT: clrlwi r3, r3, 16
; CHECK-P8-NEXT: mtfprwz f0, r4 ; CHECK-P8-NEXT: mtfprwz f0, r4
; CHECK-P8-NEXT: mtfprwz f1, r3 ; CHECK-P8-NEXT: mtfprwz f1, r3
; CHECK-P8-NEXT: xscvuxdsp f0, f0 ; CHECK-P8-NEXT: xscvuxdsp f0, f0
; CHECK-P8-NEXT: xscvuxdsp f1, f1 ; CHECK-P8-NEXT: xscvuxdsp f1, f1
; CHECK-P8-NEXT: xscvdpspn vs0, f0 ; CHECK-P8-NEXT: xscvdpspn vs0, f0
; CHECK-P8-NEXT: xscvdpspn vs1, f1 ; CHECK-P8-NEXT: xscvdpspn vs1, f1
▲ Show 20 Lines • Show All 235 Lines • ▼ Show 20 Lines
} }
define i64 @test2elt_signed(i32 %a.coerce) local_unnamed_addr #0 { define i64 @test2elt_signed(i32 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt_signed: ; CHECK-P8-LABEL: test2elt_signed:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: mffprd r3, f0 ; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: clrldi r4, r3, 48 ; CHECK-P8-NEXT: clrldi r4, r3, 48
; CHECK-P8-NEXT: rldicl r3, r3, 48, 48 ; CHECK-P8-NEXT: extrdi r3, r3, 16, 32
; CHECK-P8-NEXT: extsh r4, r4 ; CHECK-P8-NEXT: extsh r4, r4
; CHECK-P8-NEXT: extsh r3, r3 ; CHECK-P8-NEXT: extsh r3, r3
; CHECK-P8-NEXT: mtfprwa f0, r4 ; CHECK-P8-NEXT: mtfprwa f0, r4
; CHECK-P8-NEXT: mtfprwa f1, r3 ; CHECK-P8-NEXT: mtfprwa f1, r3
; CHECK-P8-NEXT: xscvsxdsp f0, f0 ; CHECK-P8-NEXT: xscvsxdsp f0, f0
; CHECK-P8-NEXT: xscvsxdsp f1, f1 ; CHECK-P8-NEXT: xscvsxdsp f1, f1
; CHECK-P8-NEXT: xscvdpspn vs0, f0 ; CHECK-P8-NEXT: xscvdpspn vs0, f0
; CHECK-P8-NEXT: xscvdpspn vs1, f1 ; CHECK-P8-NEXT: xscvdpspn vs1, f1
▲ Show 20 Lines • Show All 224 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll

Show All 9 Lines
; RUN: FileCheck %s --check-prefix=CHECK-BE ; RUN: FileCheck %s --check-prefix=CHECK-BE
define i64 @test2elt(i16 %a.coerce) local_unnamed_addr #0 { define i64 @test2elt(i16 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt: ; CHECK-P8-LABEL: test2elt:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: mffprd r3, f0 ; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: clrldi r4, r3, 56 ; CHECK-P8-NEXT: clrldi r4, r3, 56
; CHECK-P8-NEXT: rldicl r3, r3, 56, 56 ; CHECK-P8-NEXT: extrdi r3, r3, 8, 48
; CHECK-P8-NEXT: clrlwi r4, r4, 24 ; CHECK-P8-NEXT: clrlwi r4, r4, 24
; CHECK-P8-NEXT: clrlwi r3, r3, 24 ; CHECK-P8-NEXT: clrlwi r3, r3, 24
; CHECK-P8-NEXT: mtfprwz f0, r4 ; CHECK-P8-NEXT: mtfprwz f0, r4
; CHECK-P8-NEXT: mtfprwz f1, r3 ; CHECK-P8-NEXT: mtfprwz f1, r3
; CHECK-P8-NEXT: xscvuxdsp f0, f0 ; CHECK-P8-NEXT: xscvuxdsp f0, f0
; CHECK-P8-NEXT: xscvuxdsp f1, f1 ; CHECK-P8-NEXT: xscvuxdsp f1, f1
; CHECK-P8-NEXT: xscvdpspn vs0, f0 ; CHECK-P8-NEXT: xscvdpspn vs0, f0
; CHECK-P8-NEXT: xscvdpspn vs1, f1 ; CHECK-P8-NEXT: xscvdpspn vs1, f1
▲ Show 20 Lines • Show All 251 Lines • ▼ Show 20 Lines
} }
define i64 @test2elt_signed(i16 %a.coerce) local_unnamed_addr #0 { define i64 @test2elt_signed(i16 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt_signed: ; CHECK-P8-LABEL: test2elt_signed:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: mffprd r3, f0 ; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: clrldi r4, r3, 56 ; CHECK-P8-NEXT: clrldi r4, r3, 56
; CHECK-P8-NEXT: rldicl r3, r3, 56, 56 ; CHECK-P8-NEXT: extrdi r3, r3, 8, 48
; CHECK-P8-NEXT: extsb r4, r4 ; CHECK-P8-NEXT: extsb r4, r4
; CHECK-P8-NEXT: extsb r3, r3 ; CHECK-P8-NEXT: extsb r3, r3
; CHECK-P8-NEXT: mtfprwa f0, r4 ; CHECK-P8-NEXT: mtfprwa f0, r4
; CHECK-P8-NEXT: mtfprwa f1, r3 ; CHECK-P8-NEXT: mtfprwa f1, r3
; CHECK-P8-NEXT: xscvsxdsp f0, f0 ; CHECK-P8-NEXT: xscvsxdsp f0, f0
; CHECK-P8-NEXT: xscvsxdsp f1, f1 ; CHECK-P8-NEXT: xscvsxdsp f1, f1
; CHECK-P8-NEXT: xscvdpspn vs0, f0 ; CHECK-P8-NEXT: xscvdpspn vs0, f0
; CHECK-P8-NEXT: xscvdpspn vs1, f1 ; CHECK-P8-NEXT: xscvdpspn vs1, f1
▲ Show 20 Lines • Show All 279 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/vec_extract_p9.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-gnu-linux -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-LE ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-gnu-linux -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-LE
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-gnu-linux -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-BE ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-gnu-linux -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-BE
define zeroext i8 @test1(<16 x i8> %a, i32 signext %index) { define zeroext i8 @test1(<16 x i8> %a, i32 signext %index) {
; CHECK-LE-LABEL: test1: ; CHECK-LE-LABEL: test1:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: vextubrx 3, 5, 2 ; CHECK-LE-NEXT: vextubrx 3, 5, 2
; CHECK-LE-NEXT: clrldi 3, 3, 56 ; CHECK-LE-NEXT: clrldi 3, 3, 56
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
;
; CHECK-BE-LABEL: test1: ; CHECK-BE-LABEL: test1:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: vextublx 3, 5, 2 ; CHECK-BE-NEXT: vextublx 3, 5, 2
; CHECK-BE-NEXT: clrldi 3, 3, 56 ; CHECK-BE-NEXT: clrldi 3, 3, 56
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%vecext = extractelement <16 x i8> %a, i32 %index %vecext = extractelement <16 x i8> %a, i32 %index
ret i8 %vecext ret i8 %vecext
} }
define signext i8 @test2(<16 x i8> %a, i32 signext %index) { define signext i8 @test2(<16 x i8> %a, i32 signext %index) {
; CHECK-LE-LABEL: test2: ; CHECK-LE-LABEL: test2:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: vextubrx 3, 5, 2 ; CHECK-LE-NEXT: vextubrx 3, 5, 2
; CHECK-LE-NEXT: extsb 3, 3 ; CHECK-LE-NEXT: extsb 3, 3
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
;
; CHECK-BE-LABEL: test2: ; CHECK-BE-LABEL: test2:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: vextublx 3, 5, 2 ; CHECK-BE-NEXT: vextublx 3, 5, 2
; CHECK-BE-NEXT: extsb 3, 3 ; CHECK-BE-NEXT: extsb 3, 3
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%vecext = extractelement <16 x i8> %a, i32 %index %vecext = extractelement <16 x i8> %a, i32 %index
ret i8 %vecext ret i8 %vecext
} }
define zeroext i16 @test3(<8 x i16> %a, i32 signext %index) { define zeroext i16 @test3(<8 x i16> %a, i32 signext %index) {
; CHECK-LE-LABEL: test3: ; CHECK-LE-LABEL: test3:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: rlwinm 3, 5, 1, 28, 30 ; CHECK-LE-NEXT: clrlslwi 3, 5, 29, 1
; CHECK-LE-NEXT: vextuhrx 3, 3, 2 ; CHECK-LE-NEXT: vextuhrx 3, 3, 2
; CHECK-LE-NEXT: clrldi 3, 3, 48 ; CHECK-LE-NEXT: clrldi 3, 3, 48
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
;
; CHECK-BE-LABEL: test3: ; CHECK-BE-LABEL: test3:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: rlwinm 3, 5, 1, 28, 30 ; CHECK-BE-NEXT: clrlslwi 3, 5, 29, 1
; CHECK-BE-NEXT: vextuhlx 3, 3, 2 ; CHECK-BE-NEXT: vextuhlx 3, 3, 2
; CHECK-BE-NEXT: clrldi 3, 3, 48 ; CHECK-BE-NEXT: clrldi 3, 3, 48
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%vecext = extractelement <8 x i16> %a, i32 %index %vecext = extractelement <8 x i16> %a, i32 %index
ret i16 %vecext ret i16 %vecext
} }
define signext i16 @test4(<8 x i16> %a, i32 signext %index) { define signext i16 @test4(<8 x i16> %a, i32 signext %index) {
; CHECK-LE-LABEL: test4: ; CHECK-LE-LABEL: test4:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: rlwinm 3, 5, 1, 28, 30 ; CHECK-LE-NEXT: clrlslwi 3, 5, 29, 1
; CHECK-LE-NEXT: vextuhrx 3, 3, 2 ; CHECK-LE-NEXT: vextuhrx 3, 3, 2
; CHECK-LE-NEXT: extsh 3, 3 ; CHECK-LE-NEXT: extsh 3, 3
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
;
; CHECK-BE-LABEL: test4: ; CHECK-BE-LABEL: test4:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: rlwinm 3, 5, 1, 28, 30 ; CHECK-BE-NEXT: clrlslwi 3, 5, 29, 1
; CHECK-BE-NEXT: vextuhlx 3, 3, 2 ; CHECK-BE-NEXT: vextuhlx 3, 3, 2
; CHECK-BE-NEXT: extsh 3, 3 ; CHECK-BE-NEXT: extsh 3, 3
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%vecext = extractelement <8 x i16> %a, i32 %index %vecext = extractelement <8 x i16> %a, i32 %index
ret i16 %vecext ret i16 %vecext
} }
define zeroext i32 @test5(<4 x i32> %a, i32 signext %index) { define zeroext i32 @test5(<4 x i32> %a, i32 signext %index) {
; CHECK-LE-LABEL: test5: ; CHECK-LE-LABEL: test5:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: rlwinm 3, 5, 2, 28, 29 ; CHECK-LE-NEXT: clrlslwi 3, 5, 30, 2
; CHECK-LE-NEXT: vextuwrx 3, 3, 2 ; CHECK-LE-NEXT: vextuwrx 3, 3, 2
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
;
; CHECK-BE-LABEL: test5: ; CHECK-BE-LABEL: test5:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: rlwinm 3, 5, 2, 28, 29 ; CHECK-BE-NEXT: clrlslwi 3, 5, 30, 2
; CHECK-BE-NEXT: vextuwlx 3, 3, 2 ; CHECK-BE-NEXT: vextuwlx 3, 3, 2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%vecext = extractelement <4 x i32> %a, i32 %index %vecext = extractelement <4 x i32> %a, i32 %index
ret i32 %vecext ret i32 %vecext
} }
define signext i32 @test6(<4 x i32> %a, i32 signext %index) { define signext i32 @test6(<4 x i32> %a, i32 signext %index) {
; CHECK-LE-LABEL: test6: ; CHECK-LE-LABEL: test6:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: rlwinm 3, 5, 2, 28, 29 ; CHECK-LE-NEXT: clrlslwi 3, 5, 30, 2
; CHECK-LE-NEXT: vextuwrx 3, 3, 2 ; CHECK-LE-NEXT: vextuwrx 3, 3, 2
; CHECK-LE-NEXT: extsw 3, 3 ; CHECK-LE-NEXT: extsw 3, 3
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
;
; CHECK-BE-LABEL: test6: ; CHECK-BE-LABEL: test6:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: rlwinm 3, 5, 2, 28, 29 ; CHECK-BE-NEXT: clrlslwi 3, 5, 30, 2
; CHECK-BE-NEXT: vextuwlx 3, 3, 2 ; CHECK-BE-NEXT: vextuwlx 3, 3, 2
; CHECK-BE-NEXT: extsw 3, 3 ; CHECK-BE-NEXT: extsw 3, 3
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%vecext = extractelement <4 x i32> %a, i32 %index %vecext = extractelement <4 x i32> %a, i32 %index
ret i32 %vecext ret i32 %vecext
} }
; Test with immediate index ; Test with immediate index
define zeroext i8 @test7(<16 x i8> %a) { define zeroext i8 @test7(<16 x i8> %a) {
; CHECK-LE-LABEL: test7: ; CHECK-LE-LABEL: test7:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: li 3, 1 ; CHECK-LE-NEXT: li 3, 1
; CHECK-LE-NEXT: vextubrx 3, 3, 2 ; CHECK-LE-NEXT: vextubrx 3, 3, 2
; CHECK-LE-NEXT: clrldi 3, 3, 56 ; CHECK-LE-NEXT: clrldi 3, 3, 56
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
;
; CHECK-BE-LABEL: test7: ; CHECK-BE-LABEL: test7:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: li 3, 1 ; CHECK-BE-NEXT: li 3, 1
; CHECK-BE-NEXT: vextublx 3, 3, 2 ; CHECK-BE-NEXT: vextublx 3, 3, 2
; CHECK-BE-NEXT: clrldi 3, 3, 56 ; CHECK-BE-NEXT: clrldi 3, 3, 56
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%vecext = extractelement <16 x i8> %a, i32 1 %vecext = extractelement <16 x i8> %a, i32 1
ret i8 %vecext ret i8 %vecext
} }
define zeroext i16 @test8(<8 x i16> %a) { define zeroext i16 @test8(<8 x i16> %a) {
; CHECK-LE-LABEL: test8: ; CHECK-LE-LABEL: test8:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: li 3, 2 ; CHECK-LE-NEXT: li 3, 2
; CHECK-LE-NEXT: vextuhrx 3, 3, 2 ; CHECK-LE-NEXT: vextuhrx 3, 3, 2
; CHECK-LE-NEXT: clrldi 3, 3, 48 ; CHECK-LE-NEXT: clrldi 3, 3, 48
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
;
; CHECK-BE-LABEL: test8: ; CHECK-BE-LABEL: test8:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: li 3, 2 ; CHECK-BE-NEXT: li 3, 2
; CHECK-BE-NEXT: vextuhlx 3, 3, 2 ; CHECK-BE-NEXT: vextuhlx 3, 3, 2
; CHECK-BE-NEXT: clrldi 3, 3, 48 ; CHECK-BE-NEXT: clrldi 3, 3, 48
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%vecext = extractelement <8 x i16> %a, i32 1 %vecext = extractelement <8 x i16> %a, i32 1
ret i16 %vecext ret i16 %vecext
} }
define zeroext i32 @test9(<4 x i32> %a) { define zeroext i32 @test9(<4 x i32> %a) {
; CHECK-LE-LABEL: test9: ; CHECK-LE-LABEL: test9:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: li 3, 12 ; CHECK-LE-NEXT: li 3, 12
; CHECK-LE-NEXT: vextuwrx 3, 3, 2 ; CHECK-LE-NEXT: vextuwrx 3, 3, 2
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
;
; CHECK-BE-LABEL: test9: ; CHECK-BE-LABEL: test9:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: li 3, 12 ; CHECK-BE-NEXT: li 3, 12
; CHECK-BE-NEXT: vextuwlx 3, 3, 2 ; CHECK-BE-NEXT: vextuwlx 3, 3, 2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%vecext = extractelement <4 x i32> %a, i32 3 %vecext = extractelement <4 x i32> %a, i32 3
ret i32 %vecext ret i32 %vecext
} }

llvm/test/CodeGen/PowerPC/vec_extract_p9_2.ll

Show First 20 Lines • Show All 43 Lines • ▼ Show 20 Linesentry:
%add = add nuw nsw i32 %conv3, %conv14 %add = add nuw nsw i32 %conv3, %conv14
%conv2 = trunc i32 %add to i8 %conv2 = trunc i32 %add to i8
ret i8 %conv2 ret i8 %conv2
} }
define zeroext i16 @test_add3(<8 x i16> %a, i32 signext %index, i16 zeroext %c) { define zeroext i16 @test_add3(<8 x i16> %a, i32 signext %index, i16 zeroext %c) {
; CHECK-LE-LABEL: test_add3: ; CHECK-LE-LABEL: test_add3:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: rlwinm 3, 5, 1, 28, 30 ; CHECK-LE-NEXT: clrlslwi 3, 5, 29, 1
; CHECK-LE-NEXT: vextuhrx 3, 3, 2 ; CHECK-LE-NEXT: vextuhrx 3, 3, 2
; CHECK-LE-NEXT: add 3, 3, 6 ; CHECK-LE-NEXT: add 3, 3, 6
; CHECK-LE-NEXT: clrldi 3, 3, 48 ; CHECK-LE-NEXT: clrldi 3, 3, 48
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
; CHECK-BE-LABEL: test_add3: ; CHECK-BE-LABEL: test_add3:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: rlwinm 3, 5, 1, 28, 30 ; CHECK-BE-NEXT: clrlslwi 3, 5, 29, 1
; CHECK-BE-NEXT: vextuhlx 3, 3, 2 ; CHECK-BE-NEXT: vextuhlx 3, 3, 2
; CHECK-BE-NEXT: add 3, 3, 6 ; CHECK-BE-NEXT: add 3, 3, 6
; CHECK-BE-NEXT: clrldi 3, 3, 48 ; CHECK-BE-NEXT: clrldi 3, 3, 48
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%vecext = extractelement <8 x i16> %a, i32 %index %vecext = extractelement <8 x i16> %a, i32 %index
%conv = zext i16 %vecext to i32 %conv = zext i16 %vecext to i32
%conv1 = zext i16 %c to i32 %conv1 = zext i16 %c to i32
%add = add nuw nsw i32 %conv, %conv1 %add = add nuw nsw i32 %conv, %conv1
%conv2 = trunc i32 %add to i16 %conv2 = trunc i32 %add to i16
ret i16 %conv2 ret i16 %conv2
} }
define signext i16 @test_add4(<8 x i16> %a, i32 signext %index, i16 signext %c) { define signext i16 @test_add4(<8 x i16> %a, i32 signext %index, i16 signext %c) {
; CHECK-LE-LABEL: test_add4: ; CHECK-LE-LABEL: test_add4:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: rlwinm 3, 5, 1, 28, 30 ; CHECK-LE-NEXT: clrlslwi 3, 5, 29, 1
; CHECK-LE-NEXT: vextuhrx 3, 3, 2 ; CHECK-LE-NEXT: vextuhrx 3, 3, 2
; CHECK-LE-NEXT: add 3, 3, 6 ; CHECK-LE-NEXT: add 3, 3, 6
; CHECK-LE-NEXT: extsh 3, 3 ; CHECK-LE-NEXT: extsh 3, 3
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
; CHECK-BE-LABEL: test_add4: ; CHECK-BE-LABEL: test_add4:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: rlwinm 3, 5, 1, 28, 30 ; CHECK-BE-NEXT: clrlslwi 3, 5, 29, 1
; CHECK-BE-NEXT: vextuhlx 3, 3, 2 ; CHECK-BE-NEXT: vextuhlx 3, 3, 2
; CHECK-BE-NEXT: add 3, 3, 6 ; CHECK-BE-NEXT: add 3, 3, 6
; CHECK-BE-NEXT: extsh 3, 3 ; CHECK-BE-NEXT: extsh 3, 3
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%vecext = extractelement <8 x i16> %a, i32 %index %vecext = extractelement <8 x i16> %a, i32 %index
%conv5 = zext i16 %vecext to i32 %conv5 = zext i16 %vecext to i32
%conv16 = zext i16 %c to i32 %conv16 = zext i16 %c to i32
%add = add nuw nsw i32 %conv5, %conv16 %add = add nuw nsw i32 %conv5, %conv16
%conv2 = trunc i32 %add to i16 %conv2 = trunc i32 %add to i16
ret i16 %conv2 ret i16 %conv2
} }
define zeroext i32 @test_add5(<4 x i32> %a, i32 signext %index, i32 zeroext %c) { define zeroext i32 @test_add5(<4 x i32> %a, i32 signext %index, i32 zeroext %c) {
; CHECK-LE-LABEL: test_add5: ; CHECK-LE-LABEL: test_add5:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: rlwinm 3, 5, 2, 28, 29 ; CHECK-LE-NEXT: clrlslwi 3, 5, 30, 2
; CHECK-LE-NEXT: vextuwrx 3, 3, 2 ; CHECK-LE-NEXT: vextuwrx 3, 3, 2
; CHECK-LE-NEXT: add 3, 3, 6 ; CHECK-LE-NEXT: add 3, 3, 6
; CHECK-LE-NEXT: clrldi 3, 3, 32 ; CHECK-LE-NEXT: clrldi 3, 3, 32
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
; CHECK-BE-LABEL: test_add5: ; CHECK-BE-LABEL: test_add5:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: rlwinm 3, 5, 2, 28, 29 ; CHECK-BE-NEXT: clrlslwi 3, 5, 30, 2
; CHECK-BE-NEXT: vextuwlx 3, 3, 2 ; CHECK-BE-NEXT: vextuwlx 3, 3, 2
; CHECK-BE-NEXT: add 3, 3, 6 ; CHECK-BE-NEXT: add 3, 3, 6
; CHECK-BE-NEXT: clrldi 3, 3, 32 ; CHECK-BE-NEXT: clrldi 3, 3, 32
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%vecext = extractelement <4 x i32> %a, i32 %index %vecext = extractelement <4 x i32> %a, i32 %index
%add = add i32 %vecext, %c %add = add i32 %vecext, %c
ret i32 %add ret i32 %add
} }
define signext i32 @test_add6(<4 x i32> %a, i32 signext %index, i32 signext %c) { define signext i32 @test_add6(<4 x i32> %a, i32 signext %index, i32 signext %c) {
; CHECK-LE-LABEL: test_add6: ; CHECK-LE-LABEL: test_add6:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: rlwinm 3, 5, 2, 28, 29 ; CHECK-LE-NEXT: clrlslwi 3, 5, 30, 2
; CHECK-LE-NEXT: vextuwrx 3, 3, 2 ; CHECK-LE-NEXT: vextuwrx 3, 3, 2
; CHECK-LE-NEXT: add 3, 3, 6 ; CHECK-LE-NEXT: add 3, 3, 6
; CHECK-LE-NEXT: extsw 3, 3 ; CHECK-LE-NEXT: extsw 3, 3
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
; CHECK-BE-LABEL: test_add6: ; CHECK-BE-LABEL: test_add6:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: rlwinm 3, 5, 2, 28, 29 ; CHECK-BE-NEXT: clrlslwi 3, 5, 30, 2
; CHECK-BE-NEXT: vextuwlx 3, 3, 2 ; CHECK-BE-NEXT: vextuwlx 3, 3, 2
; CHECK-BE-NEXT: add 3, 3, 6 ; CHECK-BE-NEXT: add 3, 3, 6
; CHECK-BE-NEXT: extsw 3, 3 ; CHECK-BE-NEXT: extsw 3, 3
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%vecext = extractelement <4 x i32> %a, i32 %index %vecext = extractelement <4 x i32> %a, i32 %index
%add = add nsw i32 %vecext, %c %add = add nsw i32 %vecext, %c
ret i32 %add ret i32 %add
▲ Show 20 Lines • Show All 112 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/vector-rotates.ll

Show First 20 Lines • Show All 108 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P7-LABEL: rotl_v2i64: ; CHECK-P7-LABEL: rotl_v2i64:
; CHECK-P7: # %bb.0: # %entry ; CHECK-P7: # %bb.0: # %entry
; CHECK-P7-NEXT: addi r3, r1, -48 ; CHECK-P7-NEXT: addi r3, r1, -48
; CHECK-P7-NEXT: stxvd2x vs34, 0, r3 ; CHECK-P7-NEXT: stxvd2x vs34, 0, r3
; CHECK-P7-NEXT: ld r3, -40(r1) ; CHECK-P7-NEXT: ld r3, -40(r1)
; CHECK-P7-NEXT: sldi r4, r3, 53 ; CHECK-P7-NEXT: sldi r4, r3, 53
; CHECK-P7-NEXT: rldicl r3, r3, 53, 11 ; CHECK-P7-NEXT: srdi r3, r3, 11
; CHECK-P7-NEXT: std r4, -8(r1) ; CHECK-P7-NEXT: std r4, -8(r1)
; CHECK-P7-NEXT: ld r4, -48(r1) ; CHECK-P7-NEXT: ld r4, -48(r1)
; CHECK-P7-NEXT: sldi r5, r4, 41 ; CHECK-P7-NEXT: sldi r5, r4, 41
; CHECK-P7-NEXT: rldicl r4, r4, 41, 23 ; CHECK-P7-NEXT: srdi r4, r4, 23
; CHECK-P7-NEXT: std r5, -16(r1) ; CHECK-P7-NEXT: std r5, -16(r1)
; CHECK-P7-NEXT: addi r5, r1, -16 ; CHECK-P7-NEXT: addi r5, r1, -16
; CHECK-P7-NEXT: lxvw4x vs0, 0, r5 ; CHECK-P7-NEXT: lxvw4x vs0, 0, r5
; CHECK-P7-NEXT: std r3, -24(r1) ; CHECK-P7-NEXT: std r3, -24(r1)
; CHECK-P7-NEXT: addi r3, r1, -32 ; CHECK-P7-NEXT: addi r3, r1, -32
; CHECK-P7-NEXT: std r4, -32(r1) ; CHECK-P7-NEXT: std r4, -32(r1)
; CHECK-P7-NEXT: lxvw4x vs1, 0, r3 ; CHECK-P7-NEXT: lxvw4x vs1, 0, r3
; CHECK-P7-NEXT: xxlor vs34, vs0, vs1 ; CHECK-P7-NEXT: xxlor vs34, vs0, vs1
; CHECK-P7-NEXT: blr ; CHECK-P7-NEXT: blr
entry: entry:
%b = shl <2 x i64> %a, <i64 41, i64 53> %b = shl <2 x i64> %a, <i64 41, i64 53>
%c = lshr <2 x i64> %a, <i64 23, i64 11> %c = lshr <2 x i64> %a, <i64 23, i64 11>
%d = or <2 x i64> %b, %c %d = or <2 x i64> %b, %c
ret <2 x i64> %d ret <2 x i64> %d
} }

llvm/test/CodeGen/PowerPC/zext-bitperm.ll

; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu | FileCheck %s ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu | FileCheck %s
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s
; Test case for PPCTargetLowering::extendSubTreeForBitPermutation. ; Test case for PPCTargetLowering::extendSubTreeForBitPermutation.
; We expect mask and rotate are folded into a rlwinm instruction. ; We expect mask and rotate are folded into a rlwinm instruction.
define zeroext i32 @func(i32* %p, i32 zeroext %i) { define zeroext i32 @func(i32* %p, i32 zeroext %i) {
; CHECK-LABEL: @func ; CHECK-LABEL: @func
; CHECK: addi [[REG1:[0-9]+]], 4, 1 ; CHECK: addi [[REG1:[0-9]+]], 4, 1
; CHECK: rlwinm [[REG2:[0-9]+]], [[REG1]], 2, 22, 29 ; CHECK: clrlslwi [[REG2:[0-9]+]], [[REG1]], 24, 2
; CHECK-NOT: sldi ; CHECK-NOT: sldi
; CHECK: lwzx 3, 3, [[REG2]] ; CHECK: lwzx 3, 3, [[REG2]]
; CHECK: blr ; CHECK: blr
entry: entry:
%add = add i32 %i, 1 %add = add i32 %i, 1
%and = and i32 %add, 255 %and = and i32 %add, 255
%idxprom = zext i32 %and to i64 %idxprom = zext i32 %and to i64
%arrayidx = getelementptr inbounds i32, i32* %p, i64 %idxprom %arrayidx = getelementptr inbounds i32, i32* %p, i64 %idxprom
%0 = load i32, i32* %arrayidx, align 4 %0 = load i32, i32* %arrayidx, align 4
ret i32 %0 ret i32 %0
} }

llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ext.txt

Show First 20 Lines • Show All 2,062 Lines • ▼ Show 20 Lines
0x0b 0xe3 0x00 0x04 0x0b 0xe3 0x00 0x04
# CHECK: tdu 3, 4 # CHECK: tdu 3, 4
0x7f 0xe3 0x20 0x88 0x7f 0xe3 0x20 0x88
# CHECK: trap # CHECK: trap
0x7f 0xe0 0x00 0x08 0x7f 0xe0 0x00 0x08
# CHECK: rldicr 2, 3, 5, 3 # CHECK: extldi 2, 3, 4, 5
0x78 0x62 0x28 0xc4 0x78 0x62 0x28 0xc4
# CHECK: rldicr. 2, 3, 5, 3 # CHECK: extldi. 2, 3, 4, 5
0x78 0x62 0x28 0xc5 0x78 0x62 0x28 0xc5
# CHECK: rldicl 2, 3, 9, 60 # CHECK: extrdi 2, 3, 4, 5
0x78 0x62 0x4f 0x20 0x78 0x62 0x4f 0x20
# CHECK: rldicl. 2, 3, 9, 60 # CHECK: extrdi. 2, 3, 4, 5
0x78 0x62 0x4f 0x21 0x78 0x62 0x4f 0x21
# CHECK: rldimi 2, 3, 55, 5 # CHECK: insrdi 2, 3, 4, 5
0x78 0x62 0xb9 0x4e 0x78 0x62 0xb9 0x4e
# CHECK: rldimi. 2, 3, 55, 5 # CHECK: insrdi. 2, 3, 4, 5
0x78 0x62 0xb9 0x4f 0x78 0x62 0xb9 0x4f
# CHECK: rotldi 2, 3, 4 # CHECK: rotldi 2, 3, 4
0x78 0x62 0x20 0x00 0x78 0x62 0x20 0x00
# CHECK: rotldi. 2, 3, 4 # CHECK: rotldi. 2, 3, 4
0x78 0x62 0x20 0x01 0x78 0x62 0x20 0x01
# CHECK: rotldi 2, 3, 60 # CHECK: rotldi 2, 3, 60
0x78 0x62 0xe0 0x02 0x78 0x62 0xe0 0x02
# CHECK: rotldi. 2, 3, 60 # CHECK: rotldi. 2, 3, 60
0x78 0x62 0xe0 0x03 0x78 0x62 0xe0 0x03
# CHECK: rotld 2, 3, 4 # CHECK: rotld 2, 3, 4
0x78 0x62 0x20 0x10 0x78 0x62 0x20 0x10
# CHECK: rotld. 2, 3, 4 # CHECK: rotld. 2, 3, 4
0x78 0x62 0x20 0x11 0x78 0x62 0x20 0x11
# CHECK: sldi 2, 3, 4 # CHECK: sldi 2, 3, 4
0x78 0x62 0x26 0xe4 0x78 0x62 0x26 0xe4
# CHECK: rldicr. 2, 3, 4, 59 # CHECK: sldi. 2, 3, 4
0x78 0x62 0x26 0xe5 0x78 0x62 0x26 0xe5
# CHECK: rldicl 2, 3, 60, 4 # CHECK: srdi 2, 3, 4
0x78 0x62 0xe1 0x02 0x78 0x62 0xe1 0x02
# CHECK: rldicl. 2, 3, 60, 4 # CHECK: srdi. 2, 3, 4
0x78 0x62 0xe1 0x03 0x78 0x62 0xe1 0x03
# CHECK: clrldi 2, 3, 4 # CHECK: clrldi 2, 3, 4
0x78 0x62 0x01 0x00 0x78 0x62 0x01 0x00
# CHECK: clrldi. 2, 3, 4 # CHECK: clrldi. 2, 3, 4
0x78 0x62 0x01 0x01 0x78 0x62 0x01 0x01
# CHECK: rldicr 2, 3, 0, 59 # CHECK: clrrdi 2, 3, 4
0x78 0x62 0x06 0xe4 0x78 0x62 0x06 0xe4
# CHECK: rldicr. 2, 3, 0, 59 # CHECK: clrrdi. 2, 3, 4
0x78 0x62 0x06 0xe5 0x78 0x62 0x06 0xe5
# CHECK: rldic 2, 3, 4, 1 # CHECK: clrlsldi 2, 3, 5, 4
0x78 0x62 0x20 0x48 0x78 0x62 0x20 0x48
# CHECK: rldic. 2, 3, 4, 1 # CHECK: clrlsldi. 2, 3, 5, 4
0x78 0x62 0x20 0x49 0x78 0x62 0x20 0x49
# CHECK: rlwinm 2, 3, 5, 0, 3 # CHECK: extlwi 2, 3, 4, 5
0x54 0x62 0x28 0x06 0x54 0x62 0x28 0x06
# CHECK: rlwinm. 2, 3, 5, 0, 3 # CHECK: extlwi. 2, 3, 4, 5
0x54 0x62 0x28 0x07 0x54 0x62 0x28 0x07
# CHECK: rlwinm 2, 3, 9, 28, 31 # CHECK: extrwi 2, 3, 4, 5
0x54 0x62 0x4f 0x3e 0x54 0x62 0x4f 0x3e
# CHECK: rlwinm. 2, 3, 9, 28, 31 # CHECK: extrwi. 2, 3, 4, 5
0x54 0x62 0x4f 0x3f 0x54 0x62 0x4f 0x3f
# CHECK: rlwimi 2, 3, 27, 5, 8 # CHECK: inslwi 2, 3, 4, 5
0x50 0x62 0xd9 0x50 0x50 0x62 0xd9 0x50
# CHECK: rlwimi. 2, 3, 27, 5, 8 # CHECK: inslwi. 2, 3, 4, 5
0x50 0x62 0xd9 0x51 0x50 0x62 0xd9 0x51
# CHECK: rlwimi 2, 3, 23, 5, 8 # CHECK: insrwi 2, 3, 4, 5
0x50 0x62 0xb9 0x50 0x50 0x62 0xb9 0x50
# CHECK: rlwimi. 2, 3, 23, 5, 8 # CHECK: insrwi. 2, 3, 4, 5
0x50 0x62 0xb9 0x51 0x50 0x62 0xb9 0x51
# CHECK: rotlwi 2, 3, 4 # CHECK: rotlwi 2, 3, 4
0x54 0x62 0x20 0x3e 0x54 0x62 0x20 0x3e
# CHECK: rotlwi. 2, 3, 4 # CHECK: rotlwi. 2, 3, 4
0x54 0x62 0x20 0x3f 0x54 0x62 0x20 0x3f
# CHECK: rotlwi 2, 3, 28 # CHECK: rotlwi 2, 3, 28
0x54 0x62 0xe0 0x3e 0x54 0x62 0xe0 0x3e
# CHECK: rotlwi. 2, 3, 28 # CHECK: rotlwi. 2, 3, 28
0x54 0x62 0xe0 0x3f 0x54 0x62 0xe0 0x3f
# CHECK: rotlw 2, 3, 4 # CHECK: rotlw 2, 3, 4
0x5c 0x62 0x20 0x3e 0x5c 0x62 0x20 0x3e
# CHECK: rotlw. 2, 3, 4 # CHECK: rotlw. 2, 3, 4
0x5c 0x62 0x20 0x3f 0x5c 0x62 0x20 0x3f
# CHECK: slwi 2, 3, 4 # CHECK: slwi 2, 3, 4
0x54 0x62 0x20 0x36 0x54 0x62 0x20 0x36
# CHECK: rlwinm. 2, 3, 4, 0, 27 # CHECK: slwi. 2, 3, 4
0x54 0x62 0x20 0x37 0x54 0x62 0x20 0x37
# CHECK: srwi 2, 3, 4 # CHECK: srwi 2, 3, 4
0x54 0x62 0xe1 0x3e 0x54 0x62 0xe1 0x3e
# CHECK: rlwinm. 2, 3, 28, 4, 31 # CHECK: srwi. 2, 3, 4
0x54 0x62 0xe1 0x3f 0x54 0x62 0xe1 0x3f
# CHECK: clrlwi 2, 3, 4 # CHECK: clrlwi 2, 3, 4
0x54 0x62 0x01 0x3e 0x54 0x62 0x01 0x3e
# CHECK: clrlwi. 2, 3, 4 # CHECK: clrlwi. 2, 3, 4
0x54 0x62 0x01 0x3f 0x54 0x62 0x01 0x3f
# CHECK: rlwinm 2, 3, 0, 0, 27 # CHECK: clrrwi 2, 3, 4
0x54 0x62 0x00 0x36 0x54 0x62 0x00 0x36
# CHECK: rlwinm. 2, 3, 0, 0, 27 # CHECK: clrrwi. 2, 3, 4
0x54 0x62 0x00 0x37 0x54 0x62 0x00 0x37
# CHECK: rlwinm 2, 3, 4, 1, 27 # CHECK: clrlslwi 2, 3, 5, 4
0x54 0x62 0x20 0x76 0x54 0x62 0x20 0x76
# CHECK: rlwinm. 2, 3, 4, 1, 27 # CHECK: clrlslwi. 2, 3, 5, 4
0x54 0x62 0x20 0x77 0x54 0x62 0x20 0x77
# CHECK: mtxer 2 # CHECK: mtxer 2
0x7c 0x41 0x03 0xa6 0x7c 0x41 0x03 0xa6
# CHECK: mfxer 2 # CHECK: mfxer 2
0x7c 0x41 0x02 0xa6 0x7c 0x41 0x02 0xa6
▲ Show 20 Lines • Show All 101 Lines • Show Last 20 Lines

llvm/test/MC/Disassembler/PowerPC/ppc64-encoding.txt

Show First 20 Lines • Show All 739 Lines • ▼ Show 20 Lines
0x50 0x62 0x21 0x4d 0x50 0x62 0x21 0x4d
# CHECK: rldicl 2, 3, 4, 5 # CHECK: rldicl 2, 3, 4, 5
0x78 0x62 0x21 0x40 0x78 0x62 0x21 0x40
# CHECK: rldicl. 2, 3, 4, 5 # CHECK: rldicl. 2, 3, 4, 5
0x78 0x62 0x21 0x41 0x78 0x62 0x21 0x41
# CHECK: rldicr 2, 3, 4, 5 # CHECK: extldi 2, 3, 6, 4
0x78 0x62 0x21 0x44 0x78 0x62 0x21 0x44
# CHECK: rldicr. 2, 3, 4, 5 # CHECK: extldi. 2, 3, 6, 4
0x78 0x62 0x21 0x45 0x78 0x62 0x21 0x45
# CHECK: rldic 2, 3, 4, 5 # CHECK: clrlsldi 2, 3, 9, 4
0x78 0x62 0x21 0x48 0x78 0x62 0x21 0x48
# CHECK: rldic. 2, 3, 4, 5 # CHECK: clrlsldi. 2, 3, 9, 4
0x78 0x62 0x21 0x49 0x78 0x62 0x21 0x49
# CHECK: rldcl 2, 3, 4, 5 # CHECK: rldcl 2, 3, 4, 5
0x78 0x62 0x21 0x50 0x78 0x62 0x21 0x50
# CHECK: rldcl. 2, 3, 4, 5 # CHECK: rldcl. 2, 3, 4, 5
0x78 0x62 0x21 0x51 0x78 0x62 0x21 0x51
# CHECK: rldcr 2, 3, 4, 5 # CHECK: rldcr 2, 3, 4, 5
0x78 0x62 0x21 0x52 0x78 0x62 0x21 0x52
# CHECK: rldcr. 2, 3, 4, 5 # CHECK: rldcr. 2, 3, 4, 5
0x78 0x62 0x21 0x53 0x78 0x62 0x21 0x53
# CHECK: rldimi 2, 3, 4, 5 # CHECK: insrdi 2, 3, 55, 5
0x78 0x62 0x21 0x4c 0x78 0x62 0x21 0x4c
# CHECK: rldimi. 2, 3, 4, 5 # CHECK: insrdi. 2, 3, 55, 5
0x78 0x62 0x21 0x4d 0x78 0x62 0x21 0x4d
# CHECK: slw 2, 3, 4 # CHECK: slw 2, 3, 4
0x7c 0x62 0x20 0x30 0x7c 0x62 0x20 0x30
# CHECK: slw. 2, 3, 4 # CHECK: slw. 2, 3, 4
0x7c 0x62 0x20 0x31 0x7c 0x62 0x20 0x31
▲ Show 20 Lines • Show All 95 Lines • Show Last 20 Lines

llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding.txt

Show First 20 Lines • Show All 694 Lines • ▼ Show 20 Lines
0x4d 0x21 0x62 0x50 0x4d 0x21 0x62 0x50
# CHECK: rldicl 2, 3, 4, 5 # CHECK: rldicl 2, 3, 4, 5
0x40 0x21 0x62 0x78 0x40 0x21 0x62 0x78
# CHECK: rldicl. 2, 3, 4, 5 # CHECK: rldicl. 2, 3, 4, 5
0x41 0x21 0x62 0x78 0x41 0x21 0x62 0x78
# CHECK: rldicr 2, 3, 4, 5 # CHECK: extldi 2, 3, 6, 4
0x44 0x21 0x62 0x78 0x44 0x21 0x62 0x78
# CHECK: rldicr. 2, 3, 4, 5 # CHECK: extldi. 2, 3, 6, 4
0x45 0x21 0x62 0x78 0x45 0x21 0x62 0x78
# CHECK: rldic 2, 3, 4, 5 # CHECK: clrlsldi 2, 3, 9, 4
0x48 0x21 0x62 0x78 0x48 0x21 0x62 0x78
# CHECK: rldic. 2, 3, 4, 5 # CHECK: clrlsldi. 2, 3, 9, 4
0x49 0x21 0x62 0x78 0x49 0x21 0x62 0x78
# CHECK: rldcl 2, 3, 4, 5 # CHECK: rldcl 2, 3, 4, 5
0x50 0x21 0x62 0x78 0x50 0x21 0x62 0x78
# CHECK: rldcl. 2, 3, 4, 5 # CHECK: rldcl. 2, 3, 4, 5
0x51 0x21 0x62 0x78 0x51 0x21 0x62 0x78
# CHECK: rldcr 2, 3, 4, 5 # CHECK: rldcr 2, 3, 4, 5
0x52 0x21 0x62 0x78 0x52 0x21 0x62 0x78
# CHECK: rldcr. 2, 3, 4, 5 # CHECK: rldcr. 2, 3, 4, 5
0x53 0x21 0x62 0x78 0x53 0x21 0x62 0x78
# CHECK: rldimi 2, 3, 4, 5 # CHECK: insrdi 2, 3, 55, 5
0x4c 0x21 0x62 0x78 0x4c 0x21 0x62 0x78
# CHECK: rldimi. 2, 3, 4, 5 # CHECK: insrdi. 2, 3, 55, 5
0x4d 0x21 0x62 0x78 0x4d 0x21 0x62 0x78
# CHECK: slw 2, 3, 4 # CHECK: slw 2, 3, 4
0x30 0x20 0x62 0x7c 0x30 0x20 0x62 0x7c
# CHECK: slw. 2, 3, 4 # CHECK: slw. 2, 3, 4
0x31 0x20 0x62 0x7c 0x31 0x20 0x62 0x7c
▲ Show 20 Lines • Show All 64 Lines • Show Last 20 Lines

llvm/test/MC/PowerPC/ppc64-encoding-ext.s

Show First 20 Lines • Show All 3,265 Lines • ▼ Show 20 Lines# CHECK-LE: tdu 3, 4 # encoding: [0x88,0x20,0xe3,0x7f]
tdu 3, 4 tdu 3, 4
# CHECK-BE: trap # encoding: [0x7f,0xe0,0x00,0x08] # CHECK-BE: trap # encoding: [0x7f,0xe0,0x00,0x08]
# CHECK-LE: trap # encoding: [0x08,0x00,0xe0,0x7f] # CHECK-LE: trap # encoding: [0x08,0x00,0xe0,0x7f]
trap trap
# Rotate and shift mnemonics # Rotate and shift mnemonics
# CHECK-BE: rldicr 2, 3, 5, 3 # encoding: [0x78,0x62,0x28,0xc4] # CHECK-BE: extldi 2, 3, 4, 5 # encoding: [0x78,0x62,0x28,0xc4]
# CHECK-LE: rldicr 2, 3, 5, 3 # encoding: [0xc4,0x28,0x62,0x78] # CHECK-LE: extldi 2, 3, 4, 5 # encoding: [0xc4,0x28,0x62,0x78]
extldi 2, 3, 4, 5 extldi 2, 3, 4, 5
# CHECK-BE: rldicr. 2, 3, 5, 3 # encoding: [0x78,0x62,0x28,0xc5] # CHECK-BE: extldi. 2, 3, 4, 5 # encoding: [0x78,0x62,0x28,0xc5]
# CHECK-LE: rldicr. 2, 3, 5, 3 # encoding: [0xc5,0x28,0x62,0x78] # CHECK-LE: extldi. 2, 3, 4, 5 # encoding: [0xc5,0x28,0x62,0x78]
extldi. 2, 3, 4, 5 extldi. 2, 3, 4, 5
# CHECK-BE: rldicl 2, 3, 9, 60 # encoding: [0x78,0x62,0x4f,0x20] # CHECK-BE: extrdi 2, 3, 4, 5 # encoding: [0x78,0x62,0x4f,0x20]
# CHECK-LE: rldicl 2, 3, 9, 60 # encoding: [0x20,0x4f,0x62,0x78] # CHECK-LE: extrdi 2, 3, 4, 5 # encoding: [0x20,0x4f,0x62,0x78]
extrdi 2, 3, 4, 5 extrdi 2, 3, 4, 5
# CHECK-BE: rldicl. 2, 3, 9, 60 # encoding: [0x78,0x62,0x4f,0x21] # CHECK-BE: extrdi. 2, 3, 4, 5 # encoding: [0x78,0x62,0x4f,0x21]
# CHECK-LE: rldicl. 2, 3, 9, 60 # encoding: [0x21,0x4f,0x62,0x78] # CHECK-LE: extrdi. 2, 3, 4, 5 # encoding: [0x21,0x4f,0x62,0x78]
extrdi. 2, 3, 4, 5 extrdi. 2, 3, 4, 5
# CHECK-BE: rldimi 2, 3, 55, 5 # encoding: [0x78,0x62,0xb9,0x4e] # CHECK-BE: insrdi 2, 3, 4, 5 # encoding: [0x78,0x62,0xb9,0x4e]
# CHECK-LE: rldimi 2, 3, 55, 5 # encoding: [0x4e,0xb9,0x62,0x78] # CHECK-LE: insrdi 2, 3, 4, 5 # encoding: [0x4e,0xb9,0x62,0x78]
insrdi 2, 3, 4, 5 insrdi 2, 3, 4, 5
# CHECK-BE: rldimi. 2, 3, 55, 5 # encoding: [0x78,0x62,0xb9,0x4f] # CHECK-BE: insrdi. 2, 3, 4, 5 # encoding: [0x78,0x62,0xb9,0x4f]
# CHECK-LE: rldimi. 2, 3, 55, 5 # encoding: [0x4f,0xb9,0x62,0x78] # CHECK-LE: insrdi. 2, 3, 4, 5 # encoding: [0x4f,0xb9,0x62,0x78]
insrdi. 2, 3, 4, 5 insrdi. 2, 3, 4, 5
# CHECK-BE: rotldi 2, 3, 4 # encoding: [0x78,0x62,0x20,0x00] # CHECK-BE: rotldi 2, 3, 4 # encoding: [0x78,0x62,0x20,0x00]
# CHECK-LE: rotldi 2, 3, 4 # encoding: [0x00,0x20,0x62,0x78] # CHECK-LE: rotldi 2, 3, 4 # encoding: [0x00,0x20,0x62,0x78]
rotldi 2, 3, 4 rotldi 2, 3, 4
# CHECK-BE: rotldi. 2, 3, 4 # encoding: [0x78,0x62,0x20,0x01] # CHECK-BE: rotldi. 2, 3, 4 # encoding: [0x78,0x62,0x20,0x01]
# CHECK-LE: rotldi. 2, 3, 4 # encoding: [0x01,0x20,0x62,0x78] # CHECK-LE: rotldi. 2, 3, 4 # encoding: [0x01,0x20,0x62,0x78]
rotldi. 2, 3, 4 rotldi. 2, 3, 4
# CHECK-BE: rotldi 2, 3, 60 # encoding: [0x78,0x62,0xe0,0x02] # CHECK-BE: rotldi 2, 3, 60 # encoding: [0x78,0x62,0xe0,0x02]
# CHECK-LE: rotldi 2, 3, 60 # encoding: [0x02,0xe0,0x62,0x78] # CHECK-LE: rotldi 2, 3, 60 # encoding: [0x02,0xe0,0x62,0x78]
rotrdi 2, 3, 4 rotrdi 2, 3, 4
# CHECK-BE: rotldi. 2, 3, 60 # encoding: [0x78,0x62,0xe0,0x03] # CHECK-BE: rotldi. 2, 3, 60 # encoding: [0x78,0x62,0xe0,0x03]
# CHECK-LE: rotldi. 2, 3, 60 # encoding: [0x03,0xe0,0x62,0x78] # CHECK-LE: rotldi. 2, 3, 60 # encoding: [0x03,0xe0,0x62,0x78]
rotrdi. 2, 3, 4 rotrdi. 2, 3, 4
# CHECK-BE: rotld 2, 3, 4 # encoding: [0x78,0x62,0x20,0x10] # CHECK-BE: rotld 2, 3, 4 # encoding: [0x78,0x62,0x20,0x10]
# CHECK-LE: rotld 2, 3, 4 # encoding: [0x10,0x20,0x62,0x78] # CHECK-LE: rotld 2, 3, 4 # encoding: [0x10,0x20,0x62,0x78]
rotld 2, 3, 4 rotld 2, 3, 4
# CHECK-BE: rotld. 2, 3, 4 # encoding: [0x78,0x62,0x20,0x11] # CHECK-BE: rotld. 2, 3, 4 # encoding: [0x78,0x62,0x20,0x11]
# CHECK-LE: rotld. 2, 3, 4 # encoding: [0x11,0x20,0x62,0x78] # CHECK-LE: rotld. 2, 3, 4 # encoding: [0x11,0x20,0x62,0x78]
rotld. 2, 3, 4 rotld. 2, 3, 4
# CHECK-BE: sldi 2, 3, 4 # encoding: [0x78,0x62,0x26,0xe4] # CHECK-BE: sldi 2, 3, 4 # encoding: [0x78,0x62,0x26,0xe4]
# CHECK-LE: sldi 2, 3, 4 # encoding: [0xe4,0x26,0x62,0x78] # CHECK-LE: sldi 2, 3, 4 # encoding: [0xe4,0x26,0x62,0x78]
sldi 2, 3, 4 sldi 2, 3, 4
# CHECK-BE: rldicr. 2, 3, 4, 59 # encoding: [0x78,0x62,0x26,0xe5] # CHECK-BE: sldi. 2, 3, 4 # encoding: [0x78,0x62,0x26,0xe5]
# CHECK-LE: rldicr. 2, 3, 4, 59 # encoding: [0xe5,0x26,0x62,0x78] # CHECK-LE: sldi. 2, 3, 4 # encoding: [0xe5,0x26,0x62,0x78]
sldi. 2, 3, 4 sldi. 2, 3, 4
# CHECK-BE: rldicl 2, 3, 60, 4 # encoding: [0x78,0x62,0xe1,0x02] # CHECK-BE: srdi 2, 3, 4 # encoding: [0x78,0x62,0xe1,0x02]
# CHECK-LE: rldicl 2, 3, 60, 4 # encoding: [0x02,0xe1,0x62,0x78] # CHECK-LE: srdi 2, 3, 4 # encoding: [0x02,0xe1,0x62,0x78]
srdi 2, 3, 4 srdi 2, 3, 4
# CHECK-BE: rldicl. 2, 3, 60, 4 # encoding: [0x78,0x62,0xe1,0x03] # CHECK-BE: srdi. 2, 3, 4 # encoding: [0x78,0x62,0xe1,0x03]
# CHECK-LE: rldicl. 2, 3, 60, 4 # encoding: [0x03,0xe1,0x62,0x78] # CHECK-LE: srdi. 2, 3, 4 # encoding: [0x03,0xe1,0x62,0x78]
srdi. 2, 3, 4 srdi. 2, 3, 4
# CHECK-BE: clrldi 2, 3, 4 # encoding: [0x78,0x62,0x01,0x00] # CHECK-BE: clrldi 2, 3, 4 # encoding: [0x78,0x62,0x01,0x00]
# CHECK-LE: clrldi 2, 3, 4 # encoding: [0x00,0x01,0x62,0x78] # CHECK-LE: clrldi 2, 3, 4 # encoding: [0x00,0x01,0x62,0x78]
clrldi 2, 3, 4 clrldi 2, 3, 4
# CHECK-BE: clrldi. 2, 3, 4 # encoding: [0x78,0x62,0x01,0x01] # CHECK-BE: clrldi. 2, 3, 4 # encoding: [0x78,0x62,0x01,0x01]
# CHECK-LE: clrldi. 2, 3, 4 # encoding: [0x01,0x01,0x62,0x78] # CHECK-LE: clrldi. 2, 3, 4 # encoding: [0x01,0x01,0x62,0x78]
clrldi. 2, 3, 4 clrldi. 2, 3, 4
# CHECK-BE: rldicr 2, 3, 0, 59 # encoding: [0x78,0x62,0x06,0xe4] # CHECK-BE: clrrdi 2, 3, 4 # encoding: [0x78,0x62,0x06,0xe4]
# CHECK-LE: rldicr 2, 3, 0, 59 # encoding: [0xe4,0x06,0x62,0x78] # CHECK-LE: clrrdi 2, 3, 4 # encoding: [0xe4,0x06,0x62,0x78]
clrrdi 2, 3, 4 clrrdi 2, 3, 4
# CHECK-BE: rldicr. 2, 3, 0, 59 # encoding: [0x78,0x62,0x06,0xe5] # CHECK-BE: clrrdi. 2, 3, 4 # encoding: [0x78,0x62,0x06,0xe5]
# CHECK-LE: rldicr. 2, 3, 0, 59 # encoding: [0xe5,0x06,0x62,0x78] # CHECK-LE: clrrdi. 2, 3, 4 # encoding: [0xe5,0x06,0x62,0x78]
clrrdi. 2, 3, 4 clrrdi. 2, 3, 4
# CHECK-BE: rldic 2, 3, 4, 1 # encoding: [0x78,0x62,0x20,0x48] # CHECK-BE: clrlsldi 2, 3, 5, 4 # encoding: [0x78,0x62,0x20,0x48]
# CHECK-LE: rldic 2, 3, 4, 1 # encoding: [0x48,0x20,0x62,0x78] # CHECK-LE: clrlsldi 2, 3, 5, 4 # encoding: [0x48,0x20,0x62,0x78]
clrlsldi 2, 3, 5, 4 clrlsldi 2, 3, 5, 4
# CHECK-BE: rldic. 2, 3, 4, 1 # encoding: [0x78,0x62,0x20,0x49] # CHECK-BE: clrlsldi. 2, 3, 5, 4 # encoding: [0x78,0x62,0x20,0x49]
# CHECK-LE: rldic. 2, 3, 4, 1 # encoding: [0x49,0x20,0x62,0x78] # CHECK-LE: clrlsldi. 2, 3, 5, 4 # encoding: [0x49,0x20,0x62,0x78]
clrlsldi. 2, 3, 5, 4 clrlsldi. 2, 3, 5, 4
# CHECK-BE: rlwinm 2, 3, 5, 0, 3 # encoding: [0x54,0x62,0x28,0x06] # CHECK-BE: extlwi 2, 3, 4, 5 # encoding: [0x54,0x62,0x28,0x06]
# CHECK-LE: rlwinm 2, 3, 5, 0, 3 # encoding: [0x06,0x28,0x62,0x54] # CHECK-LE: extlwi 2, 3, 4, 5 # encoding: [0x06,0x28,0x62,0x54]
extlwi 2, 3, 4, 5 extlwi 2, 3, 4, 5
# CHECK-BE: rlwinm. 2, 3, 5, 0, 3 # encoding: [0x54,0x62,0x28,0x07] # CHECK-BE: extlwi. 2, 3, 4, 5 # encoding: [0x54,0x62,0x28,0x07]
# CHECK-LE: rlwinm. 2, 3, 5, 0, 3 # encoding: [0x07,0x28,0x62,0x54] # CHECK-LE: extlwi. 2, 3, 4, 5 # encoding: [0x07,0x28,0x62,0x54]
extlwi. 2, 3, 4, 5 extlwi. 2, 3, 4, 5
# CHECK-BE: rlwinm 2, 3, 9, 28, 31 # encoding: [0x54,0x62,0x4f,0x3e] # CHECK-BE: extrwi 2, 3, 4, 5 # encoding: [0x54,0x62,0x4f,0x3e]
# CHECK-LE: rlwinm 2, 3, 9, 28, 31 # encoding: [0x3e,0x4f,0x62,0x54] # CHECK-LE: extrwi 2, 3, 4, 5 # encoding: [0x3e,0x4f,0x62,0x54]
extrwi 2, 3, 4, 5 extrwi 2, 3, 4, 5
# CHECK-BE: rlwinm. 2, 3, 9, 28, 31 # encoding: [0x54,0x62,0x4f,0x3f] # CHECK-BE: extrwi. 2, 3, 4, 5 # encoding: [0x54,0x62,0x4f,0x3f]
# CHECK-LE: rlwinm. 2, 3, 9, 28, 31 # encoding: [0x3f,0x4f,0x62,0x54] # CHECK-LE: extrwi. 2, 3, 4, 5 # encoding: [0x3f,0x4f,0x62,0x54]
extrwi. 2, 3, 4, 5 extrwi. 2, 3, 4, 5
# CHECK-BE: rlwimi 2, 3, 27, 5, 8 # encoding: [0x50,0x62,0xd9,0x50] # CHECK-BE: inslwi 2, 3, 4, 5 # encoding: [0x50,0x62,0xd9,0x50]
# CHECK-LE: rlwimi 2, 3, 27, 5, 8 # encoding: [0x50,0xd9,0x62,0x50] # CHECK-LE: inslwi 2, 3, 4, 5 # encoding: [0x50,0xd9,0x62,0x50]
inslwi 2, 3, 4, 5 inslwi 2, 3, 4, 5
# CHECK-BE: rlwimi. 2, 3, 27, 5, 8 # encoding: [0x50,0x62,0xd9,0x51] # CHECK-BE: inslwi. 2, 3, 4, 5 # encoding: [0x50,0x62,0xd9,0x51]
# CHECK-LE: rlwimi. 2, 3, 27, 5, 8 # encoding: [0x51,0xd9,0x62,0x50] # CHECK-LE: inslwi. 2, 3, 4, 5 # encoding: [0x51,0xd9,0x62,0x50]
inslwi. 2, 3, 4, 5 inslwi. 2, 3, 4, 5
# CHECK-BE: rlwimi 2, 3, 23, 5, 8 # encoding: [0x50,0x62,0xb9,0x50] # CHECK-BE: insrwi 2, 3, 4, 5 # encoding: [0x50,0x62,0xb9,0x50]
# CHECK-LE: rlwimi 2, 3, 23, 5, 8 # encoding: [0x50,0xb9,0x62,0x50] # CHECK-LE: insrwi 2, 3, 4, 5 # encoding: [0x50,0xb9,0x62,0x50]
insrwi 2, 3, 4, 5 insrwi 2, 3, 4, 5
# CHECK-BE: rlwimi. 2, 3, 23, 5, 8 # encoding: [0x50,0x62,0xb9,0x51] # CHECK-BE: insrwi. 2, 3, 4, 5 # encoding: [0x50,0x62,0xb9,0x51]
# CHECK-LE: rlwimi. 2, 3, 23, 5, 8 # encoding: [0x51,0xb9,0x62,0x50] # CHECK-LE: insrwi. 2, 3, 4, 5 # encoding: [0x51,0xb9,0x62,0x50]
insrwi. 2, 3, 4, 5 insrwi. 2, 3, 4, 5
# CHECK-BE: rotlwi 2, 3, 4 # encoding: [0x54,0x62,0x20,0x3e] # CHECK-BE: rotlwi 2, 3, 4 # encoding: [0x54,0x62,0x20,0x3e]
# CHECK-LE: rotlwi 2, 3, 4 # encoding: [0x3e,0x20,0x62,0x54] # CHECK-LE: rotlwi 2, 3, 4 # encoding: [0x3e,0x20,0x62,0x54]
rotlwi 2, 3, 4 rotlwi 2, 3, 4
# CHECK-BE: rotlwi. 2, 3, 4 # encoding: [0x54,0x62,0x20,0x3f] # CHECK-BE: rotlwi. 2, 3, 4 # encoding: [0x54,0x62,0x20,0x3f]
# CHECK-LE: rotlwi. 2, 3, 4 # encoding: [0x3f,0x20,0x62,0x54] # CHECK-LE: rotlwi. 2, 3, 4 # encoding: [0x3f,0x20,0x62,0x54]
rotlwi. 2, 3, 4 rotlwi. 2, 3, 4
# CHECK-BE: rotlwi 2, 3, 28 # encoding: [0x54,0x62,0xe0,0x3e] # CHECK-BE: rotlwi 2, 3, 28 # encoding: [0x54,0x62,0xe0,0x3e]
# CHECK-LE: rotlwi 2, 3, 28 # encoding: [0x3e,0xe0,0x62,0x54] # CHECK-LE: rotlwi 2, 3, 28 # encoding: [0x3e,0xe0,0x62,0x54]
rotrwi 2, 3, 4 rotrwi 2, 3, 4
# CHECK-BE: rotlwi. 2, 3, 28 # encoding: [0x54,0x62,0xe0,0x3f] # CHECK-BE: rotlwi. 2, 3, 28 # encoding: [0x54,0x62,0xe0,0x3f]
# CHECK-LE: rotlwi. 2, 3, 28 # encoding: [0x3f,0xe0,0x62,0x54] # CHECK-LE: rotlwi. 2, 3, 28 # encoding: [0x3f,0xe0,0x62,0x54]
rotrwi. 2, 3, 4 rotrwi. 2, 3, 4
# CHECK-BE: rotlw 2, 3, 4 # encoding: [0x5c,0x62,0x20,0x3e] # CHECK-BE: rotlw 2, 3, 4 # encoding: [0x5c,0x62,0x20,0x3e]
# CHECK-LE: rotlw 2, 3, 4 # encoding: [0x3e,0x20,0x62,0x5c] # CHECK-LE: rotlw 2, 3, 4 # encoding: [0x3e,0x20,0x62,0x5c]
rotlw 2, 3, 4 rotlw 2, 3, 4
# CHECK-BE: rotlw. 2, 3, 4 # encoding: [0x5c,0x62,0x20,0x3f] # CHECK-BE: rotlw. 2, 3, 4 # encoding: [0x5c,0x62,0x20,0x3f]
# CHECK-LE: rotlw. 2, 3, 4 # encoding: [0x3f,0x20,0x62,0x5c] # CHECK-LE: rotlw. 2, 3, 4 # encoding: [0x3f,0x20,0x62,0x5c]
rotlw. 2, 3, 4 rotlw. 2, 3, 4
# CHECK-BE: slwi 2, 3, 4 # encoding: [0x54,0x62,0x20,0x36] # CHECK-BE: slwi 2, 3, 4 # encoding: [0x54,0x62,0x20,0x36]
# CHECK-LE: slwi 2, 3, 4 # encoding: [0x36,0x20,0x62,0x54] # CHECK-LE: slwi 2, 3, 4 # encoding: [0x36,0x20,0x62,0x54]
slwi 2, 3, 4 slwi 2, 3, 4
# CHECK-BE: rlwinm. 2, 3, 4, 0, 27 # encoding: [0x54,0x62,0x20,0x37] # CHECK-BE: slwi. 2, 3, 4 # encoding: [0x54,0x62,0x20,0x37]
# CHECK-LE: rlwinm. 2, 3, 4, 0, 27 # encoding: [0x37,0x20,0x62,0x54] # CHECK-LE: slwi. 2, 3, 4 # encoding: [0x37,0x20,0x62,0x54]
slwi. 2, 3, 4 slwi. 2, 3, 4
# CHECK-BE: srwi 2, 3, 4 # encoding: [0x54,0x62,0xe1,0x3e] # CHECK-BE: srwi 2, 3, 4 # encoding: [0x54,0x62,0xe1,0x3e]
# CHECK-LE: srwi 2, 3, 4 # encoding: [0x3e,0xe1,0x62,0x54] # CHECK-LE: srwi 2, 3, 4 # encoding: [0x3e,0xe1,0x62,0x54]
srwi 2, 3, 4 srwi 2, 3, 4
# CHECK-BE: rlwinm. 2, 3, 28, 4, 31 # encoding: [0x54,0x62,0xe1,0x3f] # CHECK-BE: srwi. 2, 3, 4 # encoding: [0x54,0x62,0xe1,0x3f]
# CHECK-LE: rlwinm. 2, 3, 28, 4, 31 # encoding: [0x3f,0xe1,0x62,0x54] # CHECK-LE: srwi. 2, 3, 4 # encoding: [0x3f,0xe1,0x62,0x54]
srwi. 2, 3, 4 srwi. 2, 3, 4
# CHECK-BE: clrlwi 2, 3, 4 # encoding: [0x54,0x62,0x01,0x3e] # CHECK-BE: clrlwi 2, 3, 4 # encoding: [0x54,0x62,0x01,0x3e]
# CHECK-LE: clrlwi 2, 3, 4 # encoding: [0x3e,0x01,0x62,0x54] # CHECK-LE: clrlwi 2, 3, 4 # encoding: [0x3e,0x01,0x62,0x54]
clrlwi 2, 3, 4 clrlwi 2, 3, 4
# CHECK-BE: clrlwi. 2, 3, 4 # encoding: [0x54,0x62,0x01,0x3f] # CHECK-BE: clrlwi. 2, 3, 4 # encoding: [0x54,0x62,0x01,0x3f]
# CHECK-LE: clrlwi. 2, 3, 4 # encoding: [0x3f,0x01,0x62,0x54] # CHECK-LE: clrlwi. 2, 3, 4 # encoding: [0x3f,0x01,0x62,0x54]
clrlwi. 2, 3, 4 clrlwi. 2, 3, 4
# CHECK-BE: rlwinm 2, 3, 0, 0, 27 # encoding: [0x54,0x62,0x00,0x36] # CHECK-BE: clrrwi 2, 3, 4 # encoding: [0x54,0x62,0x00,0x36]
# CHECK-LE: rlwinm 2, 3, 0, 0, 27 # encoding: [0x36,0x00,0x62,0x54] # CHECK-LE: clrrwi 2, 3, 4 # encoding: [0x36,0x00,0x62,0x54]
clrrwi 2, 3, 4 clrrwi 2, 3, 4
# CHECK-BE: rlwinm. 2, 3, 0, 0, 27 # encoding: [0x54,0x62,0x00,0x37] # CHECK-BE: clrrwi. 2, 3, 4 # encoding: [0x54,0x62,0x00,0x37]
# CHECK-LE: rlwinm. 2, 3, 0, 0, 27 # encoding: [0x37,0x00,0x62,0x54] # CHECK-LE: clrrwi. 2, 3, 4 # encoding: [0x37,0x00,0x62,0x54]
clrrwi. 2, 3, 4 clrrwi. 2, 3, 4
# CHECK-BE: rlwinm 2, 3, 4, 1, 27 # encoding: [0x54,0x62,0x20,0x76] # CHECK-BE: clrlslwi 2, 3, 5, 4 # encoding: [0x54,0x62,0x20,0x76]
# CHECK-LE: rlwinm 2, 3, 4, 1, 27 # encoding: [0x76,0x20,0x62,0x54] # CHECK-LE: clrlslwi 2, 3, 5, 4 # encoding: [0x76,0x20,0x62,0x54]
clrlslwi 2, 3, 5, 4 clrlslwi 2, 3, 5, 4
# CHECK-BE: rlwinm. 2, 3, 4, 1, 27 # encoding: [0x54,0x62,0x20,0x77] # CHECK-BE: clrlslwi. 2, 3, 5, 4 # encoding: [0x54,0x62,0x20,0x77]
# CHECK-LE: rlwinm. 2, 3, 4, 1, 27 # encoding: [0x77,0x20,0x62,0x54] # CHECK-LE: clrlslwi. 2, 3, 5, 4 # encoding: [0x77,0x20,0x62,0x54]
clrlslwi. 2, 3, 5, 4 clrlslwi. 2, 3, 5, 4
# Move to/from special purpose register mnemonics # Move to/from special purpose register mnemonics
# CHECK-BE: mtxer 2 # encoding: [0x7c,0x41,0x03,0xa6] # CHECK-BE: mtxer 2 # encoding: [0x7c,0x41,0x03,0xa6]
# CHECK-LE: mtxer 2 # encoding: [0xa6,0x03,0x41,0x7c] # CHECK-LE: mtxer 2 # encoding: [0xa6,0x03,0x41,0x7c]
mtxer 2 mtxer 2
# CHECK-BE: mfxer 2 # encoding: [0x7c,0x41,0x02,0xa6] # CHECK-BE: mfxer 2 # encoding: [0x7c,0x41,0x02,0xa6]
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llvm/test/MC/PowerPC/ppc64-encoding.s

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# CHECK-LE: rlwimi. 2, 3, 4, 5, 6 # encoding: [0x4d,0x21,0x62,0x50] # CHECK-LE: rlwimi. 2, 3, 4, 5, 6 # encoding: [0x4d,0x21,0x62,0x50]
rlwimi. 2, 3, 4, 5, 6 rlwimi. 2, 3, 4, 5, 6
# CHECK-BE: rldicl 2, 3, 4, 5 # encoding: [0x78,0x62,0x21,0x40] # CHECK-BE: rldicl 2, 3, 4, 5 # encoding: [0x78,0x62,0x21,0x40]
# CHECK-LE: rldicl 2, 3, 4, 5 # encoding: [0x40,0x21,0x62,0x78] # CHECK-LE: rldicl 2, 3, 4, 5 # encoding: [0x40,0x21,0x62,0x78]
rldicl 2, 3, 4, 5 rldicl 2, 3, 4, 5
# CHECK-BE: rldicl. 2, 3, 4, 5 # encoding: [0x78,0x62,0x21,0x41] # CHECK-BE: rldicl. 2, 3, 4, 5 # encoding: [0x78,0x62,0x21,0x41]
# CHECK-LE: rldicl. 2, 3, 4, 5 # encoding: [0x41,0x21,0x62,0x78] # CHECK-LE: rldicl. 2, 3, 4, 5 # encoding: [0x41,0x21,0x62,0x78]
rldicl. 2, 3, 4, 5 rldicl. 2, 3, 4, 5
# CHECK-BE: rldicr 2, 3, 4, 5 # encoding: [0x78,0x62,0x21,0x44] # CHECK-BE: extldi 2, 3, 6, 4 # encoding: [0x78,0x62,0x21,0x44]
# CHECK-LE: rldicr 2, 3, 4, 5 # encoding: [0x44,0x21,0x62,0x78] # CHECK-LE: extldi 2, 3, 6, 4 # encoding: [0x44,0x21,0x62,0x78]
rldicr 2, 3, 4, 5 rldicr 2, 3, 4, 5
# CHECK-BE: rldicr. 2, 3, 4, 5 # encoding: [0x78,0x62,0x21,0x45] # CHECK-BE: extldi. 2, 3, 6, 4 # encoding: [0x78,0x62,0x21,0x45]
# CHECK-LE: rldicr. 2, 3, 4, 5 # encoding: [0x45,0x21,0x62,0x78] # CHECK-LE: extldi. 2, 3, 6, 4 # encoding: [0x45,0x21,0x62,0x78]
rldicr. 2, 3, 4, 5 rldicr. 2, 3, 4, 5
# CHECK-BE: rldic 2, 3, 4, 5 # encoding: [0x78,0x62,0x21,0x48] # CHECK-BE: clrlsldi 2, 3, 9, 4 # encoding: [0x78,0x62,0x21,0x48]
# CHECK-LE: rldic 2, 3, 4, 5 # encoding: [0x48,0x21,0x62,0x78] # CHECK-LE: clrlsldi 2, 3, 9, 4 # encoding: [0x48,0x21,0x62,0x78]
rldic 2, 3, 4, 5 rldic 2, 3, 4, 5
# CHECK-BE: rldic. 2, 3, 4, 5 # encoding: [0x78,0x62,0x21,0x49] # CHECK-BE: clrlsldi. 2, 3, 9, 4 # encoding: [0x78,0x62,0x21,0x49]
# CHECK-LE: rldic. 2, 3, 4, 5 # encoding: [0x49,0x21,0x62,0x78] # CHECK-LE: clrlsldi. 2, 3, 9, 4 # encoding: [0x49,0x21,0x62,0x78]
rldic. 2, 3, 4, 5 rldic. 2, 3, 4, 5
# CHECK-BE: rldcl 2, 3, 4, 5 # encoding: [0x78,0x62,0x21,0x50] # CHECK-BE: rldcl 2, 3, 4, 5 # encoding: [0x78,0x62,0x21,0x50]
# CHECK-LE: rldcl 2, 3, 4, 5 # encoding: [0x50,0x21,0x62,0x78] # CHECK-LE: rldcl 2, 3, 4, 5 # encoding: [0x50,0x21,0x62,0x78]
rldcl 2, 3, 4, 5 rldcl 2, 3, 4, 5
# CHECK-BE: rldcl. 2, 3, 4, 5 # encoding: [0x78,0x62,0x21,0x51] # CHECK-BE: rldcl. 2, 3, 4, 5 # encoding: [0x78,0x62,0x21,0x51]
# CHECK-LE: rldcl. 2, 3, 4, 5 # encoding: [0x51,0x21,0x62,0x78] # CHECK-LE: rldcl. 2, 3, 4, 5 # encoding: [0x51,0x21,0x62,0x78]
rldcl. 2, 3, 4, 5 rldcl. 2, 3, 4, 5
# CHECK-BE: rldcr 2, 3, 4, 5 # encoding: [0x78,0x62,0x21,0x52] # CHECK-BE: rldcr 2, 3, 4, 5 # encoding: [0x78,0x62,0x21,0x52]
# CHECK-LE: rldcr 2, 3, 4, 5 # encoding: [0x52,0x21,0x62,0x78] # CHECK-LE: rldcr 2, 3, 4, 5 # encoding: [0x52,0x21,0x62,0x78]
rldcr 2, 3, 4, 5 rldcr 2, 3, 4, 5
# CHECK-BE: rldcr. 2, 3, 4, 5 # encoding: [0x78,0x62,0x21,0x53] # CHECK-BE: rldcr. 2, 3, 4, 5 # encoding: [0x78,0x62,0x21,0x53]
# CHECK-LE: rldcr. 2, 3, 4, 5 # encoding: [0x53,0x21,0x62,0x78] # CHECK-LE: rldcr. 2, 3, 4, 5 # encoding: [0x53,0x21,0x62,0x78]
rldcr. 2, 3, 4, 5 rldcr. 2, 3, 4, 5
# CHECK-BE: rldimi 2, 3, 4, 5 # encoding: [0x78,0x62,0x21,0x4c] # CHECK-BE: insrdi 2, 3, 55, 5 # encoding: [0x78,0x62,0x21,0x4c]
# CHECK-LE: rldimi 2, 3, 4, 5 # encoding: [0x4c,0x21,0x62,0x78] # CHECK-LE: insrdi 2, 3, 55, 5 # encoding: [0x4c,0x21,0x62,0x78]
rldimi 2, 3, 4, 5 rldimi 2, 3, 4, 5
# CHECK-BE: rldimi. 2, 3, 4, 5 # encoding: [0x78,0x62,0x21,0x4d] # CHECK-BE: insrdi. 2, 3, 55, 5 # encoding: [0x78,0x62,0x21,0x4d]
# CHECK-LE: rldimi. 2, 3, 4, 5 # encoding: [0x4d,0x21,0x62,0x78] # CHECK-LE: insrdi. 2, 3, 55, 5 # encoding: [0x4d,0x21,0x62,0x78]
rldimi. 2, 3, 4, 5 rldimi. 2, 3, 4, 5
# Aliases that take bit masks... # Aliases that take bit masks...
# CHECK-BE: rlwinm 0, 0, 30, 31, 31 # encoding: [0x54,0x00,0xf7,0xfe] # CHECK-BE: extrwi 0, 0, 1, 29 # encoding: [0x54,0x00,0xf7,0xfe]
rlwinm 0, 0, 30, 1 rlwinm 0, 0, 30, 1
# CHECK-BE: rlwinm. 0, 0, 30, 31, 31 # encoding: [0x54,0x00,0xf7,0xff] # CHECK-BE: extrwi. 0, 0, 1, 29 # encoding: [0x54,0x00,0xf7,0xff]
rlwinm. 0, 0, 30, 1 rlwinm. 0, 0, 30, 1
# CHECK-BE: rlwinm 0, 0, 30, 31, 0 # encoding: [0x54,0x00,0xf7,0xc0] # CHECK-BE: rlwinm 0, 0, 30, 31, 0 # encoding: [0x54,0x00,0xf7,0xc0]
rlwinm 0, 0, 30, 2147483649 rlwinm 0, 0, 30, 2147483649
# CHECK-BE: rlwinm. 0, 0, 30, 31, 0 # encoding: [0x54,0x00,0xf7,0xc1] # CHECK-BE: rlwinm. 0, 0, 30, 31, 0 # encoding: [0x54,0x00,0xf7,0xc1]
rlwinm. 0, 0, 30, 2147483649 rlwinm. 0, 0, 30, 2147483649
# CHECK-BE: rlwimi 0, 0, 30, 31, 31 # encoding: [0x50,0x00,0xf7,0xfe] # CHECK-BE: rlwimi 0, 0, 30, 31, 31 # encoding: [0x50,0x00,0xf7,0xfe]
rlwimi 0, 0, 30, 1 rlwimi 0, 0, 30, 1
# CHECK-BE: rlwimi. 0, 0, 30, 31, 31 # encoding: [0x50,0x00,0xf7,0xff] # CHECK-BE: rlwimi. 0, 0, 30, 31, 31 # encoding: [0x50,0x00,0xf7,0xff]
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