[ARM] Remove hasSideEffects from FP converts

[dmgreen]

Summary

Whether an instruction is deemed to have side effects in determined by whether it has an instruction pattern that emits a single instruction. Because of the way a lot of the the vcvt instructions are specified either in dagtodag code or with tblgen patterns that emit multiple instructions, they don't get marked as not having side effects.

This just marks them as not having side effects manually. It can help especially with instruction scheduling, to not create artificial barriers, but one of these tests also managed to produce fewer instructions.

[samparker]

Sounds good.

llvm/lib/Target/ARM/ARMInstrVFP.td

def VCVTDS  : ASuI<0b11101, 0b11, 0b0111, 0b11, 0,
 
   // Encode instruction operands.
   let Inst{3-0}   = Sm{4-1};
   let Inst{5}     = Sm{0};
   let Inst{15-12} = Dd{3-0};
   let Inst{22}    = Dd{4};
 
   let Predicates = [HasVFP2, HasDPVFP];
+  let hasSideEffects = 0;
 }
 
 // Special case encoding: bits 11-8 is 0b1011.
 def VCVTSD  : VFPAI<(outs SPR:$Sd), (ins DPR:$Dm), VFPUnaryFrm,
                     IIC_fpCVTSD, "vcvt", ".f32.f64\t$Sd, $Dm",
                     [(set SPR:$Sd, (fpround DPR:$Dm))]>,
               Sched<[WriteFPCVT]> {
   // Instruction operands.
   bits<5> Sd;
   bits<5> Dm;
 
   // Encode instruction operands.
   let Inst{3-0}   = Dm{3-0};
   let Inst{5}     = Dm{4};
   let Inst{15-12} = Sd{4-1};
   let Inst{22}    = Sd{0};
 
   let Inst{27-23} = 0b11101;
   let Inst{21-16} = 0b110111;
   let Inst{11-8}  = 0b1011;
   let Inst{7-6}   = 0b11;
   let Inst{4}     = 0;
 
   let Predicates = [HasVFP2, HasDPVFP];
+  let hasSideEffects = 0;
 }
 
 // Between half, single and double-precision.
+let hasSideEffects = 0 in
 def VCVTBHS: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
                  /* FIXME */ IIC_fpCVTSH, "vcvtb", ".f32.f16\t$Sd, $Sm",
                  [/* Intentionally left blank, see patterns below */]>,
                  Requires<[HasFP16]>,
              Sched<[WriteFPCVT]>;
 
 def : FP16Pat<(f32 (fpextend (f16 HPR:$Sm))),
               (VCVTBHS (COPY_TO_REGCLASS (f16 HPR:$Sm), SPR))>;
 def : FP16Pat<(f16_to_fp GPR:$a),
               (VCVTBHS (COPY_TO_REGCLASS GPR:$a, SPR))>;
 
+let hasSideEffects = 0 in
 def VCVTBSH: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
                  /* FIXME */ IIC_fpCVTHS, "vcvtb", ".f16.f32\t$Sd, $Sm",
                  [/* Intentionally left blank, see patterns below */]>,
                  Requires<[HasFP16]>,
              Sched<[WriteFPCVT]>;
 
 def : FP16Pat<(f16 (fpround SPR:$Sm)),
               (COPY_TO_REGCLASS (VCVTBSH SPR:$Sm), HPR)>;
 def : FP16Pat<(fp_to_f16 SPR:$a),
               (i32 (COPY_TO_REGCLASS (VCVTBSH SPR:$a), GPR))>;
 def : FP16Pat<(insertelt (v8f16 MQPR:$src1), (f16 (fpround (f32 SPR:$src2))), imm_even:$lane),
               (v8f16 (INSERT_SUBREG (v8f16 MQPR:$src1), (VCVTBSH SPR:$src2),
                                     (SSubReg_f16_reg imm:$lane)))>;
 def : FP16Pat<(insertelt (v4f16 DPR:$src1), (f16 (fpround (f32 SPR:$src2))), imm_even:$lane),
               (v4f16 (INSERT_SUBREG (v4f16 DPR:$src1), (VCVTBSH SPR:$src2),
                                     (SSubReg_f16_reg imm:$lane)))>;
 
+let hasSideEffects = 0 in
 def VCVTTHS: ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
                  /* FIXME */ IIC_fpCVTSH, "vcvtt", ".f32.f16\t$Sd, $Sm",
                  [/* Intentionally left blank, see patterns below */]>,
                  Requires<[HasFP16]>,
              Sched<[WriteFPCVT]>;
 
 def : FP16Pat<(f32 (fpextend (extractelt (v8f16 MQPR:$src), imm_odd:$lane))),
               (VCVTTHS (EXTRACT_SUBREG MQPR:$src, (SSubReg_f16_reg imm_odd:$lane)))>;
 def : FP16Pat<(f32 (fpextend (extractelt (v4f16 DPR:$src), imm_odd:$lane))),
               (VCVTTHS (EXTRACT_SUBREG
                 (v2f32 (COPY_TO_REGCLASS (v4f16 DPR:$src), DPR_VFP2)),
                 (SSubReg_f16_reg imm_odd:$lane)))>;
 
+let hasSideEffects = 0 in
 def VCVTTSH: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
                  /* FIXME */ IIC_fpCVTHS, "vcvtt", ".f16.f32\t$Sd, $Sm",
                  [/* Intentionally left blank, see patterns below */]>,
                  Requires<[HasFP16]>,
             Sched<[WriteFPCVT]>;
 
 def : FP16Pat<(insertelt (v8f16 MQPR:$src1), (f16 (fpround (f32 SPR:$src2))), imm_odd:$lane),
               (v8f16 (INSERT_SUBREG (v8f16 MQPR:$src1), (VCVTTSH SPR:$src2),
def VCVTBHD : ADuI<0b11101, 0b11, 0b0010, 0b01, 0,
                    Requires<[HasFPARMv8, HasDPVFP]>,
               Sched<[WriteFPCVT]> {
   // Instruction operands.
   bits<5> Sm;
 
   // Encode instruction operands.
   let Inst{3-0} = Sm{4-1};
   let Inst{5}   = Sm{0};
+
+  let hasSideEffects = 0;
 }
 
 def : FullFP16Pat<(f64 (fpextend (f16 HPR:$Sm))),
                   (VCVTBHD (COPY_TO_REGCLASS (f16 HPR:$Sm), SPR))>,
                   Requires<[HasFPARMv8, HasDPVFP]>;
 def : FP16Pat<(f64 (f16_to_fp GPR:$a)),
               (VCVTBHD (COPY_TO_REGCLASS GPR:$a, SPR))>,
               Requires<[HasFPARMv8, HasDPVFP]>;
 
 def VCVTBDH : ADuI<0b11101, 0b11, 0b0011, 0b01, 0,
                    (outs SPR:$Sd), (ins DPR:$Dm),
                    NoItinerary, "vcvtb", ".f16.f64\t$Sd, $Dm",
                    [/* Intentionally left blank, see patterns below */]>,
                    Requires<[HasFPARMv8, HasDPVFP]> {
   // Instruction operands.
   bits<5> Sd;
   bits<5> Dm;
 
   // Encode instruction operands.
   let Inst{3-0}     = Dm{3-0};
   let Inst{5}       = Dm{4};
   let Inst{15-12}   = Sd{4-1};
   let Inst{22}      = Sd{0};
+
+  let hasSideEffects = 0;
 }
 
 def : FullFP16Pat<(f16 (fpround DPR:$Dm)),
                   (COPY_TO_REGCLASS (VCVTBDH DPR:$Dm), HPR)>,
                   Requires<[HasFPARMv8, HasDPVFP]>;
 def : FP16Pat<(fp_to_f16 (f64 DPR:$a)),
               (i32 (COPY_TO_REGCLASS (VCVTBDH DPR:$a), GPR))>,
                    Requires<[HasFPARMv8, HasDPVFP]>;
 
 def VCVTTHD : ADuI<0b11101, 0b11, 0b0010, 0b11, 0,
                    (outs DPR:$Dd), (ins SPR:$Sm),
                    NoItinerary, "vcvtt", ".f64.f16\t$Dd, $Sm",
                    []>, Requires<[HasFPARMv8, HasDPVFP]> {
   // Instruction operands.
   bits<5> Sm;
 
   // Encode instruction operands.
   let Inst{3-0} = Sm{4-1};
   let Inst{5}   = Sm{0};
+
+  let hasSideEffects = 0;
 }
 
 def VCVTTDH : ADuI<0b11101, 0b11, 0b0011, 0b11, 0,
                    (outs SPR:$Sd), (ins DPR:$Dm),
                    NoItinerary, "vcvtt", ".f16.f64\t$Sd, $Dm",
                    []>, Requires<[HasFPARMv8, HasDPVFP]> {
   // Instruction operands.
   bits<5> Sd;
   bits<5> Dm;
 
   // Encode instruction operands.
   let Inst{15-12} = Sd{4-1};
   let Inst{22}    = Sd{0};
   let Inst{3-0}   = Dm{3-0};
   let Inst{5}     = Dm{4};
+
+  let hasSideEffects = 0;
 }
 
 multiclass vcvt_inst<string opc, bits<2> rm,
                      SDPatternOperator node = null_frag> {
-  let PostEncoderMethod = "", DecoderNamespace = "VFPV8" in {
+  let PostEncoderMethod = "", DecoderNamespace = "VFPV8", hasSideEffects = 0 in {
     def SH : AHuInp<0b11101, 0b11, 0b1100, 0b11, 0,
                     (outs SPR:$Sd), (ins HPR:$Sm),
                     NoItinerary, !strconcat("vcvt", opc, ".s32.f16\t$Sd, $Sm"),
                     []>,
                     Requires<[HasFullFP16]> {
       let Inst{17-16} = rm;
     }
 
class AVConv1IDs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
 
   // Encode instruction operands.
   let Inst{3-0}   = Sm{4-1};
   let Inst{5}     = Sm{0};
   let Inst{15-12} = Dd{3-0};
   let Inst{22}    = Dd{4};
 
   let Predicates = [HasVFP2, HasDPVFP];
+  let hasSideEffects = 0;
 }
 
 class AVConv1InSs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
                          bits<4> opcod4, dag oops, dag iops,InstrItinClass itin,
                          string opc, string asm, list<dag> pattern>
   : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
               pattern> {
   // Instruction operands.
   bits<5> Sd;
   bits<5> Sm;
 
   // Encode instruction operands.
   let Inst{3-0}   = Sm{4-1};
   let Inst{5}     = Sm{0};
   let Inst{15-12} = Sd{4-1};
   let Inst{22}    = Sd{0};
+
+  let hasSideEffects = 0;
 }
 
 class AVConv1IHs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
                         bits<4> opcod4, dag oops, dag iops,
                         InstrItinClass itin, string opc, string asm,
                         list<dag> pattern>
   : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
              pattern> {
   // Instruction operands.
   bits<5> Sd;
   bits<5> Sm;
 
   // Encode instruction operands.
   let Inst{3-0}   = Sm{4-1};
   let Inst{5}     = Sm{0};
   let Inst{15-12} = Sd{4-1};
   let Inst{22}    = Sd{0};
 
   let Predicates = [HasFullFP16];
+  let hasSideEffects = 0;
 }
 
 def VSITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
                                (outs DPR:$Dd), (ins SPR:$Sm),
                                IIC_fpCVTID, "vcvt", ".f64.s32\t$Dd, $Sm",
                                []>,
              Sched<[WriteFPCVT]> {
   let Inst{7} = 1; // s32
class AVConv1IsD_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
 
   // Encode instruction operands.
   let Inst{3-0}   = Dm{3-0};
   let Inst{5}     = Dm{4};
   let Inst{15-12} = Sd{4-1};
   let Inst{22}    = Sd{0};
 
   let Predicates = [HasVFP2, HasDPVFP];
+  let hasSideEffects = 0;
 }
 
 class AVConv1InsS_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
                          bits<4> opcod4, dag oops, dag iops,
                          InstrItinClass itin, string opc, string asm,
                          list<dag> pattern>
   : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
               pattern> {
class AVConv1IsH_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
 
   // Encode instruction operands.
   let Inst{3-0}   = Sm{4-1};
   let Inst{5}     = Sm{0};
   let Inst{15-12} = Sd{4-1};
   let Inst{22}    = Sd{0};
 
   let Predicates = [HasFullFP16];
+  let hasSideEffects = 0;
 }
 
 // Always set Z bit in the instruction, i.e. "round towards zero" variants.
 def VTOSIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
                                 (outs SPR:$Sd), (ins DPR:$Dm),
                                 IIC_fpCVTDI, "vcvt", ".s32.f64\t$Sd, $Dm",
                                 []>,
               Sched<[WriteFPCVT]> {

 class AVConv1XInsS_Encode<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4,
                           bit op5, dag oops, dag iops, InstrItinClass itin,
                           string opc, string asm, list<dag> pattern>
   : AVConv1XI<op1, op2, op3, op4, op5, oops, iops, itin, opc, asm, pattern> {
   bits<5> dst;
   // if dp_operation then UInt(D:Vd) else UInt(Vd:D);
   let Inst{22} = dst{0};
   let Inst{15-12} = dst{4-1};
+
+  let hasSideEffects = 0;
 }
 
 // Double Precision register
 class AVConv1XInsD_Encode<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4,
                           bit op5, dag oops, dag iops, InstrItinClass itin,
                           string opc, string asm, list<dag> pattern>
   : AVConv1XI<op1, op2, op3, op4, op5, oops, iops, itin, opc, asm, pattern> {
   bits<5> dst;
   // if dp_operation then UInt(D:Vd) else UInt(Vd:D);
   let Inst{22} = dst{4};
   let Inst{15-12} = dst{3-0};
 
+  let hasSideEffects = 0;
   let Predicates = [HasVFP2, HasDPVFP];
 }
 
 let isUnpredicable = 1 in {
 
 def VTOSHH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1001, 0,
                        (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
                  IIC_fpCVTHI, "vcvt", ".s16.f16\t$dst, $a, $fbits", []>,
class BF16_VCVT<string opc, bits<2> op7_6>
   let Inst{22}    = Sd{0};
 
   let Inst{27-23} = 0b11101; // opcode1
   let Inst{21-20} = 0b11;    // opcode2
   let Inst{19-16} = 0b0011;  // opcode3
   let Inst{11-8}  = 0b1001;
   let Inst{7-6}   = op7_6;
   let Inst{4}     = 0;
+
   let DecoderNamespace = "VFPV8";
+  let hasSideEffects = 0;
 }
 
 def BF16_VCVTB : BF16_VCVT<"vcvtb", 0b01>;
 def BF16_VCVTT : BF16_VCVT<"vcvtt", 0b11>;
 
 //===----------------------------------------------------------------------===//
 // FP Multiply-Accumulate Operations.
 //

llvm/test/CodeGen/ARM/cmov_fp16.ll

-; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+fullfp16 %s -o - | FileCheck %s --check-prefixes CHECK-THUMB,CHECK
-; RUN: llc -mtriple=armv8.2a-arm-none-eabi -mattr=+fullfp16 %s -o - | FileCheck %s --check-prefixes CHECK-ARM,CHECK
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+fullfp16 %s -o - | FileCheck %s --check-prefixes CHECK,CHECK-THUMB
+; RUN: llc -mtriple=armv8.2a-arm-none-eabi -mattr=+fullfp16 %s -o - | FileCheck %s --check-prefixes CHECK,CHECK-ARM
 
 define i32 @test_ne(i32 %x, i32 %y, i32 %a, i32 %b) {
 ; CHECK-LABEL: test_ne:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmov s2, r0
-; CHECK-NEXT:    cmp r2, r3
 ; CHECK-NEXT:    vmov s0, r1
-; CHECK-NEXT:    vcvt.f16.u32 s2, s2
+; CHECK-NEXT:    cmp r2, r3
+; CHECK-NEXT:    vmov s2, r0
 ; CHECK-NEXT:    vcvt.f16.u32 s0, s0
+; CHECK-NEXT:    vcvt.f16.u32 s2, s2
 ; CHECK-NEXT:    vseleq.f16 s0, s0, s2
 ; CHECK-NEXT:    vmov.f16 r0, s0
 ; CHECK-NEXT:    bx lr
 entry:
   %x.half = uitofp i32 %x to half
   %y.half = uitofp i32 %y to half
   %cmp = icmp ne i32 %a, %b
   %cond = select i1 %cmp, half %x.half, half %y.half
   %0 = bitcast half %cond to i16
   %1 = zext i16 %0 to i32
   ret i32 %1
 }
 
 define i32 @test_eq(i32 %x, i32 %y, i32 %a, i32 %b) {
 ; CHECK-LABEL: test_eq:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmov s2, r1
-; CHECK-NEXT:    cmp r2, r3
 ; CHECK-NEXT:    vmov s0, r0
-; CHECK-NEXT:    vcvt.f16.u32 s2, s2
+; CHECK-NEXT:    cmp r2, r3
+; CHECK-NEXT:    vmov s2, r1
 ; CHECK-NEXT:    vcvt.f16.u32 s0, s0
+; CHECK-NEXT:    vcvt.f16.u32 s2, s2
 ; CHECK-NEXT:    vseleq.f16 s0, s0, s2
 ; CHECK-NEXT:    vmov.f16 r0, s0
 ; CHECK-NEXT:    bx lr
 entry:
   %x.half = uitofp i32 %x to half
   %y.half = uitofp i32 %y to half
   %cmp = icmp eq i32 %a, %b
   %cond = select i1 %cmp, half %x.half, half %y.half
   %0 = bitcast half %cond to i16
   %1 = zext i16 %0 to i32
   ret i32 %1
 }
 
 define i32 @test_gt(i32 %x, i32 %y, i32 %a, i32 %b) {
 ; CHECK-LABEL: test_gt:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmov s2, r1
-; CHECK-NEXT:    cmp r2, r3
 ; CHECK-NEXT:    vmov s0, r0
-; CHECK-NEXT:    vcvt.f16.u32 s2, s2
+; CHECK-NEXT:    cmp r2, r3
+; CHECK-NEXT:    vmov s2, r1
 ; CHECK-NEXT:    vcvt.f16.u32 s0, s0
+; CHECK-NEXT:    vcvt.f16.u32 s2, s2
 ; CHECK-NEXT:    vselgt.f16 s0, s0, s2
 ; CHECK-NEXT:    vmov.f16 r0, s0
 ; CHECK-NEXT:    bx lr
 entry:
   %x.half = uitofp i32 %x to half
   %y.half = uitofp i32 %y to half
   %cmp = icmp sgt i32 %a, %b
   %cond = select i1 %cmp, half %x.half, half %y.half
   %0 = bitcast half %cond to i16
   %1 = zext i16 %0 to i32
   ret i32 %1
 }
 
 define i32 @test_ge(i32 %x, i32 %y, i32 %a, i32 %b) {
 ; CHECK-LABEL: test_ge:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmov s2, r1
-; CHECK-NEXT:    cmp r2, r3
 ; CHECK-NEXT:    vmov s0, r0
-; CHECK-NEXT:    vcvt.f16.u32 s2, s2
+; CHECK-NEXT:    cmp r2, r3
+; CHECK-NEXT:    vmov s2, r1
 ; CHECK-NEXT:    vcvt.f16.u32 s0, s0
+; CHECK-NEXT:    vcvt.f16.u32 s2, s2
 ; CHECK-NEXT:    vselge.f16 s0, s0, s2
 ; CHECK-NEXT:    vmov.f16 r0, s0
 ; CHECK-NEXT:    bx lr
 entry:
   %x.half = uitofp i32 %x to half
   %y.half = uitofp i32 %y to half
   %cmp = icmp sge i32 %a, %b
   %cond = select i1 %cmp, half %x.half, half %y.half
   %0 = bitcast half %cond to i16
   %1 = zext i16 %0 to i32
   ret i32 %1
 }
 
 define i32 @test_lt(i32 %x, i32 %y, i32 %a, i32 %b) {
 ; CHECK-LABEL: test_lt:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmov s2, r0
-; CHECK-NEXT:    cmp r2, r3
 ; CHECK-NEXT:    vmov s0, r1
-; CHECK-NEXT:    vcvt.f16.u32 s2, s2
+; CHECK-NEXT:    cmp r2, r3
+; CHECK-NEXT:    vmov s2, r0
 ; CHECK-NEXT:    vcvt.f16.u32 s0, s0
+; CHECK-NEXT:    vcvt.f16.u32 s2, s2
 ; CHECK-NEXT:    vselge.f16 s0, s0, s2
 ; CHECK-NEXT:    vmov.f16 r0, s0
 ; CHECK-NEXT:    bx lr
 entry:
   %x.half = uitofp i32 %x to half
   %y.half = uitofp i32 %y to half
   %cmp = icmp slt i32 %a, %b
   %cond = select i1 %cmp, half %x.half, half %y.half
   %0 = bitcast half %cond to i16
   %1 = zext i16 %0 to i32
   ret i32 %1
 }
 
 define i32 @test_le(i32 %x, i32 %y, i32 %a, i32 %b) {
 ; CHECK-LABEL: test_le:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmov s2, r0
-; CHECK-NEXT:    cmp r2, r3
 ; CHECK-NEXT:    vmov s0, r1
-; CHECK-NEXT:    vcvt.f16.u32 s2, s2
+; CHECK-NEXT:    cmp r2, r3
+; CHECK-NEXT:    vmov s2, r0
 ; CHECK-NEXT:    vcvt.f16.u32 s0, s0
+; CHECK-NEXT:    vcvt.f16.u32 s2, s2
 ; CHECK-NEXT:    vselgt.f16 s0, s0, s2
 ; CHECK-NEXT:    vmov.f16 r0, s0
 ; CHECK-NEXT:    bx lr
 entry:
   %x.half = uitofp i32 %x to half
   %y.half = uitofp i32 %y to half
   %cmp = icmp sle i32 %a, %b
   %cond = select i1 %cmp, half %x.half, half %y.half
   %0 = bitcast half %cond to i16
   %1 = zext i16 %0 to i32
   ret i32 %1
 }
 
 define i32 @test_hi(i32 %x, i32 %y, i32 %a, i32 %b) {
 ; CHECK-THUMB-LABEL: test_hi:
 ; CHECK-THUMB:       @ %bb.0: @ %entry
-; CHECK-THUMB-NEXT:    vmov s2, r0
-; CHECK-THUMB-NEXT:    cmp r2, r3
 ; CHECK-THUMB-NEXT:    vmov s0, r1
-; CHECK-THUMB-NEXT:    vcvt.f16.u32 s2, s2
+; CHECK-THUMB-NEXT:    cmp r2, r3
+; CHECK-THUMB-NEXT:    vmov s2, r0
 ; CHECK-THUMB-NEXT:    vcvt.f16.u32 s0, s0
+; CHECK-THUMB-NEXT:    vcvt.f16.u32 s2, s2
 ; CHECK-THUMB-NEXT:    it hi
 ; CHECK-THUMB-NEXT:    vmovhi.f32 s0, s2
 ; CHECK-THUMB-NEXT:    vmov.f16 r0, s0
 ; CHECK-THUMB-NEXT:    bx lr
 ;
 ; CHECK-ARM-LABEL: test_hi:
 ; CHECK-ARM:       @ %bb.0: @ %entry
-; CHECK-ARM-NEXT:    vmov s2, r0
-; CHECK-ARM-NEXT:    cmp r2, r3
 ; CHECK-ARM-NEXT:    vmov s0, r1
-; CHECK-ARM-NEXT:    vcvt.f16.u32 s2, s2
+; CHECK-ARM-NEXT:    cmp r2, r3
+; CHECK-ARM-NEXT:    vmov s2, r0
 ; CHECK-ARM-NEXT:    vcvt.f16.u32 s0, s0
+; CHECK-ARM-NEXT:    vcvt.f16.u32 s2, s2
 ; CHECK-ARM-NEXT:    vmovhi.f32 s0, s2
 ; CHECK-ARM-NEXT:    vmov.f16 r0, s0
 ; CHECK-ARM-NEXT:    bx lr
 entry:
   %x.half = uitofp i32 %x to half
   %y.half = uitofp i32 %y to half
   %cmp = icmp ugt i32 %a, %b
   %cond = select i1 %cmp, half %x.half, half %y.half
   %0 = bitcast half %cond to i16
   %1 = zext i16 %0 to i32
   ret i32 %1
 }
 
 define i32 @test_hs(i32 %x, i32 %y, i32 %a, i32 %b) {
 ; CHECK-THUMB-LABEL: test_hs:
 ; CHECK-THUMB:       @ %bb.0: @ %entry
-; CHECK-THUMB-NEXT:    vmov s2, r0
-; CHECK-THUMB-NEXT:    cmp r2, r3
 ; CHECK-THUMB-NEXT:    vmov s0, r1
-; CHECK-THUMB-NEXT:    vcvt.f16.u32 s2, s2
+; CHECK-THUMB-NEXT:    cmp r2, r3
+; CHECK-THUMB-NEXT:    vmov s2, r0
 ; CHECK-THUMB-NEXT:    vcvt.f16.u32 s0, s0
+; CHECK-THUMB-NEXT:    vcvt.f16.u32 s2, s2
 ; CHECK-THUMB-NEXT:    it hs
 ; CHECK-THUMB-NEXT:    vmovhs.f32 s0, s2
 ; CHECK-THUMB-NEXT:    vmov.f16 r0, s0
 ; CHECK-THUMB-NEXT:    bx lr
 ;
 ; CHECK-ARM-LABEL: test_hs:
 ; CHECK-ARM:       @ %bb.0: @ %entry
-; CHECK-ARM-NEXT:    vmov s2, r0
-; CHECK-ARM-NEXT:    cmp r2, r3
 ; CHECK-ARM-NEXT:    vmov s0, r1
-; CHECK-ARM-NEXT:    vcvt.f16.u32 s2, s2
+; CHECK-ARM-NEXT:    cmp r2, r3
+; CHECK-ARM-NEXT:    vmov s2, r0
 ; CHECK-ARM-NEXT:    vcvt.f16.u32 s0, s0
+; CHECK-ARM-NEXT:    vcvt.f16.u32 s2, s2
 ; CHECK-ARM-NEXT:    vmovhs.f32 s0, s2
 ; CHECK-ARM-NEXT:    vmov.f16 r0, s0
 ; CHECK-ARM-NEXT:    bx lr
 entry:
   %x.half = uitofp i32 %x to half
   %y.half = uitofp i32 %y to half
   %cmp = icmp uge i32 %a, %b
   %cond = select i1 %cmp, half %x.half, half %y.half
   %0 = bitcast half %cond to i16
   %1 = zext i16 %0 to i32
   ret i32 %1
 }
 
 define i32 @test_lo(i32 %x, i32 %y, i32 %a, i32 %b) {
 ; CHECK-THUMB-LABEL: test_lo:
 ; CHECK-THUMB:       @ %bb.0: @ %entry
-; CHECK-THUMB-NEXT:    vmov s2, r0
-; CHECK-THUMB-NEXT:    cmp r2, r3
 ; CHECK-THUMB-NEXT:    vmov s0, r1
-; CHECK-THUMB-NEXT:    vcvt.f16.u32 s2, s2
+; CHECK-THUMB-NEXT:    cmp r2, r3
+; CHECK-THUMB-NEXT:    vmov s2, r0
 ; CHECK-THUMB-NEXT:    vcvt.f16.u32 s0, s0
+; CHECK-THUMB-NEXT:    vcvt.f16.u32 s2, s2
 ; CHECK-THUMB-NEXT:    it lo
 ; CHECK-THUMB-NEXT:    vmovlo.f32 s0, s2
 ; CHECK-THUMB-NEXT:    vmov.f16 r0, s0
 ; CHECK-THUMB-NEXT:    bx lr
 ;
 ; CHECK-ARM-LABEL: test_lo:
 ; CHECK-ARM:       @ %bb.0: @ %entry
-; CHECK-ARM-NEXT:    vmov s2, r0
-; CHECK-ARM-NEXT:    cmp r2, r3
 ; CHECK-ARM-NEXT:    vmov s0, r1
-; CHECK-ARM-NEXT:    vcvt.f16.u32 s2, s2
+; CHECK-ARM-NEXT:    cmp r2, r3
+; CHECK-ARM-NEXT:    vmov s2, r0
 ; CHECK-ARM-NEXT:    vcvt.f16.u32 s0, s0
+; CHECK-ARM-NEXT:    vcvt.f16.u32 s2, s2
 ; CHECK-ARM-NEXT:    vmovlo.f32 s0, s2
 ; CHECK-ARM-NEXT:    vmov.f16 r0, s0
 ; CHECK-ARM-NEXT:    bx lr
 entry:
   %x.half = uitofp i32 %x to half
   %y.half = uitofp i32 %y to half
   %cmp = icmp ult i32 %a, %b
   %cond = select i1 %cmp, half %x.half, half %y.half
   %0 = bitcast half %cond to i16
   %1 = zext i16 %0 to i32
   ret i32 %1
 }
 
 define i32 @test_ls(i32 %x, i32 %y, i32 %a, i32 %b) {
 ; CHECK-THUMB-LABEL: test_ls:
 ; CHECK-THUMB:       @ %bb.0: @ %entry
-; CHECK-THUMB-NEXT:    vmov s2, r0
-; CHECK-THUMB-NEXT:    cmp r2, r3
 ; CHECK-THUMB-NEXT:    vmov s0, r1
-; CHECK-THUMB-NEXT:    vcvt.f16.u32 s2, s2
+; CHECK-THUMB-NEXT:    cmp r2, r3
+; CHECK-THUMB-NEXT:    vmov s2, r0
 ; CHECK-THUMB-NEXT:    vcvt.f16.u32 s0, s0
+; CHECK-THUMB-NEXT:    vcvt.f16.u32 s2, s2
 ; CHECK-THUMB-NEXT:    it ls
 ; CHECK-THUMB-NEXT:    vmovls.f32 s0, s2
 ; CHECK-THUMB-NEXT:    vmov.f16 r0, s0
 ; CHECK-THUMB-NEXT:    bx lr
 ;
 ; CHECK-ARM-LABEL: test_ls:
 ; CHECK-ARM:       @ %bb.0: @ %entry
-; CHECK-ARM-NEXT:    vmov s2, r0
-; CHECK-ARM-NEXT:    cmp r2, r3
 ; CHECK-ARM-NEXT:    vmov s0, r1
-; CHECK-ARM-NEXT:    vcvt.f16.u32 s2, s2
+; CHECK-ARM-NEXT:    cmp r2, r3
+; CHECK-ARM-NEXT:    vmov s2, r0
 ; CHECK-ARM-NEXT:    vcvt.f16.u32 s0, s0
+; CHECK-ARM-NEXT:    vcvt.f16.u32 s2, s2
 ; CHECK-ARM-NEXT:    vmovls.f32 s0, s2
 ; CHECK-ARM-NEXT:    vmov.f16 r0, s0
 ; CHECK-ARM-NEXT:    bx lr
 entry:
   %x.half = uitofp i32 %x to half
   %y.half = uitofp i32 %y to half
   %cmp = icmp ule i32 %a, %b
   %cond = select i1 %cmp, half %x.half, half %y.half
   %0 = bitcast half %cond to i16
   %1 = zext i16 %0 to i32
   ret i32 %1
 }
 

llvm/test/CodeGen/ARM/fp16-args.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=armv7a--none-eabi -float-abi soft -mattr=+fp16 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=SOFT
 ; RUN: llc -mtriple=armv7a--none-eabi -float-abi hard -mattr=+fp16 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=HARD
 ; RUN: llc -mtriple=armv7a--none-eabi -float-abi soft -mattr=+fullfp16 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FULL-SOFT
 ; RUN: llc -mtriple=armv7a--none-eabi -float-abi hard -mattr=+fullfp16 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FULL-HARD
 ; RUN: llc -mtriple=armv7aeb--none-eabi -float-abi soft -mattr=+fp16 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=SOFT
 ; RUN: llc -mtriple=armv7aeb--none-eabi -float-abi hard -mattr=+fp16 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=HARD
 ; RUN: llc -mtriple=armv7aeb--none-eabi -float-abi soft -mattr=+fullfp16 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FULL-SOFT
 ; RUN: llc -mtriple=armv7aeb--none-eabi -float-abi hard -mattr=+fullfp16 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FULL-HARD
 
 define half @foo(half %a, half %b) {
 ; SOFT-LABEL: foo:
 ; SOFT:       @ %bb.0: @ %entry
-; SOFT-NEXT:    vmov s2, r1
 ; SOFT-NEXT:    vmov s0, r0
-; SOFT-NEXT:    vcvtb.f32.f16 s2, s2
+; SOFT-NEXT:    vmov s2, r1
 ; SOFT-NEXT:    vcvtb.f32.f16 s0, s0
+; SOFT-NEXT:    vcvtb.f32.f16 s2, s2
 ; SOFT-NEXT:    vadd.f32 s0, s0, s2
 ; SOFT-NEXT:    vcvtb.f16.f32 s0, s0
 ; SOFT-NEXT:    vmov r0, s0
 ; SOFT-NEXT:    bx lr
 ;
 ; HARD-LABEL: foo:
 ; HARD:       @ %bb.0: @ %entry
 ; HARD-NEXT:    vcvtb.f32.f16 s2, s1

llvm/test/CodeGen/ARM/fp16-bitcast.ll

 entry:
   %add = fadd float %a, %b
   ret float %add
 }
 
 define half @addf16(half %a, half %b) {
 ; CHECK-VFPV4-SOFT-LABEL: addf16:
 ; CHECK-VFPV4-SOFT:       @ %bb.0: @ %entry
-; CHECK-VFPV4-SOFT-NEXT:    vmov s2, r1
 ; CHECK-VFPV4-SOFT-NEXT:    vmov s0, r0
-; CHECK-VFPV4-SOFT-NEXT:    vcvtb.f32.f16 s2, s2
+; CHECK-VFPV4-SOFT-NEXT:    vmov s2, r1
 ; CHECK-VFPV4-SOFT-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-VFPV4-SOFT-NEXT:    vcvtb.f32.f16 s2, s2
 ; CHECK-VFPV4-SOFT-NEXT:    vadd.f32 s0, s0, s2
 ; CHECK-VFPV4-SOFT-NEXT:    vcvtb.f16.f32 s0, s0
 ; CHECK-VFPV4-SOFT-NEXT:    vmov r0, s0
 ; CHECK-VFPV4-SOFT-NEXT:    bx lr
 ;
 ; CHECK-FP16-SOFT-LABEL: addf16:
 ; CHECK-FP16-SOFT:       @ %bb.0: @ %entry
 ; CHECK-FP16-SOFT-NEXT:    vmov.f16 s0, r1

llvm/test/CodeGen/ARM/fp16-fullfp16.ll

; CHECK-NEXT:    bx lr
   store half %r, half* %p
   ret void
 }
 
 define arm_aapcs_vfpcc void @test_frem(half* %p, half* %q) {
 ; CHECK-LABEL: test_frem:
 ; CHECK:         .save {r4, lr}
 ; CHECK-NEXT:    push {r4, lr}
-; CHECK-NEXT:    vldr.16 s2, [r1]
 ; CHECK-NEXT:    vldr.16 s0, [r0]
+; CHECK-NEXT:    vldr.16 s2, [r1]
 ; CHECK-NEXT:    mov r4, r0
 ; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
 ; CHECK-NEXT:    vcvtb.f32.f16 s1, s2
 ; CHECK-NEXT:    bl fmodf
 ; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
 ; CHECK-NEXT:    vstr.16 s0, [r4]
 ; CHECK-NEXT:    pop {r4, pc}
   %a = load half, half* %p, align 2
; CHECK-NEXT:    pop {r4, pc}
   store half %r, half* %p
   ret void
 }
 
 define void @test_pow(half* %p, half* %q) {
 ; CHECK-LABEL: test_pow:
 ; CHECK:         .save {r4, lr}
 ; CHECK-NEXT:    push {r4, lr}
-; CHECK-NEXT:    vldr.16 s2, [r1]
 ; CHECK-NEXT:    vldr.16 s0, [r0]
+; CHECK-NEXT:    vldr.16 s2, [r1]
 ; CHECK-NEXT:    mov r4, r0
 ; CHECK-NEXT:    vcvtb.f32.f16 s0, s0
 ; CHECK-NEXT:    vcvtb.f32.f16 s1, s2
 ; CHECK-NEXT:    bl powf
 ; CHECK-NEXT:    vcvtb.f16.f32 s0, s0
 ; CHECK-NEXT:    vstr.16 s0, [r4]
 ; CHECK-NEXT:    pop {r4, pc}
   %a = load half, half* %p, align 2

llvm/test/CodeGen/ARM/fp16-instructions.ll

 ; CHECK-SOFT:  bl  __aeabi_fadd
 ; CHECK-SOFT:  bl  __aeabi_f2h
 
 ; CHECK-SOFTFP-VFP3:  bl  __aeabi_h2f
 ; CHECK-SOFTFP-VFP3:  bl  __aeabi_h2f
 ; CHECK-SOFTFP-VFP3:  vadd.f32
 ; CHECK-SOFTFP-VFP3:  bl  __aeabi_f2h
 
-; CHECK-SOFTFP-FP16:  vmov          [[S2:s[0-9]]], r1
-; CHECK-SOFTFP-FP16:  vmov          [[S0:s[0-9]]], r0
-; CHECK-SOFTFP-FP16:  vcvtb.f32.f16 [[S2]], [[S2]]
-; CHECK-SOFTFP-FP16:  vcvtb.f32.f16 [[S0]], [[S0]]
+; CHECK-SOFTFP-FP16-DAG:  vmov          [[S0:s[0-9]]], r0
+; CHECK-SOFTFP-FP16-DAG:  vmov          [[S2:s[0-9]]], r1
+; CHECK-SOFTFP-FP16-DAG:  vcvtb.f32.f16 [[S0]], [[S0]]
+; CHECK-SOFTFP-FP16-DAG:  vcvtb.f32.f16 [[S2]], [[S2]]
 ; CHECK-SOFTFP-FP16:  vadd.f32      [[S0]], [[S0]], [[S2]]
 ; CHECK-SOFTFP-FP16:  vcvtb.f16.f32 [[S0]], [[S0]]
 ; CHECK-SOFTFP-FP16:  vmov  r0, s0
 
 ; CHECK-SOFTFP-FULLFP16:       vmov.f16  [[S0:s[0-9]]], r1
 ; CHECK-SOFTFP-FULLFP16:       vmov.f16  [[S2:s[0-9]]], r0
 ; CHECK-SOFTFP-FULLFP16:       vadd.f16  [[S0]], [[S2]], [[S0]]
 ; CHECK-SOFTFP-FULLFP16-NEXT:  vmov.f16  r0, s0

 ; CHECK-SOFT:  bl  __aeabi_fdiv
 ; CHECK-SOFT:  bl  __aeabi_f2h
 
 ; CHECK-SOFTFP-VFP3:  bl  __aeabi_h2f
 ; CHECK-SOFTFP-VFP3:  bl  __aeabi_h2f
 ; CHECK-SOFTFP-VFP3:  vdiv.f32
 ; CHECK-SOFTFP-VFP3:  bl  __aeabi_f2h
 
-; CHECK-SOFTFP-FP16:  vmov          [[S2:s[0-9]]], r1
-; CHECK-SOFTFP-FP16:  vmov          [[S0:s[0-9]]], r0
-; CHECK-SOFTFP-FP16:  vcvtb.f32.f16 [[S2]], [[S2]]
-; CHECK-SOFTFP-FP16:  vcvtb.f32.f16 [[S0]], [[S0]]
+; CHECK-SOFTFP-FP16-DAG:  vmov          [[S0:s[0-9]]], r0
+; CHECK-SOFTFP-FP16-DAG:  vmov          [[S2:s[0-9]]], r1
+; CHECK-SOFTFP-FP16-DAG:  vcvtb.f32.f16 [[S0]], [[S0]]
+; CHECK-SOFTFP-FP16-DAG:  vcvtb.f32.f16 [[S2]], [[S2]]
 ; CHECK-SOFTFP-FP16:  vdiv.f32      [[S0]], [[S0]], [[S2]]
 ; CHECK-SOFTFP-FP16:  vcvtb.f16.f32 [[S0]], [[S0]]
 ; CHECK-SOFTFP-FP16:  vmov  r0, s0
 
 ; CHECK-SOFTFP-FULLFP16:       vmov.f16  [[S0:s[0-9]]], r1
 ; CHECK-SOFTFP-FULLFP16:       vmov.f16  [[S2:s[0-9]]], r0
 ; CHECK-SOFTFP-FULLFP16:       vdiv.f16  [[S0]], [[S2]], [[S0]]
 ; CHECK-SOFTFP-FULLFP16-NEXT:  vmov.f16  r0, s0

 ; CHECK-SOFT:  bl  __aeabi_fmul
 ; CHECK-SOFT:  bl  __aeabi_f2h
 
 ; CHECK-SOFTFP-VFP3:  bl  __aeabi_h2f
 ; CHECK-SOFTFP-VFP3:  bl  __aeabi_h2f
 ; CHECK-SOFTFP-VFP3:  vmul.f32
 ; CHECK-SOFTFP-VFP3:  bl  __aeabi_f2h
 
-; CHECK-SOFTFP-FP16:  vmov          [[S2:s[0-9]]], r1
-; CHECK-SOFTFP-FP16:  vmov          [[S0:s[0-9]]], r0
-; CHECK-SOFTFP-FP16:  vcvtb.f32.f16 [[S2]], [[S2]]
-; CHECK-SOFTFP-FP16:  vcvtb.f32.f16 [[S0]], [[S0]]
+; CHECK-SOFTFP-FP16-DAG:  vmov          [[S0:s[0-9]]], r0
+; CHECK-SOFTFP-FP16-DAG:  vmov          [[S2:s[0-9]]], r1
+; CHECK-SOFTFP-FP16-DAG:  vcvtb.f32.f16 [[S0]], [[S0]]
+; CHECK-SOFTFP-FP16-DAG:  vcvtb.f32.f16 [[S2]], [[S2]]
 ; CHECK-SOFTFP-FP16:  vmul.f32      [[S0]], [[S0]], [[S2]]
 ; CHECK-SOFTFP-FP16:  vcvtb.f16.f32 [[S0]], [[S0]]
 ; CHECK-SOFTFP-FP16:  vmov  r0, s0
 
 ; CHECK-SOFTFP-FULLFP16:       vmov.f16  [[S0:s[0-9]]], r1
 ; CHECK-SOFTFP-FULLFP16:       vmov.f16  [[S2:s[0-9]]], r0
 ; CHECK-SOFTFP-FULLFP16:       vmul.f16  [[S0]], [[S2]], [[S0]]
 ; CHECK-SOFTFP-FULLFP16-NEXT:  vmov.f16  r0, s0

 ; CHECK-SOFT:  bl  __aeabi_fsub
 ; CHECK-SOFT:  bl  __aeabi_f2h
 
 ; CHECK-SOFTFP-VFP3:  bl  __aeabi_h2f
 ; CHECK-SOFTFP-VFP3:  bl  __aeabi_h2f
 ; CHECK-SOFTFP-VFP3:  vsub.f32
 ; CHECK-SOFTFP-VFP3:  bl  __aeabi_f2h
 
-; CHECK-SOFTFP-FP16:  vmov          [[S2:s[0-9]]], r1
-; CHECK-SOFTFP-FP16:  vmov          [[S0:s[0-9]]], r0
-; CHECK-SOFTFP-FP16:  vcvtb.f32.f16 [[S2]], [[S2]]
-; CHECK-SOFTFP-FP16:  vcvtb.f32.f16 [[S0]], [[S0]]
+; CHECK-SOFTFP-FP16-DAG:  vmov          [[S0:s[0-9]]], r0
+; CHECK-SOFTFP-FP16-DAG:  vmov          [[S2:s[0-9]]], r1
+; CHECK-SOFTFP-FP16-DAG:  vcvtb.f32.f16 [[S0]], [[S0]]
+; CHECK-SOFTFP-FP16-DAG:  vcvtb.f32.f16 [[S2]], [[S2]]
 ; CHECK-SOFTFP-FP16:  vsub.f32      [[S0]], [[S0]], [[S2]]
 ; CHECK-SOFTFP-FP16:  vcvtb.f16.f32 [[S0]], [[S0]]
 ; CHECK-SOFTFP-FP16:  vmov  r0, s0
 
 ; CHECK-SOFTFP-FULLFP16:       vmov.f16  [[S0:s[0-9]]], r1
 ; CHECK-SOFTFP-FULLFP16:       vmov.f16  [[S2:s[0-9]]], r0
 ; CHECK-SOFTFP-FULLFP16:       vsub.f16  [[S0]], [[S2]], [[S0]]
 ; CHECK-SOFTFP-FULLFP16-NEXT:  vmov.f16  r0, s0

llvm/test/CodeGen/ARM/no-fpscr-liveness.ll

 ; RUN: llc -o - %s | FileCheck %s
 ; Make sure we do not try to compute liveness for FPSCR which in this case
 ; is read before being written to (this is fine because becase FPSCR is
 ; reserved).
 target triple = "thumbv7s-apple-ios"
 
 %struct.wibble = type { double }
 
 @global = common global i32 0, align 4
 @global.1 = common global i32 0, align 4
 
 ; CHECK-LABEL: eggs:
 ; CHECK: sub sp, #8
 ; VMRS instruction comes before any other instruction writing FPSCR:
-; CHECK-NEXT: vmrs r0, fpscr
+; CHECK-NOT: vcmp
+; CHECK: vmrs {{r[0-9]}}, fpscr
+; CHECK; vcmp
 ; ...
 ; CHECK: add sp, #8
 ; CHECK: bx lr
 define i32 @eggs(double* nocapture readnone %arg) {
 bb:
   %tmp = alloca %struct.wibble, align 4
   %tmp1 = bitcast %struct.wibble* %tmp to i8*
   %tmp2 = tail call i32 @llvm.flt.rounds()

llvm/test/CodeGen/ARM/vcvt.ll

 ; CHECK-NEXT:    vmov d18, r0, r1
 ; CHECK-NEXT:    mov r12, sp
 ; CHECK-NEXT:    vld1.64 {d16, d17}, [r12]
 ; CHECK-NEXT:    vmov d19, r2, r3
 ; CHECK-NEXT:    vadd.f64 d18, d18, d18
 ; CHECK-NEXT:    vcvt.s32.f64 s0, d18
 ; CHECK-NEXT:    vmov r0, s0
 ; CHECK-NEXT:    vadd.f64 d20, d16, d16
-; CHECK-NEXT:    vadd.f64 d19, d19, d19
 ; CHECK-NEXT:    vadd.f64 d16, d17, d17
 ; CHECK-NEXT:    vcvt.s32.f64 s2, d20
-; CHECK-NEXT:    vcvt.s32.f64 s4, d19
 ; CHECK-NEXT:    vcvt.s32.f64 s6, d16
 ; CHECK-NEXT:    vmov.32 d16[0], r0
 ; CHECK-NEXT:    vmov r0, s2
+; CHECK-NEXT:    vadd.f64 d19, d19, d19
+; CHECK-NEXT:    vcvt.s32.f64 s4, d19
 ; CHECK-NEXT:    vmov.32 d17[0], r0
 ; CHECK-NEXT:    vmov r0, s4
 ; CHECK-NEXT:    vmov.32 d16[1], r0
 ; CHECK-NEXT:    vmov r0, s6
 ; CHECK-NEXT:    vmov.32 d17[1], r0
 ; CHECK-NEXT:    vuzp.16 d16, d17
 ; CHECK-NEXT:    vmov r0, r1, d16
 ; CHECK-NEXT:    mov pc, lr
; CHECK-NEXT:    mov pc, lr
   ret <2 x i64> %conv
 }
 
 define i32 @multi_sint(double %c, i32* nocapture %p, i32* nocapture %q) {
 ; CHECK-LABEL: multi_sint:
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    vmov d16, r0, r1
 ; CHECK-NEXT:    vcvt.s32.f64 s0, d16
+; CHECK-NEXT:    vmov r0, s0
 ; CHECK-NEXT:    vstr s0, [r2]
-; CHECK-NEXT:    vcvt.s32.f64 s0, d16
-; CHECK-NEXT:    vcvt.s32.f64 s2, d16
-; CHECK-NEXT:    vmov r0, s2
 ; CHECK-NEXT:    vstr s0, [r3]
 ; CHECK-NEXT:    mov pc, lr
   %conv = fptosi double %c to i32
   store i32 %conv, i32* %p, align 4
   store i32 %conv, i32* %q, align 4
   ret i32 %conv
 }
 
 define i32 @multi_uint(double %c, i32* nocapture %p, i32* nocapture %q) {
 ; CHECK-LABEL: multi_uint:
 ; CHECK:       @ %bb.0:
 ; CHECK-NEXT:    vmov d16, r0, r1
 ; CHECK-NEXT:    vcvt.u32.f64 s0, d16
+; CHECK-NEXT:    vmov r0, s0
 ; CHECK-NEXT:    vstr s0, [r2]
-; CHECK-NEXT:    vcvt.u32.f64 s0, d16
-; CHECK-NEXT:    vcvt.u32.f64 s2, d16
-; CHECK-NEXT:    vmov r0, s2
 ; CHECK-NEXT:    vstr s0, [r3]
 ; CHECK-NEXT:    mov pc, lr
   %conv = fptoui double %c to i32
   store i32 %conv, i32* %p, align 4
   store i32 %conv, i32* %q, align 4
   ret i32 %conv
 }
 

llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-float-loops.ll

 ; CHECK-NEXT:  @ %bb.8: @ %for.body.prol.preheader
 ; CHECK-NEXT:    add.w r5, r0, r12, lsl #2
 ; CHECK-NEXT:    add.w r6, r1, r12, lsl #2
 ; CHECK-NEXT:    add.w r7, r2, r12, lsl #2
 ; CHECK-NEXT:  .LBB3_9: @ %for.body.prol
 ; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    ldr r4, [r6], #4
 ; CHECK-NEXT:    add.w r12, r12, #1
-; CHECK-NEXT:    vmov s0, r4
-; CHECK-NEXT:    vcvt.f32.s32 s0, s0
 ; CHECK-NEXT:    vldr s2, [r5]
 ; CHECK-NEXT:    adds r5, #4
+; CHECK-NEXT:    vmov s0, r4
+; CHECK-NEXT:    vcvt.f32.s32 s0, s0
 ; CHECK-NEXT:    vmul.f32 s0, s2, s0
 ; CHECK-NEXT:    vstr s0, [r7]
 ; CHECK-NEXT:    adds r7, #4
 ; CHECK-NEXT:    le lr, .LBB3_9
 ; CHECK-NEXT:  .LBB3_10: @ %for.body.prol.loopexit
 ; CHECK-NEXT:    cmp.w r8, #3
 ; CHECK-NEXT:    blo .LBB3_13
 ; CHECK-NEXT:  @ %bb.11: @ %for.body.preheader1

 ; CHECK-NEXT:    adds r0, #16
 ; CHECK-NEXT:    vcvt.f32.s32 s0, s0
 ; CHECK-NEXT:    vldr s2, [r7]
 ; CHECK-NEXT:    adds r2, #16
 ; CHECK-NEXT:    subs r3, #4
 ; CHECK-NEXT:    vmul.f32 s0, s2, s0
 ; CHECK-NEXT:    vstr s0, [r6]
 ; CHECK-NEXT:    vldr s0, [r1, #-4]
-; CHECK-NEXT:    vcvt.f32.s32 s0, s0
 ; CHECK-NEXT:    vldr s2, [r7, #4]
+; CHECK-NEXT:    vcvt.f32.s32 s0, s0
 ; CHECK-NEXT:    vmul.f32 s0, s2, s0
 ; CHECK-NEXT:    vstr s0, [r6, #4]
 ; CHECK-NEXT:    vldr s0, [r1]
-; CHECK-NEXT:    vcvt.f32.s32 s0, s0
 ; CHECK-NEXT:    vldr s2, [r7, #8]
+; CHECK-NEXT:    vcvt.f32.s32 s0, s0
 ; CHECK-NEXT:    vmul.f32 s0, s2, s0
 ; CHECK-NEXT:    vstr s0, [r6, #8]
 ; CHECK-NEXT:    vldr s0, [r1, #4]
 ; CHECK-NEXT:    add.w r1, r1, #16
-; CHECK-NEXT:    vcvt.f32.s32 s0, s0
 ; CHECK-NEXT:    vldr s2, [r7, #12]
+; CHECK-NEXT:    vcvt.f32.s32 s0, s0
 ; CHECK-NEXT:    vmul.f32 s0, s2, s0
 ; CHECK-NEXT:    vstr s0, [r6, #12]
 ; CHECK-NEXT:    bne .LBB3_12
 ; CHECK-NEXT:  .LBB3_13: @ %for.cond.cleanup
 ; CHECK-NEXT:    pop.w {r4, r5, r6, r7, r8, pc}
 entry:
   %cmp8 = icmp eq i32 %N, 0
   br i1 %cmp8, label %for.cond.cleanup, label %for.body.preheader

 ; CHECK-NEXT:    adds r2, r1, r3
 ; CHECK-NEXT:    vldr.16 s2, [r2, #6]
 ; CHECK-NEXT:    vldr.16 s4, [r4, #6]
 ; CHECK-NEXT:    vldr.16 s6, [r4, #4]
 ; CHECK-NEXT:    vldr.16 s8, [r4, #2]
 ; CHECK-NEXT:    vmul.f16 s2, s4, s2
 ; CHECK-NEXT:    vldr.16 s4, [r2, #4]
 ; CHECK-NEXT:    vldr.16 s10, [r4]
-; CHECK-NEXT:    adds r3, #8
+; CHECK-NEXT:    vcvtb.f32.f16 s2, s2
 ; CHECK-NEXT:    vmul.f16 s4, s6, s4
 ; CHECK-NEXT:    vldr.16 s6, [r2, #2]
-; CHECK-NEXT:    add.w r12, r12, #4
+; CHECK-NEXT:    vcvtb.f32.f16 s4, s4
+; CHECK-NEXT:    adds r3, #8
 ; CHECK-NEXT:    vmul.f16 s6, s8, s6
 ; CHECK-NEXT:    vldr.16 s8, [r2]
+; CHECK-NEXT:    vcvtb.f32.f16 s6, s6
+; CHECK-NEXT:    add.w r12, r12, #4
 ; CHECK-NEXT:    vmul.f16 s8, s10, s8
 ; CHECK-NEXT:    vcvtb.f32.f16 s8, s8
-; CHECK-NEXT:    vcvtb.f32.f16 s6, s6
 ; CHECK-NEXT:    vadd.f32 s0, s0, s8
-; CHECK-NEXT:    vcvtb.f32.f16 s4, s4
-; CHECK-NEXT:    vcvtb.f32.f16 s2, s2
 ; CHECK-NEXT:    vadd.f32 s0, s0, s6
 ; CHECK-NEXT:    vadd.f32 s0, s0, s4
 ; CHECK-NEXT:    vadd.f32 s0, s0, s2
 ; CHECK-NEXT:    le lr, .LBB9_5
 ; CHECK-NEXT:  .LBB9_6: @ %for.cond.cleanup.loopexit.unr-lcssa
 ; CHECK-NEXT:    wls lr, r5, .LBB9_9
 ; CHECK-NEXT:  @ %bb.7: @ %for.body.epil.preheader
 ; CHECK-NEXT:    add.w r0, r0, r12, lsl #1

 ; CHECK-NEXT:    adds r2, r1, r3
 ; CHECK-NEXT:    vldr.16 s2, [r2, #6]
 ; CHECK-NEXT:    vldr.16 s4, [r4, #6]
 ; CHECK-NEXT:    vldr.16 s6, [r4, #4]
 ; CHECK-NEXT:    vldr.16 s8, [r4, #2]
 ; CHECK-NEXT:    vadd.f16 s2, s4, s2
 ; CHECK-NEXT:    vldr.16 s4, [r2, #4]
 ; CHECK-NEXT:    vldr.16 s10, [r4]
-; CHECK-NEXT:    adds r3, #8
+; CHECK-NEXT:    vcvtb.f32.f16 s2, s2
 ; CHECK-NEXT:    vadd.f16 s4, s6, s4
 ; CHECK-NEXT:    vldr.16 s6, [r2, #2]
-; CHECK-NEXT:    add.w r12, r12, #4
+; CHECK-NEXT:    vcvtb.f32.f16 s4, s4
+; CHECK-NEXT:    adds r3, #8
 ; CHECK-NEXT:    vadd.f16 s6, s8, s6
 ; CHECK-NEXT:    vldr.16 s8, [r2]
+; CHECK-NEXT:    vcvtb.f32.f16 s6, s6
+; CHECK-NEXT:    add.w r12, r12, #4
 ; CHECK-NEXT:    vadd.f16 s8, s10, s8
 ; CHECK-NEXT:    vcvtb.f32.f16 s8, s8
-; CHECK-NEXT:    vcvtb.f32.f16 s6, s6
 ; CHECK-NEXT:    vadd.f32 s0, s0, s8
-; CHECK-NEXT:    vcvtb.f32.f16 s4, s4
-; CHECK-NEXT:    vcvtb.f32.f16 s2, s2
 ; CHECK-NEXT:    vadd.f32 s0, s0, s6
 ; CHECK-NEXT:    vadd.f32 s0, s0, s4
 ; CHECK-NEXT:    vadd.f32 s0, s0, s2
 ; CHECK-NEXT:    le lr, .LBB10_5
 ; CHECK-NEXT:  .LBB10_6: @ %for.cond.cleanup.loopexit.unr-lcssa
 ; CHECK-NEXT:    wls lr, r5, .LBB10_9
 ; CHECK-NEXT:  @ %bb.7: @ %for.body.epil.preheader
 ; CHECK-NEXT:    add.w r0, r0, r12, lsl #1

 ; CHECK-NEXT:    add.w lr, r3, r2, lsr #2
 ; CHECK-NEXT:    adds r3, r1, #4
 ; CHECK-NEXT:    adds r2, r0, #4
 ; CHECK-NEXT:    dls lr, lr
 ; CHECK-NEXT:  .LBB11_5: @ %for.body
 ; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    ldrsh.w r4, [r3, #2]
 ; CHECK-NEXT:    vldr.16 s2, [r2, #2]
+; CHECK-NEXT:    ldrsh r5, [r3, #-2]
 ; CHECK-NEXT:    add.w r12, r12, #4
 ; CHECK-NEXT:    vmov s4, r4
-; CHECK-NEXT:    vcvt.f16.s32 s4, s4
 ; CHECK-NEXT:    ldrsh.w r4, [r3]
+; CHECK-NEXT:    vcvt.f16.s32 s4, s4
+; CHECK-NEXT:    vmov s8, r5
 ; CHECK-NEXT:    vmul.f16 s2, s2, s4
 ; CHECK-NEXT:    vldr.16 s4, [r2]
 ; CHECK-NEXT:    vmov s6, r4
-; CHECK-NEXT:    vcvt.f16.s32 s6, s6
-; CHECK-NEXT:    ldrsh r5, [r3, #-2]
 ; CHECK-NEXT:    ldrsh r4, [r3, #-4]
+; CHECK-NEXT:    vcvt.f16.s32 s6, s6
+; CHECK-NEXT:    vcvt.f16.s32 s8, s8
 ; CHECK-NEXT:    vmul.f16 s4, s4, s6
 ; CHECK-NEXT:    vldr.16 s6, [r2, #-2]
-; CHECK-NEXT:    adds r3, #8
-; CHECK-NEXT:    vmov s8, r5
-; CHECK-NEXT:    vcvt.f16.s32 s8, s8
 ; CHECK-NEXT:    vmov s10, r4
+; CHECK-NEXT:    vcvtb.f32.f16 s4, s4
 ; CHECK-NEXT:    vmul.f16 s6, s6, s8
 ; CHECK-NEXT:    vldr.16 s8, [r2, #-4]
 ; CHECK-NEXT:    vcvt.f16.s32 s10, s10
-; CHECK-NEXT:    adds r2, #8
+; CHECK-NEXT:    vcvtb.f32.f16 s6, s6
 ; CHECK-NEXT:    vmul.f16 s8, s8, s10
+; CHECK-NEXT:    vcvtb.f32.f16 s2, s2
 ; CHECK-NEXT:    vcvtb.f32.f16 s8, s8
-; CHECK-NEXT:    vcvtb.f32.f16 s6, s6
+; CHECK-NEXT:    adds r3, #8
 ; CHECK-NEXT:    vadd.f32 s0, s0, s8
-; CHECK-NEXT:    vcvtb.f32.f16 s4, s4
-; CHECK-NEXT:    vcvtb.f32.f16 s2, s2
+; CHECK-NEXT:    adds r2, #8
 ; CHECK-NEXT:    vadd.f32 s0, s0, s6
 ; CHECK-NEXT:    vadd.f32 s0, s0, s4
 ; CHECK-NEXT:    vadd.f32 s0, s0, s2
 ; CHECK-NEXT:    le lr, .LBB11_5
 ; CHECK-NEXT:  .LBB11_6: @ %for.cond.cleanup.loopexit.unr-lcssa
 ; CHECK-NEXT:    wls lr, r6, .LBB11_9
 ; CHECK-NEXT:  @ %bb.7: @ %for.body.epil.preheader
 ; CHECK-NEXT:    add.w r0, r0, r12, lsl #1

llvm/test/CodeGen/Thumb2/mve-masked-store.ll

entry:
   ret void
 }
 
 define arm_aapcs_vfpcc void @masked_v4f16_align4(<4 x half> *%dest, <4 x float> %a) {
 ; CHECK-LE-LABEL: masked_v4f16_align4:
 ; CHECK-LE:       @ %bb.0: @ %entry
 ; CHECK-LE-NEXT:    .pad #4
 ; CHECK-LE-NEXT:    sub sp, #4
-; CHECK-LE-NEXT:    vcvtb.f16.f32 s4, s0
 ; CHECK-LE-NEXT:    vcmp.f32 s0, #0
-; CHECK-LE-NEXT:    vcvtt.f16.f32 s4, s1
+; CHECK-LE-NEXT:    movs r1, #0
 ; CHECK-LE-NEXT:    vmrs APSR_nzcv, fpscr
-; CHECK-LE-NEXT:    vcvtb.f16.f32 s5, s2
-; CHECK-LE-NEXT:    mov.w r1, #0
-; CHECK-LE-NEXT:    vcvtt.f16.f32 s5, s3
 ; CHECK-LE-NEXT:    it gt
 ; CHECK-LE-NEXT:    movgt r1, #1
 ; CHECK-LE-NEXT:    cmp r1, #0
 ; CHECK-LE-NEXT:    vcmp.f32 s1, #0
 ; CHECK-LE-NEXT:    cset r1, ne
 ; CHECK-LE-NEXT:    vmrs APSR_nzcv, fpscr
 ; CHECK-LE-NEXT:    and r1, r1, #1
 ; CHECK-LE-NEXT:    vcmp.f32 s2, #0

 ; CHECK-LE-NEXT:    vmrs APSR_nzcv, fpscr
 ; CHECK-LE-NEXT:    it gt
 ; CHECK-LE-NEXT:    movgt r2, #1
 ; CHECK-LE-NEXT:    cmp r2, #0
 ; CHECK-LE-NEXT:    and r3, r3, #1
 ; CHECK-LE-NEXT:    cset r2, ne
 ; CHECK-LE-NEXT:    and r2, r2, #1
 ; CHECK-LE-NEXT:    rsbs r3, r3, #0
+; CHECK-LE-NEXT:    vcvtb.f16.f32 s4, s0
 ; CHECK-LE-NEXT:    bfi r1, r3, #2, #1
 ; CHECK-LE-NEXT:    rsbs r2, r2, #0
+; CHECK-LE-NEXT:    vcvtt.f16.f32 s4, s1
 ; CHECK-LE-NEXT:    bfi r1, r2, #3, #1
+; CHECK-LE-NEXT:    vcvtb.f16.f32 s5, s2
+; CHECK-LE-NEXT:    vcvtt.f16.f32 s5, s3
 ; CHECK-LE-NEXT:    lsls r2, r1, #31
 ; CHECK-LE-NEXT:    bne .LBB25_5
 ; CHECK-LE-NEXT:  @ %bb.1: @ %else
 ; CHECK-LE-NEXT:    lsls r2, r1, #30
 ; CHECK-LE-NEXT:    bmi .LBB25_6
 ; CHECK-LE-NEXT:  .LBB25_2: @ %else2
 ; CHECK-LE-NEXT:    lsls r2, r1, #29
 ; CHECK-LE-NEXT:    bmi .LBB25_7

 ; CHECK-LE-NEXT:    bx lr
 ;
 ; CHECK-BE-LABEL: masked_v4f16_align4:
 ; CHECK-BE:       @ %bb.0: @ %entry
 ; CHECK-BE-NEXT:    .pad #4
 ; CHECK-BE-NEXT:    sub sp, #4
 ; CHECK-BE-NEXT:    vrev64.32 q1, q0
 ; CHECK-BE-NEXT:    movs r1, #0
-; CHECK-BE-NEXT:    vcvtb.f16.f32 s0, s4
 ; CHECK-BE-NEXT:    vcmp.f32 s4, #0
-; CHECK-BE-NEXT:    vcvtt.f16.f32 s0, s5
+; CHECK-BE-NEXT:    movs r2, #0
 ; CHECK-BE-NEXT:    vmrs APSR_nzcv, fpscr
-; CHECK-BE-NEXT:    vcvtb.f16.f32 s1, s6
-; CHECK-BE-NEXT:    vcmp.f32 s5, #0
-; CHECK-BE-NEXT:    vcvtt.f16.f32 s1, s7
 ; CHECK-BE-NEXT:    it gt
 ; CHECK-BE-NEXT:    movgt r1, #1
 ; CHECK-BE-NEXT:    cmp r1, #0
-; CHECK-BE-NEXT:    mov.w r2, #0
+; CHECK-BE-NEXT:    vcmp.f32 s5, #0
 ; CHECK-BE-NEXT:    cset r1, ne
 ; CHECK-BE-NEXT:    vmrs APSR_nzcv, fpscr
 ; CHECK-BE-NEXT:    and r1, r1, #1
 ; CHECK-BE-NEXT:    vcmp.f32 s6, #0
 ; CHECK-BE-NEXT:    rsb.w r3, r1, #0
 ; CHECK-BE-NEXT:    mov.w r1, #0
 ; CHECK-BE-NEXT:    bfi r1, r3, #0, #1
 ; CHECK-BE-NEXT:    mov.w r3, #0
 ; CHECK-BE-NEXT:    it gt
 ; CHECK-BE-NEXT:    movgt r3, #1
 ; CHECK-BE-NEXT:    cmp r3, #0
 ; CHECK-BE-NEXT:    cset r3, ne
 ; CHECK-BE-NEXT:    vmrs APSR_nzcv, fpscr
 ; CHECK-BE-NEXT:    and r3, r3, #1
 ; CHECK-BE-NEXT:    vcmp.f32 s7, #0
 ; CHECK-BE-NEXT:    rsb.w r3, r3, #0
+; CHECK-BE-NEXT:    vcvtb.f16.f32 s0, s4
 ; CHECK-BE-NEXT:    bfi r1, r3, #1, #1
 ; CHECK-BE-NEXT:    mov.w r3, #0
 ; CHECK-BE-NEXT:    it gt
 ; CHECK-BE-NEXT:    movgt r3, #1
 ; CHECK-BE-NEXT:    cmp r3, #0
 ; CHECK-BE-NEXT:    cset r3, ne
 ; CHECK-BE-NEXT:    vmrs APSR_nzcv, fpscr
 ; CHECK-BE-NEXT:    it gt
 ; CHECK-BE-NEXT:    movgt r2, #1
 ; CHECK-BE-NEXT:    cmp r2, #0
 ; CHECK-BE-NEXT:    and r3, r3, #1
 ; CHECK-BE-NEXT:    cset r2, ne
 ; CHECK-BE-NEXT:    and r2, r2, #1
 ; CHECK-BE-NEXT:    rsbs r3, r3, #0
 ; CHECK-BE-NEXT:    bfi r1, r3, #2, #1
 ; CHECK-BE-NEXT:    rsbs r2, r2, #0
+; CHECK-BE-NEXT:    vcvtt.f16.f32 s0, s5
 ; CHECK-BE-NEXT:    bfi r1, r2, #3, #1
+; CHECK-BE-NEXT:    vcvtb.f16.f32 s1, s6
+; CHECK-BE-NEXT:    vcvtt.f16.f32 s1, s7
 ; CHECK-BE-NEXT:    lsls r2, r1, #31
 ; CHECK-BE-NEXT:    bne .LBB25_5
 ; CHECK-BE-NEXT:  @ %bb.1: @ %else
 ; CHECK-BE-NEXT:    lsls r2, r1, #30
 ; CHECK-BE-NEXT:    bmi .LBB25_6
 ; CHECK-BE-NEXT:  .LBB25_2: @ %else2
 ; CHECK-BE-NEXT:    lsls r2, r1, #29
 ; CHECK-BE-NEXT:    bmi .LBB25_7
entry:
   ret void
 }
 
 define arm_aapcs_vfpcc void @masked_v4f16_align2(<4 x half> *%dest, <4 x float> %a) {
 ; CHECK-LE-LABEL: masked_v4f16_align2:
 ; CHECK-LE:       @ %bb.0: @ %entry
 ; CHECK-LE-NEXT:    .pad #4
 ; CHECK-LE-NEXT:    sub sp, #4
-; CHECK-LE-NEXT:    vcvtb.f16.f32 s4, s0
 ; CHECK-LE-NEXT:    vcmp.f32 s0, #0
-; CHECK-LE-NEXT:    vcvtt.f16.f32 s4, s1
+; CHECK-LE-NEXT:    movs r1, #0
 ; CHECK-LE-NEXT:    vmrs APSR_nzcv, fpscr
-; CHECK-LE-NEXT:    vcvtb.f16.f32 s5, s2
-; CHECK-LE-NEXT:    mov.w r1, #0
-; CHECK-LE-NEXT:    vcvtt.f16.f32 s5, s3
 ; CHECK-LE-NEXT:    it gt
 ; CHECK-LE-NEXT:    movgt r1, #1
 ; CHECK-LE-NEXT:    cmp r1, #0
 ; CHECK-LE-NEXT:    vcmp.f32 s1, #0
 ; CHECK-LE-NEXT:    cset r1, ne
 ; CHECK-LE-NEXT:    vmrs APSR_nzcv, fpscr
 ; CHECK-LE-NEXT:    and r1, r1, #1
 ; CHECK-LE-NEXT:    vcmp.f32 s2, #0

 ; CHECK-LE-NEXT:    vmrs APSR_nzcv, fpscr
 ; CHECK-LE-NEXT:    it gt
 ; CHECK-LE-NEXT:    movgt r2, #1
 ; CHECK-LE-NEXT:    cmp r2, #0
 ; CHECK-LE-NEXT:    and r3, r3, #1
 ; CHECK-LE-NEXT:    cset r2, ne
 ; CHECK-LE-NEXT:    and r2, r2, #1
 ; CHECK-LE-NEXT:    rsbs r3, r3, #0
+; CHECK-LE-NEXT:    vcvtb.f16.f32 s4, s0
 ; CHECK-LE-NEXT:    bfi r1, r3, #2, #1
 ; CHECK-LE-NEXT:    rsbs r2, r2, #0
+; CHECK-LE-NEXT:    vcvtt.f16.f32 s4, s1
 ; CHECK-LE-NEXT:    bfi r1, r2, #3, #1
+; CHECK-LE-NEXT:    vcvtb.f16.f32 s5, s2
+; CHECK-LE-NEXT:    vcvtt.f16.f32 s5, s3
 ; CHECK-LE-NEXT:    lsls r2, r1, #31
 ; CHECK-LE-NEXT:    bne .LBB26_5
 ; CHECK-LE-NEXT:  @ %bb.1: @ %else
 ; CHECK-LE-NEXT:    lsls r2, r1, #30
 ; CHECK-LE-NEXT:    bmi .LBB26_6
 ; CHECK-LE-NEXT:  .LBB26_2: @ %else2
 ; CHECK-LE-NEXT:    lsls r2, r1, #29
 ; CHECK-LE-NEXT:    bmi .LBB26_7

 ; CHECK-LE-NEXT:    bx lr
 ;
 ; CHECK-BE-LABEL: masked_v4f16_align2:
 ; CHECK-BE:       @ %bb.0: @ %entry
 ; CHECK-BE-NEXT:    .pad #4
 ; CHECK-BE-NEXT:    sub sp, #4
 ; CHECK-BE-NEXT:    vrev64.32 q1, q0
 ; CHECK-BE-NEXT:    movs r1, #0
-; CHECK-BE-NEXT:    vcvtb.f16.f32 s0, s4
 ; CHECK-BE-NEXT:    vcmp.f32 s4, #0
-; CHECK-BE-NEXT:    vcvtt.f16.f32 s0, s5
+; CHECK-BE-NEXT:    movs r2, #0
 ; CHECK-BE-NEXT:    vmrs APSR_nzcv, fpscr
-; CHECK-BE-NEXT:    vcvtb.f16.f32 s1, s6
-; CHECK-BE-NEXT:    vcmp.f32 s5, #0
-; CHECK-BE-NEXT:    vcvtt.f16.f32 s1, s7
 ; CHECK-BE-NEXT:    it gt
 ; CHECK-BE-NEXT:    movgt r1, #1
 ; CHECK-BE-NEXT:    cmp r1, #0
-; CHECK-BE-NEXT:    mov.w r2, #0
+; CHECK-BE-NEXT:    vcmp.f32 s5, #0
 ; CHECK-BE-NEXT:    cset r1, ne
 ; CHECK-BE-NEXT:    vmrs APSR_nzcv, fpscr
 ; CHECK-BE-NEXT:    and r1, r1, #1
 ; CHECK-BE-NEXT:    vcmp.f32 s6, #0
 ; CHECK-BE-NEXT:    rsb.w r3, r1, #0
 ; CHECK-BE-NEXT:    mov.w r1, #0
 ; CHECK-BE-NEXT:    bfi r1, r3, #0, #1
 ; CHECK-BE-NEXT:    mov.w r3, #0
 ; CHECK-BE-NEXT:    it gt
 ; CHECK-BE-NEXT:    movgt r3, #1
 ; CHECK-BE-NEXT:    cmp r3, #0
 ; CHECK-BE-NEXT:    cset r3, ne
 ; CHECK-BE-NEXT:    vmrs APSR_nzcv, fpscr
 ; CHECK-BE-NEXT:    and r3, r3, #1
 ; CHECK-BE-NEXT:    vcmp.f32 s7, #0
 ; CHECK-BE-NEXT:    rsb.w r3, r3, #0
+; CHECK-BE-NEXT:    vcvtb.f16.f32 s0, s4
 ; CHECK-BE-NEXT:    bfi r1, r3, #1, #1
 ; CHECK-BE-NEXT:    mov.w r3, #0
 ; CHECK-BE-NEXT:    it gt
 ; CHECK-BE-NEXT:    movgt r3, #1
 ; CHECK-BE-NEXT:    cmp r3, #0
 ; CHECK-BE-NEXT:    cset r3, ne
 ; CHECK-BE-NEXT:    vmrs APSR_nzcv, fpscr
 ; CHECK-BE-NEXT:    it gt
 ; CHECK-BE-NEXT:    movgt r2, #1
 ; CHECK-BE-NEXT:    cmp r2, #0
 ; CHECK-BE-NEXT:    and r3, r3, #1
 ; CHECK-BE-NEXT:    cset r2, ne
 ; CHECK-BE-NEXT:    and r2, r2, #1
 ; CHECK-BE-NEXT:    rsbs r3, r3, #0
 ; CHECK-BE-NEXT:    bfi r1, r3, #2, #1
 ; CHECK-BE-NEXT:    rsbs r2, r2, #0
+; CHECK-BE-NEXT:    vcvtt.f16.f32 s0, s5
 ; CHECK-BE-NEXT:    bfi r1, r2, #3, #1
+; CHECK-BE-NEXT:    vcvtb.f16.f32 s1, s6
+; CHECK-BE-NEXT:    vcvtt.f16.f32 s1, s7
 ; CHECK-BE-NEXT:    lsls r2, r1, #31
 ; CHECK-BE-NEXT:    bne .LBB26_5
 ; CHECK-BE-NEXT:  @ %bb.1: @ %else
 ; CHECK-BE-NEXT:    lsls r2, r1, #30
 ; CHECK-BE-NEXT:    bmi .LBB26_6
 ; CHECK-BE-NEXT:  .LBB26_2: @ %else2
 ; CHECK-BE-NEXT:    lsls r2, r1, #29
 ; CHECK-BE-NEXT:    bmi .LBB26_7
entry:
   ret void
 }
 
 define arm_aapcs_vfpcc void @masked_v4f16_align1(<4 x half> *%dest, <4 x float> %a) {
 ; CHECK-LE-LABEL: masked_v4f16_align1:
 ; CHECK-LE:       @ %bb.0: @ %entry
 ; CHECK-LE-NEXT:    .pad #20
 ; CHECK-LE-NEXT:    sub sp, #20
-; CHECK-LE-NEXT:    vcvtb.f16.f32 s4, s0
 ; CHECK-LE-NEXT:    vcmp.f32 s0, #0
-; CHECK-LE-NEXT:    vcvtt.f16.f32 s4, s1
+; CHECK-LE-NEXT:    movs r1, #0
 ; CHECK-LE-NEXT:    vmrs APSR_nzcv, fpscr
-; CHECK-LE-NEXT:    vcvtb.f16.f32 s5, s2
-; CHECK-LE-NEXT:    mov.w r1, #0
-; CHECK-LE-NEXT:    vcvtt.f16.f32 s5, s3
 ; CHECK-LE-NEXT:    it gt
 ; CHECK-LE-NEXT:    movgt r1, #1
 ; CHECK-LE-NEXT:    cmp r1, #0
 ; CHECK-LE-NEXT:    vcmp.f32 s1, #0
 ; CHECK-LE-NEXT:    cset r1, ne
 ; CHECK-LE-NEXT:    vmrs APSR_nzcv, fpscr
 ; CHECK-LE-NEXT:    and r1, r1, #1
 ; CHECK-LE-NEXT:    vcmp.f32 s2, #0

 ; CHECK-LE-NEXT:    vmrs APSR_nzcv, fpscr
 ; CHECK-LE-NEXT:    it gt
 ; CHECK-LE-NEXT:    movgt r2, #1
 ; CHECK-LE-NEXT:    cmp r2, #0
 ; CHECK-LE-NEXT:    and r3, r3, #1
 ; CHECK-LE-NEXT:    cset r2, ne
 ; CHECK-LE-NEXT:    and r2, r2, #1
 ; CHECK-LE-NEXT:    rsbs r3, r3, #0
+; CHECK-LE-NEXT:    vcvtb.f16.f32 s4, s0
 ; CHECK-LE-NEXT:    bfi r1, r3, #2, #1
 ; CHECK-LE-NEXT:    rsbs r2, r2, #0
+; CHECK-LE-NEXT:    vcvtt.f16.f32 s4, s1
 ; CHECK-LE-NEXT:    bfi r1, r2, #3, #1
+; CHECK-LE-NEXT:    vcvtb.f16.f32 s5, s2
+; CHECK-LE-NEXT:    vcvtt.f16.f32 s5, s3
 ; CHECK-LE-NEXT:    lsls r2, r1, #31
 ; CHECK-LE-NEXT:    bne .LBB27_5
 ; CHECK-LE-NEXT:  @ %bb.1: @ %else
 ; CHECK-LE-NEXT:    lsls r2, r1, #30
 ; CHECK-LE-NEXT:    bmi .LBB27_6
 ; CHECK-LE-NEXT:  .LBB27_2: @ %else2
 ; CHECK-LE-NEXT:    lsls r2, r1, #29
 ; CHECK-LE-NEXT:    bmi .LBB27_7

 ; CHECK-LE-NEXT:    bx lr
 ;
 ; CHECK-BE-LABEL: masked_v4f16_align1:
 ; CHECK-BE:       @ %bb.0: @ %entry
 ; CHECK-BE-NEXT:    .pad #20
 ; CHECK-BE-NEXT:    sub sp, #20
 ; CHECK-BE-NEXT:    vrev64.32 q1, q0
 ; CHECK-BE-NEXT:    movs r1, #0
-; CHECK-BE-NEXT:    vcvtb.f16.f32 s0, s4
 ; CHECK-BE-NEXT:    vcmp.f32 s4, #0
-; CHECK-BE-NEXT:    vcvtt.f16.f32 s0, s5
+; CHECK-BE-NEXT:    movs r2, #0
 ; CHECK-BE-NEXT:    vmrs APSR_nzcv, fpscr
-; CHECK-BE-NEXT:    vcvtb.f16.f32 s1, s6
-; CHECK-BE-NEXT:    vcmp.f32 s5, #0
-; CHECK-BE-NEXT:    vcvtt.f16.f32 s1, s7
 ; CHECK-BE-NEXT:    it gt
 ; CHECK-BE-NEXT:    movgt r1, #1
 ; CHECK-BE-NEXT:    cmp r1, #0
-; CHECK-BE-NEXT:    mov.w r2, #0
+; CHECK-BE-NEXT:    vcmp.f32 s5, #0
 ; CHECK-BE-NEXT:    cset r1, ne
 ; CHECK-BE-NEXT:    vmrs APSR_nzcv, fpscr
 ; CHECK-BE-NEXT:    and r1, r1, #1
 ; CHECK-BE-NEXT:    vcmp.f32 s6, #0
 ; CHECK-BE-NEXT:    rsb.w r3, r1, #0
 ; CHECK-BE-NEXT:    mov.w r1, #0
 ; CHECK-BE-NEXT:    bfi r1, r3, #0, #1
 ; CHECK-BE-NEXT:    mov.w r3, #0
 ; CHECK-BE-NEXT:    it gt
 ; CHECK-BE-NEXT:    movgt r3, #1
 ; CHECK-BE-NEXT:    cmp r3, #0
 ; CHECK-BE-NEXT:    cset r3, ne
 ; CHECK-BE-NEXT:    vmrs APSR_nzcv, fpscr
 ; CHECK-BE-NEXT:    and r3, r3, #1
 ; CHECK-BE-NEXT:    vcmp.f32 s7, #0
 ; CHECK-BE-NEXT:    rsb.w r3, r3, #0
+; CHECK-BE-NEXT:    vcvtb.f16.f32 s0, s4
 ; CHECK-BE-NEXT:    bfi r1, r3, #1, #1
 ; CHECK-BE-NEXT:    mov.w r3, #0
 ; CHECK-BE-NEXT:    it gt
 ; CHECK-BE-NEXT:    movgt r3, #1
 ; CHECK-BE-NEXT:    cmp r3, #0
 ; CHECK-BE-NEXT:    cset r3, ne
 ; CHECK-BE-NEXT:    vmrs APSR_nzcv, fpscr
 ; CHECK-BE-NEXT:    it gt
 ; CHECK-BE-NEXT:    movgt r2, #1
 ; CHECK-BE-NEXT:    cmp r2, #0
 ; CHECK-BE-NEXT:    and r3, r3, #1
 ; CHECK-BE-NEXT:    cset r2, ne
 ; CHECK-BE-NEXT:    and r2, r2, #1
 ; CHECK-BE-NEXT:    rsbs r3, r3, #0
 ; CHECK-BE-NEXT:    bfi r1, r3, #2, #1
 ; CHECK-BE-NEXT:    rsbs r2, r2, #0
+; CHECK-BE-NEXT:    vcvtt.f16.f32 s0, s5
 ; CHECK-BE-NEXT:    bfi r1, r2, #3, #1
+; CHECK-BE-NEXT:    vcvtb.f16.f32 s1, s6
+; CHECK-BE-NEXT:    vcvtt.f16.f32 s1, s7
 ; CHECK-BE-NEXT:    lsls r2, r1, #31
 ; CHECK-BE-NEXT:    bne .LBB27_5
 ; CHECK-BE-NEXT:  @ %bb.1: @ %else
 ; CHECK-BE-NEXT:    lsls r2, r1, #30
 ; CHECK-BE-NEXT:    bmi .LBB27_6
 ; CHECK-BE-NEXT:  .LBB27_2: @ %else2
 ; CHECK-BE-NEXT:    lsls r2, r1, #29
 ; CHECK-BE-NEXT:    bmi .LBB27_7

llvm/test/CodeGen/Thumb2/mve-vcvt.ll

 entry:
   %out = uitofp <8 x i16> %src to <8 x half>
   ret <8 x half> %out
 }
 
 define arm_aapcs_vfpcc <8 x i16> @foo_int16_half(<8 x half> %src) {
 ; CHECK-MVE-LABEL: foo_int16_half:
 ; CHECK-MVE:       @ %bb.0: @ %entry
+; CHECK-MVE-NEXT:    vmovx.f16 s14, s0
+; CHECK-MVE-NEXT:    vcvt.s32.f16 s0, s0
+; CHECK-MVE-NEXT:    vcvt.s32.f16 s14, s14
+; CHECK-MVE-NEXT:    vmov r0, s0
 ; CHECK-MVE-NEXT:    vmovx.f16 s4, s3
 ; CHECK-MVE-NEXT:    vmovx.f16 s6, s2
 ; CHECK-MVE-NEXT:    vmovx.f16 s10, s1
-; CHECK-MVE-NEXT:    vmovx.f16 s14, s0
-; CHECK-MVE-NEXT:    vcvt.s32.f16 s4, s4
-; CHECK-MVE-NEXT:    vcvt.s32.f16 s6, s6
 ; CHECK-MVE-NEXT:    vcvt.s32.f16 s8, s3
-; CHECK-MVE-NEXT:    vcvt.s32.f16 s10, s10
 ; CHECK-MVE-NEXT:    vcvt.s32.f16 s12, s2
-; CHECK-MVE-NEXT:    vcvt.s32.f16 s14, s14
 ; CHECK-MVE-NEXT:    vcvt.s32.f16 s5, s1
-; CHECK-MVE-NEXT:    vcvt.s32.f16 s0, s0
-; CHECK-MVE-NEXT:    vmov r0, s0
 ; CHECK-MVE-NEXT:    vmov.16 q0[0], r0
 ; CHECK-MVE-NEXT:    vmov r0, s14
 ; CHECK-MVE-NEXT:    vmov.16 q0[1], r0
 ; CHECK-MVE-NEXT:    vmov r0, s5
+; CHECK-MVE-NEXT:    vcvt.s32.f16 s10, s10
 ; CHECK-MVE-NEXT:    vmov.16 q0[2], r0
 ; CHECK-MVE-NEXT:    vmov r0, s10
+; CHECK-MVE-NEXT:    vcvt.s32.f16 s6, s6
 ; CHECK-MVE-NEXT:    vmov.16 q0[3], r0
 ; CHECK-MVE-NEXT:    vmov r0, s12
 ; CHECK-MVE-NEXT:    vmov.16 q0[4], r0
 ; CHECK-MVE-NEXT:    vmov r0, s6
 ; CHECK-MVE-NEXT:    vmov.16 q0[5], r0
 ; CHECK-MVE-NEXT:    vmov r0, s8
+; CHECK-MVE-NEXT:    vcvt.s32.f16 s4, s4
 ; CHECK-MVE-NEXT:    vmov.16 q0[6], r0
 ; CHECK-MVE-NEXT:    vmov r0, s4
 ; CHECK-MVE-NEXT:    vmov.16 q0[7], r0
 ; CHECK-MVE-NEXT:    bx lr
 ;
 ; CHECK-MVEFP-LABEL: foo_int16_half:
 ; CHECK-MVEFP:       @ %bb.0: @ %entry
 ; CHECK-MVEFP-NEXT:    vcvt.s16.f16 q0, q0
 ; CHECK-MVEFP-NEXT:    bx lr
 entry:
   %out = fptosi <8 x half> %src to <8 x i16>
   ret <8 x i16> %out
 }
 
 define arm_aapcs_vfpcc <8 x i16> @foo_uint16_half(<8 x half> %src) {
 ; CHECK-MVE-LABEL: foo_uint16_half:
 ; CHECK-MVE:       @ %bb.0: @ %entry
+; CHECK-MVE-NEXT:    vmovx.f16 s14, s0
+; CHECK-MVE-NEXT:    vcvt.s32.f16 s0, s0
+; CHECK-MVE-NEXT:    vcvt.s32.f16 s14, s14
+; CHECK-MVE-NEXT:    vmov r0, s0
 ; CHECK-MVE-NEXT:    vmovx.f16 s4, s3
 ; CHECK-MVE-NEXT:    vmovx.f16 s6, s2
 ; CHECK-MVE-NEXT:    vmovx.f16 s10, s1
-; CHECK-MVE-NEXT:    vmovx.f16 s14, s0
-; CHECK-MVE-NEXT:    vcvt.s32.f16 s4, s4
-; CHECK-MVE-NEXT:    vcvt.s32.f16 s6, s6
 ; CHECK-MVE-NEXT:    vcvt.s32.f16 s8, s3
-; CHECK-MVE-NEXT:    vcvt.s32.f16 s10, s10
 ; CHECK-MVE-NEXT:    vcvt.s32.f16 s12, s2
-; CHECK-MVE-NEXT:    vcvt.s32.f16 s14, s14
 ; CHECK-MVE-NEXT:    vcvt.s32.f16 s5, s1
-; CHECK-MVE-NEXT:    vcvt.s32.f16 s0, s0
-; CHECK-MVE-NEXT:    vmov r0, s0
 ; CHECK-MVE-NEXT:    vmov.16 q0[0], r0
 ; CHECK-MVE-NEXT:    vmov r0, s14
 ; CHECK-MVE-NEXT:    vmov.16 q0[1], r0
 ; CHECK-MVE-NEXT:    vmov r0, s5
+; CHECK-MVE-NEXT:    vcvt.s32.f16 s10, s10
 ; CHECK-MVE-NEXT:    vmov.16 q0[2], r0
 ; CHECK-MVE-NEXT:    vmov r0, s10
+; CHECK-MVE-NEXT:    vcvt.s32.f16 s6, s6
 ; CHECK-MVE-NEXT:    vmov.16 q0[3], r0
 ; CHECK-MVE-NEXT:    vmov r0, s12
 ; CHECK-MVE-NEXT:    vmov.16 q0[4], r0
 ; CHECK-MVE-NEXT:    vmov r0, s6
 ; CHECK-MVE-NEXT:    vmov.16 q0[5], r0
 ; CHECK-MVE-NEXT:    vmov r0, s8
+; CHECK-MVE-NEXT:    vcvt.s32.f16 s4, s4
 ; CHECK-MVE-NEXT:    vmov.16 q0[6], r0
 ; CHECK-MVE-NEXT:    vmov r0, s4
 ; CHECK-MVE-NEXT:    vmov.16 q0[7], r0
 ; CHECK-MVE-NEXT:    bx lr
 ;
 ; CHECK-MVEFP-LABEL: foo_uint16_half:
 ; CHECK-MVEFP:       @ %bb.0: @ %entry
 ; CHECK-MVEFP-NEXT:    vcvt.u16.f16 q0, q0

llvm/test/CodeGen/Thumb2/mve-vcvt16.ll

 entry:
   %out = fpext <4 x half> %src1 to <4 x float>
   ret <4 x float> %out
 }
 
 define arm_aapcs_vfpcc <8 x float> @fpext_8(<8 x half> %src1) {
 ; CHECK-LABEL: fpext_8:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vcvtt.f32.f16 s11, s1
-; CHECK-NEXT:    vcvtb.f32.f16 s10, s1
-; CHECK-NEXT:    vcvtt.f32.f16 s9, s0
-; CHECK-NEXT:    vcvtb.f32.f16 s8, s0
-; CHECK-NEXT:    vcvtt.f32.f16 s7, s3
-; CHECK-NEXT:    vcvtb.f32.f16 s6, s3
-; CHECK-NEXT:    vcvtt.f32.f16 s5, s2
-; CHECK-NEXT:    vcvtb.f32.f16 s4, s2
-; CHECK-NEXT:    vmov q0, q2
+; CHECK-NEXT:    vmov q2, q0
+; CHECK-NEXT:    vcvtt.f32.f16 s3, s9
+; CHECK-NEXT:    vcvtt.f32.f16 s7, s11
+; CHECK-NEXT:    vcvtb.f32.f16 s2, s9
+; CHECK-NEXT:    vcvtb.f32.f16 s6, s11
+; CHECK-NEXT:    vcvtt.f32.f16 s1, s8
+; CHECK-NEXT:    vcvtt.f32.f16 s5, s10
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s8
+; CHECK-NEXT:    vcvtb.f32.f16 s4, s10
 ; CHECK-NEXT:    bx lr
 entry:
   %out = fpext <8 x half> %src1 to <8 x float>
   ret <8 x float> %out
 }
 
 
 define arm_aapcs_vfpcc <4 x half> @fptrunc_4(<4 x float> %src1) {

 }
 
 define arm_aapcs_vfpcc <8 x float> @load_shuffleext_16(<16 x half>* %src) {
 ; CHECK-LABEL: load_shuffleext_16:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vld20.16 {q2, q3}, [r0]
 ; CHECK-NEXT:    vld21.16 {q2, q3}, [r0]
 ; CHECK-NEXT:    vcvtt.f32.f16 s3, s9
-; CHECK-NEXT:    vcvtb.f32.f16 s2, s9
-; CHECK-NEXT:    vcvtt.f32.f16 s1, s8
-; CHECK-NEXT:    vcvtb.f32.f16 s0, s8
 ; CHECK-NEXT:    vcvtt.f32.f16 s7, s11
+; CHECK-NEXT:    vcvtb.f32.f16 s2, s9
 ; CHECK-NEXT:    vcvtb.f32.f16 s6, s11
+; CHECK-NEXT:    vcvtt.f32.f16 s1, s8
 ; CHECK-NEXT:    vcvtt.f32.f16 s5, s10
+; CHECK-NEXT:    vcvtb.f32.f16 s0, s8
 ; CHECK-NEXT:    vcvtb.f32.f16 s4, s10
 ; CHECK-NEXT:    bx lr
 entry:
   %wide.load = load <16 x half>, <16 x half>* %src, align 4
   %sh = shufflevector <16 x half> %wide.load, <16 x half> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
   %e = fpext <8 x half> %sh to <8 x float>
   ret <8 x float> %e
 }

llvm/unittests/Target/ARM/MachineInstrTest.cpp

for (auto &Op : Desc.operands()) {
       break;
     }
   }
 }
 
 TEST(MachineInstr, HasSideEffects) {
   using namespace ARM;
   std::set<unsigned> UnpredictableOpcodes = {
-      MVE_VCTP8,     MVE_VCTP16,    MVE_VCTP32,    MVE_VCTP64,    MVE_VPST,
-      MVE_VPTv16i8,  MVE_VPTv8i16,  MVE_VPTv4i32,  MVE_VPTv16i8r, MVE_VPTv8i16r,
-      MVE_VPTv4i32r, MVE_VPTv16s8,  MVE_VPTv8s16,  MVE_VPTv4s32,  MVE_VPTv16s8r,
-      MVE_VPTv8s16r, MVE_VPTv4s32r, MVE_VPTv16u8,  MVE_VPTv8u16,  MVE_VPTv4u32,
-      MVE_VPTv16u8r, MVE_VPTv8u16r, MVE_VPTv4u32r, MVE_VPTv8f16,  MVE_VPTv4f32,
-      MVE_VPTv8f16r, MVE_VPTv4f32r, MVE_VADC,      MVE_VADCI,     MVE_VSBC,
-      MVE_VSBCI,     MVE_VSHLC,
+      // MVE Instructions
+      MVE_VCTP8,
+      MVE_VCTP16,
+      MVE_VCTP32,
+      MVE_VCTP64,
+      MVE_VPST,
+      MVE_VPTv16i8,
+      MVE_VPTv8i16,
+      MVE_VPTv4i32,
+      MVE_VPTv16i8r,
+      MVE_VPTv8i16r,
+      MVE_VPTv4i32r,
+      MVE_VPTv16s8,
+      MVE_VPTv8s16,
+      MVE_VPTv4s32,
+      MVE_VPTv16s8r,
+      MVE_VPTv8s16r,
+      MVE_VPTv4s32r,
+      MVE_VPTv16u8,
+      MVE_VPTv8u16,
+      MVE_VPTv4u32,
+      MVE_VPTv16u8r,
+      MVE_VPTv8u16r,
+      MVE_VPTv4u32r,
+      MVE_VPTv8f16,
+      MVE_VPTv4f32,
+      MVE_VPTv8f16r,
+      MVE_VPTv4f32r,
+      MVE_VADC,
+      MVE_VADCI,
+      MVE_VSBC,
+      MVE_VSBCI,
+      MVE_VSHLC,
+      // FP Instructions
+      FLDMXIA,
+      FLDMXDB_UPD,
+      FLDMXIA_UPD,
+      FSTMXDB_UPD,
+      FSTMXIA,
+      FSTMXIA_UPD,
+      VLDR_FPCXTNS_off,
+      VLDR_FPCXTNS_off,
+      VLDR_FPCXTNS_post,
+      VLDR_FPCXTNS_pre,
+      VLDR_FPCXTS_off,
+      VLDR_FPCXTS_post,
+      VLDR_FPCXTS_pre,
+      VLDR_FPSCR_NZCVQC_off,
+      VLDR_FPSCR_NZCVQC_post,
+      VLDR_FPSCR_NZCVQC_pre,
+      VLDR_FPSCR_off,
+      VLDR_FPSCR_post,
+      VLDR_FPSCR_pre,
+      VLDR_P0_off,
+      VLDR_P0_post,
+      VLDR_P0_pre,
+      VLDR_VPR_off,
+      VLDR_VPR_post,
+      VLDR_VPR_pre,
+      VLLDM,
+      VLSTM,
+      VMRS,
+      VMRS_FPCXTNS,
+      VMRS_FPCXTS,
+      VMRS_FPEXC,
+      VMRS_FPINST,
+      VMRS_FPINST2,
+      VMRS_FPSCR_NZCVQC,
+      VMRS_FPSID,
+      VMRS_MVFR0,
+      VMRS_MVFR1,
+      VMRS_MVFR2,
+      VMRS_P0,
+      VMRS_VPR,
+      VMSR,
+      VMSR_FPCXTNS,
+      VMSR_FPCXTS,
+      VMSR_FPEXC,
+      VMSR_FPINST,
+      VMSR_FPINST2,
+      VMSR_FPSCR_NZCVQC,
+      VMSR_FPSID,
+      VMSR_P0,
+      VMSR_VPR,
+      VSCCLRMD,
+      VSCCLRMS,
+      VSTR_FPCXTNS_off,
+      VSTR_FPCXTNS_post,
+      VSTR_FPCXTNS_pre,
+      VSTR_FPCXTS_off,
+      VSTR_FPCXTS_post,
+      VSTR_FPCXTS_pre,
+      VSTR_FPSCR_NZCVQC_off,
+      VSTR_FPSCR_NZCVQC_post,
+      VSTR_FPSCR_NZCVQC_pre,
+      VSTR_FPSCR_off,
+      VSTR_FPSCR_post,
+      VSTR_FPSCR_pre,
+      VSTR_P0_off,
+      VSTR_P0_post,
+      VSTR_P0_pre,
+      VSTR_VPR_off,
+      VSTR_VPR_post,
+      VSTR_VPR_pre,
   };
 
   LLVMInitializeARMTargetInfo();
   LLVMInitializeARMTarget();
   LLVMInitializeARMTargetMC();
 
   auto TT(Triple::normalize("thumbv8.1m.main-none-none-eabi"));
   std::string Error;
TEST(MachineInstr, HasSideEffects) {
   ARMSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),
                   std::string(TM->getTargetFeatureString()),
                   *static_cast<const ARMBaseTargetMachine *>(TM.get()), false);
   const ARMBaseInstrInfo *TII = ST.getInstrInfo();
   auto MII = TM->getMCInstrInfo();
 
   for (unsigned Op = 0; Op < ARM::INSTRUCTION_LIST_END; ++Op) {
     const MCInstrDesc &Desc = TII->get(Op);
-    if ((Desc.TSFlags & ARMII::DomainMask) != ARMII::DomainMVE)
+    if ((Desc.TSFlags & ARMII::DomainMask) != ARMII::DomainMVE &&
+        (Desc.TSFlags & ARMII::DomainMask) != ARMII::DomainVFP)
       continue;
     if (UnpredictableOpcodes.count(Op))
       continue;
 
     ASSERT_FALSE(Desc.hasUnmodeledSideEffects())
         << MII->getName(Op) << " has unexpected side effects";
   }
 }