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Differential D81637

[ARM] VCVTT fpround instruction selection
ClosedPublic

Authored by dmgreen on Jun 11 2020, 2:35 AM.

Details

Reviewers
ostannard
efriedma
SjoerdMeijer
simon_tatham
samparker
Commits
rGd428f8815208: [ARM] VCVTT fpround instruction selection
Summary

Similar to D81556, this adds vcvtb and vcvtt with insert into vector instruction selection patterns. This helps clear up a lot of register shuffling that we would otherwise do.

Diff Detail

Event Timeline

dmgreen created this revision.Jun 11 2020, 2:35 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 11 2020, 2:35 AM
Herald added subscribers: danielkiss, hiraditya, kristof.beyls. · View Herald Transcript
samparker accepted this revision.Jun 11 2020, 6:12 AM

LGTM

This revision is now accepted and ready to land.Jun 11 2020, 6:12 AM
Closed by commit rGd428f8815208: [ARM] VCVTT fpround instruction selection (authored by dmgreen). · Explain WhyJun 26 2020, 2:41 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
lib/
Target/
ARM/
15 lines
test/
CodeGen/
ARM/
50 lines
Thumb2/
43 lines
344 lines
102 lines
44 lines

Diff 270058

llvm/lib/Target/ARM/ARMInstrVFP.td

Show First 20 Lines • Show All 725 Lines • ▼ Show 20 Linesdef VCVTBSH: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
[/* Intentionally left blank, see patterns below */]>, [/* Intentionally left blank, see patterns below */]>,
Requires<[HasFP16]>, Requires<[HasFP16]>,
Sched<[WriteFPCVT]>; Sched<[WriteFPCVT]>;
def : FP16Pat<(f16 (fpround SPR:$Sm)), def : FP16Pat<(f16 (fpround SPR:$Sm)),
(COPY_TO_REGCLASS (VCVTBSH SPR:$Sm), HPR)>; (COPY_TO_REGCLASS (VCVTBSH SPR:$Sm), HPR)>;
def : FP16Pat<(fp_to_f16 SPR:$a), def : FP16Pat<(fp_to_f16 SPR:$a),
(i32 (COPY_TO_REGCLASS (VCVTBSH SPR:$a), GPR))>; (i32 (COPY_TO_REGCLASS (VCVTBSH SPR:$a), GPR))>;
def : FP16Pat<(insertelt (v8f16 MQPR:$src1), (f16 (fpround (f32 SPR:$src2))), imm_even:$lane),
(v8f16 (INSERT_SUBREG (v8f16 MQPR:$src1), (VCVTBSH SPR:$src2),
(SSubReg_f16_reg imm:$lane)))>;
def : FP16Pat<(insertelt (v4f16 DPR:$src1), (f16 (fpround (f32 SPR:$src2))), imm_even:$lane),
(v4f16 (INSERT_SUBREG (v4f16 DPR:$src1), (VCVTBSH SPR:$src2),
(SSubReg_f16_reg imm:$lane)))>;
def VCVTTHS: ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm), def VCVTTHS: ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
/* FIXME */ IIC_fpCVTSH, "vcvtt", ".f32.f16\t$Sd, $Sm", /* FIXME */ IIC_fpCVTSH, "vcvtt", ".f32.f16\t$Sd, $Sm",
[/* Intentionally left blank, see patterns below */]>, [/* Intentionally left blank, see patterns below */]>,
Requires<[HasFP16]>, Requires<[HasFP16]>,
Sched<[WriteFPCVT]>; Sched<[WriteFPCVT]>;
def : FP16Pat<(f32 (fpextend (extractelt (v8f16 MQPR:$src), imm_odd:$lane))), def : FP16Pat<(f32 (fpextend (extractelt (v8f16 MQPR:$src), imm_odd:$lane))),
(VCVTTHS (EXTRACT_SUBREG MQPR:$src, (SSubReg_f16_reg imm_odd:$lane)))>; (VCVTTHS (EXTRACT_SUBREG MQPR:$src, (SSubReg_f16_reg imm_odd:$lane)))>;
def : FP16Pat<(f32 (fpextend (extractelt (v4f16 DPR:$src), imm_odd:$lane))), def : FP16Pat<(f32 (fpextend (extractelt (v4f16 DPR:$src), imm_odd:$lane))),
(VCVTTHS (EXTRACT_SUBREG (VCVTTHS (EXTRACT_SUBREG
(v2f32 (COPY_TO_REGCLASS (v4f16 DPR:$src), DPR_VFP2)), (v2f32 (COPY_TO_REGCLASS (v4f16 DPR:$src), DPR_VFP2)),
(SSubReg_f16_reg imm_odd:$lane)))>; (SSubReg_f16_reg imm_odd:$lane)))>;
def VCVTTSH: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm), def VCVTTSH: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
/* FIXME */ IIC_fpCVTHS, "vcvtt", ".f16.f32\t$Sd, $Sm", /* FIXME */ IIC_fpCVTHS, "vcvtt", ".f16.f32\t$Sd, $Sm",
[/* For disassembly only; pattern left blank */]>, [/* Intentionally left blank, see patterns below */]>,
Requires<[HasFP16]>, Requires<[HasFP16]>,
Sched<[WriteFPCVT]>; Sched<[WriteFPCVT]>;
def : FP16Pat<(insertelt (v8f16 MQPR:$src1), (f16 (fpround (f32 SPR:$src2))), imm_odd:$lane),
(v8f16 (INSERT_SUBREG (v8f16 MQPR:$src1), (VCVTTSH SPR:$src2),
(SSubReg_f16_reg imm:$lane)))>;
def : FP16Pat<(insertelt (v4f16 DPR:$src1), (f16 (fpround (f32 SPR:$src2))), imm_odd:$lane),
(v4f16 (INSERT_SUBREG (v4f16 DPR:$src1), (VCVTTSH SPR:$src2),
(SSubReg_f16_reg imm:$lane)))>;
def VCVTBHD : ADuI<0b11101, 0b11, 0b0010, 0b01, 0, def VCVTBHD : ADuI<0b11101, 0b11, 0b0010, 0b01, 0,
(outs DPR:$Dd), (ins SPR:$Sm), (outs DPR:$Dd), (ins SPR:$Sm),
NoItinerary, "vcvtb", ".f64.f16\t$Dd, $Sm", NoItinerary, "vcvtb", ".f64.f16\t$Dd, $Sm",
[/* Intentionally left blank, see patterns below */]>, [/* Intentionally left blank, see patterns below */]>,
Requires<[HasFPARMv8, HasDPVFP]>, Requires<[HasFPARMv8, HasDPVFP]>,
Sched<[WriteFPCVT]> { Sched<[WriteFPCVT]> {
// Instruction operands. // Instruction operands.
bits<5> Sm; bits<5> Sm;
▲ Show 20 Lines • Show All 2,041 Lines • Show Last 20 Lines

llvm/test/CodeGen/ARM/fp16-insert-extract.ll

Show First 20 Lines • Show All 71 Lines • ▼ Show 20 Linesentry:
%elt = extractelement <8 x half> %a, i32 7 %elt = extractelement <8 x half> %a, i32 7
%conv = fpext half %elt to float %conv = fpext half %elt to float
ret float %conv ret float %conv
} }
define <4 x half> @test_vset_lane_f16(<4 x half> %a, float %fb) nounwind { define <4 x half> @test_vset_lane_f16(<4 x half> %a, float %fb) nounwind {
; CHECKHARD-LABEL: test_vset_lane_f16: ; CHECKHARD-LABEL: test_vset_lane_f16:
; CHECKHARD: @ %bb.0: @ %entry ; CHECKHARD: @ %bb.0: @ %entry
; CHECKHARD-NEXT: vcvtb.f16.f32 s2, s2 ; CHECKHARD-NEXT: vcvtt.f16.f32 s1, s2
; CHECKHARD-NEXT: vmov.f16 r0, s2
; CHECKHARD-NEXT: vmov.16 d0[3], r0
; CHECKHARD-NEXT: bx lr ; CHECKHARD-NEXT: bx lr
; ;
; CHECKSOFT-LABEL: test_vset_lane_f16: ; CHECKSOFT-LABEL: test_vset_lane_f16:
; CHECKSOFT: @ %bb.0: @ %entry ; CHECKSOFT: @ %bb.0: @ %entry
; CHECKSOFT-NEXT: vmov s0, r2 ; CHECKSOFT-NEXT: vmov d0, r0, r1
; CHECKSOFT-NEXT: vcvtb.f16.f32 s0, s0 ; CHECKSOFT-NEXT: vmov s2, r2
; CHECKSOFT-NEXT: vmov d16, r0, r1 ; CHECKSOFT-NEXT: vcvtt.f16.f32 s1, s2
; CHECKSOFT-NEXT: vmov.f16 r2, s0 ; CHECKSOFT-NEXT: vmov r0, r1, d0
; CHECKSOFT-NEXT: vmov.16 d16[3], r2
; CHECKSOFT-NEXT: vmov r0, r1, d16
; CHECKSOFT-NEXT: bx lr ; CHECKSOFT-NEXT: bx lr
entry: entry:
%b = fptrunc float %fb to half %b = fptrunc float %fb to half
%x = insertelement <4 x half> %a, half %b, i32 3 %x = insertelement <4 x half> %a, half %b, i32 3
ret <4 x half> %x ret <4 x half> %x
} }
define <8 x half> @test_vset_laneq_f16_1(<8 x half> %a, float %fb) nounwind { define <8 x half> @test_vset_laneq_f16_1(<8 x half> %a, float %fb) nounwind {
; CHECKHARD-LABEL: test_vset_laneq_f16_1: ; CHECKHARD-LABEL: test_vset_laneq_f16_1:
; CHECKHARD: @ %bb.0: @ %entry ; CHECKHARD: @ %bb.0: @ %entry
; CHECKHARD-NEXT: vcvtb.f16.f32 s4, s4 ; CHECKHARD-NEXT: vcvtt.f16.f32 s0, s4
; CHECKHARD-NEXT: vmov.f16 r0, s4
; CHECKHARD-NEXT: vmov.16 d0[1], r0
; CHECKHARD-NEXT: bx lr ; CHECKHARD-NEXT: bx lr
; ;
; CHECKSOFT-LABEL: test_vset_laneq_f16_1: ; CHECKSOFT-LABEL: test_vset_laneq_f16_1:
; CHECKSOFT: @ %bb.0: @ %entry ; CHECKSOFT: @ %bb.0: @ %entry
; CHECKSOFT-NEXT: vldr s0, [sp] ; CHECKSOFT-NEXT: vmov d1, r2, r3
; CHECKSOFT-NEXT: vmov d17, r2, r3 ; CHECKSOFT-NEXT: vldr s4, [sp]
; CHECKSOFT-NEXT: vmov d16, r0, r1 ; CHECKSOFT-NEXT: vmov d0, r0, r1
; CHECKSOFT-NEXT: vcvtb.f16.f32 s0, s0 ; CHECKSOFT-NEXT: vcvtt.f16.f32 s0, s4
; CHECKSOFT-NEXT: vmov.f16 r12, s0 ; CHECKSOFT-NEXT: vmov r2, r3, d1
; CHECKSOFT-NEXT: vmov.16 d16[1], r12 ; CHECKSOFT-NEXT: vmov r0, r1, d0
; CHECKSOFT-NEXT: vmov r2, r3, d17
; CHECKSOFT-NEXT: vmov r0, r1, d16
; CHECKSOFT-NEXT: bx lr ; CHECKSOFT-NEXT: bx lr
entry: entry:
%b = fptrunc float %fb to half %b = fptrunc float %fb to half
%x = insertelement <8 x half> %a, half %b, i32 1 %x = insertelement <8 x half> %a, half %b, i32 1
ret <8 x half> %x ret <8 x half> %x
} }
define <8 x half> @test_vset_laneq_f16_7(<8 x half> %a, float %fb) nounwind { define <8 x half> @test_vset_laneq_f16_7(<8 x half> %a, float %fb) nounwind {
; CHECKHARD-LABEL: test_vset_laneq_f16_7: ; CHECKHARD-LABEL: test_vset_laneq_f16_7:
; CHECKHARD: @ %bb.0: @ %entry ; CHECKHARD: @ %bb.0: @ %entry
; CHECKHARD-NEXT: vcvtb.f16.f32 s4, s4 ; CHECKHARD-NEXT: vcvtt.f16.f32 s3, s4
; CHECKHARD-NEXT: vmov.f16 r0, s4
; CHECKHARD-NEXT: vmov.16 d1[3], r0
; CHECKHARD-NEXT: bx lr ; CHECKHARD-NEXT: bx lr
; ;
; CHECKSOFT-LABEL: test_vset_laneq_f16_7: ; CHECKSOFT-LABEL: test_vset_laneq_f16_7:
; CHECKSOFT: @ %bb.0: @ %entry ; CHECKSOFT: @ %bb.0: @ %entry
; CHECKSOFT-NEXT: vldr s0, [sp] ; CHECKSOFT-NEXT: vmov d1, r2, r3
; CHECKSOFT-NEXT: vmov d17, r2, r3 ; CHECKSOFT-NEXT: vldr s4, [sp]
; CHECKSOFT-NEXT: vmov d16, r0, r1 ; CHECKSOFT-NEXT: vmov d0, r0, r1
; CHECKSOFT-NEXT: vcvtb.f16.f32 s0, s0 ; CHECKSOFT-NEXT: vcvtt.f16.f32 s3, s4
; CHECKSOFT-NEXT: vmov.f16 r12, s0 ; CHECKSOFT-NEXT: vmov r0, r1, d0
; CHECKSOFT-NEXT: vmov.16 d17[3], r12 ; CHECKSOFT-NEXT: vmov r2, r3, d1
; CHECKSOFT-NEXT: vmov r0, r1, d16
; CHECKSOFT-NEXT: vmov r2, r3, d17
; CHECKSOFT-NEXT: bx lr ; CHECKSOFT-NEXT: bx lr
entry: entry:
%b = fptrunc float %fb to half %b = fptrunc float %fb to half
%x = insertelement <8 x half> %a, half %b, i32 7 %x = insertelement <8 x half> %a, half %b, i32 7
ret <8 x half> %x ret <8 x half> %x
} }

llvm/test/CodeGen/Thumb2/mve-div-expand.ll

Show First 20 Lines • Show All 962 Lines • ▼ Show 20 Lines
entry: entry:
%out = fdiv <8 x half> %in1, %in2 %out = fdiv <8 x half> %in1, %in2
ret <8 x half> %out ret <8 x half> %out
} }
define arm_aapcs_vfpcc <8 x half> @frem_f16(<8 x half> %in1, <8 x half> %in2) { define arm_aapcs_vfpcc <8 x half> @frem_f16(<8 x half> %in1, <8 x half> %in2) {
; CHECK-LABEL: frem_f16: ; CHECK-LABEL: frem_f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, lr} ; CHECK-NEXT: .save {r7, lr}
; CHECK-NEXT: push {r4, lr} ; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: vmov q5, q0 ; CHECK-NEXT: vmov q5, q0
; CHECK-NEXT: vmov q4, q1 ; CHECK-NEXT: vmov q4, q1
; CHECK-NEXT: vcvtb.f32.f16 s0, s20 ; CHECK-NEXT: vcvtb.f32.f16 s0, s20
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s16 ; CHECK-NEXT: vcvtb.f32.f16 s0, s16
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: bl fmodf ; CHECK-NEXT: bl fmodf
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r4, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s20 ; CHECK-NEXT: vcvtt.f32.f16 s0, s20
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov s24, r0
; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s16 ; CHECK-NEXT: vcvtt.f32.f16 s0, s16
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: mov r0, r2
; CHECK-NEXT: bl fmodf ; CHECK-NEXT: bl fmodf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vmov.16 q6[0], r4 ; CHECK-NEXT: vcvtb.f16.f32 s24, s24
; CHECK-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-NEXT: vcvtt.f16.f32 s24, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s21 ; CHECK-NEXT: vcvtb.f32.f16 s0, s21
; CHECK-NEXT: vmov.16 q6[1], r0
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s17 ; CHECK-NEXT: vcvtb.f32.f16 s0, s17
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: bl fmodf ; CHECK-NEXT: bl fmodf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-NEXT: vcvtb.f16.f32 s25, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s21 ; CHECK-NEXT: vcvtt.f32.f16 s0, s21
; CHECK-NEXT: vmov.16 q6[2], r0
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s17 ; CHECK-NEXT: vcvtt.f32.f16 s0, s17
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: bl fmodf ; CHECK-NEXT: bl fmodf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-NEXT: vcvtt.f16.f32 s25, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s22 ; CHECK-NEXT: vcvtb.f32.f16 s0, s22
; CHECK-NEXT: vmov.16 q6[3], r0
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s18 ; CHECK-NEXT: vcvtb.f32.f16 s0, s18
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: bl fmodf ; CHECK-NEXT: bl fmodf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-NEXT: vcvtb.f16.f32 s26, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s22 ; CHECK-NEXT: vcvtt.f32.f16 s0, s22
; CHECK-NEXT: vmov.16 q6[4], r0
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s18 ; CHECK-NEXT: vcvtt.f32.f16 s0, s18
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: bl fmodf ; CHECK-NEXT: bl fmodf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-NEXT: vcvtt.f16.f32 s26, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s23 ; CHECK-NEXT: vcvtb.f32.f16 s0, s23
; CHECK-NEXT: vmov.16 q6[5], r0
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s19 ; CHECK-NEXT: vcvtb.f32.f16 s0, s19
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: bl fmodf ; CHECK-NEXT: bl fmodf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-NEXT: vcvtb.f16.f32 s27, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s23 ; CHECK-NEXT: vcvtt.f32.f16 s0, s23
; CHECK-NEXT: vmov.16 q6[6], r0
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s19 ; CHECK-NEXT: vcvtt.f32.f16 s0, s19
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: bl fmodf ; CHECK-NEXT: bl fmodf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-NEXT: vcvtt.f16.f32 s27, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q6[7], r0
; CHECK-NEXT: vmov q0, q6 ; CHECK-NEXT: vmov q0, q6
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: pop {r4, pc} ; CHECK-NEXT: pop {r7, pc}
entry: entry:
%out = frem <8 x half> %in1, %in2 %out = frem <8 x half> %in1, %in2
ret <8 x half> %out ret <8 x half> %out
} }
define arm_aapcs_vfpcc <2 x double> @fdiv_f64(<2 x double> %in1, <2 x double> %in2) { define arm_aapcs_vfpcc <2 x double> @fdiv_f64(<2 x double> %in1, <2 x double> %in2) {
; CHECK-LABEL: fdiv_f64: ; CHECK-LABEL: fdiv_f64:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
▲ Show 20 Lines • Show All 52 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-fmath.ll

Show First 20 Lines • Show All 106 Lines • ▼ Show 20 Lines
entry: entry:
%0 = call fast <4 x float> @llvm.cos.v4f32(<4 x float> %src) %0 = call fast <4 x float> @llvm.cos.v4f32(<4 x float> %src)
ret <4 x float> %0 ret <4 x float> %0
} }
define arm_aapcs_vfpcc <8 x half> @cos_float16_t(<8 x half> %src) { define arm_aapcs_vfpcc <8 x half> @cos_float16_t(<8 x half> %src) {
; CHECK-LABEL: cos_float16_t: ; CHECK-LABEL: cos_float16_t:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, lr} ; CHECK-NEXT: .save {r7, lr}
; CHECK-NEXT: push {r4, lr} ; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-NEXT: vpush {d8, d9, d10, d11} ; CHECK-NEXT: vpush {d8, d9, d10, d11}
; CHECK-NEXT: vmov q4, q0 ; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vcvtb.f32.f16 s0, s16 ; CHECK-NEXT: vcvtb.f32.f16 s0, s16
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl cosf ; CHECK-NEXT: bl cosf
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r4, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s16 ; CHECK-NEXT: vcvtt.f32.f16 s0, s16
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov s20, r0
; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: mov r0, r1
; CHECK-NEXT: bl cosf ; CHECK-NEXT: bl cosf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vmov.16 q5[0], r4 ; CHECK-NEXT: vcvtb.f16.f32 s20, s20
; CHECK-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-NEXT: vcvtt.f16.f32 s20, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s17 ; CHECK-NEXT: vcvtb.f32.f16 s0, s17
; CHECK-NEXT: vmov.16 q5[1], r0
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl cosf ; CHECK-NEXT: bl cosf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-NEXT: vcvtb.f16.f32 s21, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s17 ; CHECK-NEXT: vcvtt.f32.f16 s0, s17
; CHECK-NEXT: vmov.16 q5[2], r0
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl cosf ; CHECK-NEXT: bl cosf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-NEXT: vcvtt.f16.f32 s21, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s18 ; CHECK-NEXT: vcvtb.f32.f16 s0, s18
; CHECK-NEXT: vmov.16 q5[3], r0
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl cosf ; CHECK-NEXT: bl cosf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-NEXT: vcvtb.f16.f32 s22, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s18 ; CHECK-NEXT: vcvtt.f32.f16 s0, s18
; CHECK-NEXT: vmov.16 q5[4], r0
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl cosf ; CHECK-NEXT: bl cosf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-NEXT: vcvtt.f16.f32 s22, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s19 ; CHECK-NEXT: vcvtb.f32.f16 s0, s19
; CHECK-NEXT: vmov.16 q5[5], r0
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl cosf ; CHECK-NEXT: bl cosf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-NEXT: vcvtb.f16.f32 s23, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s19 ; CHECK-NEXT: vcvtt.f32.f16 s0, s19
; CHECK-NEXT: vmov.16 q5[6], r0
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl cosf ; CHECK-NEXT: bl cosf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-NEXT: vcvtt.f16.f32 s23, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q5[7], r0
; CHECK-NEXT: vmov q0, q5 ; CHECK-NEXT: vmov q0, q5
; CHECK-NEXT: vpop {d8, d9, d10, d11} ; CHECK-NEXT: vpop {d8, d9, d10, d11}
; CHECK-NEXT: pop {r4, pc} ; CHECK-NEXT: pop {r7, pc}
entry: entry:
%0 = call fast <8 x half> @llvm.cos.v8f16(<8 x half> %src) %0 = call fast <8 x half> @llvm.cos.v8f16(<8 x half> %src)
ret <8 x half> %0 ret <8 x half> %0
} }
define arm_aapcs_vfpcc <2 x double> @cos_float64_t(<2 x double> %src) { define arm_aapcs_vfpcc <2 x double> @cos_float64_t(<2 x double> %src) {
; CHECK-LABEL: cos_float64_t: ; CHECK-LABEL: cos_float64_t:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
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entry: entry:
%0 = call fast <4 x float> @llvm.sin.v4f32(<4 x float> %src) %0 = call fast <4 x float> @llvm.sin.v4f32(<4 x float> %src)
ret <4 x float> %0 ret <4 x float> %0
} }
define arm_aapcs_vfpcc <8 x half> @sin_float16_t(<8 x half> %src) { define arm_aapcs_vfpcc <8 x half> @sin_float16_t(<8 x half> %src) {
; CHECK-LABEL: sin_float16_t: ; CHECK-LABEL: sin_float16_t:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, lr} ; CHECK-NEXT: .save {r7, lr}
; CHECK-NEXT: push {r4, lr} ; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-NEXT: vpush {d8, d9, d10, d11} ; CHECK-NEXT: vpush {d8, d9, d10, d11}
; CHECK-NEXT: vmov q4, q0 ; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vcvtb.f32.f16 s0, s16 ; CHECK-NEXT: vcvtb.f32.f16 s0, s16
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl sinf ; CHECK-NEXT: bl sinf
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r4, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s16 ; CHECK-NEXT: vcvtt.f32.f16 s0, s16
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov s20, r0
; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: mov r0, r1
; CHECK-NEXT: bl sinf ; CHECK-NEXT: bl sinf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vmov.16 q5[0], r4 ; CHECK-NEXT: vcvtb.f16.f32 s20, s20
; CHECK-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-NEXT: vcvtt.f16.f32 s20, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s17 ; CHECK-NEXT: vcvtb.f32.f16 s0, s17
; CHECK-NEXT: vmov.16 q5[1], r0
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl sinf ; CHECK-NEXT: bl sinf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-NEXT: vcvtb.f16.f32 s21, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s17 ; CHECK-NEXT: vcvtt.f32.f16 s0, s17
; CHECK-NEXT: vmov.16 q5[2], r0
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl sinf ; CHECK-NEXT: bl sinf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-NEXT: vcvtt.f16.f32 s21, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s18 ; CHECK-NEXT: vcvtb.f32.f16 s0, s18
; CHECK-NEXT: vmov.16 q5[3], r0
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl sinf ; CHECK-NEXT: bl sinf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-NEXT: vcvtb.f16.f32 s22, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s18 ; CHECK-NEXT: vcvtt.f32.f16 s0, s18
; CHECK-NEXT: vmov.16 q5[4], r0
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl sinf ; CHECK-NEXT: bl sinf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-NEXT: vcvtt.f16.f32 s22, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s19 ; CHECK-NEXT: vcvtb.f32.f16 s0, s19
; CHECK-NEXT: vmov.16 q5[5], r0
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl sinf ; CHECK-NEXT: bl sinf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-NEXT: vcvtb.f16.f32 s23, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s19 ; CHECK-NEXT: vcvtt.f32.f16 s0, s19
; CHECK-NEXT: vmov.16 q5[6], r0
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl sinf ; CHECK-NEXT: bl sinf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-NEXT: vcvtt.f16.f32 s23, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q5[7], r0
; CHECK-NEXT: vmov q0, q5 ; CHECK-NEXT: vmov q0, q5
; CHECK-NEXT: vpop {d8, d9, d10, d11} ; CHECK-NEXT: vpop {d8, d9, d10, d11}
; CHECK-NEXT: pop {r4, pc} ; CHECK-NEXT: pop {r7, pc}
entry: entry:
%0 = call fast <8 x half> @llvm.sin.v8f16(<8 x half> %src) %0 = call fast <8 x half> @llvm.sin.v8f16(<8 x half> %src)
ret <8 x half> %0 ret <8 x half> %0
} }
define arm_aapcs_vfpcc <2 x double> @sin_float64_t(<2 x double> %src) { define arm_aapcs_vfpcc <2 x double> @sin_float64_t(<2 x double> %src) {
; CHECK-LABEL: sin_float64_t: ; CHECK-LABEL: sin_float64_t:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
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entry: entry:
%0 = call fast <4 x float> @llvm.exp.v4f32(<4 x float> %src) %0 = call fast <4 x float> @llvm.exp.v4f32(<4 x float> %src)
ret <4 x float> %0 ret <4 x float> %0
} }
define arm_aapcs_vfpcc <8 x half> @exp_float16_t(<8 x half> %src) { define arm_aapcs_vfpcc <8 x half> @exp_float16_t(<8 x half> %src) {
; CHECK-LABEL: exp_float16_t: ; CHECK-LABEL: exp_float16_t:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, lr} ; CHECK-NEXT: .save {r7, lr}
; CHECK-NEXT: push {r4, lr} ; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-NEXT: vpush {d8, d9, d10, d11} ; CHECK-NEXT: vpush {d8, d9, d10, d11}
; CHECK-NEXT: vmov q4, q0 ; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vcvtb.f32.f16 s0, s16 ; CHECK-NEXT: vcvtb.f32.f16 s0, s16
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl expf ; CHECK-NEXT: bl expf
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r4, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s16 ; CHECK-NEXT: vcvtt.f32.f16 s0, s16
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov s20, r0
; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: mov r0, r1
; CHECK-NEXT: bl expf ; CHECK-NEXT: bl expf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vmov.16 q5[0], r4 ; CHECK-NEXT: vcvtb.f16.f32 s20, s20
; CHECK-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-NEXT: vcvtt.f16.f32 s20, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s17 ; CHECK-NEXT: vcvtb.f32.f16 s0, s17
; CHECK-NEXT: vmov.16 q5[1], r0
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl expf ; CHECK-NEXT: bl expf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-NEXT: vcvtb.f16.f32 s21, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s17 ; CHECK-NEXT: vcvtt.f32.f16 s0, s17
; CHECK-NEXT: vmov.16 q5[2], r0
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl expf ; CHECK-NEXT: bl expf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-NEXT: vcvtt.f16.f32 s21, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s18 ; CHECK-NEXT: vcvtb.f32.f16 s0, s18
; CHECK-NEXT: vmov.16 q5[3], r0
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl expf ; CHECK-NEXT: bl expf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-NEXT: vcvtb.f16.f32 s22, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s18 ; CHECK-NEXT: vcvtt.f32.f16 s0, s18
; CHECK-NEXT: vmov.16 q5[4], r0
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl expf ; CHECK-NEXT: bl expf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-NEXT: vcvtt.f16.f32 s22, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s19 ; CHECK-NEXT: vcvtb.f32.f16 s0, s19
; CHECK-NEXT: vmov.16 q5[5], r0
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl expf ; CHECK-NEXT: bl expf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-NEXT: vcvtb.f16.f32 s23, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s19 ; CHECK-NEXT: vcvtt.f32.f16 s0, s19
; CHECK-NEXT: vmov.16 q5[6], r0
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl expf ; CHECK-NEXT: bl expf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-NEXT: vcvtt.f16.f32 s23, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q5[7], r0
; CHECK-NEXT: vmov q0, q5 ; CHECK-NEXT: vmov q0, q5
; CHECK-NEXT: vpop {d8, d9, d10, d11} ; CHECK-NEXT: vpop {d8, d9, d10, d11}
; CHECK-NEXT: pop {r4, pc} ; CHECK-NEXT: pop {r7, pc}
entry: entry:
%0 = call fast <8 x half> @llvm.exp.v8f16(<8 x half> %src) %0 = call fast <8 x half> @llvm.exp.v8f16(<8 x half> %src)
ret <8 x half> %0 ret <8 x half> %0
} }
define arm_aapcs_vfpcc <2 x double> @exp_float64_t(<2 x double> %src) { define arm_aapcs_vfpcc <2 x double> @exp_float64_t(<2 x double> %src) {
; CHECK-LABEL: exp_float64_t: ; CHECK-LABEL: exp_float64_t:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
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entry: entry:
%0 = call fast <4 x float> @llvm.exp2.v4f32(<4 x float> %src) %0 = call fast <4 x float> @llvm.exp2.v4f32(<4 x float> %src)
ret <4 x float> %0 ret <4 x float> %0
} }
define arm_aapcs_vfpcc <8 x half> @exp2_float16_t(<8 x half> %src) { define arm_aapcs_vfpcc <8 x half> @exp2_float16_t(<8 x half> %src) {
; CHECK-LABEL: exp2_float16_t: ; CHECK-LABEL: exp2_float16_t:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, lr} ; CHECK-NEXT: .save {r7, lr}
; CHECK-NEXT: push {r4, lr} ; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-NEXT: vpush {d8, d9, d10, d11} ; CHECK-NEXT: vpush {d8, d9, d10, d11}
; CHECK-NEXT: vmov q4, q0 ; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vcvtb.f32.f16 s0, s16 ; CHECK-NEXT: vcvtb.f32.f16 s0, s16
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl exp2f ; CHECK-NEXT: bl exp2f
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r4, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s16 ; CHECK-NEXT: vcvtt.f32.f16 s0, s16
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov s20, r0
; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: mov r0, r1
; CHECK-NEXT: bl exp2f ; CHECK-NEXT: bl exp2f
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vmov.16 q5[0], r4 ; CHECK-NEXT: vcvtb.f16.f32 s20, s20
; CHECK-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-NEXT: vcvtt.f16.f32 s20, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s17 ; CHECK-NEXT: vcvtb.f32.f16 s0, s17
; CHECK-NEXT: vmov.16 q5[1], r0
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl exp2f ; CHECK-NEXT: bl exp2f
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-NEXT: vcvtb.f16.f32 s21, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s17 ; CHECK-NEXT: vcvtt.f32.f16 s0, s17
; CHECK-NEXT: vmov.16 q5[2], r0
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl exp2f ; CHECK-NEXT: bl exp2f
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-NEXT: vcvtt.f16.f32 s21, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s18 ; CHECK-NEXT: vcvtb.f32.f16 s0, s18
; CHECK-NEXT: vmov.16 q5[3], r0
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl exp2f ; CHECK-NEXT: bl exp2f
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-NEXT: vcvtb.f16.f32 s22, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s18 ; CHECK-NEXT: vcvtt.f32.f16 s0, s18
; CHECK-NEXT: vmov.16 q5[4], r0
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl exp2f ; CHECK-NEXT: bl exp2f
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-NEXT: vcvtt.f16.f32 s22, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s19 ; CHECK-NEXT: vcvtb.f32.f16 s0, s19
; CHECK-NEXT: vmov.16 q5[5], r0
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl exp2f ; CHECK-NEXT: bl exp2f
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-NEXT: vcvtb.f16.f32 s23, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s19 ; CHECK-NEXT: vcvtt.f32.f16 s0, s19
; CHECK-NEXT: vmov.16 q5[6], r0
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl exp2f ; CHECK-NEXT: bl exp2f
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-NEXT: vcvtt.f16.f32 s23, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q5[7], r0
; CHECK-NEXT: vmov q0, q5 ; CHECK-NEXT: vmov q0, q5
; CHECK-NEXT: vpop {d8, d9, d10, d11} ; CHECK-NEXT: vpop {d8, d9, d10, d11}
; CHECK-NEXT: pop {r4, pc} ; CHECK-NEXT: pop {r7, pc}
entry: entry:
%0 = call fast <8 x half> @llvm.exp2.v8f16(<8 x half> %src) %0 = call fast <8 x half> @llvm.exp2.v8f16(<8 x half> %src)
ret <8 x half> %0 ret <8 x half> %0
} }
define arm_aapcs_vfpcc <2 x double> @exp2_float64_t(<2 x double> %src) { define arm_aapcs_vfpcc <2 x double> @exp2_float64_t(<2 x double> %src) {
; CHECK-LABEL: exp2_float64_t: ; CHECK-LABEL: exp2_float64_t:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
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entry: entry:
%0 = call fast <4 x float> @llvm.log.v4f32(<4 x float> %src) %0 = call fast <4 x float> @llvm.log.v4f32(<4 x float> %src)
ret <4 x float> %0 ret <4 x float> %0
} }
define arm_aapcs_vfpcc <8 x half> @log_float16_t(<8 x half> %src) { define arm_aapcs_vfpcc <8 x half> @log_float16_t(<8 x half> %src) {
; CHECK-LABEL: log_float16_t: ; CHECK-LABEL: log_float16_t:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, lr} ; CHECK-NEXT: .save {r7, lr}
; CHECK-NEXT: push {r4, lr} ; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-NEXT: vpush {d8, d9, d10, d11} ; CHECK-NEXT: vpush {d8, d9, d10, d11}
; CHECK-NEXT: vmov q4, q0 ; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vcvtb.f32.f16 s0, s16 ; CHECK-NEXT: vcvtb.f32.f16 s0, s16
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl logf ; CHECK-NEXT: bl logf
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r4, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s16 ; CHECK-NEXT: vcvtt.f32.f16 s0, s16
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov s20, r0
; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: mov r0, r1
; CHECK-NEXT: bl logf ; CHECK-NEXT: bl logf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vmov.16 q5[0], r4 ; CHECK-NEXT: vcvtb.f16.f32 s20, s20
; CHECK-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-NEXT: vcvtt.f16.f32 s20, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s17 ; CHECK-NEXT: vcvtb.f32.f16 s0, s17
; CHECK-NEXT: vmov.16 q5[1], r0
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl logf ; CHECK-NEXT: bl logf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-NEXT: vcvtb.f16.f32 s21, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s17 ; CHECK-NEXT: vcvtt.f32.f16 s0, s17
; CHECK-NEXT: vmov.16 q5[2], r0
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl logf ; CHECK-NEXT: bl logf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-NEXT: vcvtt.f16.f32 s21, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s18 ; CHECK-NEXT: vcvtb.f32.f16 s0, s18
; CHECK-NEXT: vmov.16 q5[3], r0
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl logf ; CHECK-NEXT: bl logf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-NEXT: vcvtb.f16.f32 s22, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s18 ; CHECK-NEXT: vcvtt.f32.f16 s0, s18
; CHECK-NEXT: vmov.16 q5[4], r0
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl logf ; CHECK-NEXT: bl logf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-NEXT: vcvtt.f16.f32 s22, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s19 ; CHECK-NEXT: vcvtb.f32.f16 s0, s19
; CHECK-NEXT: vmov.16 q5[5], r0
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl logf ; CHECK-NEXT: bl logf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-NEXT: vcvtb.f16.f32 s23, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s19 ; CHECK-NEXT: vcvtt.f32.f16 s0, s19
; CHECK-NEXT: vmov.16 q5[6], r0
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl logf ; CHECK-NEXT: bl logf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-NEXT: vcvtt.f16.f32 s23, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q5[7], r0
; CHECK-NEXT: vmov q0, q5 ; CHECK-NEXT: vmov q0, q5
; CHECK-NEXT: vpop {d8, d9, d10, d11} ; CHECK-NEXT: vpop {d8, d9, d10, d11}
; CHECK-NEXT: pop {r4, pc} ; CHECK-NEXT: pop {r7, pc}
entry: entry:
%0 = call fast <8 x half> @llvm.log.v8f16(<8 x half> %src) %0 = call fast <8 x half> @llvm.log.v8f16(<8 x half> %src)
ret <8 x half> %0 ret <8 x half> %0
} }
define arm_aapcs_vfpcc <2 x double> @log_float64_t(<2 x double> %src) { define arm_aapcs_vfpcc <2 x double> @log_float64_t(<2 x double> %src) {
; CHECK-LABEL: log_float64_t: ; CHECK-LABEL: log_float64_t:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
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entry: entry:
%0 = call fast <4 x float> @llvm.log2.v4f32(<4 x float> %src) %0 = call fast <4 x float> @llvm.log2.v4f32(<4 x float> %src)
ret <4 x float> %0 ret <4 x float> %0
} }
define arm_aapcs_vfpcc <8 x half> @log2_float16_t(<8 x half> %src) { define arm_aapcs_vfpcc <8 x half> @log2_float16_t(<8 x half> %src) {
; CHECK-LABEL: log2_float16_t: ; CHECK-LABEL: log2_float16_t:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, lr} ; CHECK-NEXT: .save {r7, lr}
; CHECK-NEXT: push {r4, lr} ; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-NEXT: vpush {d8, d9, d10, d11} ; CHECK-NEXT: vpush {d8, d9, d10, d11}
; CHECK-NEXT: vmov q4, q0 ; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vcvtb.f32.f16 s0, s16 ; CHECK-NEXT: vcvtb.f32.f16 s0, s16
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl log2f ; CHECK-NEXT: bl log2f
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r4, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s16 ; CHECK-NEXT: vcvtt.f32.f16 s0, s16
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov s20, r0
; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: mov r0, r1
; CHECK-NEXT: bl log2f ; CHECK-NEXT: bl log2f
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vmov.16 q5[0], r4 ; CHECK-NEXT: vcvtb.f16.f32 s20, s20
; CHECK-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-NEXT: vcvtt.f16.f32 s20, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s17 ; CHECK-NEXT: vcvtb.f32.f16 s0, s17
; CHECK-NEXT: vmov.16 q5[1], r0
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl log2f ; CHECK-NEXT: bl log2f
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-NEXT: vcvtb.f16.f32 s21, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s17 ; CHECK-NEXT: vcvtt.f32.f16 s0, s17
; CHECK-NEXT: vmov.16 q5[2], r0
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl log2f ; CHECK-NEXT: bl log2f
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-NEXT: vcvtt.f16.f32 s21, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s18 ; CHECK-NEXT: vcvtb.f32.f16 s0, s18
; CHECK-NEXT: vmov.16 q5[3], r0
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl log2f ; CHECK-NEXT: bl log2f
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-NEXT: vcvtb.f16.f32 s22, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s18 ; CHECK-NEXT: vcvtt.f32.f16 s0, s18
; CHECK-NEXT: vmov.16 q5[4], r0
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl log2f ; CHECK-NEXT: bl log2f
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-NEXT: vcvtt.f16.f32 s22, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s19 ; CHECK-NEXT: vcvtb.f32.f16 s0, s19
; CHECK-NEXT: vmov.16 q5[5], r0
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl log2f ; CHECK-NEXT: bl log2f
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-NEXT: vcvtb.f16.f32 s23, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s19 ; CHECK-NEXT: vcvtt.f32.f16 s0, s19
; CHECK-NEXT: vmov.16 q5[6], r0
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl log2f ; CHECK-NEXT: bl log2f
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-NEXT: vcvtt.f16.f32 s23, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q5[7], r0
; CHECK-NEXT: vmov q0, q5 ; CHECK-NEXT: vmov q0, q5
; CHECK-NEXT: vpop {d8, d9, d10, d11} ; CHECK-NEXT: vpop {d8, d9, d10, d11}
; CHECK-NEXT: pop {r4, pc} ; CHECK-NEXT: pop {r7, pc}
entry: entry:
%0 = call fast <8 x half> @llvm.log2.v8f16(<8 x half> %src) %0 = call fast <8 x half> @llvm.log2.v8f16(<8 x half> %src)
ret <8 x half> %0 ret <8 x half> %0
} }
define arm_aapcs_vfpcc <2 x double> @log2_float64_t(<2 x double> %src) { define arm_aapcs_vfpcc <2 x double> @log2_float64_t(<2 x double> %src) {
; CHECK-LABEL: log2_float64_t: ; CHECK-LABEL: log2_float64_t:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
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entry: entry:
%0 = call fast <4 x float> @llvm.log10.v4f32(<4 x float> %src) %0 = call fast <4 x float> @llvm.log10.v4f32(<4 x float> %src)
ret <4 x float> %0 ret <4 x float> %0
} }
define arm_aapcs_vfpcc <8 x half> @log10_float16_t(<8 x half> %src) { define arm_aapcs_vfpcc <8 x half> @log10_float16_t(<8 x half> %src) {
; CHECK-LABEL: log10_float16_t: ; CHECK-LABEL: log10_float16_t:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, lr} ; CHECK-NEXT: .save {r7, lr}
; CHECK-NEXT: push {r4, lr} ; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-NEXT: vpush {d8, d9, d10, d11} ; CHECK-NEXT: vpush {d8, d9, d10, d11}
; CHECK-NEXT: vmov q4, q0 ; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vcvtb.f32.f16 s0, s16 ; CHECK-NEXT: vcvtb.f32.f16 s0, s16
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl log10f ; CHECK-NEXT: bl log10f
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r4, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s16 ; CHECK-NEXT: vcvtt.f32.f16 s0, s16
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov s20, r0
; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: mov r0, r1
; CHECK-NEXT: bl log10f ; CHECK-NEXT: bl log10f
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vmov.16 q5[0], r4 ; CHECK-NEXT: vcvtb.f16.f32 s20, s20
; CHECK-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-NEXT: vcvtt.f16.f32 s20, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s17 ; CHECK-NEXT: vcvtb.f32.f16 s0, s17
; CHECK-NEXT: vmov.16 q5[1], r0
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl log10f ; CHECK-NEXT: bl log10f
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-NEXT: vcvtb.f16.f32 s21, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s17 ; CHECK-NEXT: vcvtt.f32.f16 s0, s17
; CHECK-NEXT: vmov.16 q5[2], r0
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl log10f ; CHECK-NEXT: bl log10f
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-NEXT: vcvtt.f16.f32 s21, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s18 ; CHECK-NEXT: vcvtb.f32.f16 s0, s18
; CHECK-NEXT: vmov.16 q5[3], r0
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl log10f ; CHECK-NEXT: bl log10f
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-NEXT: vcvtb.f16.f32 s22, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s18 ; CHECK-NEXT: vcvtt.f32.f16 s0, s18
; CHECK-NEXT: vmov.16 q5[4], r0
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl log10f ; CHECK-NEXT: bl log10f
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-NEXT: vcvtt.f16.f32 s22, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s19 ; CHECK-NEXT: vcvtb.f32.f16 s0, s19
; CHECK-NEXT: vmov.16 q5[5], r0
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl log10f ; CHECK-NEXT: bl log10f
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-NEXT: vcvtb.f16.f32 s23, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s19 ; CHECK-NEXT: vcvtt.f32.f16 s0, s19
; CHECK-NEXT: vmov.16 q5[6], r0
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl log10f ; CHECK-NEXT: bl log10f
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-NEXT: vcvtt.f16.f32 s23, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q5[7], r0
; CHECK-NEXT: vmov q0, q5 ; CHECK-NEXT: vmov q0, q5
; CHECK-NEXT: vpop {d8, d9, d10, d11} ; CHECK-NEXT: vpop {d8, d9, d10, d11}
; CHECK-NEXT: pop {r4, pc} ; CHECK-NEXT: pop {r7, pc}
entry: entry:
%0 = call fast <8 x half> @llvm.log10.v8f16(<8 x half> %src) %0 = call fast <8 x half> @llvm.log10.v8f16(<8 x half> %src)
ret <8 x half> %0 ret <8 x half> %0
} }
define arm_aapcs_vfpcc <2 x double> @log10_float64_t(<2 x double> %src) { define arm_aapcs_vfpcc <2 x double> @log10_float64_t(<2 x double> %src) {
; CHECK-LABEL: log10_float64_t: ; CHECK-LABEL: log10_float64_t:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
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entry: entry:
%0 = call fast <4 x float> @llvm.pow.v4f32(<4 x float> %src1, <4 x float> %src2) %0 = call fast <4 x float> @llvm.pow.v4f32(<4 x float> %src1, <4 x float> %src2)
ret <4 x float> %0 ret <4 x float> %0
} }
define arm_aapcs_vfpcc <8 x half> @pow_float16_t(<8 x half> %src1, <8 x half> %src2) { define arm_aapcs_vfpcc <8 x half> @pow_float16_t(<8 x half> %src1, <8 x half> %src2) {
; CHECK-LABEL: pow_float16_t: ; CHECK-LABEL: pow_float16_t:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, lr} ; CHECK-NEXT: .save {r7, lr}
; CHECK-NEXT: push {r4, lr} ; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: vmov q5, q0 ; CHECK-NEXT: vmov q5, q0
; CHECK-NEXT: vmov q4, q1 ; CHECK-NEXT: vmov q4, q1
; CHECK-NEXT: vcvtb.f32.f16 s0, s20 ; CHECK-NEXT: vcvtb.f32.f16 s0, s20
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s16 ; CHECK-NEXT: vcvtb.f32.f16 s0, s16
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: bl powf ; CHECK-NEXT: bl powf
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r4, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s20 ; CHECK-NEXT: vcvtt.f32.f16 s0, s20
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov s24, r0
; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s16 ; CHECK-NEXT: vcvtt.f32.f16 s0, s16
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: mov r0, r2
; CHECK-NEXT: bl powf ; CHECK-NEXT: bl powf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vmov.16 q6[0], r4 ; CHECK-NEXT: vcvtb.f16.f32 s24, s24
; CHECK-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-NEXT: vcvtt.f16.f32 s24, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s21 ; CHECK-NEXT: vcvtb.f32.f16 s0, s21
; CHECK-NEXT: vmov.16 q6[1], r0
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s17 ; CHECK-NEXT: vcvtb.f32.f16 s0, s17
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: bl powf ; CHECK-NEXT: bl powf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-NEXT: vcvtb.f16.f32 s25, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s21 ; CHECK-NEXT: vcvtt.f32.f16 s0, s21
; CHECK-NEXT: vmov.16 q6[2], r0
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s17 ; CHECK-NEXT: vcvtt.f32.f16 s0, s17
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: bl powf ; CHECK-NEXT: bl powf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-NEXT: vcvtt.f16.f32 s25, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s22 ; CHECK-NEXT: vcvtb.f32.f16 s0, s22
; CHECK-NEXT: vmov.16 q6[3], r0
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s18 ; CHECK-NEXT: vcvtb.f32.f16 s0, s18
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: bl powf ; CHECK-NEXT: bl powf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-NEXT: vcvtb.f16.f32 s26, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s22 ; CHECK-NEXT: vcvtt.f32.f16 s0, s22
; CHECK-NEXT: vmov.16 q6[4], r0
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s18 ; CHECK-NEXT: vcvtt.f32.f16 s0, s18
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: bl powf ; CHECK-NEXT: bl powf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-NEXT: vcvtt.f16.f32 s26, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s23 ; CHECK-NEXT: vcvtb.f32.f16 s0, s23
; CHECK-NEXT: vmov.16 q6[5], r0
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s19 ; CHECK-NEXT: vcvtb.f32.f16 s0, s19
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: bl powf ; CHECK-NEXT: bl powf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-NEXT: vcvtb.f16.f32 s27, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s23 ; CHECK-NEXT: vcvtt.f32.f16 s0, s23
; CHECK-NEXT: vmov.16 q6[6], r0
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vcvtt.f32.f16 s0, s19 ; CHECK-NEXT: vcvtt.f32.f16 s0, s19
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: bl powf ; CHECK-NEXT: bl powf
; CHECK-NEXT: vmov s0, r0 ; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-NEXT: vcvtt.f16.f32 s27, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q6[7], r0
; CHECK-NEXT: vmov q0, q6 ; CHECK-NEXT: vmov q0, q6
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: pop {r4, pc} ; CHECK-NEXT: pop {r7, pc}
entry: entry:
%0 = call fast <8 x half> @llvm.pow.v8f16(<8 x half> %src1, <8 x half> %src2) %0 = call fast <8 x half> @llvm.pow.v8f16(<8 x half> %src1, <8 x half> %src2)
ret <8 x half> %0 ret <8 x half> %0
} }
define arm_aapcs_vfpcc <2 x double> @pow_float64_t(<2 x double> %src1, <2 x double> %src2) { define arm_aapcs_vfpcc <2 x double> @pow_float64_t(<2 x double> %src1, <2 x double> %src2) {
; CHECK-LABEL: pow_float64_t: ; CHECK-LABEL: pow_float64_t:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
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llvm/test/CodeGen/Thumb2/mve-masked-store.ll

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define arm_aapcs_vfpcc void @masked_v4f16_align4(<4 x half> *%dest, <4 x float> %a) { define arm_aapcs_vfpcc void @masked_v4f16_align4(<4 x half> *%dest, <4 x float> %a) {
; CHECK-LE-LABEL: masked_v4f16_align4: ; CHECK-LE-LABEL: masked_v4f16_align4:
; CHECK-LE: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-LE-NEXT: .pad #4 ; CHECK-LE-NEXT: .pad #4
; CHECK-LE-NEXT: sub sp, #4 ; CHECK-LE-NEXT: sub sp, #4
; CHECK-LE-NEXT: vcvtb.f16.f32 s4, s0 ; CHECK-LE-NEXT: vcvtb.f16.f32 s4, s0
; CHECK-LE-NEXT: vcmp.f32 s0, #0 ; CHECK-LE-NEXT: vcmp.f32 s0, #0
; CHECK-LE-NEXT: vmov r1, s4 ; CHECK-LE-NEXT: vcvtt.f16.f32 s4, s1
; CHECK-LE-NEXT: vcvtb.f16.f32 s4, s1
; CHECK-LE-NEXT: vmov r2, s4
; CHECK-LE-NEXT: vmov.16 q1[0], r1
; CHECK-LE-NEXT: vcvtb.f16.f32 s8, s2
; CHECK-LE-NEXT: vmov.16 q1[1], r2
; CHECK-LE-NEXT: vmov r1, s8
; CHECK-LE-NEXT: vcvtb.f16.f32 s8, s3
; CHECK-LE-NEXT: vmov.16 q1[2], r1
; CHECK-LE-NEXT: vmov r1, s8
; CHECK-LE-NEXT: vmov.16 q1[3], r1
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-LE-NEXT: vcvtb.f16.f32 s5, s2
; CHECK-LE-NEXT: mov.w r1, #0 ; CHECK-LE-NEXT: mov.w r1, #0
; CHECK-LE-NEXT: vcmp.f32 s1, #0 ; CHECK-LE-NEXT: vcvtt.f16.f32 s5, s3
; CHECK-LE-NEXT: it gt ; CHECK-LE-NEXT: it gt
; CHECK-LE-NEXT: movgt r1, #1 ; CHECK-LE-NEXT: movgt r1, #1
; CHECK-LE-NEXT: cmp r1, #0 ; CHECK-LE-NEXT: cmp r1, #0
; CHECK-LE-NEXT: vcmp.f32 s1, #0
; CHECK-LE-NEXT: cset r1, ne ; CHECK-LE-NEXT: cset r1, ne
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-LE-NEXT: and r1, r1, #1 ; CHECK-LE-NEXT: and r1, r1, #1
; CHECK-LE-NEXT: vcmp.f32 s2, #0 ; CHECK-LE-NEXT: vcmp.f32 s2, #0
; CHECK-LE-NEXT: rsb.w r3, r1, #0 ; CHECK-LE-NEXT: rsb.w r3, r1, #0
; CHECK-LE-NEXT: mov.w r1, #0 ; CHECK-LE-NEXT: mov.w r1, #0
; CHECK-LE-NEXT: bfi r1, r3, #0, #1 ; CHECK-LE-NEXT: bfi r1, r3, #0, #1
; CHECK-LE-NEXT: mov.w r3, #0 ; CHECK-LE-NEXT: mov.w r3, #0
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; CHECK-LE-NEXT: add sp, #4 ; CHECK-LE-NEXT: add sp, #4
; CHECK-LE-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
; ;
; CHECK-BE-LABEL: masked_v4f16_align4: ; CHECK-BE-LABEL: masked_v4f16_align4:
; CHECK-BE: @ %bb.0: @ %entry ; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: .pad #4 ; CHECK-BE-NEXT: .pad #4
; CHECK-BE-NEXT: sub sp, #4 ; CHECK-BE-NEXT: sub sp, #4
; CHECK-BE-NEXT: vrev64.32 q1, q0 ; CHECK-BE-NEXT: vrev64.32 q1, q0
; CHECK-BE-NEXT: movs r1, #0
; CHECK-BE-NEXT: vcvtb.f16.f32 s0, s4 ; CHECK-BE-NEXT: vcvtb.f16.f32 s0, s4
; CHECK-BE-NEXT: vcmp.f32 s4, #0 ; CHECK-BE-NEXT: vcmp.f32 s4, #0
; CHECK-BE-NEXT: vmov r1, s0 ; CHECK-BE-NEXT: vcvtt.f16.f32 s0, s5
; CHECK-BE-NEXT: vcvtb.f16.f32 s0, s5
; CHECK-BE-NEXT: vmov r2, s0
; CHECK-BE-NEXT: vmov.16 q0[0], r1
; CHECK-BE-NEXT: vcvtb.f16.f32 s8, s6
; CHECK-BE-NEXT: vmov.16 q0[1], r2
; CHECK-BE-NEXT: vmov r1, s8
; CHECK-BE-NEXT: vcvtb.f16.f32 s8, s7
; CHECK-BE-NEXT: vmov.16 q0[2], r1
; CHECK-BE-NEXT: vmov r1, s8
; CHECK-BE-NEXT: vmov.16 q0[3], r1
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-BE-NEXT: mov.w r1, #0 ; CHECK-BE-NEXT: vcvtb.f16.f32 s1, s6
; CHECK-BE-NEXT: vcmp.f32 s5, #0 ; CHECK-BE-NEXT: vcmp.f32 s5, #0
; CHECK-BE-NEXT: vcvtt.f16.f32 s1, s7
; CHECK-BE-NEXT: it gt ; CHECK-BE-NEXT: it gt
; CHECK-BE-NEXT: movgt r1, #1 ; CHECK-BE-NEXT: movgt r1, #1
; CHECK-BE-NEXT: cmp r1, #0 ; CHECK-BE-NEXT: cmp r1, #0
; CHECK-BE-NEXT: mov.w r2, #0
; CHECK-BE-NEXT: cset r1, ne ; CHECK-BE-NEXT: cset r1, ne
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-BE-NEXT: and r1, r1, #1 ; CHECK-BE-NEXT: and r1, r1, #1
; CHECK-BE-NEXT: vcmp.f32 s6, #0 ; CHECK-BE-NEXT: vcmp.f32 s6, #0
; CHECK-BE-NEXT: rsb.w r3, r1, #0 ; CHECK-BE-NEXT: rsb.w r3, r1, #0
; CHECK-BE-NEXT: mov.w r1, #0 ; CHECK-BE-NEXT: mov.w r1, #0
; CHECK-BE-NEXT: bfi r1, r3, #0, #1 ; CHECK-BE-NEXT: bfi r1, r3, #0, #1
; CHECK-BE-NEXT: mov.w r3, #0 ; CHECK-BE-NEXT: mov.w r3, #0
; CHECK-BE-NEXT: it gt ; CHECK-BE-NEXT: it gt
; CHECK-BE-NEXT: movgt r3, #1 ; CHECK-BE-NEXT: movgt r3, #1
; CHECK-BE-NEXT: cmp r3, #0 ; CHECK-BE-NEXT: cmp r3, #0
; CHECK-BE-NEXT: cset r3, ne ; CHECK-BE-NEXT: cset r3, ne
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-BE-NEXT: and r3, r3, #1 ; CHECK-BE-NEXT: and r3, r3, #1
; CHECK-BE-NEXT: vcmp.f32 s7, #0 ; CHECK-BE-NEXT: vcmp.f32 s7, #0
; CHECK-BE-NEXT: rsb.w r3, r3, #0 ; CHECK-BE-NEXT: rsb.w r3, r3, #0
; CHECK-BE-NEXT: mov.w r2, #0
; CHECK-BE-NEXT: bfi r1, r3, #1, #1 ; CHECK-BE-NEXT: bfi r1, r3, #1, #1
; CHECK-BE-NEXT: mov.w r3, #0 ; CHECK-BE-NEXT: mov.w r3, #0
; CHECK-BE-NEXT: it gt ; CHECK-BE-NEXT: it gt
; CHECK-BE-NEXT: movgt r3, #1 ; CHECK-BE-NEXT: movgt r3, #1
; CHECK-BE-NEXT: cmp r3, #0 ; CHECK-BE-NEXT: cmp r3, #0
; CHECK-BE-NEXT: cset r3, ne ; CHECK-BE-NEXT: cset r3, ne
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-BE-NEXT: it gt ; CHECK-BE-NEXT: it gt
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define arm_aapcs_vfpcc void @masked_v4f16_align2(<4 x half> *%dest, <4 x float> %a) { define arm_aapcs_vfpcc void @masked_v4f16_align2(<4 x half> *%dest, <4 x float> %a) {
; CHECK-LE-LABEL: masked_v4f16_align2: ; CHECK-LE-LABEL: masked_v4f16_align2:
; CHECK-LE: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-LE-NEXT: .pad #4 ; CHECK-LE-NEXT: .pad #4
; CHECK-LE-NEXT: sub sp, #4 ; CHECK-LE-NEXT: sub sp, #4
; CHECK-LE-NEXT: vcvtb.f16.f32 s4, s0 ; CHECK-LE-NEXT: vcvtb.f16.f32 s4, s0
; CHECK-LE-NEXT: vcmp.f32 s0, #0 ; CHECK-LE-NEXT: vcmp.f32 s0, #0
; CHECK-LE-NEXT: vmov r1, s4 ; CHECK-LE-NEXT: vcvtt.f16.f32 s4, s1
; CHECK-LE-NEXT: vcvtb.f16.f32 s4, s1
; CHECK-LE-NEXT: vmov r2, s4
; CHECK-LE-NEXT: vmov.16 q1[0], r1
; CHECK-LE-NEXT: vcvtb.f16.f32 s8, s2
; CHECK-LE-NEXT: vmov.16 q1[1], r2
; CHECK-LE-NEXT: vmov r1, s8
; CHECK-LE-NEXT: vcvtb.f16.f32 s8, s3
; CHECK-LE-NEXT: vmov.16 q1[2], r1
; CHECK-LE-NEXT: vmov r1, s8
; CHECK-LE-NEXT: vmov.16 q1[3], r1
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-LE-NEXT: vcvtb.f16.f32 s5, s2
; CHECK-LE-NEXT: mov.w r1, #0 ; CHECK-LE-NEXT: mov.w r1, #0
; CHECK-LE-NEXT: vcmp.f32 s1, #0 ; CHECK-LE-NEXT: vcvtt.f16.f32 s5, s3
; CHECK-LE-NEXT: it gt ; CHECK-LE-NEXT: it gt
; CHECK-LE-NEXT: movgt r1, #1 ; CHECK-LE-NEXT: movgt r1, #1
; CHECK-LE-NEXT: cmp r1, #0 ; CHECK-LE-NEXT: cmp r1, #0
; CHECK-LE-NEXT: vcmp.f32 s1, #0
; CHECK-LE-NEXT: cset r1, ne ; CHECK-LE-NEXT: cset r1, ne
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-LE-NEXT: and r1, r1, #1 ; CHECK-LE-NEXT: and r1, r1, #1
; CHECK-LE-NEXT: vcmp.f32 s2, #0 ; CHECK-LE-NEXT: vcmp.f32 s2, #0
; CHECK-LE-NEXT: rsb.w r3, r1, #0 ; CHECK-LE-NEXT: rsb.w r3, r1, #0
; CHECK-LE-NEXT: mov.w r1, #0 ; CHECK-LE-NEXT: mov.w r1, #0
; CHECK-LE-NEXT: bfi r1, r3, #0, #1 ; CHECK-LE-NEXT: bfi r1, r3, #0, #1
; CHECK-LE-NEXT: mov.w r3, #0 ; CHECK-LE-NEXT: mov.w r3, #0
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; CHECK-LE-NEXT: add sp, #4 ; CHECK-LE-NEXT: add sp, #4
; CHECK-LE-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
; ;
; CHECK-BE-LABEL: masked_v4f16_align2: ; CHECK-BE-LABEL: masked_v4f16_align2:
; CHECK-BE: @ %bb.0: @ %entry ; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: .pad #4 ; CHECK-BE-NEXT: .pad #4
; CHECK-BE-NEXT: sub sp, #4 ; CHECK-BE-NEXT: sub sp, #4
; CHECK-BE-NEXT: vrev64.32 q1, q0 ; CHECK-BE-NEXT: vrev64.32 q1, q0
; CHECK-BE-NEXT: movs r1, #0
; CHECK-BE-NEXT: vcvtb.f16.f32 s0, s4 ; CHECK-BE-NEXT: vcvtb.f16.f32 s0, s4
; CHECK-BE-NEXT: vcmp.f32 s4, #0 ; CHECK-BE-NEXT: vcmp.f32 s4, #0
; CHECK-BE-NEXT: vmov r1, s0 ; CHECK-BE-NEXT: vcvtt.f16.f32 s0, s5
; CHECK-BE-NEXT: vcvtb.f16.f32 s0, s5
; CHECK-BE-NEXT: vmov r2, s0
; CHECK-BE-NEXT: vmov.16 q0[0], r1
; CHECK-BE-NEXT: vcvtb.f16.f32 s8, s6
; CHECK-BE-NEXT: vmov.16 q0[1], r2
; CHECK-BE-NEXT: vmov r1, s8
; CHECK-BE-NEXT: vcvtb.f16.f32 s8, s7
; CHECK-BE-NEXT: vmov.16 q0[2], r1
; CHECK-BE-NEXT: vmov r1, s8
; CHECK-BE-NEXT: vmov.16 q0[3], r1
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-BE-NEXT: mov.w r1, #0 ; CHECK-BE-NEXT: vcvtb.f16.f32 s1, s6
; CHECK-BE-NEXT: vcmp.f32 s5, #0 ; CHECK-BE-NEXT: vcmp.f32 s5, #0
; CHECK-BE-NEXT: vcvtt.f16.f32 s1, s7
; CHECK-BE-NEXT: it gt ; CHECK-BE-NEXT: it gt
; CHECK-BE-NEXT: movgt r1, #1 ; CHECK-BE-NEXT: movgt r1, #1
; CHECK-BE-NEXT: cmp r1, #0 ; CHECK-BE-NEXT: cmp r1, #0
; CHECK-BE-NEXT: mov.w r2, #0
; CHECK-BE-NEXT: cset r1, ne ; CHECK-BE-NEXT: cset r1, ne
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-BE-NEXT: and r1, r1, #1 ; CHECK-BE-NEXT: and r1, r1, #1
; CHECK-BE-NEXT: vcmp.f32 s6, #0 ; CHECK-BE-NEXT: vcmp.f32 s6, #0
; CHECK-BE-NEXT: rsb.w r3, r1, #0 ; CHECK-BE-NEXT: rsb.w r3, r1, #0
; CHECK-BE-NEXT: mov.w r1, #0 ; CHECK-BE-NEXT: mov.w r1, #0
; CHECK-BE-NEXT: bfi r1, r3, #0, #1 ; CHECK-BE-NEXT: bfi r1, r3, #0, #1
; CHECK-BE-NEXT: mov.w r3, #0 ; CHECK-BE-NEXT: mov.w r3, #0
; CHECK-BE-NEXT: it gt ; CHECK-BE-NEXT: it gt
; CHECK-BE-NEXT: movgt r3, #1 ; CHECK-BE-NEXT: movgt r3, #1
; CHECK-BE-NEXT: cmp r3, #0 ; CHECK-BE-NEXT: cmp r3, #0
; CHECK-BE-NEXT: cset r3, ne ; CHECK-BE-NEXT: cset r3, ne
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-BE-NEXT: and r3, r3, #1 ; CHECK-BE-NEXT: and r3, r3, #1
; CHECK-BE-NEXT: vcmp.f32 s7, #0 ; CHECK-BE-NEXT: vcmp.f32 s7, #0
; CHECK-BE-NEXT: rsb.w r3, r3, #0 ; CHECK-BE-NEXT: rsb.w r3, r3, #0
; CHECK-BE-NEXT: mov.w r2, #0
; CHECK-BE-NEXT: bfi r1, r3, #1, #1 ; CHECK-BE-NEXT: bfi r1, r3, #1, #1
; CHECK-BE-NEXT: mov.w r3, #0 ; CHECK-BE-NEXT: mov.w r3, #0
; CHECK-BE-NEXT: it gt ; CHECK-BE-NEXT: it gt
; CHECK-BE-NEXT: movgt r3, #1 ; CHECK-BE-NEXT: movgt r3, #1
; CHECK-BE-NEXT: cmp r3, #0 ; CHECK-BE-NEXT: cmp r3, #0
; CHECK-BE-NEXT: cset r3, ne ; CHECK-BE-NEXT: cset r3, ne
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-BE-NEXT: it gt ; CHECK-BE-NEXT: it gt
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define arm_aapcs_vfpcc void @masked_v4f16_align1(<4 x half> *%dest, <4 x float> %a) { define arm_aapcs_vfpcc void @masked_v4f16_align1(<4 x half> *%dest, <4 x float> %a) {
; CHECK-LE-LABEL: masked_v4f16_align1: ; CHECK-LE-LABEL: masked_v4f16_align1:
; CHECK-LE: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-LE-NEXT: .pad #20 ; CHECK-LE-NEXT: .pad #20
; CHECK-LE-NEXT: sub sp, #20 ; CHECK-LE-NEXT: sub sp, #20
; CHECK-LE-NEXT: vcvtb.f16.f32 s4, s0 ; CHECK-LE-NEXT: vcvtb.f16.f32 s4, s0
; CHECK-LE-NEXT: vcmp.f32 s0, #0 ; CHECK-LE-NEXT: vcmp.f32 s0, #0
; CHECK-LE-NEXT: vmov r1, s4 ; CHECK-LE-NEXT: vcvtt.f16.f32 s4, s1
; CHECK-LE-NEXT: vcvtb.f16.f32 s4, s1
; CHECK-LE-NEXT: vmov r2, s4
; CHECK-LE-NEXT: vmov.16 q1[0], r1
; CHECK-LE-NEXT: vcvtb.f16.f32 s8, s2
; CHECK-LE-NEXT: vmov.16 q1[1], r2
; CHECK-LE-NEXT: vmov r1, s8
; CHECK-LE-NEXT: vcvtb.f16.f32 s8, s3
; CHECK-LE-NEXT: vmov.16 q1[2], r1
; CHECK-LE-NEXT: vmov r1, s8
; CHECK-LE-NEXT: vmov.16 q1[3], r1
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-LE-NEXT: vcvtb.f16.f32 s5, s2
; CHECK-LE-NEXT: mov.w r1, #0 ; CHECK-LE-NEXT: mov.w r1, #0
; CHECK-LE-NEXT: vcmp.f32 s1, #0 ; CHECK-LE-NEXT: vcvtt.f16.f32 s5, s3
; CHECK-LE-NEXT: it gt ; CHECK-LE-NEXT: it gt
; CHECK-LE-NEXT: movgt r1, #1 ; CHECK-LE-NEXT: movgt r1, #1
; CHECK-LE-NEXT: cmp r1, #0 ; CHECK-LE-NEXT: cmp r1, #0
; CHECK-LE-NEXT: vcmp.f32 s1, #0
; CHECK-LE-NEXT: cset r1, ne ; CHECK-LE-NEXT: cset r1, ne
; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-LE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-LE-NEXT: and r1, r1, #1 ; CHECK-LE-NEXT: and r1, r1, #1
; CHECK-LE-NEXT: vcmp.f32 s2, #0 ; CHECK-LE-NEXT: vcmp.f32 s2, #0
; CHECK-LE-NEXT: rsb.w r3, r1, #0 ; CHECK-LE-NEXT: rsb.w r3, r1, #0
; CHECK-LE-NEXT: mov.w r1, #0 ; CHECK-LE-NEXT: mov.w r1, #0
; CHECK-LE-NEXT: bfi r1, r3, #0, #1 ; CHECK-LE-NEXT: bfi r1, r3, #0, #1
; CHECK-LE-NEXT: mov.w r3, #0 ; CHECK-LE-NEXT: mov.w r3, #0
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; CHECK-LE-NEXT: add sp, #20 ; CHECK-LE-NEXT: add sp, #20
; CHECK-LE-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
; ;
; CHECK-BE-LABEL: masked_v4f16_align1: ; CHECK-BE-LABEL: masked_v4f16_align1:
; CHECK-BE: @ %bb.0: @ %entry ; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: .pad #20 ; CHECK-BE-NEXT: .pad #20
; CHECK-BE-NEXT: sub sp, #20 ; CHECK-BE-NEXT: sub sp, #20
; CHECK-BE-NEXT: vrev64.32 q1, q0 ; CHECK-BE-NEXT: vrev64.32 q1, q0
; CHECK-BE-NEXT: movs r1, #0
; CHECK-BE-NEXT: vcvtb.f16.f32 s0, s4 ; CHECK-BE-NEXT: vcvtb.f16.f32 s0, s4
; CHECK-BE-NEXT: vcmp.f32 s4, #0 ; CHECK-BE-NEXT: vcmp.f32 s4, #0
; CHECK-BE-NEXT: vmov r1, s0 ; CHECK-BE-NEXT: vcvtt.f16.f32 s0, s5
; CHECK-BE-NEXT: vcvtb.f16.f32 s0, s5
; CHECK-BE-NEXT: vmov r2, s0
; CHECK-BE-NEXT: vmov.16 q0[0], r1
; CHECK-BE-NEXT: vcvtb.f16.f32 s8, s6
; CHECK-BE-NEXT: vmov.16 q0[1], r2
; CHECK-BE-NEXT: vmov r1, s8
; CHECK-BE-NEXT: vcvtb.f16.f32 s8, s7
; CHECK-BE-NEXT: vmov.16 q0[2], r1
; CHECK-BE-NEXT: vmov r1, s8
; CHECK-BE-NEXT: vmov.16 q0[3], r1
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-BE-NEXT: mov.w r1, #0 ; CHECK-BE-NEXT: vcvtb.f16.f32 s1, s6
; CHECK-BE-NEXT: vcmp.f32 s5, #0 ; CHECK-BE-NEXT: vcmp.f32 s5, #0
; CHECK-BE-NEXT: vcvtt.f16.f32 s1, s7
; CHECK-BE-NEXT: it gt ; CHECK-BE-NEXT: it gt
; CHECK-BE-NEXT: movgt r1, #1 ; CHECK-BE-NEXT: movgt r1, #1
; CHECK-BE-NEXT: cmp r1, #0 ; CHECK-BE-NEXT: cmp r1, #0
; CHECK-BE-NEXT: mov.w r2, #0
; CHECK-BE-NEXT: cset r1, ne ; CHECK-BE-NEXT: cset r1, ne
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-BE-NEXT: and r1, r1, #1 ; CHECK-BE-NEXT: and r1, r1, #1
; CHECK-BE-NEXT: vcmp.f32 s6, #0 ; CHECK-BE-NEXT: vcmp.f32 s6, #0
; CHECK-BE-NEXT: rsb.w r3, r1, #0 ; CHECK-BE-NEXT: rsb.w r3, r1, #0
; CHECK-BE-NEXT: mov.w r1, #0 ; CHECK-BE-NEXT: mov.w r1, #0
; CHECK-BE-NEXT: bfi r1, r3, #0, #1 ; CHECK-BE-NEXT: bfi r1, r3, #0, #1
; CHECK-BE-NEXT: mov.w r3, #0 ; CHECK-BE-NEXT: mov.w r3, #0
; CHECK-BE-NEXT: it gt ; CHECK-BE-NEXT: it gt
; CHECK-BE-NEXT: movgt r3, #1 ; CHECK-BE-NEXT: movgt r3, #1
; CHECK-BE-NEXT: cmp r3, #0 ; CHECK-BE-NEXT: cmp r3, #0
; CHECK-BE-NEXT: cset r3, ne ; CHECK-BE-NEXT: cset r3, ne
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-BE-NEXT: and r3, r3, #1 ; CHECK-BE-NEXT: and r3, r3, #1
; CHECK-BE-NEXT: vcmp.f32 s7, #0 ; CHECK-BE-NEXT: vcmp.f32 s7, #0
; CHECK-BE-NEXT: rsb.w r3, r3, #0 ; CHECK-BE-NEXT: rsb.w r3, r3, #0
; CHECK-BE-NEXT: mov.w r2, #0
; CHECK-BE-NEXT: bfi r1, r3, #1, #1 ; CHECK-BE-NEXT: bfi r1, r3, #1, #1
; CHECK-BE-NEXT: mov.w r3, #0 ; CHECK-BE-NEXT: mov.w r3, #0
; CHECK-BE-NEXT: it gt ; CHECK-BE-NEXT: it gt
; CHECK-BE-NEXT: movgt r3, #1 ; CHECK-BE-NEXT: movgt r3, #1
; CHECK-BE-NEXT: cmp r3, #0 ; CHECK-BE-NEXT: cmp r3, #0
; CHECK-BE-NEXT: cset r3, ne ; CHECK-BE-NEXT: cset r3, ne
; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-BE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-BE-NEXT: it gt ; CHECK-BE-NEXT: it gt
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llvm/test/CodeGen/Thumb2/mve-vcvt16.ll

Show All 32 Linesentry:
ret <8 x float> %out ret <8 x float> %out
} }
define arm_aapcs_vfpcc <4 x half> @fptrunc_4(<4 x float> %src1) { define arm_aapcs_vfpcc <4 x half> @fptrunc_4(<4 x float> %src1) {
; CHECK-LABEL: fptrunc_4: ; CHECK-LABEL: fptrunc_4:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vcvtb.f16.f32 s4, s0 ; CHECK-NEXT: vcvtb.f16.f32 s4, s0
; CHECK-NEXT: vmov r0, s4 ; CHECK-NEXT: vcvtt.f16.f32 s4, s1
; CHECK-NEXT: vcvtb.f16.f32 s4, s1 ; CHECK-NEXT: vcvtb.f16.f32 s5, s2
; CHECK-NEXT: vmov r1, s4 ; CHECK-NEXT: vcvtt.f16.f32 s5, s3
; CHECK-NEXT: vmov.16 q1[0], r0
; CHECK-NEXT: vcvtb.f16.f32 s8, s2
; CHECK-NEXT: vmov.16 q1[1], r1
; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vcvtb.f16.f32 s0, s3
; CHECK-NEXT: vmov.16 q1[2], r0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q1[3], r0
; CHECK-NEXT: vmov q0, q1 ; CHECK-NEXT: vmov q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%out = fptrunc <4 x float> %src1 to <4 x half> %out = fptrunc <4 x float> %src1 to <4 x half>
ret <4 x half> %out ret <4 x half> %out
} }
define arm_aapcs_vfpcc <8 x half> @fptrunc_8(<8 x float> %src1) { define arm_aapcs_vfpcc <8 x half> @fptrunc_8(<8 x float> %src1) {
; CHECK-LABEL: fptrunc_8: ; CHECK-LABEL: fptrunc_8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov q2, q0 ; CHECK-NEXT: vmov q2, q0
; CHECK-NEXT: vcvtb.f16.f32 s0, s8 ; CHECK-NEXT: vcvtb.f16.f32 s0, s8
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vcvtt.f16.f32 s0, s9
; CHECK-NEXT: vcvtb.f16.f32 s0, s9 ; CHECK-NEXT: vcvtb.f16.f32 s1, s10
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vcvtt.f16.f32 s1, s11
; CHECK-NEXT: vmov.16 q0[0], r0 ; CHECK-NEXT: vcvtb.f16.f32 s2, s4
; CHECK-NEXT: vcvtb.f16.f32 s12, s10 ; CHECK-NEXT: vcvtt.f16.f32 s2, s5
; CHECK-NEXT: vmov.16 q0[1], r1 ; CHECK-NEXT: vcvtb.f16.f32 s3, s6
; CHECK-NEXT: vmov r0, s12 ; CHECK-NEXT: vcvtt.f16.f32 s3, s7
; CHECK-NEXT: vcvtb.f16.f32 s8, s11
; CHECK-NEXT: vmov.16 q0[2], r0
; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vcvtb.f16.f32 s8, s4
; CHECK-NEXT: vmov.16 q0[3], r0
; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vcvtb.f16.f32 s8, s5
; CHECK-NEXT: vmov.16 q0[4], r0
; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vcvtb.f16.f32 s8, s6
; CHECK-NEXT: vmov.16 q0[5], r0
; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vcvtb.f16.f32 s4, s7
; CHECK-NEXT: vmov.16 q0[6], r0
; CHECK-NEXT: vmov r0, s4
; CHECK-NEXT: vmov.16 q0[7], r0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%out = fptrunc <8 x float> %src1 to <8 x half> %out = fptrunc <8 x float> %src1 to <8 x half>
ret <8 x half> %out ret <8 x half> %out
} }
define arm_aapcs_vfpcc <8 x half> @shuffle_trunc1(<4 x float> %src1, <4 x float> %src2) { define arm_aapcs_vfpcc <8 x half> @shuffle_trunc1(<4 x float> %src1, <4 x float> %src2) {
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