[ARM] Describe defs/uses of VLLDM and VLSTM

[chill]

Summary

The VLLDM and VLSTM instructions are incompletely specified. They (potentially)
write (or read, respectively) registers Q0-Q7, VPR, and FPSCR, but the compiler
is unaware of it.

In the new test case cmse-vlldm-no-reorder.ll case the compiler missed an
anti-dependency and reordered a VLLDM ahead of the instruction, which stashed
the return value from the non-secure call, effectively clobbering said
value.

This test case does not fail with upstream LLVM, because of scheduling
differences and I couldn't find a test case for the VLSTM either.

[efriedma]

llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp

1285

RegState::Undef seems wrong: presumably the registers may actually contain data we need to preserve, or we wouldn't bother saving them in the first place.

[chill]

llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp

1285

Saving/restoring is fine even if we didn't have to.

The "undef" is because we don't want to require the register to be defined at the point before the vlstm. Defined or not, we save then restore, don't care about values.

Otherwise, the machine verifier complains about the use of undefined register.

Is it possible for the scheduler to reorder a def after the "undef"-ed use in vlstm ? If yes, indeed, that'd be a problem, in which case maybe we can just set the insn as a scheduling barrier.

[efriedma]

llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp

1285

Generally, registers which are explicitly saved by the callee are part of the live-in list of the entry block. The "definition" comes from the caller. I would expect save/restore of the FP registers here to work the same way.

[chill]

Updated to take into account liveness of registers. Whenever we blanket push registers, the live ones are ordinary operands,
the dead ones are Undef operands.

[chill]

PIng.

[efriedma]

Can you add a testcase showing the MIR before/after ARMExpandPseudoInsts?

[efriedma]

LGTM

[chill]

Thanks!

llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp

private:
     MachineBasicBlock &CMSEClearFPRegsV8(MachineBasicBlock &MBB,
                                          MachineBasicBlock::iterator MBBI,
                                          const BitVector &ClearRegs);
     MachineBasicBlock &CMSEClearFPRegsV81(MachineBasicBlock &MBB,
                                           MachineBasicBlock::iterator MBBI,
                                           const BitVector &ClearRegs);
     void CMSESaveClearFPRegs(MachineBasicBlock &MBB,
                              MachineBasicBlock::iterator MBBI, DebugLoc &DL,
+                             const LivePhysRegs &LiveRegs,
                              SmallVectorImpl<unsigned> &AvailableRegs);
     void CMSESaveClearFPRegsV8(MachineBasicBlock &MBB,
                                MachineBasicBlock::iterator MBBI, DebugLoc &DL,
+                               const LivePhysRegs &LiveRegs,
                                SmallVectorImpl<unsigned> &ScratchRegs);
     void CMSESaveClearFPRegsV81(MachineBasicBlock &MBB,
-                                MachineBasicBlock::iterator MBBI, DebugLoc &DL);
+                                MachineBasicBlock::iterator MBBI, DebugLoc &DL,
+                                const LivePhysRegs &LiveRegs);
     void CMSERestoreFPRegs(MachineBasicBlock &MBB,
                            MachineBasicBlock::iterator MBBI, DebugLoc &DL,
                            SmallVectorImpl<unsigned> &AvailableRegs);
     void CMSERestoreFPRegsV8(MachineBasicBlock &MBB,
                              MachineBasicBlock::iterator MBBI, DebugLoc &DL,
                              SmallVectorImpl<unsigned> &AvailableRegs);
     void CMSERestoreFPRegsV81(MachineBasicBlock &MBB,
                               MachineBasicBlock::iterator MBBI, DebugLoc &DL,
if (Start < End) {
     VSCCLRM.addReg(ARM::VPR, RegState::Define);
   }
 
   return MBB;
 }
 
 void ARMExpandPseudo::CMSESaveClearFPRegs(
     MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc &DL,
-    SmallVectorImpl<unsigned> &ScratchRegs) {
+    const LivePhysRegs &LiveRegs, SmallVectorImpl<unsigned> &ScratchRegs) {
   if (STI->hasV8_1MMainlineOps())
-    CMSESaveClearFPRegsV81(MBB, MBBI, DL);
+    CMSESaveClearFPRegsV81(MBB, MBBI, DL, LiveRegs);
   else
-    CMSESaveClearFPRegsV8(MBB, MBBI, DL, ScratchRegs);
+    CMSESaveClearFPRegsV8(MBB, MBBI, DL, LiveRegs, ScratchRegs);
 }
 
 // Save and clear FP registers if present
 void ARMExpandPseudo::CMSESaveClearFPRegsV8(
     MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc &DL,
-    SmallVectorImpl<unsigned> &ScratchRegs) {
+    const LivePhysRegs &LiveRegs, SmallVectorImpl<unsigned> &ScratchRegs) {
   if (!STI->hasFPRegs())
     return;
 
   // Store an available register for FPSCR clearing
   assert(!ScratchRegs.empty());
   unsigned SpareReg = ScratchRegs.front();
 
   // save space on stack for VLSTM
for (const MachineOperand &Op : MBBI->operands()) {
     }
   }
 
   bool passesFPReg = (!NonclearedFPRegs.empty() || !ClearedFPRegs.empty());
 
   // Lazy store all fp registers to the stack
   MachineInstrBuilder VLSTM = BuildMI(MBB, MBBI, DL, TII->get(ARM::VLSTM))
                                   .addReg(ARM::SP)
                                   .add(predOps(ARMCC::AL));
+  for (auto R : {ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, ARM::Q0, ARM::Q1,
+                 ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7})
+    VLSTM.addReg(R, RegState::Implicit |
+                        (LiveRegs.contains(R) ? 0 : RegState::Undef));
 
   // Restore all arguments
   for (const auto &Regs : ClearedFPRegs) {
     unsigned Reg, SaveReg1, SaveReg2;
     std::tie(Reg, SaveReg1, SaveReg2) = Regs;
     if (ARM::DPR_VFP2RegClass.contains(Reg))
       BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVDRR), Reg)
           .addReg(SaveReg1)
           .addReg(SaveReg2)
           .add(predOps(ARMCC::AL));
     else if (ARM::SPRRegClass.contains(Reg))
       BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVSR), Reg)
if (passesFPReg) {
     // The ldr must happen after a floating point instruction. To prevent the
     // post-ra scheduler to mess with the order, we create a bundle.
     finalizeBundle(MBB, VLSTM->getIterator(), MBBI->getIterator());
   }
 }
 
 void ARMExpandPseudo::CMSESaveClearFPRegsV81(MachineBasicBlock &MBB,
                                              MachineBasicBlock::iterator MBBI,
-                                             DebugLoc &DL) {
+                                             DebugLoc &DL,
+                                             const LivePhysRegs &LiveRegs) {
   BitVector ClearRegs(32, true);
   bool DefFP = determineFPRegsToClear(*MBBI, ClearRegs);
 
   // If the instruction does not write to a FP register and no elements were
   // removed from the set, then no FP registers were used to pass
   // arguments/returns.
   if (!DefFP && ClearRegs.count() == ClearRegs.size()) {
     // save space on stack for VLSTM
     BuildMI(MBB, MBBI, DL, TII->get(ARM::tSUBspi), ARM::SP)
         .addReg(ARM::SP)
         .addImm(CMSE_FP_SAVE_SIZE >> 2)
         .add(predOps(ARMCC::AL));
 
     // Lazy store all FP registers to the stack
-    BuildMI(MBB, MBBI, DL, TII->get(ARM::VLSTM))
+    MachineInstrBuilder VLSTM = BuildMI(MBB, MBBI, DL, TII->get(ARM::VLSTM))
                                     .addReg(ARM::SP)
                                     .add(predOps(ARMCC::AL));
+    for (auto R : {ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, ARM::Q0, ARM::Q1,
+                   ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7})
+      VLSTM.addReg(R, RegState::Implicit |
+                          (LiveRegs.contains(R) ? 0 : RegState::Undef));
   } else {
     // Push all the callee-saved registers (s16-s31).
     MachineInstrBuilder VPUSH =
         BuildMI(MBB, MBBI, DL, TII->get(ARM::VSTMSDB_UPD), ARM::SP)
             .addReg(ARM::SP)
             .add(predOps(ARMCC::AL));
     for (int Reg = ARM::S16; Reg <= ARM::S31; ++Reg)
       VPUSH.addReg(Reg);
bool ARMExpandPseudo::ExpandCMP_SWAP_64(MachineBasicBlock &MBB,
   computeAndAddLiveIns(LiveRegs, *LoadCmpBB);
 
   return true;
 }
 
 static void CMSEPushCalleeSaves(const TargetInstrInfo &TII,
                                 MachineBasicBlock &MBB,
                                 MachineBasicBlock::iterator MBBI, int JumpReg,
-                                bool Thumb1Only) {
+                                const LivePhysRegs &LiveRegs, bool Thumb1Only) {
   const DebugLoc &DL = MBBI->getDebugLoc();
   if (Thumb1Only) { // push Lo and Hi regs separately
     MachineInstrBuilder PushMIB =
         BuildMI(MBB, MBBI, DL, TII.get(ARM::tPUSH)).add(predOps(ARMCC::AL));
-    for (int Reg = ARM::R4; Reg < ARM::R8; ++Reg)
-      PushMIB.addReg(Reg, Reg != JumpReg ? RegState::Undef : 0);
+    for (int Reg = ARM::R4; Reg < ARM::R8; ++Reg) {
+      PushMIB.addReg(
+          Reg, Reg == JumpReg || LiveRegs.contains(Reg) ? 0 : RegState::Undef);
+    }
 
     // Thumb1 can only tPUSH low regs, so we copy the high regs to the low
     // regs that we just saved and push the low regs again, taking care to
     // not clobber JumpReg. If JumpReg is one of the low registers, push first
     // the values of r9-r11, and then r8. That would leave them ordered in
     // memory, and allow us to later pop them with a single instructions.
     // FIXME: Could also use any of r0-r3 that are free (including in the
     // first PUSH above).
     for (int LoReg = ARM::R7, HiReg = ARM::R11; LoReg >= ARM::R4; --LoReg) {
       if (JumpReg == LoReg)
         continue;
       BuildMI(MBB, MBBI, DL, TII.get(ARM::tMOVr), LoReg)
-          .addReg(HiReg, RegState::Undef)
+          .addReg(HiReg, LiveRegs.contains(HiReg) ? 0 : RegState::Undef)
           .add(predOps(ARMCC::AL));
       --HiReg;
     }
     MachineInstrBuilder PushMIB2 =
         BuildMI(MBB, MBBI, DL, TII.get(ARM::tPUSH)).add(predOps(ARMCC::AL));
     for (int Reg = ARM::R4; Reg < ARM::R8; ++Reg) {
       if (Reg == JumpReg)
         continue;
       PushMIB2.addReg(Reg, RegState::Kill);
     }
 
     // If we couldn't use a low register for temporary storage (because it was
     // the JumpReg), use r4 or r5, whichever is not JumpReg. It has already been
     // saved.
     if (JumpReg >= ARM::R4 && JumpReg <= ARM::R7) {
       int LoReg = JumpReg == ARM::R4 ? ARM::R5 : ARM::R4;
       BuildMI(MBB, MBBI, DL, TII.get(ARM::tMOVr), LoReg)
-          .addReg(ARM::R8)
+          .addReg(ARM::R8, LiveRegs.contains(ARM::R8) ? 0 : RegState::Undef)
           .add(predOps(ARMCC::AL));
       BuildMI(MBB, MBBI, DL, TII.get(ARM::tPUSH))
           .add(predOps(ARMCC::AL))
-          .addReg(LoReg);
+          .addReg(LoReg, RegState::Kill);
     }
   } else { // push Lo and Hi registers with a single instruction
     MachineInstrBuilder PushMIB =
         BuildMI(MBB, MBBI, DL, TII.get(ARM::t2STMDB_UPD), ARM::SP)
             .addReg(ARM::SP)
             .add(predOps(ARMCC::AL));
-    for (int Reg = ARM::R4; Reg < ARM::R12; ++Reg)
-      PushMIB.addReg(Reg, Reg != JumpReg ? RegState::Undef : 0);
+    for (int Reg = ARM::R4; Reg < ARM::R12; ++Reg) {
+      PushMIB.addReg(
+          Reg, Reg == JumpReg || LiveRegs.contains(Reg) ? 0 : RegState::Undef);
+    }
   }
 }
 
 static void CMSEPopCalleeSaves(const TargetInstrInfo &TII,
                                MachineBasicBlock &MBB,
                                MachineBasicBlock::iterator MBBI, int JumpReg,
                                bool Thumb1Only) {
   const DebugLoc &DL = MBBI->getDebugLoc();
case ARM::tBXNS_RET: {
       for (const MachineOperand &Op : MI.operands())
         NewMI->addOperand(Op);
       MI.eraseFromParent();
       return true;
     }
     case ARM::tBLXNS_CALL: {
       DebugLoc DL = MBBI->getDebugLoc();
       unsigned JumpReg = MBBI->getOperand(0).getReg();
-      CMSEPushCalleeSaves(*TII, MBB, MBBI, JumpReg,
+
+      // Figure out which registers are live at the point immediately before the
+      // call. When we indiscriminately push a set of registers, the live
+      // registers are added as ordinary use operands, whereas dead registers
+      // are "undef".
+      LivePhysRegs LiveRegs(*TRI);
+      LiveRegs.addLiveOuts(MBB);
+      for (const MachineInstr &MI : make_range(MBB.rbegin(), MBBI.getReverse()))
+        LiveRegs.stepBackward(MI);
+      LiveRegs.stepBackward(*MBBI);
+
+      CMSEPushCalleeSaves(*TII, MBB, MBBI, JumpReg, LiveRegs,
                           AFI->isThumb1OnlyFunction());
 
       SmallVector<unsigned, 16> ClearRegs;
       determineGPRegsToClear(*MBBI,
                              {ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4,
                               ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9,
                               ARM::R10, ARM::R11, ARM::R12},
                              ClearRegs);
case ARM::tBLXNS_CALL: {
             .add(predOps(ARMCC::AL));
         BuildMI(MBB, MBBI, DL, TII->get(ARM::tBIC), JumpReg)
             .addReg(ARM::CPSR, RegState::Define)
             .addReg(JumpReg)
             .addReg(ScratchReg)
             .add(predOps(ARMCC::AL));
       }
 
-      CMSESaveClearFPRegs(MBB, MBBI, DL,
+      CMSESaveClearFPRegs(MBB, MBBI, DL, LiveRegs,
                           ClearRegs); // save+clear FP regs with ClearRegs
       CMSEClearGPRegs(MBB, MBBI, DL, ClearRegs, JumpReg);
 
       const MachineInstrBuilder NewCall =
           BuildMI(MBB, MBBI, DL, TII->get(ARM::tBLXNSr))
               .add(predOps(ARMCC::AL))
               .addReg(JumpReg, RegState::Kill);
 

llvm/lib/Target/ARM/ARMInstrVFP.td

 
 def : MnemonicAlias<"vldm", "vldmia">;
 def : MnemonicAlias<"vstm", "vstmia">;
 
 
 //===----------------------------------------------------------------------===//
 //  Lazy load / store multiple Instructions
 //
-let mayLoad = 1 in
 def VLLDM : AXSI4<(outs), (ins GPRnopc:$Rn, pred:$p), IndexModeNone,
                   NoItinerary, "vlldm${p}\t$Rn", "", []>,
             Requires<[HasV8MMainline, Has8MSecExt]> {
     let Inst{24-23} = 0b00;
     let Inst{22}    = 0;
     let Inst{21}    = 1;
     let Inst{20}    = 1;
     let Inst{15-12} = 0;
     let Inst{7-0}   = 0;
     let mayLoad     = 1;
+    let Defs = [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, VPR, FPSCR, FPSCR_NZCV];
 }
 
-let mayStore = 1 in
 def VLSTM : AXSI4<(outs), (ins GPRnopc:$Rn, pred:$p), IndexModeNone,
                   NoItinerary, "vlstm${p}\t$Rn", "", []>,
             Requires<[HasV8MMainline, Has8MSecExt]> {
     let Inst{24-23} = 0b00;
     let Inst{22}    = 0;
     let Inst{21}    = 1;
     let Inst{20}    = 0;
     let Inst{15-12} = 0;

llvm/test/CodeGen/ARM/cmse-vlldm-no-reorder.ll

+; RUN: llc -mtriple=thumbv8m.main -mcpu=cortex-m33 --float-abi=hard %s -o - | \
+; RUN:   FileCheck %s
+
+@g = hidden local_unnamed_addr global float (...)* null, align 4
+@a = hidden local_unnamed_addr global float 0.000000e+00, align 4
+
+define hidden void @f() local_unnamed_addr #0 {
+entry:
+  %0 = load float ()*, float ()** bitcast (float (...)** @g to float ()**), align 4
+  %call = tail call nnan ninf nsz float %0() #1
+  store float %call, float* @a, align 4
+  ret void
+}
+
+; CHECK: blxns r{{[0-9]+}}
+; CHECK: vmov  r[[T:[0-9]+]], s0
+; CHECK: vlldm sp
+; CHECK: vmov  s0, r[[T]]
+
+attributes #0 = { nounwind }
+attributes #1 = { nounwind "cmse_nonsecure_call" }

llvm/test/CodeGen/ARM/cmse-vlldm-no-reorder.mir

+# RUN: llc -mtriple=thumbv8m.main -mcpu=cortex-m33 --float-abi=hard --run-pass=arm-pseudo %s -o - | \
+# RUN: FileCheck %s
+--- |
+  ; ModuleID = 'cmse-vlldm-no-reorder.ll'
+  source_filename = "cmse-vlldm-no-reorder.ll"
+  target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
+  target triple = "thumbv8m.main"
+  
+  @g = hidden local_unnamed_addr global float (...)* null, align 4
+  @a = hidden local_unnamed_addr global float 0.000000e+00, align 4
+  
+  ; Function Attrs: nounwind
+  define hidden void @f() local_unnamed_addr #0 {
+  entry:
+    %0 = load float ()*, float ()** bitcast (float (...)** @g to float ()**), align 4
+    %call = tail call nnan ninf nsz float %0() #2
+    store float %call, float* @a, align 4
+    ret void
+  }
+  
+  ; Function Attrs: nounwind
+  declare void @llvm.stackprotector(i8*, i8**) #1
+  
+  attributes #0 = { nounwind "target-cpu"="cortex-m33" }
+  attributes #1 = { nounwind }
+  attributes #2 = { nounwind "cmse_nonsecure_call" }
+
+...
+---
+name:            f
+alignment:       2
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+failedISel:      false
+tracksRegLiveness: true
+hasWinCFI:       false
+registers:       []
+liveins:         []
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       8
+  offsetAdjustment: 0
+  maxAlignment:    4
+  adjustsStack:    true
+  hasCalls:        true
+  stackProtector:  ''
+  maxCallFrameSize: 0
+  cvBytesOfCalleeSavedRegisters: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+  localFrameSize:  0
+  savePoint:       ''
+  restorePoint:    ''
+fixedStack:      []
+stack:
+  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 
+      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, 
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 
+      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, 
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+callSites:       []
+constants:       []
+machineFunctionInfo: {}
+body:             |
+  bb.0.entry:
+    liveins: $r7, $lr
+  
+    $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r7, killed $lr
+    frame-setup CFI_INSTRUCTION def_cfa_offset 8
+    frame-setup CFI_INSTRUCTION offset $lr, -4
+    frame-setup CFI_INSTRUCTION offset $r7, -8
+    renamable $r0 = t2MOVi32imm @g
+    renamable $r0 = t2LDRi12 killed renamable $r0, 0, 14 /* CC::al */, $noreg :: (dereferenceable load 4 from `float ()** bitcast (float (...)** @g to float ()**)`)
+    tBLXNS_CALL killed renamable $r0, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def $s0
+    renamable $r0 = t2MOVi32imm @a
+    VSTRS killed renamable $s0, killed renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 4 into @a)
+    $sp = frame-destroy t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r7, def $pc
+
+...
+
+# CHECK-LABEL: bb.0.entry:
+# CHECK: $sp = t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, $r4, $r5, $r6, undef $r7, $r8, $r9, $r10, $r11
+# CHECK-NEXT:  $r0 = t2BICri $r0, 1, 14 /* CC::al */, $noreg, $noreg
+# CHECK-NEXT:  $sp = tSUBspi $sp, 34, 14 /* CC::al */, $noreg
+# CHECK-NEXT:  VLSTM $sp, 14 /* CC::al */, $noreg, implicit undef $vpr, implicit undef $fpscr, implicit undef $fpscr_nzcv, implicit undef $q0, implicit undef $q1, implicit undef $q2, implicit undef $q3, implicit undef $q4, implicit undef $q5, implicit undef $q6, implicit undef $q7
+# CHECK-NEXT:  $r1 = tMOVr $r0, 14 /* CC::al */, $noreg
+# CHECK-NEXT:  $r2 = tMOVr $r0, 14 /* CC::al */, $noreg
+# CHECK-NEXT:  $r3 = tMOVr $r0, 14 /* CC::al */, $noreg
+# CHECK-NEXT:  $r4 = tMOVr $r0, 14 /* CC::al */, $noreg
+# CHECK-NEXT:  $r5 = tMOVr $r0, 14 /* CC::al */, $noreg
+# CHECK-NEXT:  $r6 = tMOVr $r0, 14 /* CC::al */, $noreg
+# CHECK-NEXT:  $r7 = tMOVr $r0, 14 /* CC::al */, $noreg
+# CHECK-NEXT:  $r8 = tMOVr $r0, 14 /* CC::al */, $noreg
+# CHECK-NEXT:  $r9 = tMOVr $r0, 14 /* CC::al */, $noreg
+# CHECK-NEXT:  $r10 = tMOVr $r0, 14 /* CC::al */, $noreg
+# CHECK-NEXT:  $r11 = tMOVr $r0, 14 /* CC::al */, $noreg
+# CHECK-NEXT:  $r12 = tMOVr $r0, 14 /* CC::al */, $noreg
+# CHECK-NEXT:  t2MSR_M 3072, $r0, 14 /* CC::al */, $noreg, implicit-def $cpsr
+# CHECK-NEXT:  tBLXNSr 14 /* CC::al */, $noreg, killed $r0, csr_aapcs, implicit-def $lr, implicit $sp, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def $s0
+# CHECK-NEXT:  $r12 = VMOVRS $s0, 14 /* CC::al */, $noreg
+# CHECK-NEXT:  VLLDM $sp, 14 /* CC::al */, $noreg, implicit-def $q0, implicit-def $q1, implicit-def $q2, implicit-def $q3, implicit-def $q4, implicit-def $q5, implicit-def $q6, implicit-def $q7, implicit-def $vpr, implicit-def $fpscr, implicit-def $fpscr_nzcv
+# CHECK-NEXT:  $s0 = VMOVSR $r12, 14 /* CC::al */, $noreg
+# CHECK-NEXT:  $sp = tADDspi $sp, 34, 14 /* CC::al */, $noreg
+# CHECK-NEXT:  $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11
+ 
 No newline at end of file

llvm/test/CodeGen/ARM/vlldm-vlstm-uops.mir

body:             |
   bb.2.land.end:
     liveins: $r4
 
     $sp = t2STMDB_UPD $sp, 14, $noreg, $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11
     $r4 = t2BICri $r4, 1, 14, $noreg, $noreg
     $sp = tSUBspi $sp, 34, 14, $noreg
     VLSTM $sp, 14, $noreg
     tBLXNSr 14, $noreg, killed $r4, csr_aapcs, implicit-def $lr, implicit $sp, implicit-def dead $lr, implicit $sp, implicit-def $sp
-    VLLDM $sp, 14, $noreg
+    VLLDM $sp, 14, $noreg, implicit-def $q0, implicit-def $q1, implicit-def $q2, implicit-def $q3, implicit-def $q4, implicit-def $q5, implicit-def $q6, implicit-def $q7, implicit-def $vpr, implicit-def $fpscr, implicit-def $fpscr_nzcv
     $sp = tADDspi $sp, 34, 14, $noreg
     $sp = t2LDMIA_UPD $sp, 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11
     $sp = t2LDMIA_RET $sp, 14, $noreg, def $r4, def $pc
 
 ...
 # Just check there is no ICE (in debug builds)
 # CHECK: name: foo