This is an archive of the discontinued LLVM Phabricator instance.

Differential D81458

[AArch64][SVE] Change pointer type of struct load/store intrinsics.
ClosedPublic

Authored by sdesmalen on Jun 9 2020, 4:56 AM.

Details

Reviewers
fpetrogalli
c-rhodes
rengolin
efriedma
Commits
rGa0e3ceea6ce9: [AArch64][SVE] Change pointer type of struct load/store intrinsics.
Summary

Instead of loading from e.g. <vscale x 16 x i8>*, load from element
pointer i8*. This is more in line with the other load/store
intrinsics for SVE.

Diff Detail

Event Timeline

sdesmalen created this revision.Jun 9 2020, 4:56 AM
Herald added a reviewer: rengolin. · View Herald TranscriptJun 9 2020, 4:56 AM
Herald added a reviewer: efriedma. · View Herald Transcript
Herald added a project: Restricted Project. · View Herald Transcript
Herald added subscribers: danielkiss, psnobl, rkruppe and 2 others. · View Herald Transcript
sdesmalen added a child revision: D81466: [SveEmitter] Add builtins for struct loads/stores (ld2/ld3/etc).Jun 9 2020, 6:10 AM
Harbormaster failed remote builds in B59617: Diff 269494!Jun 9 2020, 6:33 AM
sdesmalen updated this revision to Diff 269567.Jun 9 2020, 9:07 AM

Fixed sve-intrinsics-stN-reg-reg-addr-mode.ll

efriedma accepted this revision.Jun 9 2020, 10:05 AM

LGTM

This revision is now accepted and ready to land.Jun 9 2020, 10:05 AM
Closed by commit rGa0e3ceea6ce9: [AArch64][SVE] Change pointer type of struct load/store intrinsics. (authored by sdesmalen). · Explain WhyJun 10 2020, 6:32 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

Diff 269826

llvm/include/llvm/IR/IntrinsicsAArch64.td

Show First 20 Lines • Show All 809 Lines • ▼ Show 20 Lines : Intrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, llvm_i32_ty, llvm_anyvector_ty], [LLVMMatchType<0>, llvm_i32_ty, llvm_anyvector_ty],
[IntrReadMem, ImmArg<ArgIndex<1>>]>; [IntrReadMem, ImmArg<ArgIndex<1>>]>;
class AdvSIMD_SVE_Get_Vector_Tuple class AdvSIMD_SVE_Get_Vector_Tuple
: Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty, llvm_i32_ty], : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty, llvm_i32_ty],
[IntrReadMem, IntrArgMemOnly, ImmArg<ArgIndex<1>>]>; [IntrReadMem, IntrArgMemOnly, ImmArg<ArgIndex<1>>]>;
class AdvSIMD_ManyVec_PredLoad_Intrinsic class AdvSIMD_ManyVec_PredLoad_Intrinsic
: Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty, llvm_anyptr_ty], : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty, LLVMPointerToElt<0>],
[IntrReadMem, IntrArgMemOnly]>; [IntrReadMem, IntrArgMemOnly]>;
class AdvSIMD_1Vec_PredLoad_Intrinsic class AdvSIMD_1Vec_PredLoad_Intrinsic
: Intrinsic<[llvm_anyvector_ty], : Intrinsic<[llvm_anyvector_ty],
[LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, [LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
LLVMPointerToElt<0>], LLVMPointerToElt<0>],
[IntrReadMem, IntrArgMemOnly]>; [IntrReadMem, IntrArgMemOnly]>;
class AdvSIMD_1Vec_PredStore_Intrinsic class AdvSIMD_1Vec_PredStore_Intrinsic
: Intrinsic<[], : Intrinsic<[],
[llvm_anyvector_ty, [llvm_anyvector_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
LLVMPointerToElt<0>], LLVMPointerToElt<0>],
[IntrArgMemOnly, NoCapture<ArgIndex<2>>]>; [IntrArgMemOnly, NoCapture<ArgIndex<2>>]>;
class AdvSIMD_2Vec_PredStore_Intrinsic class AdvSIMD_2Vec_PredStore_Intrinsic
: Intrinsic<[], : Intrinsic<[],
[llvm_anyvector_ty, LLVMMatchType<0>, [llvm_anyvector_ty, LLVMMatchType<0>,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMPointerTo<0>], LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMPointerToElt<0>],
[IntrArgMemOnly, NoCapture<ArgIndex<3>>]>; [IntrArgMemOnly, NoCapture<ArgIndex<3>>]>;
class AdvSIMD_3Vec_PredStore_Intrinsic class AdvSIMD_3Vec_PredStore_Intrinsic
: Intrinsic<[], : Intrinsic<[],
[llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>, [llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMPointerTo<0>], LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMPointerToElt<0>],
[IntrArgMemOnly, NoCapture<ArgIndex<4>>]>; [IntrArgMemOnly, NoCapture<ArgIndex<4>>]>;
class AdvSIMD_4Vec_PredStore_Intrinsic class AdvSIMD_4Vec_PredStore_Intrinsic
: Intrinsic<[], : Intrinsic<[],
[llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>, [llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>,
LLVMMatchType<0>, LLVMMatchType<0>,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMPointerTo<0>], LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMPointerToElt<0>],
[IntrArgMemOnly, NoCapture<ArgIndex<5>>]>; [IntrArgMemOnly, NoCapture<ArgIndex<5>>]>;
class AdvSIMD_SVE_Index_Intrinsic class AdvSIMD_SVE_Index_Intrinsic
: Intrinsic<[llvm_anyvector_ty], : Intrinsic<[llvm_anyvector_ty],
[LLVMVectorElementType<0>, [LLVMVectorElementType<0>,
LLVMVectorElementType<0>], LLVMVectorElementType<0>],
[IntrNoMem]>; [IntrNoMem]>;
▲ Show 20 Lines • Show All 1,484 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/sve-intrinsics-loads.ll

Show First 20 Lines • Show All 250 Lines • ▼ Show 20 Lines %res = call <vscale x 2 x double> @llvm.aarch64.sve.ldnt1.nxv2f64(<vscale x 2 x i1> %pred,
double* %addr) double* %addr)
ret <vscale x 2 x double> %res ret <vscale x 2 x double> %res
} }
; ;
; LD2B ; LD2B
; ;
define <vscale x 32 x i8> @ld2b_i8(<vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) { define <vscale x 32 x i8> @ld2b_i8(<vscale x 16 x i1> %pred, i8* %addr) {
; CHECK-LABEL: ld2b_i8: ; CHECK-LABEL: ld2b_i8:
; CHECK: ld2b { z0.b, z1.b }, p0/z, [x0] ; CHECK: ld2b { z0.b, z1.b }, p0/z, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 32 x i8> @llvm.aarch64.sve.ld2.nxv32i8.nxv16i1.p0nxv16i8(<vscale x 16 x i1> %pred, %res = call <vscale x 32 x i8> @llvm.aarch64.sve.ld2.nxv32i8.nxv16i1.p0i8(<vscale x 16 x i1> %pred, i8* %addr)
<vscale x 16 x i8>* %addr)
ret <vscale x 32 x i8> %res ret <vscale x 32 x i8> %res
} }
; ;
; LD2H ; LD2H
; ;
define <vscale x 16 x i16> @ld2h_i16(<vscale x 8 x i1> %pred, <vscale x 8 x i16>* %addr) { define <vscale x 16 x i16> @ld2h_i16(<vscale x 8 x i1> %pred, i16* %addr) {
; CHECK-LABEL: ld2h_i16: ; CHECK-LABEL: ld2h_i16:
; CHECK: ld2h { z0.h, z1.h }, p0/z, [x0] ; CHECK: ld2h { z0.h, z1.h }, p0/z, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 16 x i16> @llvm.aarch64.sve.ld2.nxv16i16.nxv8i1.p0nxv8i16(<vscale x 8 x i1> %pred, %res = call <vscale x 16 x i16> @llvm.aarch64.sve.ld2.nxv16i16.nxv8i1.p0i16(<vscale x 8 x i1> %pred, i16* %addr)
<vscale x 8 x i16>* %addr)
ret <vscale x 16 x i16> %res ret <vscale x 16 x i16> %res
} }
define <vscale x 16 x half> @ld2h_f16(<vscale x 8 x i1> %pred, <vscale x 8 x half>* %addr) { define <vscale x 16 x half> @ld2h_f16(<vscale x 8 x i1> %pred, half* %addr) {
; CHECK-LABEL: ld2h_f16: ; CHECK-LABEL: ld2h_f16:
; CHECK: ld2h { z0.h, z1.h }, p0/z, [x0] ; CHECK: ld2h { z0.h, z1.h }, p0/z, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 16 x half> @llvm.aarch64.sve.ld2.nxv16f16.nxv8i1.p0nxv8f16(<vscale x 8 x i1> %pred, %res = call <vscale x 16 x half> @llvm.aarch64.sve.ld2.nxv16f16.nxv8i1.p0f16(<vscale x 8 x i1> %pred, half* %addr)
<vscale x 8 x half>* %addr)
ret <vscale x 16 x half> %res ret <vscale x 16 x half> %res
} }
; ;
; LD2W ; LD2W
; ;
define <vscale x 8 x i32> @ld2w_i32(<vscale x 4 x i1> %pred, <vscale x 4 x i32>* %addr) { define <vscale x 8 x i32> @ld2w_i32(<vscale x 4 x i1> %pred, i32* %addr) {
; CHECK-LABEL: ld2w_i32: ; CHECK-LABEL: ld2w_i32:
; CHECK: ld2w { z0.s, z1.s }, p0/z, [x0] ; CHECK: ld2w { z0.s, z1.s }, p0/z, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 8 x i32> @llvm.aarch64.sve.ld2.nxv8i32.nxv4i1.p0nxv4i32(<vscale x 4 x i1> %pred, %res = call <vscale x 8 x i32> @llvm.aarch64.sve.ld2.nxv8i32.nxv4i1.p0i32(<vscale x 4 x i1> %pred, i32* %addr)
<vscale x 4 x i32>* %addr)
ret <vscale x 8 x i32> %res ret <vscale x 8 x i32> %res
} }
define <vscale x 8 x float> @ld2w_f32(<vscale x 4 x i1> %pred, <vscale x 4 x float>* %addr) { define <vscale x 8 x float> @ld2w_f32(<vscale x 4 x i1> %pred, float* %addr) {
; CHECK-LABEL: ld2w_f32: ; CHECK-LABEL: ld2w_f32:
; CHECK: ld2w { z0.s, z1.s }, p0/z, [x0] ; CHECK: ld2w { z0.s, z1.s }, p0/z, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 8 x float> @llvm.aarch64.sve.ld2.nxv8f32.nxv4i1.p0nxv4f32(<vscale x 4 x i1> %pred, %res = call <vscale x 8 x float> @llvm.aarch64.sve.ld2.nxv8f32.nxv4i1.p0f32(<vscale x 4 x i1> %pred, float* %addr)
<vscale x 4 x float>* %addr)
ret <vscale x 8 x float> %res ret <vscale x 8 x float> %res
} }
; ;
; LD2D ; LD2D
; ;
define <vscale x 4 x i64> @ld2d_i64(<vscale x 2 x i1> %pred, <vscale x 2 x i64>* %addr) { define <vscale x 4 x i64> @ld2d_i64(<vscale x 2 x i1> %pred, i64* %addr) {
; CHECK-LABEL: ld2d_i64: ; CHECK-LABEL: ld2d_i64:
; CHECK: ld2d { z0.d, z1.d }, p0/z, [x0] ; CHECK: ld2d { z0.d, z1.d }, p0/z, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x i64> @llvm.aarch64.sve.ld2.nxv4i64.nxv2i1.p0nxv2i64(<vscale x 2 x i1> %pred, %res = call <vscale x 4 x i64> @llvm.aarch64.sve.ld2.nxv4i64.nxv2i1.p0i64(<vscale x 2 x i1> %pred, i64* %addr)
<vscale x 2 x i64>* %addr)
ret <vscale x 4 x i64> %res ret <vscale x 4 x i64> %res
} }
define <vscale x 4 x double> @ld2d_f64(<vscale x 2 x i1> %pred, <vscale x 2 x double>* %addr) { define <vscale x 4 x double> @ld2d_f64(<vscale x 2 x i1> %pred, double* %addr) {
; CHECK-LABEL: ld2d_f64: ; CHECK-LABEL: ld2d_f64:
; CHECK: ld2d { z0.d, z1.d }, p0/z, [x0] ; CHECK: ld2d { z0.d, z1.d }, p0/z, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x double> @llvm.aarch64.sve.ld2.nxv4f64.nxv2i1.p0nxv2f64(<vscale x 2 x i1> %pred, %res = call <vscale x 4 x double> @llvm.aarch64.sve.ld2.nxv4f64.nxv2i1.p0f64(<vscale x 2 x i1> %pred, double* %addr)
<vscale x 2 x double>* %addr)
ret <vscale x 4 x double> %res ret <vscale x 4 x double> %res
} }
; ;
; LD3B ; LD3B
; ;
define <vscale x 48 x i8> @ld3b_i8(<vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) { define <vscale x 48 x i8> @ld3b_i8(<vscale x 16 x i1> %pred, i8* %addr) {
; CHECK-LABEL: ld3b_i8: ; CHECK-LABEL: ld3b_i8:
; CHECK: ld3b { z0.b, z1.b, z2.b }, p0/z, [x0] ; CHECK: ld3b { z0.b, z1.b, z2.b }, p0/z, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 48 x i8> @llvm.aarch64.sve.ld3.nxv48i8.nxv16i1.p0nxv16i8(<vscale x 16 x i1> %pred, %res = call <vscale x 48 x i8> @llvm.aarch64.sve.ld3.nxv48i8.nxv16i1.p0i8(<vscale x 16 x i1> %pred, i8* %addr)
<vscale x 16 x i8>* %addr)
ret <vscale x 48 x i8> %res ret <vscale x 48 x i8> %res
} }
; ;
; LD3H ; LD3H
; ;
define <vscale x 24 x i16> @ld3h_i16(<vscale x 8 x i1> %pred, <vscale x 8 x i16>* %addr) { define <vscale x 24 x i16> @ld3h_i16(<vscale x 8 x i1> %pred, i16* %addr) {
; CHECK-LABEL: ld3h_i16: ; CHECK-LABEL: ld3h_i16:
; CHECK: ld3h { z0.h, z1.h, z2.h }, p0/z, [x0] ; CHECK: ld3h { z0.h, z1.h, z2.h }, p0/z, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 24 x i16> @llvm.aarch64.sve.ld3.nxv24i16.nxv8i1.p0nxv8i16(<vscale x 8 x i1> %pred, %res = call <vscale x 24 x i16> @llvm.aarch64.sve.ld3.nxv24i16.nxv8i1.p0i16(<vscale x 8 x i1> %pred, i16* %addr)
<vscale x 8 x i16>* %addr)
ret <vscale x 24 x i16> %res ret <vscale x 24 x i16> %res
} }
define <vscale x 24 x half> @ld3h_f16(<vscale x 8 x i1> %pred, <vscale x 8 x half>* %addr) { define <vscale x 24 x half> @ld3h_f16(<vscale x 8 x i1> %pred, half* %addr) {
; CHECK-LABEL: ld3h_f16: ; CHECK-LABEL: ld3h_f16:
; CHECK: ld3h { z0.h, z1.h, z2.h }, p0/z, [x0] ; CHECK: ld3h { z0.h, z1.h, z2.h }, p0/z, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 24 x half> @llvm.aarch64.sve.ld3.nxv24f16.nxv8i1.p0nxv8f16(<vscale x 8 x i1> %pred, %res = call <vscale x 24 x half> @llvm.aarch64.sve.ld3.nxv24f16.nxv8i1.p0f16(<vscale x 8 x i1> %pred, half* %addr)
<vscale x 8 x half>* %addr)
ret <vscale x 24 x half> %res ret <vscale x 24 x half> %res
} }
; ;
; LD3W ; LD3W
; ;
define <vscale x 12 x i32> @ld3w_i32(<vscale x 4 x i1> %pred, <vscale x 4 x i32>* %addr) { define <vscale x 12 x i32> @ld3w_i32(<vscale x 4 x i1> %pred, i32* %addr) {
; CHECK-LABEL: ld3w_i32: ; CHECK-LABEL: ld3w_i32:
; CHECK: ld3w { z0.s, z1.s, z2.s }, p0/z, [x0] ; CHECK: ld3w { z0.s, z1.s, z2.s }, p0/z, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 12 x i32> @llvm.aarch64.sve.ld3.nxv12i32.nxv4i1.p0nxv4i32(<vscale x 4 x i1> %pred, %res = call <vscale x 12 x i32> @llvm.aarch64.sve.ld3.nxv12i32.nxv4i1.p0i32(<vscale x 4 x i1> %pred, i32* %addr)
<vscale x 4 x i32>* %addr)
ret <vscale x 12 x i32> %res ret <vscale x 12 x i32> %res
} }
define <vscale x 12 x float> @ld3w_f32(<vscale x 4 x i1> %pred, <vscale x 4 x float>* %addr) { define <vscale x 12 x float> @ld3w_f32(<vscale x 4 x i1> %pred, float* %addr) {
; CHECK-LABEL: ld3w_f32: ; CHECK-LABEL: ld3w_f32:
; CHECK: ld3w { z0.s, z1.s, z2.s }, p0/z, [x0] ; CHECK: ld3w { z0.s, z1.s, z2.s }, p0/z, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 12 x float> @llvm.aarch64.sve.ld3.nxv12f32.nxv4i1.p0nxv4f32(<vscale x 4 x i1> %pred, %res = call <vscale x 12 x float> @llvm.aarch64.sve.ld3.nxv12f32.nxv4i1.p0f32(<vscale x 4 x i1> %pred, float* %addr)
<vscale x 4 x float>* %addr)
ret <vscale x 12 x float> %res ret <vscale x 12 x float> %res
} }
; ;
; LD3D ; LD3D
; ;
define <vscale x 6 x i64> @ld3d_i64(<vscale x 2 x i1> %pred, <vscale x 2 x i64>* %addr) { define <vscale x 6 x i64> @ld3d_i64(<vscale x 2 x i1> %pred, i64* %addr) {
; CHECK-LABEL: ld3d_i64: ; CHECK-LABEL: ld3d_i64:
; CHECK: ld3d { z0.d, z1.d, z2.d }, p0/z, [x0] ; CHECK: ld3d { z0.d, z1.d, z2.d }, p0/z, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 6 x i64> @llvm.aarch64.sve.ld3.nxv6i64.nxv2i1.p0nxv2i64(<vscale x 2 x i1> %pred, %res = call <vscale x 6 x i64> @llvm.aarch64.sve.ld3.nxv6i64.nxv2i1.p0i64(<vscale x 2 x i1> %pred, i64* %addr)
<vscale x 2 x i64>* %addr)
ret <vscale x 6 x i64> %res ret <vscale x 6 x i64> %res
} }
define <vscale x 6 x double> @ld3d_f64(<vscale x 2 x i1> %pred, <vscale x 2 x double>* %addr) { define <vscale x 6 x double> @ld3d_f64(<vscale x 2 x i1> %pred, double* %addr) {
; CHECK-LABEL: ld3d_f64: ; CHECK-LABEL: ld3d_f64:
; CHECK: ld3d { z0.d, z1.d, z2.d }, p0/z, [x0] ; CHECK: ld3d { z0.d, z1.d, z2.d }, p0/z, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 6 x double> @llvm.aarch64.sve.ld3.nxv6f64.nxv2i1.p0nxv2f64(<vscale x 2 x i1> %pred, %res = call <vscale x 6 x double> @llvm.aarch64.sve.ld3.nxv6f64.nxv2i1.p0f64(<vscale x 2 x i1> %pred, double* %addr)
<vscale x 2 x double>* %addr)
ret <vscale x 6 x double> %res ret <vscale x 6 x double> %res
} }
; ;
; LD4B ; LD4B
; ;
define <vscale x 64 x i8> @ld4b_i8(<vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) { define <vscale x 64 x i8> @ld4b_i8(<vscale x 16 x i1> %pred, i8* %addr) {
; CHECK-LABEL: ld4b_i8: ; CHECK-LABEL: ld4b_i8:
; CHECK: ld4b { z0.b, z1.b, z2.b, z3.b }, p0/z, [x0] ; CHECK: ld4b { z0.b, z1.b, z2.b, z3.b }, p0/z, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 64 x i8> @llvm.aarch64.sve.ld4.nxv64i8.nxv16i1.p0nxv16i8(<vscale x 16 x i1> %pred, %res = call <vscale x 64 x i8> @llvm.aarch64.sve.ld4.nxv64i8.nxv16i1.p0i8(<vscale x 16 x i1> %pred, i8* %addr)
<vscale x 16 x i8>* %addr)
ret <vscale x 64 x i8> %res ret <vscale x 64 x i8> %res
} }
; ;
; LD4H ; LD4H
; ;
define <vscale x 32 x i16> @ld4h_i16(<vscale x 8 x i1> %pred, <vscale x 8 x i16>* %addr) { define <vscale x 32 x i16> @ld4h_i16(<vscale x 8 x i1> %pred, i16* %addr) {
; CHECK-LABEL: ld4h_i16: ; CHECK-LABEL: ld4h_i16:
; CHECK: ld4h { z0.h, z1.h, z2.h, z3.h }, p0/z, [x0] ; CHECK: ld4h { z0.h, z1.h, z2.h, z3.h }, p0/z, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 32 x i16> @llvm.aarch64.sve.ld4.nxv32i16.nxv8i1.p0nxv8i16(<vscale x 8 x i1> %pred, %res = call <vscale x 32 x i16> @llvm.aarch64.sve.ld4.nxv32i16.nxv8i1.p0i16(<vscale x 8 x i1> %pred, i16* %addr)
<vscale x 8 x i16>* %addr)
ret <vscale x 32 x i16> %res ret <vscale x 32 x i16> %res
} }
define <vscale x 32 x half> @ld4h_f16(<vscale x 8 x i1> %pred, <vscale x 8 x half>* %addr) { define <vscale x 32 x half> @ld4h_f16(<vscale x 8 x i1> %pred, half* %addr) {
; CHECK-LABEL: ld4h_f16: ; CHECK-LABEL: ld4h_f16:
; CHECK: ld4h { z0.h, z1.h, z2.h, z3.h }, p0/z, [x0] ; CHECK: ld4h { z0.h, z1.h, z2.h, z3.h }, p0/z, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 32 x half> @llvm.aarch64.sve.ld4.nxv32f16.nxv8i1.p0nxv8f16(<vscale x 8 x i1> %pred, %res = call <vscale x 32 x half> @llvm.aarch64.sve.ld4.nxv32f16.nxv8i1.p0f16(<vscale x 8 x i1> %pred, half* %addr)
<vscale x 8 x half>* %addr)
ret <vscale x 32 x half> %res ret <vscale x 32 x half> %res
} }
; ;
; LD4W ; LD4W
; ;
define <vscale x 16 x i32> @ld4w_i32(<vscale x 4 x i1> %pred, <vscale x 4 x i32>* %addr) { define <vscale x 16 x i32> @ld4w_i32(<vscale x 4 x i1> %pred, i32* %addr) {
; CHECK-LABEL: ld4w_i32: ; CHECK-LABEL: ld4w_i32:
; CHECK: ld4w { z0.s, z1.s, z2.s, z3.s }, p0/z, [x0] ; CHECK: ld4w { z0.s, z1.s, z2.s, z3.s }, p0/z, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 16 x i32> @llvm.aarch64.sve.ld4.nxv16i32.nxv4i1.p0nxv4i32(<vscale x 4 x i1> %pred, %res = call <vscale x 16 x i32> @llvm.aarch64.sve.ld4.nxv16i32.nxv4i1.p0i32(<vscale x 4 x i1> %pred, i32* %addr)
<vscale x 4 x i32>* %addr)
ret <vscale x 16 x i32> %res ret <vscale x 16 x i32> %res
} }
define <vscale x 16 x float> @ld4w_f32(<vscale x 4 x i1> %pred, <vscale x 4 x float>* %addr) { define <vscale x 16 x float> @ld4w_f32(<vscale x 4 x i1> %pred, float* %addr) {
; CHECK-LABEL: ld4w_f32: ; CHECK-LABEL: ld4w_f32:
; CHECK: ld4w { z0.s, z1.s, z2.s, z3.s }, p0/z, [x0] ; CHECK: ld4w { z0.s, z1.s, z2.s, z3.s }, p0/z, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 16 x float> @llvm.aarch64.sve.ld4.nxv16f32.nxv4i1.p0nxv4f32(<vscale x 4 x i1> %pred, %res = call <vscale x 16 x float> @llvm.aarch64.sve.ld4.nxv16f32.nxv4i1.p0f32(<vscale x 4 x i1> %pred, float* %addr)
<vscale x 4 x float>* %addr)
ret <vscale x 16 x float> %res ret <vscale x 16 x float> %res
} }
; ;
; LD4D ; LD4D
; ;
define <vscale x 8 x i64> @ld4d_i64(<vscale x 2 x i1> %pred, <vscale x 2 x i64>* %addr) { define <vscale x 8 x i64> @ld4d_i64(<vscale x 2 x i1> %pred, i64* %addr) {
; CHECK-LABEL: ld4d_i64: ; CHECK-LABEL: ld4d_i64:
; CHECK: ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0] ; CHECK: ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 8 x i64> @llvm.aarch64.sve.ld4.nxv8i64.nxv2i1.p0nxv2i64(<vscale x 2 x i1> %pred, %res = call <vscale x 8 x i64> @llvm.aarch64.sve.ld4.nxv8i64.nxv2i1.p0i64(<vscale x 2 x i1> %pred, i64* %addr)
<vscale x 2 x i64>* %addr)
ret <vscale x 8 x i64> %res ret <vscale x 8 x i64> %res
} }
define <vscale x 8 x double> @ld4d_f64(<vscale x 2 x i1> %pred, <vscale x 2 x double>* %addr) { define <vscale x 8 x double> @ld4d_f64(<vscale x 2 x i1> %pred, double* %addr) {
; CHECK-LABEL: ld4d_f64: ; CHECK-LABEL: ld4d_f64:
; CHECK: ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0] ; CHECK: ld4d { z0.d, z1.d, z2.d, z3.d }, p0/z, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 8 x double> @llvm.aarch64.sve.ld4.nxv8f64.nxv2i1.p0nxv2f64(<vscale x 2 x i1> %pred, %res = call <vscale x 8 x double> @llvm.aarch64.sve.ld4.nxv8f64.nxv2i1.p0f64(<vscale x 2 x i1> %pred, double* %addr)
<vscale x 2 x double>* %addr)
ret <vscale x 8 x double> %res ret <vscale x 8 x double> %res
} }
declare <vscale x 16 x i8> @llvm.aarch64.sve.ld1rq.nxv16i8(<vscale x 16 x i1>, i8*) declare <vscale x 16 x i8> @llvm.aarch64.sve.ld1rq.nxv16i8(<vscale x 16 x i1>, i8*)
declare <vscale x 8 x i16> @llvm.aarch64.sve.ld1rq.nxv8i16(<vscale x 8 x i1>, i16*) declare <vscale x 8 x i16> @llvm.aarch64.sve.ld1rq.nxv8i16(<vscale x 8 x i1>, i16*)
declare <vscale x 4 x i32> @llvm.aarch64.sve.ld1rq.nxv4i32(<vscale x 4 x i1>, i32*) declare <vscale x 4 x i32> @llvm.aarch64.sve.ld1rq.nxv4i32(<vscale x 4 x i1>, i32*)
declare <vscale x 2 x i64> @llvm.aarch64.sve.ld1rq.nxv2i64(<vscale x 2 x i1>, i64*) declare <vscale x 2 x i64> @llvm.aarch64.sve.ld1rq.nxv2i64(<vscale x 2 x i1>, i64*)
declare <vscale x 8 x half> @llvm.aarch64.sve.ld1rq.nxv8f16(<vscale x 8 x i1>, half*) declare <vscale x 8 x half> @llvm.aarch64.sve.ld1rq.nxv8f16(<vscale x 8 x i1>, half*)
declare <vscale x 4 x float> @llvm.aarch64.sve.ld1rq.nxv4f32(<vscale x 4 x i1>, float*) declare <vscale x 4 x float> @llvm.aarch64.sve.ld1rq.nxv4f32(<vscale x 4 x i1>, float*)
declare <vscale x 2 x double> @llvm.aarch64.sve.ld1rq.nxv2f64(<vscale x 2 x i1>, double*) declare <vscale x 2 x double> @llvm.aarch64.sve.ld1rq.nxv2f64(<vscale x 2 x i1>, double*)
declare <vscale x 16 x i8> @llvm.aarch64.sve.ldnt1.nxv16i8(<vscale x 16 x i1>, i8*) declare <vscale x 16 x i8> @llvm.aarch64.sve.ldnt1.nxv16i8(<vscale x 16 x i1>, i8*)
declare <vscale x 8 x i16> @llvm.aarch64.sve.ldnt1.nxv8i16(<vscale x 8 x i1>, i16*) declare <vscale x 8 x i16> @llvm.aarch64.sve.ldnt1.nxv8i16(<vscale x 8 x i1>, i16*)
declare <vscale x 4 x i32> @llvm.aarch64.sve.ldnt1.nxv4i32(<vscale x 4 x i1>, i32*) declare <vscale x 4 x i32> @llvm.aarch64.sve.ldnt1.nxv4i32(<vscale x 4 x i1>, i32*)
declare <vscale x 2 x i64> @llvm.aarch64.sve.ldnt1.nxv2i64(<vscale x 2 x i1>, i64*) declare <vscale x 2 x i64> @llvm.aarch64.sve.ldnt1.nxv2i64(<vscale x 2 x i1>, i64*)
declare <vscale x 8 x half> @llvm.aarch64.sve.ldnt1.nxv8f16(<vscale x 8 x i1>, half*) declare <vscale x 8 x half> @llvm.aarch64.sve.ldnt1.nxv8f16(<vscale x 8 x i1>, half*)
declare <vscale x 4 x float> @llvm.aarch64.sve.ldnt1.nxv4f32(<vscale x 4 x i1>, float*) declare <vscale x 4 x float> @llvm.aarch64.sve.ldnt1.nxv4f32(<vscale x 4 x i1>, float*)
declare <vscale x 2 x double> @llvm.aarch64.sve.ldnt1.nxv2f64(<vscale x 2 x i1>, double*) declare <vscale x 2 x double> @llvm.aarch64.sve.ldnt1.nxv2f64(<vscale x 2 x i1>, double*)
declare <vscale x 32 x i8> @llvm.aarch64.sve.ld2.nxv32i8.nxv16i1.p0nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>*) declare <vscale x 32 x i8> @llvm.aarch64.sve.ld2.nxv32i8.nxv16i1.p0i8(<vscale x 16 x i1>, i8*)
declare <vscale x 16 x i16> @llvm.aarch64.sve.ld2.nxv16i16.nxv8i1.p0nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>*) declare <vscale x 16 x i16> @llvm.aarch64.sve.ld2.nxv16i16.nxv8i1.p0i16(<vscale x 8 x i1>, i16*)
declare <vscale x 8 x i32> @llvm.aarch64.sve.ld2.nxv8i32.nxv4i1.p0nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>*) declare <vscale x 8 x i32> @llvm.aarch64.sve.ld2.nxv8i32.nxv4i1.p0i32(<vscale x 4 x i1>, i32*)
declare <vscale x 4 x i64> @llvm.aarch64.sve.ld2.nxv4i64.nxv2i1.p0nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>*) declare <vscale x 4 x i64> @llvm.aarch64.sve.ld2.nxv4i64.nxv2i1.p0i64(<vscale x 2 x i1>, i64*)
declare <vscale x 16 x half> @llvm.aarch64.sve.ld2.nxv16f16.nxv8i1.p0nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>*) declare <vscale x 16 x half> @llvm.aarch64.sve.ld2.nxv16f16.nxv8i1.p0f16(<vscale x 8 x i1>, half*)
declare <vscale x 8 x float> @llvm.aarch64.sve.ld2.nxv8f32.nxv4i1.p0nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>*) declare <vscale x 8 x float> @llvm.aarch64.sve.ld2.nxv8f32.nxv4i1.p0f32(<vscale x 4 x i1>, float*)
declare <vscale x 4 x double> @llvm.aarch64.sve.ld2.nxv4f64.nxv2i1.p0nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>*) declare <vscale x 4 x double> @llvm.aarch64.sve.ld2.nxv4f64.nxv2i1.p0f64(<vscale x 2 x i1>, double*)
declare <vscale x 48 x i8> @llvm.aarch64.sve.ld3.nxv48i8.nxv16i1.p0nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>*) declare <vscale x 48 x i8> @llvm.aarch64.sve.ld3.nxv48i8.nxv16i1.p0i8(<vscale x 16 x i1>, i8*)
declare <vscale x 24 x i16> @llvm.aarch64.sve.ld3.nxv24i16.nxv8i1.p0nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>*) declare <vscale x 24 x i16> @llvm.aarch64.sve.ld3.nxv24i16.nxv8i1.p0i16(<vscale x 8 x i1>, i16*)
declare <vscale x 12 x i32> @llvm.aarch64.sve.ld3.nxv12i32.nxv4i1.p0nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>*) declare <vscale x 12 x i32> @llvm.aarch64.sve.ld3.nxv12i32.nxv4i1.p0i32(<vscale x 4 x i1>, i32*)
declare <vscale x 6 x i64> @llvm.aarch64.sve.ld3.nxv6i64.nxv2i1.p0nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>*) declare <vscale x 6 x i64> @llvm.aarch64.sve.ld3.nxv6i64.nxv2i1.p0i64(<vscale x 2 x i1>, i64*)
declare <vscale x 24 x half> @llvm.aarch64.sve.ld3.nxv24f16.nxv8i1.p0nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>*) declare <vscale x 24 x half> @llvm.aarch64.sve.ld3.nxv24f16.nxv8i1.p0f16(<vscale x 8 x i1>, half*)
declare <vscale x 12 x float> @llvm.aarch64.sve.ld3.nxv12f32.nxv4i1.p0nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>*) declare <vscale x 12 x float> @llvm.aarch64.sve.ld3.nxv12f32.nxv4i1.p0f32(<vscale x 4 x i1>, float*)
declare <vscale x 6 x double> @llvm.aarch64.sve.ld3.nxv6f64.nxv2i1.p0nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>*) declare <vscale x 6 x double> @llvm.aarch64.sve.ld3.nxv6f64.nxv2i1.p0f64(<vscale x 2 x i1>, double*)
declare <vscale x 64 x i8> @llvm.aarch64.sve.ld4.nxv64i8.nxv16i1.p0nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>*) declare <vscale x 64 x i8> @llvm.aarch64.sve.ld4.nxv64i8.nxv16i1.p0i8(<vscale x 16 x i1>, i8*)
declare <vscale x 32 x i16> @llvm.aarch64.sve.ld4.nxv32i16.nxv8i1.p0nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>*) declare <vscale x 32 x i16> @llvm.aarch64.sve.ld4.nxv32i16.nxv8i1.p0i16(<vscale x 8 x i1>, i16*)
declare <vscale x 16 x i32> @llvm.aarch64.sve.ld4.nxv16i32.nxv4i1.p0nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>*) declare <vscale x 16 x i32> @llvm.aarch64.sve.ld4.nxv16i32.nxv4i1.p0i32(<vscale x 4 x i1>, i32*)
declare <vscale x 8 x i64> @llvm.aarch64.sve.ld4.nxv8i64.nxv2i1.p0nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>*) declare <vscale x 8 x i64> @llvm.aarch64.sve.ld4.nxv8i64.nxv2i1.p0i64(<vscale x 2 x i1>, i64*)
declare <vscale x 32 x half> @llvm.aarch64.sve.ld4.nxv32f16.nxv8i1.p0nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>*) declare <vscale x 32 x half> @llvm.aarch64.sve.ld4.nxv32f16.nxv8i1.p0f16(<vscale x 8 x i1>, half*)
declare <vscale x 16 x float> @llvm.aarch64.sve.ld4.nxv16f32.nxv4i1.p0nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>*) declare <vscale x 16 x float> @llvm.aarch64.sve.ld4.nxv16f32.nxv4i1.p0f32(<vscale x 4 x i1>, float*)
declare <vscale x 8 x double> @llvm.aarch64.sve.ld4.nxv8f64.nxv2i1.p0nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>*) declare <vscale x 8 x double> @llvm.aarch64.sve.ld4.nxv8f64.nxv2i1.p0f64(<vscale x 2 x i1>, double*)

llvm/test/CodeGen/AArch64/sve-intrinsics-stN-reg-imm-addr-mode.ll

; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -asm-verbose=0 < %s | FileCheck %s ; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -asm-verbose=0 < %s | FileCheck %s
; NOTE: invalid, upper and lower bound immediate values of the reg+imm ; NOTE: invalid, upper and lower bound immediate values of the reg+imm
; addressing mode are checked only for the byte version of each ; addressing mode are checked only for the byte version of each
; instruction (`st<N>b`), as the code for detecting the immediate is ; instruction (`st<N>b`), as the code for detecting the immediate is
; common to all instructions, and varies only for the number of ; common to all instructions, and varies only for the number of
; elements of the structured store, which is <N> = 2, 3, 4. ; elements of the structured store, which is <N> = 2, 3, 4.
; ;
; ST2B ; ST2B
; ;
define void @st2b_i8_valid_imm(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) { define void @st2b_i8_valid_imm(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) {
; CHECK-LABEL: st2b_i8_valid_imm: ; CHECK-LABEL: st2b_i8_valid_imm:
; CHECK: st2b { z0.b, z1.b }, p0, [x0, #2, mul vl] ; CHECK: st2b { z0.b, z1.b }, p0, [x0, #2, mul vl]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 2 %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 2, i64 0
call void @llvm.aarch64.sve.st2.nxv16i8(<vscale x 16 x i8> %v0, call void @llvm.aarch64.sve.st2.nxv16i8(<vscale x 16 x i8> %v0,
<vscale x 16 x i8> %v1, <vscale x 16 x i8> %v1,
<vscale x 16 x i1> %pred, <vscale x 16 x i1> %pred,
<vscale x 16 x i8>* %base) i8* %base)
ret void ret void
} }
define void @st2b_i8_invalid_imm_not_multiple_of_2(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) { define void @st2b_i8_invalid_imm_not_multiple_of_2(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) {
; CHECK-LABEL: st2b_i8_invalid_imm_not_multiple_of_2: ; CHECK-LABEL: st2b_i8_invalid_imm_not_multiple_of_2:
; CHECK: rdvl x[[N:[0-9]+]], #3 ; CHECK: rdvl x[[N:[0-9]+]], #3
; CHECK-NEXT: st2b { z0.b, z1.b }, p0, [x0, x[[N]]] ; CHECK-NEXT: st2b { z0.b, z1.b }, p0, [x0, x[[N]]]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 3 %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 3, i64 0
call void @llvm.aarch64.sve.st2.nxv16i8(<vscale x 16 x i8> %v0, call void @llvm.aarch64.sve.st2.nxv16i8(<vscale x 16 x i8> %v0,
<vscale x 16 x i8> %v1, <vscale x 16 x i8> %v1,
<vscale x 16 x i1> %pred, <vscale x 16 x i1> %pred,
<vscale x 16 x i8>* %base) i8* %base)
ret void ret void
} }
define void @st2b_i8_invalid_imm_out_of_lower_bound(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) { define void @st2b_i8_invalid_imm_out_of_lower_bound(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) {
; CHECK-LABEL: st2b_i8_invalid_imm_out_of_lower_bound: ; CHECK-LABEL: st2b_i8_invalid_imm_out_of_lower_bound:
; CHECK: rdvl x[[N:[0-9]+]], #-18 ; CHECK: rdvl x[[N:[0-9]+]], #-18
; CHECK-NEXT: st2b { z0.b, z1.b }, p0, [x0, x[[N]]] ; CHECK-NEXT: st2b { z0.b, z1.b }, p0, [x0, x[[N]]]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 -18 %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 -18, i64 0
call void @llvm.aarch64.sve.st2.nxv16i8(<vscale x 16 x i8> %v0, call void @llvm.aarch64.sve.st2.nxv16i8(<vscale x 16 x i8> %v0,
<vscale x 16 x i8> %v1, <vscale x 16 x i8> %v1,
<vscale x 16 x i1> %pred, <vscale x 16 x i1> %pred,
<vscale x 16 x i8>* %base) i8* %base)
ret void ret void
} }
define void @st2b_i8_invalid_imm_out_of_upper_bound(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) { define void @st2b_i8_invalid_imm_out_of_upper_bound(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) {
; CHECK-LABEL: st2b_i8_invalid_imm_out_of_upper_bound: ; CHECK-LABEL: st2b_i8_invalid_imm_out_of_upper_bound:
; CHECK: rdvl x[[N:[0-9]+]], #16 ; CHECK: rdvl x[[N:[0-9]+]], #16
; CHECK-NEXT: st2b { z0.b, z1.b }, p0, [x0, x[[N]]] ; CHECK-NEXT: st2b { z0.b, z1.b }, p0, [x0, x[[N]]]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 16 %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 16, i64 0
call void @llvm.aarch64.sve.st2.nxv16i8(<vscale x 16 x i8> %v0, call void @llvm.aarch64.sve.st2.nxv16i8(<vscale x 16 x i8> %v0,
<vscale x 16 x i8> %v1, <vscale x 16 x i8> %v1,
<vscale x 16 x i1> %pred, <vscale x 16 x i1> %pred,
<vscale x 16 x i8>* %base) i8* %base)
ret void ret void
} }
define void @st2b_i8_valid_imm_lower_bound(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) { define void @st2b_i8_valid_imm_lower_bound(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) {
; CHECK-LABEL: st2b_i8_valid_imm_lower_bound: ; CHECK-LABEL: st2b_i8_valid_imm_lower_bound:
; CHECK: st2b { z0.b, z1.b }, p0, [x0, #-16, mul vl] ; CHECK: st2b { z0.b, z1.b }, p0, [x0, #-16, mul vl]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 -16 %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 -16, i64 0
call void @llvm.aarch64.sve.st2.nxv16i8(<vscale x 16 x i8> %v0, call void @llvm.aarch64.sve.st2.nxv16i8(<vscale x 16 x i8> %v0,
<vscale x 16 x i8> %v1, <vscale x 16 x i8> %v1,
<vscale x 16 x i1> %pred, <vscale x 16 x i1> %pred,
<vscale x 16 x i8>* %base) i8* %base)
ret void ret void
} }
define void @st2b_i8_valid_imm_upper_bound(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) { define void @st2b_i8_valid_imm_upper_bound(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) {
; CHECK-LABEL: st2b_i8_valid_imm_upper_bound: ; CHECK-LABEL: st2b_i8_valid_imm_upper_bound:
; CHECK: st2b { z0.b, z1.b }, p0, [x0, #14, mul vl] ; CHECK: st2b { z0.b, z1.b }, p0, [x0, #14, mul vl]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 14 %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 14, i64 0
call void @llvm.aarch64.sve.st2.nxv16i8(<vscale x 16 x i8> %v0, call void @llvm.aarch64.sve.st2.nxv16i8(<vscale x 16 x i8> %v0,
<vscale x 16 x i8> %v1, <vscale x 16 x i8> %v1,
<vscale x 16 x i1> %pred, <vscale x 16 x i1> %pred,
<vscale x 16 x i8>* %base) i8* %base)
ret void ret void
} }
; ;
; ST2H ; ST2H
; ;
define void @st2h_i16(<vscale x 8 x i16> %v0, <vscale x 8 x i16> %v1, <vscale x 8 x i1> %pred, <vscale x 8 x i16>* %addr) { define void @st2h_i16(<vscale x 8 x i16> %v0, <vscale x 8 x i16> %v1, <vscale x 8 x i1> %pred, <vscale x 8 x i16>* %addr) {
; CHECK-LABEL: st2h_i16: ; CHECK-LABEL: st2h_i16:
; CHECK: st2h { z0.h, z1.h }, p0, [x0, #2, mul vl] ; CHECK: st2h { z0.h, z1.h }, p0, [x0, #2, mul vl]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%base = getelementptr <vscale x 8 x i16>, <vscale x 8 x i16>* %addr, i64 2 %base = getelementptr <vscale x 8 x i16>, <vscale x 8 x i16>* %addr, i64 2, i64 0
call void @llvm.aarch64.sve.st2.nxv8i16(<vscale x 8 x i16> %v0, call void @llvm.aarch64.sve.st2.nxv8i16(<vscale x 8 x i16> %v0,
<vscale x 8 x i16> %v1, <vscale x 8 x i16> %v1,
<vscale x 8 x i1> %pred, <vscale x 8 x i1> %pred,
<vscale x 8 x i16>* %base) i16* %base)
ret void ret void
} }
define void @st2h_f16(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1, <vscale x 8 x i1> %pred, <vscale x 8 x half>* %addr) { define void @st2h_f16(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1, <vscale x 8 x i1> %pred, <vscale x 8 x half>* %addr) {
; CHECK-LABEL: st2h_f16: ; CHECK-LABEL: st2h_f16:
; CHECK: st2h { z0.h, z1.h }, p0, [x0, #2, mul vl] ; CHECK: st2h { z0.h, z1.h }, p0, [x0, #2, mul vl]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%base = getelementptr <vscale x 8 x half>, <vscale x 8 x half>* %addr, i64 2 %base = getelementptr <vscale x 8 x half>, <vscale x 8 x half>* %addr, i64 2, i64 0
call void @llvm.aarch64.sve.st2.nxv8f16(<vscale x 8 x half> %v0, call void @llvm.aarch64.sve.st2.nxv8f16(<vscale x 8 x half> %v0,
<vscale x 8 x half> %v1, <vscale x 8 x half> %v1,
<vscale x 8 x i1> %pred, <vscale x 8 x i1> %pred,
<vscale x 8 x half>* %base) half* %base)
ret void ret void
} }
; ;
; ST2W ; ST2W
; ;
define void @st2w_i32(<vscale x 4 x i32> %v0, <vscale x 4 x i32> %v1, <vscale x 4 x i1> %pred, <vscale x 4 x i32>* %addr) { define void @st2w_i32(<vscale x 4 x i32> %v0, <vscale x 4 x i32> %v1, <vscale x 4 x i1> %pred, <vscale x 4 x i32>* %addr) {
; CHECK-LABEL: st2w_i32: ; CHECK-LABEL: st2w_i32:
; CHECK: st2w { z0.s, z1.s }, p0, [x0, #4, mul vl] ; CHECK: st2w { z0.s, z1.s }, p0, [x0, #4, mul vl]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%base = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* %addr, i64 4 %base = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* %addr, i64 4, i64 0
call void @llvm.aarch64.sve.st2.nxv4i32(<vscale x 4 x i32> %v0, call void @llvm.aarch64.sve.st2.nxv4i32(<vscale x 4 x i32> %v0,
<vscale x 4 x i32> %v1, <vscale x 4 x i32> %v1,
<vscale x 4 x i1> %pred, <vscale x 4 x i1> %pred,
<vscale x 4 x i32>* %base) i32* %base)
ret void ret void
} }
define void @st2w_f32(<vscale x 4 x float> %v0, <vscale x 4 x float> %v1, <vscale x 4 x i1> %pred, <vscale x 4 x float>* %addr) { define void @st2w_f32(<vscale x 4 x float> %v0, <vscale x 4 x float> %v1, <vscale x 4 x i1> %pred, <vscale x 4 x float>* %addr) {
; CHECK-LABEL: st2w_f32: ; CHECK-LABEL: st2w_f32:
; CHECK: st2w { z0.s, z1.s }, p0, [x0, #6, mul vl] ; CHECK: st2w { z0.s, z1.s }, p0, [x0, #6, mul vl]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%base = getelementptr <vscale x 4 x float>, <vscale x 4 x float>* %addr, i64 6 %base = getelementptr <vscale x 4 x float>, <vscale x 4 x float>* %addr, i64 6, i64 0
call void @llvm.aarch64.sve.st2.nxv4f32(<vscale x 4 x float> %v0, call void @llvm.aarch64.sve.st2.nxv4f32(<vscale x 4 x float> %v0,
<vscale x 4 x float> %v1, <vscale x 4 x float> %v1,
<vscale x 4 x i1> %pred, <vscale x 4 x i1> %pred,
<vscale x 4 x float>* %base) float* %base)
ret void ret void
} }
; ;
; ST2D ; ST2D
; ;
define void @st2d_i64(<vscale x 2 x i64> %v0, <vscale x 2 x i64> %v1, <vscale x 2 x i1> %pred, <vscale x 2 x i64>* %addr) { define void @st2d_i64(<vscale x 2 x i64> %v0, <vscale x 2 x i64> %v1, <vscale x 2 x i1> %pred, <vscale x 2 x i64>* %addr) {
; CHECK-LABEL: st2d_i64: ; CHECK-LABEL: st2d_i64:
; CHECK: st2d { z0.d, z1.d }, p0, [x0, #8, mul vl] ; CHECK: st2d { z0.d, z1.d }, p0, [x0, #8, mul vl]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%base = getelementptr <vscale x 2 x i64>, <vscale x 2 x i64>* %addr, i64 8 %base = getelementptr <vscale x 2 x i64>, <vscale x 2 x i64>* %addr, i64 8, i64 0
call void @llvm.aarch64.sve.st2.nxv2i64(<vscale x 2 x i64> %v0, call void @llvm.aarch64.sve.st2.nxv2i64(<vscale x 2 x i64> %v0,
<vscale x 2 x i64> %v1, <vscale x 2 x i64> %v1,
<vscale x 2 x i1> %pred, <vscale x 2 x i1> %pred,
<vscale x 2 x i64>* %base) i64* %base)
ret void ret void
} }
define void @st2d_f64(<vscale x 2 x double> %v0, <vscale x 2 x double> %v1, <vscale x 2 x i1> %pred, <vscale x 2 x double>* %addr) { define void @st2d_f64(<vscale x 2 x double> %v0, <vscale x 2 x double> %v1, <vscale x 2 x i1> %pred, <vscale x 2 x double>* %addr) {
; CHECK-LABEL: st2d_f64: ; CHECK-LABEL: st2d_f64:
; CHECK: st2d { z0.d, z1.d }, p0, [x0, #10, mul vl] ; CHECK: st2d { z0.d, z1.d }, p0, [x0, #10, mul vl]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%base = getelementptr <vscale x 2 x double>, <vscale x 2 x double>* %addr, i64 10 %base = getelementptr <vscale x 2 x double>, <vscale x 2 x double>* %addr, i64 10, i64 0
call void @llvm.aarch64.sve.st2.nxv2f64(<vscale x 2 x double> %v0, call void @llvm.aarch64.sve.st2.nxv2f64(<vscale x 2 x double> %v0,
<vscale x 2 x double> %v1, <vscale x 2 x double> %v1,
<vscale x 2 x i1> %pred, <vscale x 2 x i1> %pred,
<vscale x 2 x double>* %base) double* %base)
ret void ret void
} }
; ;
; ST3B ; ST3B
; ;
define void @st3b_i8_valid_imm(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) { define void @st3b_i8_valid_imm(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) {
; CHECK-LABEL: st3b_i8_valid_imm: ; CHECK-LABEL: st3b_i8_valid_imm:
; CHECK: st3b { z0.b, z1.b, z2.b }, p0, [x0, #3, mul vl] ; CHECK: st3b { z0.b, z1.b, z2.b }, p0, [x0, #3, mul vl]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 3 %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 3, i64 0
call void @llvm.aarch64.sve.st3.nxv16i8(<vscale x 16 x i8> %v0, call void @llvm.aarch64.sve.st3.nxv16i8(<vscale x 16 x i8> %v0,
<vscale x 16 x i8> %v1, <vscale x 16 x i8> %v1,
<vscale x 16 x i8> %v2, <vscale x 16 x i8> %v2,
<vscale x 16 x i1> %pred, <vscale x 16 x i1> %pred,
<vscale x 16 x i8>* %base) i8* %base)
ret void ret void
} }
define void @st3b_i8_invalid_imm_not_multiple_of_3_01(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) { define void @st3b_i8_invalid_imm_not_multiple_of_3_01(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) {
; CHECK-LABEL: st3b_i8_invalid_imm_not_multiple_of_3_01: ; CHECK-LABEL: st3b_i8_invalid_imm_not_multiple_of_3_01:
; CHECK: rdvl x[[N:[0-9]+]], #4 ; CHECK: rdvl x[[N:[0-9]+]], #4
; CHECK-NEXT: st3b { z0.b, z1.b, z2.b }, p0, [x0, x[[N]]] ; CHECK-NEXT: st3b { z0.b, z1.b, z2.b }, p0, [x0, x[[N]]]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 4 %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 4, i64 0
call void @llvm.aarch64.sve.st3.nxv16i8(<vscale x 16 x i8> %v0, call void @llvm.aarch64.sve.st3.nxv16i8(<vscale x 16 x i8> %v0,
<vscale x 16 x i8> %v1, <vscale x 16 x i8> %v1,
<vscale x 16 x i8> %v2, <vscale x 16 x i8> %v2,
<vscale x 16 x i1> %pred, <vscale x 16 x i1> %pred,
<vscale x 16 x i8>* %base) i8* %base)
ret void ret void
} }
define void @st3b_i8_invalid_imm_not_multiple_of_3_02(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) { define void @st3b_i8_invalid_imm_not_multiple_of_3_02(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) {
; CHECK-LABEL: st3b_i8_invalid_imm_not_multiple_of_3_02: ; CHECK-LABEL: st3b_i8_invalid_imm_not_multiple_of_3_02:
; CHECK: rdvl x[[N:[0-9]+]], #5 ; CHECK: rdvl x[[N:[0-9]+]], #5
; CHECK-NEXT: st3b { z0.b, z1.b, z2.b }, p0, [x0, x[[N]]] ; CHECK-NEXT: st3b { z0.b, z1.b, z2.b }, p0, [x0, x[[N]]]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 5 %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 5, i64 0
call void @llvm.aarch64.sve.st3.nxv16i8(<vscale x 16 x i8> %v0, call void @llvm.aarch64.sve.st3.nxv16i8(<vscale x 16 x i8> %v0,
<vscale x 16 x i8> %v1, <vscale x 16 x i8> %v1,
<vscale x 16 x i8> %v2, <vscale x 16 x i8> %v2,
<vscale x 16 x i1> %pred, <vscale x 16 x i1> %pred,
<vscale x 16 x i8>* %base) i8* %base)
ret void ret void
} }
define void @st3b_i8_invalid_imm_out_of_lower_bound(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) { define void @st3b_i8_invalid_imm_out_of_lower_bound(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) {
; CHECK-LABEL: st3b_i8_invalid_imm_out_of_lower_bound: ; CHECK-LABEL: st3b_i8_invalid_imm_out_of_lower_bound:
; CHECK: rdvl x[[N:[0-9]+]], #-27 ; CHECK: rdvl x[[N:[0-9]+]], #-27
; CHECK-NEXT: st3b { z0.b, z1.b, z2.b }, p0, [x0, x[[N]]] ; CHECK-NEXT: st3b { z0.b, z1.b, z2.b }, p0, [x0, x[[N]]]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 -27 %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 -27, i64 0
call void @llvm.aarch64.sve.st3.nxv16i8(<vscale x 16 x i8> %v0, call void @llvm.aarch64.sve.st3.nxv16i8(<vscale x 16 x i8> %v0,
<vscale x 16 x i8> %v1, <vscale x 16 x i8> %v1,
<vscale x 16 x i8> %v2, <vscale x 16 x i8> %v2,
<vscale x 16 x i1> %pred, <vscale x 16 x i1> %pred,
<vscale x 16 x i8>* %base) i8* %base)
ret void ret void
} }
define void @st3b_i8_invalid_imm_out_of_upper_bound(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) { define void @st3b_i8_invalid_imm_out_of_upper_bound(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) {
; CHECK-LABEL: st3b_i8_invalid_imm_out_of_upper_bound: ; CHECK-LABEL: st3b_i8_invalid_imm_out_of_upper_bound:
; CHECK: rdvl x[[N:[0-9]+]], #24 ; CHECK: rdvl x[[N:[0-9]+]], #24
; CHECK-NEXT: st3b { z0.b, z1.b, z2.b }, p0, [x0, x[[N]]] ; CHECK-NEXT: st3b { z0.b, z1.b, z2.b }, p0, [x0, x[[N]]]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 24 %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 24, i64 0
call void @llvm.aarch64.sve.st3.nxv16i8(<vscale x 16 x i8> %v0, call void @llvm.aarch64.sve.st3.nxv16i8(<vscale x 16 x i8> %v0,
<vscale x 16 x i8> %v1, <vscale x 16 x i8> %v1,
<vscale x 16 x i8> %v2, <vscale x 16 x i8> %v2,
<vscale x 16 x i1> %pred, <vscale x 16 x i1> %pred,
<vscale x 16 x i8>* %base) i8* %base)
ret void ret void
} }
define void @st3b_i8_valid_imm_lower_bound(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) { define void @st3b_i8_valid_imm_lower_bound(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) {
; CHECK-LABEL: st3b_i8_valid_imm_lower_bound: ; CHECK-LABEL: st3b_i8_valid_imm_lower_bound:
; CHECK: st3b { z0.b, z1.b, z2.b }, p0, [x0, #-24, mul vl] ; CHECK: st3b { z0.b, z1.b, z2.b }, p0, [x0, #-24, mul vl]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 -24 %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 -24, i64 0
call void @llvm.aarch64.sve.st3.nxv16i8(<vscale x 16 x i8> %v0, call void @llvm.aarch64.sve.st3.nxv16i8(<vscale x 16 x i8> %v0,
<vscale x 16 x i8> %v1, <vscale x 16 x i8> %v1,
<vscale x 16 x i8> %v2, <vscale x 16 x i8> %v2,
<vscale x 16 x i1> %pred, <vscale x 16 x i1> %pred,
<vscale x 16 x i8>* %base) i8* %base)
ret void ret void
} }
define void @st3b_i8_valid_imm_upper_bound(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) { define void @st3b_i8_valid_imm_upper_bound(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) {
; CHECK-LABEL: st3b_i8_valid_imm_upper_bound: ; CHECK-LABEL: st3b_i8_valid_imm_upper_bound:
; CHECK: st3b { z0.b, z1.b, z2.b }, p0, [x0, #21, mul vl] ; CHECK: st3b { z0.b, z1.b, z2.b }, p0, [x0, #21, mul vl]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 21 %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 21, i64 0
call void @llvm.aarch64.sve.st3.nxv16i8(<vscale x 16 x i8> %v0, call void @llvm.aarch64.sve.st3.nxv16i8(<vscale x 16 x i8> %v0,
<vscale x 16 x i8> %v1, <vscale x 16 x i8> %v1,
<vscale x 16 x i8> %v2, <vscale x 16 x i8> %v2,
<vscale x 16 x i1> %pred, <vscale x 16 x i1> %pred,
<vscale x 16 x i8>* %base) i8* %base)
ret void ret void
} }
; ;
; ST3H ; ST3H
; ;
define void @st3h_i16(<vscale x 8 x i16> %v0, <vscale x 8 x i16> %v1, <vscale x 8 x i16> %v2, <vscale x 8 x i1> %pred, <vscale x 8 x i16>* %addr) { define void @st3h_i16(<vscale x 8 x i16> %v0, <vscale x 8 x i16> %v1, <vscale x 8 x i16> %v2, <vscale x 8 x i1> %pred, <vscale x 8 x i16>* %addr) {
; CHECK-LABEL: st3h_i16: ; CHECK-LABEL: st3h_i16:
; CHECK: st3h { z0.h, z1.h, z2.h }, p0, [x0, #6, mul vl] ; CHECK: st3h { z0.h, z1.h, z2.h }, p0, [x0, #6, mul vl]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%base = getelementptr <vscale x 8 x i16>, <vscale x 8 x i16>* %addr, i64 6 %base = getelementptr <vscale x 8 x i16>, <vscale x 8 x i16>* %addr, i64 6, i64 0
call void @llvm.aarch64.sve.st3.nxv8i16(<vscale x 8 x i16> %v0, call void @llvm.aarch64.sve.st3.nxv8i16(<vscale x 8 x i16> %v0,
<vscale x 8 x i16> %v1, <vscale x 8 x i16> %v1,
<vscale x 8 x i16> %v2, <vscale x 8 x i16> %v2,
<vscale x 8 x i1> %pred, <vscale x 8 x i1> %pred,
<vscale x 8 x i16>* %base) i16* %base)
ret void ret void
} }
define void @st3h_f16(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1, <vscale x 8 x half> %v2, <vscale x 8 x i1> %pred, <vscale x 8 x half>* %addr) { define void @st3h_f16(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1, <vscale x 8 x half> %v2, <vscale x 8 x i1> %pred, <vscale x 8 x half>* %addr) {
; CHECK-LABEL: st3h_f16: ; CHECK-LABEL: st3h_f16:
; CHECK: st3h { z0.h, z1.h, z2.h }, p0, [x0, #9, mul vl] ; CHECK: st3h { z0.h, z1.h, z2.h }, p0, [x0, #9, mul vl]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%base = getelementptr <vscale x 8 x half>, <vscale x 8 x half>* %addr, i64 9 %base = getelementptr <vscale x 8 x half>, <vscale x 8 x half>* %addr, i64 9, i64 0
call void @llvm.aarch64.sve.st3.nxv8f16(<vscale x 8 x half> %v0, call void @llvm.aarch64.sve.st3.nxv8f16(<vscale x 8 x half> %v0,
<vscale x 8 x half> %v1, <vscale x 8 x half> %v1,
<vscale x 8 x half> %v2, <vscale x 8 x half> %v2,
<vscale x 8 x i1> %pred, <vscale x 8 x i1> %pred,
<vscale x 8 x half>* %base) half* %base)
ret void ret void
} }
; ;
; ST3W ; ST3W
; ;
define void @st3w_i32(<vscale x 4 x i32> %v0, <vscale x 4 x i32> %v1, <vscale x 4 x i32> %v2, <vscale x 4 x i1> %pred, <vscale x 4 x i32>* %addr) { define void @st3w_i32(<vscale x 4 x i32> %v0, <vscale x 4 x i32> %v1, <vscale x 4 x i32> %v2, <vscale x 4 x i1> %pred, <vscale x 4 x i32>* %addr) {
; CHECK-LABEL: st3w_i32: ; CHECK-LABEL: st3w_i32:
; CHECK: st3w { z0.s, z1.s, z2.s }, p0, [x0, #12, mul vl] ; CHECK: st3w { z0.s, z1.s, z2.s }, p0, [x0, #12, mul vl]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%base = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* %addr, i64 12 %base = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* %addr, i64 12, i64 0
call void @llvm.aarch64.sve.st3.nxv4i32(<vscale x 4 x i32> %v0, call void @llvm.aarch64.sve.st3.nxv4i32(<vscale x 4 x i32> %v0,
<vscale x 4 x i32> %v1, <vscale x 4 x i32> %v1,
<vscale x 4 x i32> %v2, <vscale x 4 x i32> %v2,
<vscale x 4 x i1> %pred, <vscale x 4 x i1> %pred,
<vscale x 4 x i32>* %base) i32* %base)
ret void ret void
} }
define void @st3w_f32(<vscale x 4 x float> %v0, <vscale x 4 x float> %v1, <vscale x 4 x float> %v2, <vscale x 4 x i1> %pred, <vscale x 4 x float>* %addr) { define void @st3w_f32(<vscale x 4 x float> %v0, <vscale x 4 x float> %v1, <vscale x 4 x float> %v2, <vscale x 4 x i1> %pred, <vscale x 4 x float>* %addr) {
; CHECK-LABEL: st3w_f32: ; CHECK-LABEL: st3w_f32:
; CHECK: st3w { z0.s, z1.s, z2.s }, p0, [x0, #15, mul vl] ; CHECK: st3w { z0.s, z1.s, z2.s }, p0, [x0, #15, mul vl]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%base = getelementptr <vscale x 4 x float>, <vscale x 4 x float>* %addr, i64 15 %base = getelementptr <vscale x 4 x float>, <vscale x 4 x float>* %addr, i64 15, i64 0
call void @llvm.aarch64.sve.st3.nxv4f32(<vscale x 4 x float> %v0, call void @llvm.aarch64.sve.st3.nxv4f32(<vscale x 4 x float> %v0,
<vscale x 4 x float> %v1, <vscale x 4 x float> %v1,
<vscale x 4 x float> %v2, <vscale x 4 x float> %v2,
<vscale x 4 x i1> %pred, <vscale x 4 x i1> %pred,
<vscale x 4 x float>* %base) float* %base)
ret void ret void
} }
; ;
; ST3D ; ST3D
; ;
define void @st3d_i64(<vscale x 2 x i64> %v0, <vscale x 2 x i64> %v1, <vscale x 2 x i64> %v2, <vscale x 2 x i1> %pred, <vscale x 2 x i64>* %addr) { define void @st3d_i64(<vscale x 2 x i64> %v0, <vscale x 2 x i64> %v1, <vscale x 2 x i64> %v2, <vscale x 2 x i1> %pred, <vscale x 2 x i64>* %addr) {
; CHECK-LABEL: st3d_i64: ; CHECK-LABEL: st3d_i64:
; CHECK: st3d { z0.d, z1.d, z2.d }, p0, [x0, #18, mul vl] ; CHECK: st3d { z0.d, z1.d, z2.d }, p0, [x0, #18, mul vl]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%base = getelementptr <vscale x 2 x i64>, <vscale x 2 x i64>* %addr, i64 18 %base = getelementptr <vscale x 2 x i64>, <vscale x 2 x i64>* %addr, i64 18, i64 0
call void @llvm.aarch64.sve.st3.nxv2i64(<vscale x 2 x i64> %v0, call void @llvm.aarch64.sve.st3.nxv2i64(<vscale x 2 x i64> %v0,
<vscale x 2 x i64> %v1, <vscale x 2 x i64> %v1,
<vscale x 2 x i64> %v2, <vscale x 2 x i64> %v2,
<vscale x 2 x i1> %pred, <vscale x 2 x i1> %pred,
<vscale x 2 x i64>* %base) i64* %base)
ret void ret void
} }
define void @st3d_f64(<vscale x 2 x double> %v0, <vscale x 2 x double> %v1, <vscale x 2 x double> %v2, <vscale x 2 x i1> %pred, <vscale x 2 x double>* %addr) { define void @st3d_f64(<vscale x 2 x double> %v0, <vscale x 2 x double> %v1, <vscale x 2 x double> %v2, <vscale x 2 x i1> %pred, <vscale x 2 x double>* %addr) {
; CHECK-LABEL: st3d_f64: ; CHECK-LABEL: st3d_f64:
; CHECK: st3d { z0.d, z1.d, z2.d }, p0, [x0, #-3, mul vl] ; CHECK: st3d { z0.d, z1.d, z2.d }, p0, [x0, #-3, mul vl]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%base = getelementptr <vscale x 2 x double>, <vscale x 2 x double>* %addr, i64 -3 %base = getelementptr <vscale x 2 x double>, <vscale x 2 x double>* %addr, i64 -3, i64 0
call void @llvm.aarch64.sve.st3.nxv2f64(<vscale x 2 x double> %v0, call void @llvm.aarch64.sve.st3.nxv2f64(<vscale x 2 x double> %v0,
<vscale x 2 x double> %v1, <vscale x 2 x double> %v1,
<vscale x 2 x double> %v2, <vscale x 2 x double> %v2,
<vscale x 2 x i1> %pred, <vscale x 2 x i1> %pred,
<vscale x 2 x double>* %base) double* %base)
ret void ret void
} }
; ;
; ST4B ; ST4B
; ;
define void @st4b_i8_valid_imm(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i8> %v3, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) { define void @st4b_i8_valid_imm(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i8> %v3, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) {
; CHECK-LABEL: st4b_i8_valid_imm: ; CHECK-LABEL: st4b_i8_valid_imm:
; CHECK: st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, #4, mul vl] ; CHECK: st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, #4, mul vl]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 4 %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 4, i64 0
call void @llvm.aarch64.sve.st4.nxv16i8(<vscale x 16 x i8> %v0, call void @llvm.aarch64.sve.st4.nxv16i8(<vscale x 16 x i8> %v0,
<vscale x 16 x i8> %v1, <vscale x 16 x i8> %v1,
<vscale x 16 x i8> %v2, <vscale x 16 x i8> %v2,
<vscale x 16 x i8> %v3, <vscale x 16 x i8> %v3,
<vscale x 16 x i1> %pred, <vscale x 16 x i1> %pred,
<vscale x 16 x i8>* %base) i8* %base)
ret void ret void
} }
define void @st4b_i8_invalid_imm_not_multiple_of_4_01(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i8> %v3, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) { define void @st4b_i8_invalid_imm_not_multiple_of_4_01(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i8> %v3, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) {
; CHECK-LABEL: st4b_i8_invalid_imm_not_multiple_of_4_01: ; CHECK-LABEL: st4b_i8_invalid_imm_not_multiple_of_4_01:
; CHECK: rdvl x[[N:[0-9]+]], #5 ; CHECK: rdvl x[[N:[0-9]+]], #5
; CHECK-NEXT: st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, x[[N]]] ; CHECK-NEXT: st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, x[[N]]]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 5 %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 5, i64 0
call void @llvm.aarch64.sve.st4.nxv16i8(<vscale x 16 x i8> %v0, call void @llvm.aarch64.sve.st4.nxv16i8(<vscale x 16 x i8> %v0,
<vscale x 16 x i8> %v1, <vscale x 16 x i8> %v1,
<vscale x 16 x i8> %v2, <vscale x 16 x i8> %v2,
<vscale x 16 x i8> %v3, <vscale x 16 x i8> %v3,
<vscale x 16 x i1> %pred, <vscale x 16 x i1> %pred,
<vscale x 16 x i8>* %base) i8* %base)
ret void ret void
} }
define void @st4b_i8_invalid_imm_not_multiple_of_4_02(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i8> %v3, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) { define void @st4b_i8_invalid_imm_not_multiple_of_4_02(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i8> %v3, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) {
; CHECK-LABEL: st4b_i8_invalid_imm_not_multiple_of_4_02: ; CHECK-LABEL: st4b_i8_invalid_imm_not_multiple_of_4_02:
; CHECK: rdvl x[[N:[0-9]+]], #6 ; CHECK: rdvl x[[N:[0-9]+]], #6
; CHECK-NEXT: st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, x[[N]]] ; CHECK-NEXT: st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, x[[N]]]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 6 %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 6, i64 0
call void @llvm.aarch64.sve.st4.nxv16i8(<vscale x 16 x i8> %v0, call void @llvm.aarch64.sve.st4.nxv16i8(<vscale x 16 x i8> %v0,
<vscale x 16 x i8> %v1, <vscale x 16 x i8> %v1,
<vscale x 16 x i8> %v2, <vscale x 16 x i8> %v2,
<vscale x 16 x i8> %v3, <vscale x 16 x i8> %v3,
<vscale x 16 x i1> %pred, <vscale x 16 x i1> %pred,
<vscale x 16 x i8>* %base) i8* %base)
ret void ret void
} }
define void @st4b_i8_invalid_imm_not_multiple_of_4_03(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i8> %v3, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) { define void @st4b_i8_invalid_imm_not_multiple_of_4_03(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i8> %v3, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) {
; CHECK-LABEL: st4b_i8_invalid_imm_not_multiple_of_4_03: ; CHECK-LABEL: st4b_i8_invalid_imm_not_multiple_of_4_03:
; CHECK: rdvl x[[N:[0-9]+]], #7 ; CHECK: rdvl x[[N:[0-9]+]], #7
; CHECK-NEXT: st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, x[[N]]] ; CHECK-NEXT: st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, x[[N]]]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 7 %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 7, i64 0
call void @llvm.aarch64.sve.st4.nxv16i8(<vscale x 16 x i8> %v0, call void @llvm.aarch64.sve.st4.nxv16i8(<vscale x 16 x i8> %v0,
<vscale x 16 x i8> %v1, <vscale x 16 x i8> %v1,
<vscale x 16 x i8> %v2, <vscale x 16 x i8> %v2,
<vscale x 16 x i8> %v3, <vscale x 16 x i8> %v3,
<vscale x 16 x i1> %pred, <vscale x 16 x i1> %pred,
<vscale x 16 x i8>* %base) i8* %base)
ret void ret void
} }
define void @st4b_i8_invalid_imm_out_of_lower_bound(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i8> %v3, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) { define void @st4b_i8_invalid_imm_out_of_lower_bound(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i8> %v3, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) {
; CHECK-LABEL: st4b_i8_invalid_imm_out_of_lower_bound: ; CHECK-LABEL: st4b_i8_invalid_imm_out_of_lower_bound:
; FIXME: optimize OFFSET computation so that xOFFSET = (mul (RDVL #4) #9) ; FIXME: optimize OFFSET computation so that xOFFSET = (mul (RDVL #4) #9)
; xM = -9 * 2^6 ; xM = -9 * 2^6
; xP = RDVL * 2^-4 ; xP = RDVL * 2^-4
; xBASE = RDVL * 2^-4 * -9 * 2^6 = RDVL * -36 ; xBASE = RDVL * 2^-4 * -9 * 2^6 = RDVL * -36
; CHECK: rdvl x[[N:[0-9]+]], #1 ; CHECK: rdvl x[[N:[0-9]+]], #1
; CHECK-DAG: mov x[[M:[0-9]+]], #-576 ; CHECK-DAG: mov x[[M:[0-9]+]], #-576
; CHECK-DAG: lsr x[[P:[0-9]+]], x[[N]], #4 ; CHECK-DAG: lsr x[[P:[0-9]+]], x[[N]], #4
; CHECK-DAG: mul x[[OFFSET:[0-9]+]], x[[P]], x[[M]] ; CHECK-DAG: mul x[[OFFSET:[0-9]+]], x[[P]], x[[M]]
; CHECK-NEXT: st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, x[[OFFSET]]] ; CHECK-NEXT: st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, x[[OFFSET]]]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 -36 %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 -36, i64 0
call void @llvm.aarch64.sve.st4.nxv16i8(<vscale x 16 x i8> %v0, call void @llvm.aarch64.sve.st4.nxv16i8(<vscale x 16 x i8> %v0,
<vscale x 16 x i8> %v1, <vscale x 16 x i8> %v1,
<vscale x 16 x i8> %v2, <vscale x 16 x i8> %v2,
<vscale x 16 x i8> %v3, <vscale x 16 x i8> %v3,
<vscale x 16 x i1> %pred, <vscale x 16 x i1> %pred,
<vscale x 16 x i8>* %base) i8* %base)
ret void ret void
} }
define void @st4b_i8_invalid_imm_out_of_upper_bound(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i8> %v3, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) { define void @st4b_i8_invalid_imm_out_of_upper_bound(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i8> %v3, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) {
; CHECK-LABEL: st4b_i8_invalid_imm_out_of_upper_bound: ; CHECK-LABEL: st4b_i8_invalid_imm_out_of_upper_bound:
; FIXME: optimize OFFSET computation so that xOFFSET = (shl (RDVL #16) #1) ; FIXME: optimize OFFSET computation so that xOFFSET = (shl (RDVL #16) #1)
; xM = 2^9 ; xM = 2^9
; xP = RDVL * 2^-4 ; xP = RDVL * 2^-4
; xOFFSET = RDVL * 2^-4 * 2^9 = RDVL * 32 ; xOFFSET = RDVL * 2^-4 * 2^9 = RDVL * 32
; CHECK: rdvl x[[N:[0-9]+]], #1 ; CHECK: rdvl x[[N:[0-9]+]], #1
; CHECK-DAG: mov w[[M:[0-9]+]], #512 ; CHECK-DAG: mov w[[M:[0-9]+]], #512
; CHECK-DAG: lsr x[[P:[0-9]+]], x[[N]], #4 ; CHECK-DAG: lsr x[[P:[0-9]+]], x[[N]], #4
; CHECK-DAG: mul x[[OFFSET:[0-9]+]], x[[P]], x[[M]] ; CHECK-DAG: mul x[[OFFSET:[0-9]+]], x[[P]], x[[M]]
; CHECK-NEXT: st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, x[[OFFSET]]] ; CHECK-NEXT: st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, x[[OFFSET]]]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 32 %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 32, i64 0
call void @llvm.aarch64.sve.st4.nxv16i8(<vscale x 16 x i8> %v0, call void @llvm.aarch64.sve.st4.nxv16i8(<vscale x 16 x i8> %v0,
<vscale x 16 x i8> %v1, <vscale x 16 x i8> %v1,
<vscale x 16 x i8> %v2, <vscale x 16 x i8> %v2,
<vscale x 16 x i8> %v3, <vscale x 16 x i8> %v3,
<vscale x 16 x i1> %pred, <vscale x 16 x i1> %pred,
<vscale x 16 x i8>* %base) i8* %base)
ret void ret void
} }
define void @st4b_i8_valid_imm_lower_bound(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i8> %v3, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) { define void @st4b_i8_valid_imm_lower_bound(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i8> %v3, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) {
; CHECK-LABEL: st4b_i8_valid_imm_lower_bound: ; CHECK-LABEL: st4b_i8_valid_imm_lower_bound:
; CHECK: st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, #-32, mul vl] ; CHECK: st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, #-32, mul vl]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 -32 %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 -32, i64 0
call void @llvm.aarch64.sve.st4.nxv16i8(<vscale x 16 x i8> %v0, call void @llvm.aarch64.sve.st4.nxv16i8(<vscale x 16 x i8> %v0,
<vscale x 16 x i8> %v1, <vscale x 16 x i8> %v1,
<vscale x 16 x i8> %v2, <vscale x 16 x i8> %v2,
<vscale x 16 x i8> %v3, <vscale x 16 x i8> %v3,
<vscale x 16 x i1> %pred, <vscale x 16 x i1> %pred,
<vscale x 16 x i8>* %base) i8* %base)
ret void ret void
} }
define void @st4b_i8_valid_imm_upper_bound(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i8> %v3, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) { define void @st4b_i8_valid_imm_upper_bound(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i8> %v3, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) {
; CHECK-LABEL: st4b_i8_valid_imm_upper_bound: ; CHECK-LABEL: st4b_i8_valid_imm_upper_bound:
; CHECK: st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, #28, mul vl] ; CHECK: st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, #28, mul vl]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 28 %base = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %addr, i64 28, i64 0
call void @llvm.aarch64.sve.st4.nxv16i8(<vscale x 16 x i8> %v0, call void @llvm.aarch64.sve.st4.nxv16i8(<vscale x 16 x i8> %v0,
<vscale x 16 x i8> %v1, <vscale x 16 x i8> %v1,
<vscale x 16 x i8> %v2, <vscale x 16 x i8> %v2,
<vscale x 16 x i8> %v3, <vscale x 16 x i8> %v3,
<vscale x 16 x i1> %pred, <vscale x 16 x i1> %pred,
<vscale x 16 x i8>* %base) i8* %base)
ret void ret void
} }
; ;
; ST4H ; ST4H
; ;
define void @st4h_i16(<vscale x 8 x i16> %v0, <vscale x 8 x i16> %v1, <vscale x 8 x i16> %v2, <vscale x 8 x i16> %v3, <vscale x 8 x i1> %pred, <vscale x 8 x i16>* %addr) { define void @st4h_i16(<vscale x 8 x i16> %v0, <vscale x 8 x i16> %v1, <vscale x 8 x i16> %v2, <vscale x 8 x i16> %v3, <vscale x 8 x i1> %pred, <vscale x 8 x i16>* %addr) {
; CHECK-LABEL: st4h_i16: ; CHECK-LABEL: st4h_i16:
; CHECK: st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, #8, mul vl] ; CHECK: st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, #8, mul vl]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%base = getelementptr <vscale x 8 x i16>, <vscale x 8 x i16>* %addr, i64 8 %base = getelementptr <vscale x 8 x i16>, <vscale x 8 x i16>* %addr, i64 8, i64 0
call void @llvm.aarch64.sve.st4.nxv8i16(<vscale x 8 x i16> %v0, call void @llvm.aarch64.sve.st4.nxv8i16(<vscale x 8 x i16> %v0,
<vscale x 8 x i16> %v1, <vscale x 8 x i16> %v1,
<vscale x 8 x i16> %v2, <vscale x 8 x i16> %v2,
<vscale x 8 x i16> %v3, <vscale x 8 x i16> %v3,
<vscale x 8 x i1> %pred, <vscale x 8 x i1> %pred,
<vscale x 8 x i16>* %base) i16* %base)
ret void ret void
} }
define void @st4h_f16(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1, <vscale x 8 x half> %v2, <vscale x 8 x half> %v3, <vscale x 8 x i1> %pred, <vscale x 8 x half>* %addr) { define void @st4h_f16(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1, <vscale x 8 x half> %v2, <vscale x 8 x half> %v3, <vscale x 8 x i1> %pred, <vscale x 8 x half>* %addr) {
; CHECK-LABEL: st4h_f16: ; CHECK-LABEL: st4h_f16:
; CHECK: st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, #12, mul vl] ; CHECK: st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, #12, mul vl]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%base = getelementptr <vscale x 8 x half>, <vscale x 8 x half>* %addr, i64 12 %base = getelementptr <vscale x 8 x half>, <vscale x 8 x half>* %addr, i64 12, i64 0
call void @llvm.aarch64.sve.st4.nxv8f16(<vscale x 8 x half> %v0, call void @llvm.aarch64.sve.st4.nxv8f16(<vscale x 8 x half> %v0,
<vscale x 8 x half> %v1, <vscale x 8 x half> %v1,
<vscale x 8 x half> %v2, <vscale x 8 x half> %v2,
<vscale x 8 x half> %v3, <vscale x 8 x half> %v3,
<vscale x 8 x i1> %pred, <vscale x 8 x i1> %pred,
<vscale x 8 x half>* %base) half* %base)
ret void ret void
} }
; ;
; ST4W ; ST4W
; ;
define void @st4w_i32(<vscale x 4 x i32> %v0, <vscale x 4 x i32> %v1, <vscale x 4 x i32> %v2, <vscale x 4 x i32> %v3, <vscale x 4 x i1> %pred, <vscale x 4 x i32>* %addr) { define void @st4w_i32(<vscale x 4 x i32> %v0, <vscale x 4 x i32> %v1, <vscale x 4 x i32> %v2, <vscale x 4 x i32> %v3, <vscale x 4 x i1> %pred, <vscale x 4 x i32>* %addr) {
; CHECK-LABEL: st4w_i32: ; CHECK-LABEL: st4w_i32:
; CHECK: st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, #16, mul vl] ; CHECK: st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, #16, mul vl]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%base = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* %addr, i64 16 %base = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* %addr, i64 16, i64 0
call void @llvm.aarch64.sve.st4.nxv4i32(<vscale x 4 x i32> %v0, call void @llvm.aarch64.sve.st4.nxv4i32(<vscale x 4 x i32> %v0,
<vscale x 4 x i32> %v1, <vscale x 4 x i32> %v1,
<vscale x 4 x i32> %v2, <vscale x 4 x i32> %v2,
<vscale x 4 x i32> %v3, <vscale x 4 x i32> %v3,
<vscale x 4 x i1> %pred, <vscale x 4 x i1> %pred,
<vscale x 4 x i32>* %base) i32* %base)
ret void ret void
} }
define void @st4w_f32(<vscale x 4 x float> %v0, <vscale x 4 x float> %v1, <vscale x 4 x float> %v2, <vscale x 4 x float> %v3, <vscale x 4 x i1> %pred, <vscale x 4 x float>* %addr) { define void @st4w_f32(<vscale x 4 x float> %v0, <vscale x 4 x float> %v1, <vscale x 4 x float> %v2, <vscale x 4 x float> %v3, <vscale x 4 x i1> %pred, <vscale x 4 x float>* %addr) {
; CHECK-LABEL: st4w_f32: ; CHECK-LABEL: st4w_f32:
; CHECK: st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, #20, mul vl] ; CHECK: st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, #20, mul vl]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%base = getelementptr <vscale x 4 x float>, <vscale x 4 x float>* %addr, i64 20 %base = getelementptr <vscale x 4 x float>, <vscale x 4 x float>* %addr, i64 20, i64 0
call void @llvm.aarch64.sve.st4.nxv4f32(<vscale x 4 x float> %v0, call void @llvm.aarch64.sve.st4.nxv4f32(<vscale x 4 x float> %v0,
<vscale x 4 x float> %v1, <vscale x 4 x float> %v1,
<vscale x 4 x float> %v2, <vscale x 4 x float> %v2,
<vscale x 4 x float> %v3, <vscale x 4 x float> %v3,
<vscale x 4 x i1> %pred, <vscale x 4 x i1> %pred,
<vscale x 4 x float>* %base) float* %base)
ret void ret void
} }
; ;
; ST4D ; ST4D
; ;
define void @st4d_i64(<vscale x 2 x i64> %v0, <vscale x 2 x i64> %v1, <vscale x 2 x i64> %v2, <vscale x 2 x i64> %v3, <vscale x 2 x i1> %pred, <vscale x 2 x i64>* %addr) { define void @st4d_i64(<vscale x 2 x i64> %v0, <vscale x 2 x i64> %v1, <vscale x 2 x i64> %v2, <vscale x 2 x i64> %v3, <vscale x 2 x i1> %pred, <vscale x 2 x i64>* %addr) {
; CHECK-LABEL: st4d_i64: ; CHECK-LABEL: st4d_i64:
; CHECK: st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0, #24, mul vl] ; CHECK: st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0, #24, mul vl]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%base = getelementptr <vscale x 2 x i64>, <vscale x 2 x i64>* %addr, i64 24 %base = getelementptr <vscale x 2 x i64>, <vscale x 2 x i64>* %addr, i64 24, i64 0
call void @llvm.aarch64.sve.st4.nxv2i64(<vscale x 2 x i64> %v0, call void @llvm.aarch64.sve.st4.nxv2i64(<vscale x 2 x i64> %v0,
<vscale x 2 x i64> %v1, <vscale x 2 x i64> %v1,
<vscale x 2 x i64> %v2, <vscale x 2 x i64> %v2,
<vscale x 2 x i64> %v3, <vscale x 2 x i64> %v3,
<vscale x 2 x i1> %pred, <vscale x 2 x i1> %pred,
<vscale x 2 x i64>* %base) i64* %base)
ret void ret void
} }
define void @st4d_f64(<vscale x 2 x double> %v0, <vscale x 2 x double> %v1, <vscale x 2 x double> %v2, <vscale x 2 x double> %v3, <vscale x 2 x i1> %pred, <vscale x 2 x double>* %addr) { define void @st4d_f64(<vscale x 2 x double> %v0, <vscale x 2 x double> %v1, <vscale x 2 x double> %v2, <vscale x 2 x double> %v3, <vscale x 2 x i1> %pred, <vscale x 2 x double>* %addr) {
; CHECK-LABEL: st4d_f64: ; CHECK-LABEL: st4d_f64:
; CHECK: st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0, #28, mul vl] ; CHECK: st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0, #28, mul vl]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%base = getelementptr <vscale x 2 x double>, <vscale x 2 x double>* %addr, i64 28 %base = getelementptr <vscale x 2 x double>, <vscale x 2 x double>* %addr, i64 28, i64 0
call void @llvm.aarch64.sve.st4.nxv2f64(<vscale x 2 x double> %v0, call void @llvm.aarch64.sve.st4.nxv2f64(<vscale x 2 x double> %v0,
<vscale x 2 x double> %v1, <vscale x 2 x double> %v1,
<vscale x 2 x double> %v2, <vscale x 2 x double> %v2,
<vscale x 2 x double> %v3, <vscale x 2 x double> %v3,
<vscale x 2 x i1> %pred, <vscale x 2 x i1> %pred,
<vscale x 2 x double>* %base) double* %base)
ret void ret void
} }
declare void @llvm.aarch64.sve.st2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>*) declare void @llvm.aarch64.sve.st2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i1>, i8*)
declare void @llvm.aarch64.sve.st2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>*) declare void @llvm.aarch64.sve.st2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i1>, i16*)
declare void @llvm.aarch64.sve.st2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>*) declare void @llvm.aarch64.sve.st2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, i32*)
declare void @llvm.aarch64.sve.st2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>*) declare void @llvm.aarch64.sve.st2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i1>, i64*)
declare void @llvm.aarch64.sve.st2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>*) declare void @llvm.aarch64.sve.st2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, half*)
declare void @llvm.aarch64.sve.st2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>*) declare void @llvm.aarch64.sve.st2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i1>, float*)
declare void @llvm.aarch64.sve.st2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>*) declare void @llvm.aarch64.sve.st2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x i1>, double*)
declare void @llvm.aarch64.sve.st3.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>*) declare void @llvm.aarch64.sve.st3.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i1>, i8*)
declare void @llvm.aarch64.sve.st3.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>*) declare void @llvm.aarch64.sve.st3.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i1>, i16*)
declare void @llvm.aarch64.sve.st3.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>*) declare void @llvm.aarch64.sve.st3.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, i32*)
declare void @llvm.aarch64.sve.st3.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>*) declare void @llvm.aarch64.sve.st3.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i1>, i64*)
declare void @llvm.aarch64.sve.st3.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>*) declare void @llvm.aarch64.sve.st3.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, half*)
declare void @llvm.aarch64.sve.st3.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>*) declare void @llvm.aarch64.sve.st3.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i1>, float*)
declare void @llvm.aarch64.sve.st3.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>*) declare void @llvm.aarch64.sve.st3.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x i1>, double*)
declare void @llvm.aarch64.sve.st4.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>*) declare void @llvm.aarch64.sve.st4.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i1>, i8*)
declare void @llvm.aarch64.sve.st4.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>*) declare void @llvm.aarch64.sve.st4.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i1>, i16*)
declare void @llvm.aarch64.sve.st4.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>*) declare void @llvm.aarch64.sve.st4.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, i32*)
declare void @llvm.aarch64.sve.st4.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>*) declare void @llvm.aarch64.sve.st4.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i1>, i64*)
declare void @llvm.aarch64.sve.st4.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>*) declare void @llvm.aarch64.sve.st4.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, half*)
declare void @llvm.aarch64.sve.st4.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>*) declare void @llvm.aarch64.sve.st4.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i1>, float*)
declare void @llvm.aarch64.sve.st4.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>*) declare void @llvm.aarch64.sve.st4.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x i1>, double*)

llvm/test/CodeGen/AArch64/sve-intrinsics-stN-reg-reg-addr-mode.ll

; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -asm-verbose=0 < %s | FileCheck %s ; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -asm-verbose=0 < %s | FileCheck %s
; ;
; ST2B ; ST2B
; ;
define void @st2b_i8(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i1> %pred, i8* %addr, i64 %offset) { define void @st2b_i8(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i1> %pred, i8* %addr, i64 %offset) {
; CHECK-LABEL: st2b_i8: ; CHECK-LABEL: st2b_i8:
; CHECK: st2b { z0.b, z1.b }, p0, [x0, x1] ; CHECK: st2b { z0.b, z1.b }, p0, [x0, x1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = getelementptr i8, i8* %addr, i64 %offset %1 = getelementptr i8, i8* %addr, i64 %offset
%base = bitcast i8* %1 to <vscale x 16 x i8>*
call void @llvm.aarch64.sve.st2.nxv16i8(<vscale x 16 x i8> %v0, call void @llvm.aarch64.sve.st2.nxv16i8(<vscale x 16 x i8> %v0,
<vscale x 16 x i8> %v1, <vscale x 16 x i8> %v1,
<vscale x 16 x i1> %pred, <vscale x 16 x i1> %pred,
<vscale x 16 x i8>* %base) i8* %1)
ret void ret void
} }
; ;
; ST2H ; ST2H
; ;
define void @st2h_i16(<vscale x 8 x i16> %v0, <vscale x 8 x i16> %v1, <vscale x 8 x i1> %pred, i16* %addr, i64 %offset) { define void @st2h_i16(<vscale x 8 x i16> %v0, <vscale x 8 x i16> %v1, <vscale x 8 x i1> %pred, i16* %addr, i64 %offset) {
; CHECK-LABEL: st2h_i16: ; CHECK-LABEL: st2h_i16:
; CHECK: st2h { z0.h, z1.h }, p0, [x0, x1, lsl #1] ; CHECK: st2h { z0.h, z1.h }, p0, [x0, x1, lsl #1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = getelementptr i16, i16* %addr, i64 %offset %1 = getelementptr i16, i16* %addr, i64 %offset
%base = bitcast i16* %1 to <vscale x 8 x i16>*
call void @llvm.aarch64.sve.st2.nxv8i16(<vscale x 8 x i16> %v0, call void @llvm.aarch64.sve.st2.nxv8i16(<vscale x 8 x i16> %v0,
<vscale x 8 x i16> %v1, <vscale x 8 x i16> %v1,
<vscale x 8 x i1> %pred, <vscale x 8 x i1> %pred,
<vscale x 8 x i16>* %base) i16* %1)
ret void ret void
} }
define void @st2h_f16(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1, <vscale x 8 x i1> %pred, half* %addr, i64 %offset) { define void @st2h_f16(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1, <vscale x 8 x i1> %pred, half* %addr, i64 %offset) {
; CHECK-LABEL: st2h_f16: ; CHECK-LABEL: st2h_f16:
; CHECK: st2h { z0.h, z1.h }, p0, [x0, x1, lsl #1] ; CHECK: st2h { z0.h, z1.h }, p0, [x0, x1, lsl #1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = getelementptr half, half* %addr, i64 %offset %1 = getelementptr half, half* %addr, i64 %offset
%base = bitcast half* %1 to <vscale x 8 x half>*
call void @llvm.aarch64.sve.st2.nxv8f16(<vscale x 8 x half> %v0, call void @llvm.aarch64.sve.st2.nxv8f16(<vscale x 8 x half> %v0,
<vscale x 8 x half> %v1, <vscale x 8 x half> %v1,
<vscale x 8 x i1> %pred, <vscale x 8 x i1> %pred,
<vscale x 8 x half>* %base) half* %1)
ret void ret void
} }
; ;
; ST2W ; ST2W
; ;
define void @st2w_i32(<vscale x 4 x i32> %v0, <vscale x 4 x i32> %v1, <vscale x 4 x i1> %pred, i32* %addr, i64 %offset) { define void @st2w_i32(<vscale x 4 x i32> %v0, <vscale x 4 x i32> %v1, <vscale x 4 x i1> %pred, i32* %addr, i64 %offset) {
; CHECK-LABEL: st2w_i32: ; CHECK-LABEL: st2w_i32:
; CHECK: st2w { z0.s, z1.s }, p0, [x0, x1, lsl #2] ; CHECK: st2w { z0.s, z1.s }, p0, [x0, x1, lsl #2]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = getelementptr i32, i32* %addr, i64 %offset %1 = getelementptr i32, i32* %addr, i64 %offset
%base = bitcast i32* %1 to <vscale x 4 x i32>*
call void @llvm.aarch64.sve.st2.nxv4i32(<vscale x 4 x i32> %v0, call void @llvm.aarch64.sve.st2.nxv4i32(<vscale x 4 x i32> %v0,
<vscale x 4 x i32> %v1, <vscale x 4 x i32> %v1,
<vscale x 4 x i1> %pred, <vscale x 4 x i1> %pred,
<vscale x 4 x i32>* %base) i32* %1)
ret void ret void
} }
define void @st2w_f32(<vscale x 4 x float> %v0, <vscale x 4 x float> %v1, <vscale x 4 x i1> %pred, float* %addr, i64 %offset) { define void @st2w_f32(<vscale x 4 x float> %v0, <vscale x 4 x float> %v1, <vscale x 4 x i1> %pred, float* %addr, i64 %offset) {
; CHECK-LABEL: st2w_f32: ; CHECK-LABEL: st2w_f32:
; CHECK: st2w { z0.s, z1.s }, p0, [x0, x1, lsl #2] ; CHECK: st2w { z0.s, z1.s }, p0, [x0, x1, lsl #2]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = getelementptr float, float* %addr, i64 %offset %1 = getelementptr float, float* %addr, i64 %offset
%base = bitcast float* %1 to <vscale x 4 x float>*
call void @llvm.aarch64.sve.st2.nxv4f32(<vscale x 4 x float> %v0, call void @llvm.aarch64.sve.st2.nxv4f32(<vscale x 4 x float> %v0,
<vscale x 4 x float> %v1, <vscale x 4 x float> %v1,
<vscale x 4 x i1> %pred, <vscale x 4 x i1> %pred,
<vscale x 4 x float>* %base) float* %1)
ret void ret void
} }
; ;
; ST2D ; ST2D
; ;
define void @st2d_i64(<vscale x 2 x i64> %v0, <vscale x 2 x i64> %v1, <vscale x 2 x i1> %pred, i64* %addr, i64 %offset) { define void @st2d_i64(<vscale x 2 x i64> %v0, <vscale x 2 x i64> %v1, <vscale x 2 x i1> %pred, i64* %addr, i64 %offset) {
; CHECK-LABEL: st2d_i64: ; CHECK-LABEL: st2d_i64:
; CHECK: st2d { z0.d, z1.d }, p0, [x0, x1, lsl #3] ; CHECK: st2d { z0.d, z1.d }, p0, [x0, x1, lsl #3]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = getelementptr i64, i64* %addr, i64 %offset %1 = getelementptr i64, i64* %addr, i64 %offset
%base = bitcast i64* %1 to <vscale x 2 x i64>*
call void @llvm.aarch64.sve.st2.nxv2i64(<vscale x 2 x i64> %v0, call void @llvm.aarch64.sve.st2.nxv2i64(<vscale x 2 x i64> %v0,
<vscale x 2 x i64> %v1, <vscale x 2 x i64> %v1,
<vscale x 2 x i1> %pred, <vscale x 2 x i1> %pred,
<vscale x 2 x i64>* %base) i64* %1)
ret void ret void
} }
define void @st2d_f64(<vscale x 2 x double> %v0, <vscale x 2 x double> %v1, <vscale x 2 x i1> %pred, double* %addr, i64 %offset) { define void @st2d_f64(<vscale x 2 x double> %v0, <vscale x 2 x double> %v1, <vscale x 2 x i1> %pred, double* %addr, i64 %offset) {
; CHECK-LABEL: st2d_f64: ; CHECK-LABEL: st2d_f64:
; CHECK: st2d { z0.d, z1.d }, p0, [x0, x1, lsl #3] ; CHECK: st2d { z0.d, z1.d }, p0, [x0, x1, lsl #3]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = getelementptr double, double* %addr, i64 %offset %1 = getelementptr double, double* %addr, i64 %offset
%base = bitcast double* %1 to <vscale x 2 x double>*
call void @llvm.aarch64.sve.st2.nxv2f64(<vscale x 2 x double> %v0, call void @llvm.aarch64.sve.st2.nxv2f64(<vscale x 2 x double> %v0,
<vscale x 2 x double> %v1, <vscale x 2 x double> %v1,
<vscale x 2 x i1> %pred, <vscale x 2 x i1> %pred,
<vscale x 2 x double>* %base) double* %1)
ret void ret void
} }
; ;
; ST3B ; ST3B
; ;
define void @st3b_i8(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i1> %pred, i8* %addr, i64 %offset) { define void @st3b_i8(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i1> %pred, i8* %addr, i64 %offset) {
; CHECK-LABEL: st3b_i8: ; CHECK-LABEL: st3b_i8:
; CHECK: st3b { z0.b, z1.b, z2.b }, p0, [x0, x1] ; CHECK: st3b { z0.b, z1.b, z2.b }, p0, [x0, x1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = getelementptr i8, i8* %addr, i64 %offset %1 = getelementptr i8, i8* %addr, i64 %offset
%base = bitcast i8* %1 to <vscale x 16 x i8>*
call void @llvm.aarch64.sve.st3.nxv16i8(<vscale x 16 x i8> %v0, call void @llvm.aarch64.sve.st3.nxv16i8(<vscale x 16 x i8> %v0,
<vscale x 16 x i8> %v1, <vscale x 16 x i8> %v1,
<vscale x 16 x i8> %v2, <vscale x 16 x i8> %v2,
<vscale x 16 x i1> %pred, <vscale x 16 x i1> %pred,
<vscale x 16 x i8>* %base) i8* %1)
ret void ret void
} }
; ;
; ST3H ; ST3H
; ;
define void @st3h_i16(<vscale x 8 x i16> %v0, <vscale x 8 x i16> %v1, <vscale x 8 x i16> %v2, <vscale x 8 x i1> %pred, i16* %addr, i64 %offset) { define void @st3h_i16(<vscale x 8 x i16> %v0, <vscale x 8 x i16> %v1, <vscale x 8 x i16> %v2, <vscale x 8 x i1> %pred, i16* %addr, i64 %offset) {
; CHECK-LABEL: st3h_i16: ; CHECK-LABEL: st3h_i16:
; CHECK: st3h { z0.h, z1.h, z2.h }, p0, [x0, x1, lsl #1] ; CHECK: st3h { z0.h, z1.h, z2.h }, p0, [x0, x1, lsl #1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = getelementptr i16, i16* %addr, i64 %offset %1 = getelementptr i16, i16* %addr, i64 %offset
%base = bitcast i16* %1 to <vscale x 8 x i16>*
call void @llvm.aarch64.sve.st3.nxv8i16(<vscale x 8 x i16> %v0, call void @llvm.aarch64.sve.st3.nxv8i16(<vscale x 8 x i16> %v0,
<vscale x 8 x i16> %v1, <vscale x 8 x i16> %v1,
<vscale x 8 x i16> %v2, <vscale x 8 x i16> %v2,
<vscale x 8 x i1> %pred, <vscale x 8 x i1> %pred,
<vscale x 8 x i16>* %base) i16* %1)
ret void ret void
} }
define void @st3h_f16(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1, <vscale x 8 x half> %v2, <vscale x 8 x i1> %pred, half* %addr, i64 %offset) { define void @st3h_f16(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1, <vscale x 8 x half> %v2, <vscale x 8 x i1> %pred, half* %addr, i64 %offset) {
; CHECK-LABEL: st3h_f16: ; CHECK-LABEL: st3h_f16:
; CHECK: st3h { z0.h, z1.h, z2.h }, p0, [x0, x1, lsl #1] ; CHECK: st3h { z0.h, z1.h, z2.h }, p0, [x0, x1, lsl #1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = getelementptr half, half* %addr, i64 %offset %1 = getelementptr half, half* %addr, i64 %offset
%base = bitcast half* %1 to <vscale x 8 x half>*
call void @llvm.aarch64.sve.st3.nxv8f16(<vscale x 8 x half> %v0, call void @llvm.aarch64.sve.st3.nxv8f16(<vscale x 8 x half> %v0,
<vscale x 8 x half> %v1, <vscale x 8 x half> %v1,
<vscale x 8 x half> %v2, <vscale x 8 x half> %v2,
<vscale x 8 x i1> %pred, <vscale x 8 x i1> %pred,
<vscale x 8 x half>* %base) half* %1)
ret void ret void
} }
; ;
; ST3W ; ST3W
; ;
define void @st3w_i32(<vscale x 4 x i32> %v0, <vscale x 4 x i32> %v1, <vscale x 4 x i32> %v2, <vscale x 4 x i1> %pred, i32* %addr, i64 %offset) { define void @st3w_i32(<vscale x 4 x i32> %v0, <vscale x 4 x i32> %v1, <vscale x 4 x i32> %v2, <vscale x 4 x i1> %pred, i32* %addr, i64 %offset) {
; CHECK-LABEL: st3w_i32: ; CHECK-LABEL: st3w_i32:
; CHECK: st3w { z0.s, z1.s, z2.s }, p0, [x0, x1, lsl #2] ; CHECK: st3w { z0.s, z1.s, z2.s }, p0, [x0, x1, lsl #2]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = getelementptr i32, i32* %addr, i64 %offset %1 = getelementptr i32, i32* %addr, i64 %offset
%base = bitcast i32* %1 to <vscale x 4 x i32>*
call void @llvm.aarch64.sve.st3.nxv4i32(<vscale x 4 x i32> %v0, call void @llvm.aarch64.sve.st3.nxv4i32(<vscale x 4 x i32> %v0,
<vscale x 4 x i32> %v1, <vscale x 4 x i32> %v1,
<vscale x 4 x i32> %v2, <vscale x 4 x i32> %v2,
<vscale x 4 x i1> %pred, <vscale x 4 x i1> %pred,
<vscale x 4 x i32>* %base) i32* %1)
ret void ret void
} }
define void @st3w_f32(<vscale x 4 x float> %v0, <vscale x 4 x float> %v1, <vscale x 4 x float> %v2, <vscale x 4 x i1> %pred, float* %addr, i64 %offset) { define void @st3w_f32(<vscale x 4 x float> %v0, <vscale x 4 x float> %v1, <vscale x 4 x float> %v2, <vscale x 4 x i1> %pred, float* %addr, i64 %offset) {
; CHECK-LABEL: st3w_f32: ; CHECK-LABEL: st3w_f32:
; CHECK: st3w { z0.s, z1.s, z2.s }, p0, [x0, x1, lsl #2] ; CHECK: st3w { z0.s, z1.s, z2.s }, p0, [x0, x1, lsl #2]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = getelementptr float, float* %addr, i64 %offset %1 = getelementptr float, float* %addr, i64 %offset
%base = bitcast float* %1 to <vscale x 4 x float>*
call void @llvm.aarch64.sve.st3.nxv4f32(<vscale x 4 x float> %v0, call void @llvm.aarch64.sve.st3.nxv4f32(<vscale x 4 x float> %v0,
<vscale x 4 x float> %v1, <vscale x 4 x float> %v1,
<vscale x 4 x float> %v2, <vscale x 4 x float> %v2,
<vscale x 4 x i1> %pred, <vscale x 4 x i1> %pred,
<vscale x 4 x float>* %base) float* %1)
ret void ret void
} }
; ;
; ST3D ; ST3D
; ;
define void @st3d_i64(<vscale x 2 x i64> %v0, <vscale x 2 x i64> %v1, <vscale x 2 x i64> %v2, <vscale x 2 x i1> %pred, i64* %addr, i64 %offset) { define void @st3d_i64(<vscale x 2 x i64> %v0, <vscale x 2 x i64> %v1, <vscale x 2 x i64> %v2, <vscale x 2 x i1> %pred, i64* %addr, i64 %offset) {
; CHECK-LABEL: st3d_i64: ; CHECK-LABEL: st3d_i64:
; CHECK: st3d { z0.d, z1.d, z2.d }, p0, [x0, x1, lsl #3] ; CHECK: st3d { z0.d, z1.d, z2.d }, p0, [x0, x1, lsl #3]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = getelementptr i64, i64* %addr, i64 %offset %1 = getelementptr i64, i64* %addr, i64 %offset
%base = bitcast i64* %1 to <vscale x 2 x i64>*
call void @llvm.aarch64.sve.st3.nxv2i64(<vscale x 2 x i64> %v0, call void @llvm.aarch64.sve.st3.nxv2i64(<vscale x 2 x i64> %v0,
<vscale x 2 x i64> %v1, <vscale x 2 x i64> %v1,
<vscale x 2 x i64> %v2, <vscale x 2 x i64> %v2,
<vscale x 2 x i1> %pred, <vscale x 2 x i1> %pred,
<vscale x 2 x i64>* %base) i64* %1)
ret void ret void
} }
define void @st3d_f64(<vscale x 2 x double> %v0, <vscale x 2 x double> %v1, <vscale x 2 x double> %v2, <vscale x 2 x i1> %pred, double* %addr, i64 %offset) { define void @st3d_f64(<vscale x 2 x double> %v0, <vscale x 2 x double> %v1, <vscale x 2 x double> %v2, <vscale x 2 x i1> %pred, double* %addr, i64 %offset) {
; CHECK-LABEL: st3d_f64: ; CHECK-LABEL: st3d_f64:
; CHECK: st3d { z0.d, z1.d, z2.d }, p0, [x0, x1, lsl #3] ; CHECK: st3d { z0.d, z1.d, z2.d }, p0, [x0, x1, lsl #3]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = getelementptr double, double* %addr, i64 %offset %1 = getelementptr double, double* %addr, i64 %offset
%base = bitcast double* %1 to <vscale x 2 x double>*
call void @llvm.aarch64.sve.st3.nxv2f64(<vscale x 2 x double> %v0, call void @llvm.aarch64.sve.st3.nxv2f64(<vscale x 2 x double> %v0,
<vscale x 2 x double> %v1, <vscale x 2 x double> %v1,
<vscale x 2 x double> %v2, <vscale x 2 x double> %v2,
<vscale x 2 x i1> %pred, <vscale x 2 x i1> %pred,
<vscale x 2 x double>* %base) double* %1)
ret void ret void
} }
; ;
; ST4B ; ST4B
; ;
define void @st4b_i8(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i8> %v3, <vscale x 16 x i1> %pred, i8* %addr, i64 %offset) { define void @st4b_i8(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i8> %v3, <vscale x 16 x i1> %pred, i8* %addr, i64 %offset) {
; CHECK-LABEL: st4b_i8: ; CHECK-LABEL: st4b_i8:
; CHECK: st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, x1] ; CHECK: st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0, x1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = getelementptr i8, i8* %addr, i64 %offset %1 = getelementptr i8, i8* %addr, i64 %offset
%base = bitcast i8* %1 to <vscale x 16 x i8>*
call void @llvm.aarch64.sve.st4.nxv16i8(<vscale x 16 x i8> %v0, call void @llvm.aarch64.sve.st4.nxv16i8(<vscale x 16 x i8> %v0,
<vscale x 16 x i8> %v1, <vscale x 16 x i8> %v1,
<vscale x 16 x i8> %v2, <vscale x 16 x i8> %v2,
<vscale x 16 x i8> %v3, <vscale x 16 x i8> %v3,
<vscale x 16 x i1> %pred, <vscale x 16 x i1> %pred,
<vscale x 16 x i8>* %base) i8* %1)
ret void ret void
} }
; ;
; ST4H ; ST4H
; ;
define void @st4h_i16(<vscale x 8 x i16> %v0, <vscale x 8 x i16> %v1, <vscale x 8 x i16> %v2, <vscale x 8 x i16> %v3, <vscale x 8 x i1> %pred, i16* %addr, i64 %offset) { define void @st4h_i16(<vscale x 8 x i16> %v0, <vscale x 8 x i16> %v1, <vscale x 8 x i16> %v2, <vscale x 8 x i16> %v3, <vscale x 8 x i1> %pred, i16* %addr, i64 %offset) {
; CHECK-LABEL: st4h_i16: ; CHECK-LABEL: st4h_i16:
; CHECK: st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, x1, lsl #1] ; CHECK: st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, x1, lsl #1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = getelementptr i16, i16* %addr, i64 %offset %1 = getelementptr i16, i16* %addr, i64 %offset
%base = bitcast i16* %1 to <vscale x 8 x i16>*
call void @llvm.aarch64.sve.st4.nxv8i16(<vscale x 8 x i16> %v0, call void @llvm.aarch64.sve.st4.nxv8i16(<vscale x 8 x i16> %v0,
<vscale x 8 x i16> %v1, <vscale x 8 x i16> %v1,
<vscale x 8 x i16> %v2, <vscale x 8 x i16> %v2,
<vscale x 8 x i16> %v3, <vscale x 8 x i16> %v3,
<vscale x 8 x i1> %pred, <vscale x 8 x i1> %pred,
<vscale x 8 x i16>* %base) i16* %1)
ret void ret void
} }
define void @st4h_f16(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1, <vscale x 8 x half> %v2, <vscale x 8 x half> %v3, <vscale x 8 x i1> %pred, half* %addr, i64 %offset) { define void @st4h_f16(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1, <vscale x 8 x half> %v2, <vscale x 8 x half> %v3, <vscale x 8 x i1> %pred, half* %addr, i64 %offset) {
; CHECK-LABEL: st4h_f16: ; CHECK-LABEL: st4h_f16:
; CHECK: st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, x1, lsl #1] ; CHECK: st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0, x1, lsl #1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = getelementptr half, half* %addr, i64 %offset %1 = getelementptr half, half* %addr, i64 %offset
%base = bitcast half* %1 to <vscale x 8 x half>*
call void @llvm.aarch64.sve.st4.nxv8f16(<vscale x 8 x half> %v0, call void @llvm.aarch64.sve.st4.nxv8f16(<vscale x 8 x half> %v0,
<vscale x 8 x half> %v1, <vscale x 8 x half> %v1,
<vscale x 8 x half> %v2, <vscale x 8 x half> %v2,
<vscale x 8 x half> %v3, <vscale x 8 x half> %v3,
<vscale x 8 x i1> %pred, <vscale x 8 x i1> %pred,
<vscale x 8 x half>* %base) half* %1)
ret void ret void
} }
; ;
; ST4W ; ST4W
; ;
define void @st4w_i32(<vscale x 4 x i32> %v0, <vscale x 4 x i32> %v1, <vscale x 4 x i32> %v2, <vscale x 4 x i32> %v3, <vscale x 4 x i1> %pred, i32* %addr, i64 %offset) { define void @st4w_i32(<vscale x 4 x i32> %v0, <vscale x 4 x i32> %v1, <vscale x 4 x i32> %v2, <vscale x 4 x i32> %v3, <vscale x 4 x i1> %pred, i32* %addr, i64 %offset) {
; CHECK-LABEL: st4w_i32: ; CHECK-LABEL: st4w_i32:
; CHECK: st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, x1, lsl #2] ; CHECK: st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, x1, lsl #2]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = getelementptr i32, i32* %addr, i64 %offset %1 = getelementptr i32, i32* %addr, i64 %offset
%base = bitcast i32* %1 to <vscale x 4 x i32>*
call void @llvm.aarch64.sve.st4.nxv4i32(<vscale x 4 x i32> %v0, call void @llvm.aarch64.sve.st4.nxv4i32(<vscale x 4 x i32> %v0,
<vscale x 4 x i32> %v1, <vscale x 4 x i32> %v1,
<vscale x 4 x i32> %v2, <vscale x 4 x i32> %v2,
<vscale x 4 x i32> %v3, <vscale x 4 x i32> %v3,
<vscale x 4 x i1> %pred, <vscale x 4 x i1> %pred,
<vscale x 4 x i32>* %base) i32* %1)
ret void ret void
} }
define void @st4w_f32(<vscale x 4 x float> %v0, <vscale x 4 x float> %v1, <vscale x 4 x float> %v2, <vscale x 4 x float> %v3, <vscale x 4 x i1> %pred, float* %addr, i64 %offset) { define void @st4w_f32(<vscale x 4 x float> %v0, <vscale x 4 x float> %v1, <vscale x 4 x float> %v2, <vscale x 4 x float> %v3, <vscale x 4 x i1> %pred, float* %addr, i64 %offset) {
; CHECK-LABEL: st4w_f32: ; CHECK-LABEL: st4w_f32:
; CHECK: st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, x1, lsl #2] ; CHECK: st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0, x1, lsl #2]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = getelementptr float, float* %addr, i64 %offset %1 = getelementptr float, float* %addr, i64 %offset
%base = bitcast float* %1 to <vscale x 4 x float>*
call void @llvm.aarch64.sve.st4.nxv4f32(<vscale x 4 x float> %v0, call void @llvm.aarch64.sve.st4.nxv4f32(<vscale x 4 x float> %v0,
<vscale x 4 x float> %v1, <vscale x 4 x float> %v1,
<vscale x 4 x float> %v2, <vscale x 4 x float> %v2,
<vscale x 4 x float> %v3, <vscale x 4 x float> %v3,
<vscale x 4 x i1> %pred, <vscale x 4 x i1> %pred,
<vscale x 4 x float>* %base) float* %1)
ret void ret void
} }
; ;
; ST4D ; ST4D
; ;
define void @st4d_i64(<vscale x 2 x i64> %v0, <vscale x 2 x i64> %v1, <vscale x 2 x i64> %v2, <vscale x 2 x i64> %v3, <vscale x 2 x i1> %pred, i64* %addr, i64 %offset) { define void @st4d_i64(<vscale x 2 x i64> %v0, <vscale x 2 x i64> %v1, <vscale x 2 x i64> %v2, <vscale x 2 x i64> %v3, <vscale x 2 x i1> %pred, i64* %addr, i64 %offset) {
; CHECK-LABEL: st4d_i64: ; CHECK-LABEL: st4d_i64:
; CHECK: st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0, x1, lsl #3] ; CHECK: st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0, x1, lsl #3]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = getelementptr i64, i64* %addr, i64 %offset %1 = getelementptr i64, i64* %addr, i64 %offset
%base = bitcast i64* %1 to <vscale x 2 x i64>*
call void @llvm.aarch64.sve.st4.nxv2i64(<vscale x 2 x i64> %v0, call void @llvm.aarch64.sve.st4.nxv2i64(<vscale x 2 x i64> %v0,
<vscale x 2 x i64> %v1, <vscale x 2 x i64> %v1,
<vscale x 2 x i64> %v2, <vscale x 2 x i64> %v2,
<vscale x 2 x i64> %v3, <vscale x 2 x i64> %v3,
<vscale x 2 x i1> %pred, <vscale x 2 x i1> %pred,
<vscale x 2 x i64>* %base) i64* %1)
ret void ret void
} }
define void @st4d_f64(<vscale x 2 x double> %v0, <vscale x 2 x double> %v1, <vscale x 2 x double> %v2, <vscale x 2 x double> %v3, <vscale x 2 x i1> %pred, double* %addr, i64 %offset) { define void @st4d_f64(<vscale x 2 x double> %v0, <vscale x 2 x double> %v1, <vscale x 2 x double> %v2, <vscale x 2 x double> %v3, <vscale x 2 x i1> %pred, double* %addr, i64 %offset) {
; CHECK-LABEL: st4d_f64: ; CHECK-LABEL: st4d_f64:
; CHECK: st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0, x1, lsl #3] ; CHECK: st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0, x1, lsl #3]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = getelementptr double, double* %addr, i64 %offset %1 = getelementptr double, double* %addr, i64 %offset
%base = bitcast double* %1 to <vscale x 2 x double>*
call void @llvm.aarch64.sve.st4.nxv2f64(<vscale x 2 x double> %v0, call void @llvm.aarch64.sve.st4.nxv2f64(<vscale x 2 x double> %v0,
<vscale x 2 x double> %v1, <vscale x 2 x double> %v1,
<vscale x 2 x double> %v2, <vscale x 2 x double> %v2,
<vscale x 2 x double> %v3, <vscale x 2 x double> %v3,
<vscale x 2 x i1> %pred, <vscale x 2 x i1> %pred,
<vscale x 2 x double>* %base) double* %1)
ret void ret void
} }
declare void @llvm.aarch64.sve.st2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>*) declare void @llvm.aarch64.sve.st2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i1>, i8*)
declare void @llvm.aarch64.sve.st2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>*) declare void @llvm.aarch64.sve.st2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i1>, i16*)
declare void @llvm.aarch64.sve.st2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>*) declare void @llvm.aarch64.sve.st2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, i32*)
declare void @llvm.aarch64.sve.st2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>*) declare void @llvm.aarch64.sve.st2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i1>, i64*)
declare void @llvm.aarch64.sve.st2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>*) declare void @llvm.aarch64.sve.st2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, half*)
declare void @llvm.aarch64.sve.st2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>*) declare void @llvm.aarch64.sve.st2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i1>, float*)
declare void @llvm.aarch64.sve.st2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>*) declare void @llvm.aarch64.sve.st2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x i1>, double*)
declare void @llvm.aarch64.sve.st3.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>*) declare void @llvm.aarch64.sve.st3.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i1>, i8*)
declare void @llvm.aarch64.sve.st3.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>*) declare void @llvm.aarch64.sve.st3.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i1>, i16*)
declare void @llvm.aarch64.sve.st3.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>*) declare void @llvm.aarch64.sve.st3.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, i32*)
declare void @llvm.aarch64.sve.st3.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>*) declare void @llvm.aarch64.sve.st3.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i1>, i64*)
declare void @llvm.aarch64.sve.st3.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>*) declare void @llvm.aarch64.sve.st3.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, half*)
declare void @llvm.aarch64.sve.st3.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>*) declare void @llvm.aarch64.sve.st3.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i1>, float*)
declare void @llvm.aarch64.sve.st3.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>*) declare void @llvm.aarch64.sve.st3.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x i1>, double*)
declare void @llvm.aarch64.sve.st4.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>*) declare void @llvm.aarch64.sve.st4.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i1>, i8*)
declare void @llvm.aarch64.sve.st4.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>*) declare void @llvm.aarch64.sve.st4.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i1>, i16*)
declare void @llvm.aarch64.sve.st4.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>*) declare void @llvm.aarch64.sve.st4.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, i32*)
declare void @llvm.aarch64.sve.st4.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>*) declare void @llvm.aarch64.sve.st4.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i1>, i64*)
declare void @llvm.aarch64.sve.st4.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>*) declare void @llvm.aarch64.sve.st4.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, half*)
declare void @llvm.aarch64.sve.st4.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>*) declare void @llvm.aarch64.sve.st4.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i1>, float*)
declare void @llvm.aarch64.sve.st4.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>*) declare void @llvm.aarch64.sve.st4.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x i1>, double*)

llvm/test/CodeGen/AArch64/sve-intrinsics-stores.ll

; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s ; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
; ;
; ST2B ; ST2B
; ;
define void @st2b_i8(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) { define void @st2b_i8(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i1> %pred, i8* %addr) {
; CHECK-LABEL: st2b_i8: ; CHECK-LABEL: st2b_i8:
; CHECK: st2b { z0.b, z1.b }, p0, [x0] ; CHECK: st2b { z0.b, z1.b }, p0, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
call void @llvm.aarch64.sve.st2.nxv16i8(<vscale x 16 x i8> %v0, call void @llvm.aarch64.sve.st2.nxv16i8(<vscale x 16 x i8> %v0,
<vscale x 16 x i8> %v1, <vscale x 16 x i8> %v1,
<vscale x 16 x i1> %pred, <vscale x 16 x i1> %pred,
<vscale x 16 x i8>* %addr) i8* %addr)
ret void ret void
} }
; ;
; ST2H ; ST2H
; ;
define void @st2h_i16(<vscale x 8 x i16> %v0, <vscale x 8 x i16> %v1, <vscale x 8 x i1> %pred, <vscale x 8 x i16>* %addr) { define void @st2h_i16(<vscale x 8 x i16> %v0, <vscale x 8 x i16> %v1, <vscale x 8 x i1> %pred, i16* %addr) {
; CHECK-LABEL: st2h_i16: ; CHECK-LABEL: st2h_i16:
; CHECK: st2h { z0.h, z1.h }, p0, [x0] ; CHECK: st2h { z0.h, z1.h }, p0, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
call void @llvm.aarch64.sve.st2.nxv8i16(<vscale x 8 x i16> %v0, call void @llvm.aarch64.sve.st2.nxv8i16(<vscale x 8 x i16> %v0,
<vscale x 8 x i16> %v1, <vscale x 8 x i16> %v1,
<vscale x 8 x i1> %pred, <vscale x 8 x i1> %pred,
<vscale x 8 x i16>* %addr) i16* %addr)
ret void ret void
} }
define void @st2h_f16(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1, <vscale x 8 x i1> %pred, <vscale x 8 x half>* %addr) { define void @st2h_f16(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1, <vscale x 8 x i1> %pred, half* %addr) {
; CHECK-LABEL: st2h_f16: ; CHECK-LABEL: st2h_f16:
; CHECK: st2h { z0.h, z1.h }, p0, [x0] ; CHECK: st2h { z0.h, z1.h }, p0, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
call void @llvm.aarch64.sve.st2.nxv8f16(<vscale x 8 x half> %v0, call void @llvm.aarch64.sve.st2.nxv8f16(<vscale x 8 x half> %v0,
<vscale x 8 x half> %v1, <vscale x 8 x half> %v1,
<vscale x 8 x i1> %pred, <vscale x 8 x i1> %pred,
<vscale x 8 x half>* %addr) half* %addr)
ret void ret void
} }
; ;
; ST2W ; ST2W
; ;
define void @st2w_i32(<vscale x 4 x i32> %v0, <vscale x 4 x i32> %v1, <vscale x 4 x i1> %pred, <vscale x 4 x i32>* %addr) { define void @st2w_i32(<vscale x 4 x i32> %v0, <vscale x 4 x i32> %v1, <vscale x 4 x i1> %pred, i32* %addr) {
; CHECK-LABEL: st2w_i32: ; CHECK-LABEL: st2w_i32:
; CHECK: st2w { z0.s, z1.s }, p0, [x0] ; CHECK: st2w { z0.s, z1.s }, p0, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
call void @llvm.aarch64.sve.st2.nxv4i32(<vscale x 4 x i32> %v0, call void @llvm.aarch64.sve.st2.nxv4i32(<vscale x 4 x i32> %v0,
<vscale x 4 x i32> %v1, <vscale x 4 x i32> %v1,
<vscale x 4 x i1> %pred, <vscale x 4 x i1> %pred,
<vscale x 4 x i32>* %addr) i32* %addr)
ret void ret void
} }
define void @st2w_f32(<vscale x 4 x float> %v0, <vscale x 4 x float> %v1, <vscale x 4 x i1> %pred, <vscale x 4 x float>* %addr) { define void @st2w_f32(<vscale x 4 x float> %v0, <vscale x 4 x float> %v1, <vscale x 4 x i1> %pred, float* %addr) {
; CHECK-LABEL: st2w_f32: ; CHECK-LABEL: st2w_f32:
; CHECK: st2w { z0.s, z1.s }, p0, [x0] ; CHECK: st2w { z0.s, z1.s }, p0, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
call void @llvm.aarch64.sve.st2.nxv4f32(<vscale x 4 x float> %v0, call void @llvm.aarch64.sve.st2.nxv4f32(<vscale x 4 x float> %v0,
<vscale x 4 x float> %v1, <vscale x 4 x float> %v1,
<vscale x 4 x i1> %pred, <vscale x 4 x i1> %pred,
<vscale x 4 x float>* %addr) float* %addr)
ret void ret void
} }
; ;
; ST2D ; ST2D
; ;
define void @st2d_i64(<vscale x 2 x i64> %v0, <vscale x 2 x i64> %v1, <vscale x 2 x i1> %pred, <vscale x 2 x i64>* %addr) { define void @st2d_i64(<vscale x 2 x i64> %v0, <vscale x 2 x i64> %v1, <vscale x 2 x i1> %pred, i64* %addr) {
; CHECK-LABEL: st2d_i64: ; CHECK-LABEL: st2d_i64:
; CHECK: st2d { z0.d, z1.d }, p0, [x0] ; CHECK: st2d { z0.d, z1.d }, p0, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
call void @llvm.aarch64.sve.st2.nxv2i64(<vscale x 2 x i64> %v0, call void @llvm.aarch64.sve.st2.nxv2i64(<vscale x 2 x i64> %v0,
<vscale x 2 x i64> %v1, <vscale x 2 x i64> %v1,
<vscale x 2 x i1> %pred, <vscale x 2 x i1> %pred,
<vscale x 2 x i64>* %addr) i64* %addr)
ret void ret void
} }
define void @st2d_f64(<vscale x 2 x double> %v0, <vscale x 2 x double> %v1, <vscale x 2 x i1> %pred, <vscale x 2 x double>* %addr) { define void @st2d_f64(<vscale x 2 x double> %v0, <vscale x 2 x double> %v1, <vscale x 2 x i1> %pred, double* %addr) {
; CHECK-LABEL: st2d_f64: ; CHECK-LABEL: st2d_f64:
; CHECK: st2d { z0.d, z1.d }, p0, [x0] ; CHECK: st2d { z0.d, z1.d }, p0, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
call void @llvm.aarch64.sve.st2.nxv2f64(<vscale x 2 x double> %v0, call void @llvm.aarch64.sve.st2.nxv2f64(<vscale x 2 x double> %v0,
<vscale x 2 x double> %v1, <vscale x 2 x double> %v1,
<vscale x 2 x i1> %pred, <vscale x 2 x i1> %pred,
<vscale x 2 x double>* %addr) double* %addr)
ret void ret void
} }
; ;
; ST3B ; ST3B
; ;
define void @st3b_i8(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) { define void @st3b_i8(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i1> %pred, i8* %addr) {
; CHECK-LABEL: st3b_i8: ; CHECK-LABEL: st3b_i8:
; CHECK: st3b { z0.b, z1.b, z2.b }, p0, [x0] ; CHECK: st3b { z0.b, z1.b, z2.b }, p0, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
call void @llvm.aarch64.sve.st3.nxv16i8(<vscale x 16 x i8> %v0, call void @llvm.aarch64.sve.st3.nxv16i8(<vscale x 16 x i8> %v0,
<vscale x 16 x i8> %v1, <vscale x 16 x i8> %v1,
<vscale x 16 x i8> %v2, <vscale x 16 x i8> %v2,
<vscale x 16 x i1> %pred, <vscale x 16 x i1> %pred,
<vscale x 16 x i8>* %addr) i8* %addr)
ret void ret void
} }
; ;
; ST3H ; ST3H
; ;
define void @st3h_i16(<vscale x 8 x i16> %v0, <vscale x 8 x i16> %v1, <vscale x 8 x i16> %v2, <vscale x 8 x i1> %pred, <vscale x 8 x i16>* %addr) { define void @st3h_i16(<vscale x 8 x i16> %v0, <vscale x 8 x i16> %v1, <vscale x 8 x i16> %v2, <vscale x 8 x i1> %pred, i16* %addr) {
; CHECK-LABEL: st3h_i16: ; CHECK-LABEL: st3h_i16:
; CHECK: st3h { z0.h, z1.h, z2.h }, p0, [x0] ; CHECK: st3h { z0.h, z1.h, z2.h }, p0, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
call void @llvm.aarch64.sve.st3.nxv8i16(<vscale x 8 x i16> %v0, call void @llvm.aarch64.sve.st3.nxv8i16(<vscale x 8 x i16> %v0,
<vscale x 8 x i16> %v1, <vscale x 8 x i16> %v1,
<vscale x 8 x i16> %v2, <vscale x 8 x i16> %v2,
<vscale x 8 x i1> %pred, <vscale x 8 x i1> %pred,
<vscale x 8 x i16>* %addr) i16* %addr)
ret void ret void
} }
define void @st3h_f16(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1, <vscale x 8 x half> %v2, <vscale x 8 x i1> %pred, <vscale x 8 x half>* %addr) { define void @st3h_f16(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1, <vscale x 8 x half> %v2, <vscale x 8 x i1> %pred, half* %addr) {
; CHECK-LABEL: st3h_f16: ; CHECK-LABEL: st3h_f16:
; CHECK: st3h { z0.h, z1.h, z2.h }, p0, [x0] ; CHECK: st3h { z0.h, z1.h, z2.h }, p0, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
call void @llvm.aarch64.sve.st3.nxv8f16(<vscale x 8 x half> %v0, call void @llvm.aarch64.sve.st3.nxv8f16(<vscale x 8 x half> %v0,
<vscale x 8 x half> %v1, <vscale x 8 x half> %v1,
<vscale x 8 x half> %v2, <vscale x 8 x half> %v2,
<vscale x 8 x i1> %pred, <vscale x 8 x i1> %pred,
<vscale x 8 x half>* %addr) half* %addr)
ret void ret void
} }
; ;
; ST3W ; ST3W
; ;
define void @st3w_i32(<vscale x 4 x i32> %v0, <vscale x 4 x i32> %v1, <vscale x 4 x i32> %v2, <vscale x 4 x i1> %pred, <vscale x 4 x i32>* %addr) { define void @st3w_i32(<vscale x 4 x i32> %v0, <vscale x 4 x i32> %v1, <vscale x 4 x i32> %v2, <vscale x 4 x i1> %pred, i32* %addr) {
; CHECK-LABEL: st3w_i32: ; CHECK-LABEL: st3w_i32:
; CHECK: st3w { z0.s, z1.s, z2.s }, p0, [x0] ; CHECK: st3w { z0.s, z1.s, z2.s }, p0, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
call void @llvm.aarch64.sve.st3.nxv4i32(<vscale x 4 x i32> %v0, call void @llvm.aarch64.sve.st3.nxv4i32(<vscale x 4 x i32> %v0,
<vscale x 4 x i32> %v1, <vscale x 4 x i32> %v1,
<vscale x 4 x i32> %v2, <vscale x 4 x i32> %v2,
<vscale x 4 x i1> %pred, <vscale x 4 x i1> %pred,
<vscale x 4 x i32>* %addr) i32* %addr)
ret void ret void
} }
define void @st3w_f32(<vscale x 4 x float> %v0, <vscale x 4 x float> %v1, <vscale x 4 x float> %v2, <vscale x 4 x i1> %pred, <vscale x 4 x float>* %addr) { define void @st3w_f32(<vscale x 4 x float> %v0, <vscale x 4 x float> %v1, <vscale x 4 x float> %v2, <vscale x 4 x i1> %pred, float* %addr) {
; CHECK-LABEL: st3w_f32: ; CHECK-LABEL: st3w_f32:
; CHECK: st3w { z0.s, z1.s, z2.s }, p0, [x0] ; CHECK: st3w { z0.s, z1.s, z2.s }, p0, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
call void @llvm.aarch64.sve.st3.nxv4f32(<vscale x 4 x float> %v0, call void @llvm.aarch64.sve.st3.nxv4f32(<vscale x 4 x float> %v0,
<vscale x 4 x float> %v1, <vscale x 4 x float> %v1,
<vscale x 4 x float> %v2, <vscale x 4 x float> %v2,
<vscale x 4 x i1> %pred, <vscale x 4 x i1> %pred,
<vscale x 4 x float>* %addr) float* %addr)
ret void ret void
} }
; ;
; ST3D ; ST3D
; ;
define void @st3d_i64(<vscale x 2 x i64> %v0, <vscale x 2 x i64> %v1, <vscale x 2 x i64> %v2, <vscale x 2 x i1> %pred, <vscale x 2 x i64>* %addr) { define void @st3d_i64(<vscale x 2 x i64> %v0, <vscale x 2 x i64> %v1, <vscale x 2 x i64> %v2, <vscale x 2 x i1> %pred, i64* %addr) {
; CHECK-LABEL: st3d_i64: ; CHECK-LABEL: st3d_i64:
; CHECK: st3d { z0.d, z1.d, z2.d }, p0, [x0] ; CHECK: st3d { z0.d, z1.d, z2.d }, p0, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
call void @llvm.aarch64.sve.st3.nxv2i64(<vscale x 2 x i64> %v0, call void @llvm.aarch64.sve.st3.nxv2i64(<vscale x 2 x i64> %v0,
<vscale x 2 x i64> %v1, <vscale x 2 x i64> %v1,
<vscale x 2 x i64> %v2, <vscale x 2 x i64> %v2,
<vscale x 2 x i1> %pred, <vscale x 2 x i1> %pred,
<vscale x 2 x i64>* %addr) i64* %addr)
ret void ret void
} }
define void @st3d_f64(<vscale x 2 x double> %v0, <vscale x 2 x double> %v1, <vscale x 2 x double> %v2, <vscale x 2 x i1> %pred, <vscale x 2 x double>* %addr) { define void @st3d_f64(<vscale x 2 x double> %v0, <vscale x 2 x double> %v1, <vscale x 2 x double> %v2, <vscale x 2 x i1> %pred, double* %addr) {
; CHECK-LABEL: st3d_f64: ; CHECK-LABEL: st3d_f64:
; CHECK: st3d { z0.d, z1.d, z2.d }, p0, [x0] ; CHECK: st3d { z0.d, z1.d, z2.d }, p0, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
call void @llvm.aarch64.sve.st3.nxv2f64(<vscale x 2 x double> %v0, call void @llvm.aarch64.sve.st3.nxv2f64(<vscale x 2 x double> %v0,
<vscale x 2 x double> %v1, <vscale x 2 x double> %v1,
<vscale x 2 x double> %v2, <vscale x 2 x double> %v2,
<vscale x 2 x i1> %pred, <vscale x 2 x i1> %pred,
<vscale x 2 x double>* %addr) double* %addr)
ret void ret void
} }
; ;
; ST4B ; ST4B
; ;
define void @st4b_i8(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i8> %v3, <vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) { define void @st4b_i8(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1, <vscale x 16 x i8> %v2, <vscale x 16 x i8> %v3, <vscale x 16 x i1> %pred, i8* %addr) {
; CHECK-LABEL: st4b_i8: ; CHECK-LABEL: st4b_i8:
; CHECK: st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0] ; CHECK: st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
call void @llvm.aarch64.sve.st4.nxv16i8(<vscale x 16 x i8> %v0, call void @llvm.aarch64.sve.st4.nxv16i8(<vscale x 16 x i8> %v0,
<vscale x 16 x i8> %v1, <vscale x 16 x i8> %v1,
<vscale x 16 x i8> %v2, <vscale x 16 x i8> %v2,
<vscale x 16 x i8> %v3, <vscale x 16 x i8> %v3,
<vscale x 16 x i1> %pred, <vscale x 16 x i1> %pred,
<vscale x 16 x i8>* %addr) i8* %addr)
ret void ret void
} }
; ;
; ST4H ; ST4H
; ;
define void @st4h_i16(<vscale x 8 x i16> %v0, <vscale x 8 x i16> %v1, <vscale x 8 x i16> %v2, <vscale x 8 x i16> %v3, <vscale x 8 x i1> %pred, <vscale x 8 x i16>* %addr) { define void @st4h_i16(<vscale x 8 x i16> %v0, <vscale x 8 x i16> %v1, <vscale x 8 x i16> %v2, <vscale x 8 x i16> %v3, <vscale x 8 x i1> %pred, i16* %addr) {
; CHECK-LABEL: st4h_i16: ; CHECK-LABEL: st4h_i16:
; CHECK: st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0] ; CHECK: st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
call void @llvm.aarch64.sve.st4.nxv8i16(<vscale x 8 x i16> %v0, call void @llvm.aarch64.sve.st4.nxv8i16(<vscale x 8 x i16> %v0,
<vscale x 8 x i16> %v1, <vscale x 8 x i16> %v1,
<vscale x 8 x i16> %v2, <vscale x 8 x i16> %v2,
<vscale x 8 x i16> %v3, <vscale x 8 x i16> %v3,
<vscale x 8 x i1> %pred, <vscale x 8 x i1> %pred,
<vscale x 8 x i16>* %addr) i16* %addr)
ret void ret void
} }
define void @st4h_f16(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1, <vscale x 8 x half> %v2, <vscale x 8 x half> %v3, <vscale x 8 x i1> %pred, <vscale x 8 x half>* %addr) { define void @st4h_f16(<vscale x 8 x half> %v0, <vscale x 8 x half> %v1, <vscale x 8 x half> %v2, <vscale x 8 x half> %v3, <vscale x 8 x i1> %pred, half* %addr) {
; CHECK-LABEL: st4h_f16: ; CHECK-LABEL: st4h_f16:
; CHECK: st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0] ; CHECK: st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
call void @llvm.aarch64.sve.st4.nxv8f16(<vscale x 8 x half> %v0, call void @llvm.aarch64.sve.st4.nxv8f16(<vscale x 8 x half> %v0,
<vscale x 8 x half> %v1, <vscale x 8 x half> %v1,
<vscale x 8 x half> %v2, <vscale x 8 x half> %v2,
<vscale x 8 x half> %v3, <vscale x 8 x half> %v3,
<vscale x 8 x i1> %pred, <vscale x 8 x i1> %pred,
<vscale x 8 x half>* %addr) half* %addr)
ret void ret void
} }
; ;
; ST4W ; ST4W
; ;
define void @st4w_i32(<vscale x 4 x i32> %v0, <vscale x 4 x i32> %v1, <vscale x 4 x i32> %v2, <vscale x 4 x i32> %v3, <vscale x 4 x i1> %pred, <vscale x 4 x i32>* %addr) { define void @st4w_i32(<vscale x 4 x i32> %v0, <vscale x 4 x i32> %v1, <vscale x 4 x i32> %v2, <vscale x 4 x i32> %v3, <vscale x 4 x i1> %pred, i32* %addr) {
; CHECK-LABEL: st4w_i32: ; CHECK-LABEL: st4w_i32:
; CHECK: st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0] ; CHECK: st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
call void @llvm.aarch64.sve.st4.nxv4i32(<vscale x 4 x i32> %v0, call void @llvm.aarch64.sve.st4.nxv4i32(<vscale x 4 x i32> %v0,
<vscale x 4 x i32> %v1, <vscale x 4 x i32> %v1,
<vscale x 4 x i32> %v2, <vscale x 4 x i32> %v2,
<vscale x 4 x i32> %v3, <vscale x 4 x i32> %v3,
<vscale x 4 x i1> %pred, <vscale x 4 x i1> %pred,
<vscale x 4 x i32>* %addr) i32* %addr)
ret void ret void
} }
define void @st4w_f32(<vscale x 4 x float> %v0, <vscale x 4 x float> %v1, <vscale x 4 x float> %v2, <vscale x 4 x float> %v3, <vscale x 4 x i1> %pred, <vscale x 4 x float>* %addr) { define void @st4w_f32(<vscale x 4 x float> %v0, <vscale x 4 x float> %v1, <vscale x 4 x float> %v2, <vscale x 4 x float> %v3, <vscale x 4 x i1> %pred, float* %addr) {
; CHECK-LABEL: st4w_f32: ; CHECK-LABEL: st4w_f32:
; CHECK: st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0] ; CHECK: st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
call void @llvm.aarch64.sve.st4.nxv4f32(<vscale x 4 x float> %v0, call void @llvm.aarch64.sve.st4.nxv4f32(<vscale x 4 x float> %v0,
<vscale x 4 x float> %v1, <vscale x 4 x float> %v1,
<vscale x 4 x float> %v2, <vscale x 4 x float> %v2,
<vscale x 4 x float> %v3, <vscale x 4 x float> %v3,
<vscale x 4 x i1> %pred, <vscale x 4 x i1> %pred,
<vscale x 4 x float>* %addr) float* %addr)
ret void ret void
} }
; ;
; ST4D ; ST4D
; ;
define void @st4d_i64(<vscale x 2 x i64> %v0, <vscale x 2 x i64> %v1, <vscale x 2 x i64> %v2, <vscale x 2 x i64> %v3, <vscale x 2 x i1> %pred, <vscale x 2 x i64>* %addr) { define void @st4d_i64(<vscale x 2 x i64> %v0, <vscale x 2 x i64> %v1, <vscale x 2 x i64> %v2, <vscale x 2 x i64> %v3, <vscale x 2 x i1> %pred, i64* %addr) {
; CHECK-LABEL: st4d_i64: ; CHECK-LABEL: st4d_i64:
; CHECK: st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0] ; CHECK: st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
call void @llvm.aarch64.sve.st4.nxv2i64(<vscale x 2 x i64> %v0, call void @llvm.aarch64.sve.st4.nxv2i64(<vscale x 2 x i64> %v0,
<vscale x 2 x i64> %v1, <vscale x 2 x i64> %v1,
<vscale x 2 x i64> %v2, <vscale x 2 x i64> %v2,
<vscale x 2 x i64> %v3, <vscale x 2 x i64> %v3,
<vscale x 2 x i1> %pred, <vscale x 2 x i1> %pred,
<vscale x 2 x i64>* %addr) i64* %addr)
ret void ret void
} }
define void @st4d_f64(<vscale x 2 x double> %v0, <vscale x 2 x double> %v1, <vscale x 2 x double> %v2, <vscale x 2 x double> %v3, <vscale x 2 x i1> %pred, <vscale x 2 x double>* %addr) { define void @st4d_f64(<vscale x 2 x double> %v0, <vscale x 2 x double> %v1, <vscale x 2 x double> %v2, <vscale x 2 x double> %v3, <vscale x 2 x i1> %pred, double* %addr) {
; CHECK-LABEL: st4d_f64: ; CHECK-LABEL: st4d_f64:
; CHECK: st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0] ; CHECK: st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
call void @llvm.aarch64.sve.st4.nxv2f64(<vscale x 2 x double> %v0, call void @llvm.aarch64.sve.st4.nxv2f64(<vscale x 2 x double> %v0,
<vscale x 2 x double> %v1, <vscale x 2 x double> %v1,
<vscale x 2 x double> %v2, <vscale x 2 x double> %v2,
<vscale x 2 x double> %v3, <vscale x 2 x double> %v3,
<vscale x 2 x i1> %pred, <vscale x 2 x i1> %pred,
<vscale x 2 x double>* %addr) double* %addr)
ret void ret void
} }
; ;
; STNT1B ; STNT1B
; ;
define void @stnt1b_i8(<vscale x 16 x i8> %data, <vscale x 16 x i1> %pred, i8* %addr) { define void @stnt1b_i8(<vscale x 16 x i8> %data, <vscale x 16 x i1> %pred, i8* %addr) {
▲ Show 20 Lines • Show All 74 Lines • ▼ Show 20 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
call void @llvm.aarch64.sve.stnt1.nxv2f64(<vscale x 2 x double> %data, call void @llvm.aarch64.sve.stnt1.nxv2f64(<vscale x 2 x double> %data,
<vscale x 2 x i1> %pred, <vscale x 2 x i1> %pred,
double* %addr) double* %addr)
ret void ret void
} }
declare void @llvm.aarch64.sve.st2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>*) declare void @llvm.aarch64.sve.st2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i1>, i8*)
declare void @llvm.aarch64.sve.st2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>*) declare void @llvm.aarch64.sve.st2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i1>, i16*)
declare void @llvm.aarch64.sve.st2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>*) declare void @llvm.aarch64.sve.st2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, i32*)
declare void @llvm.aarch64.sve.st2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>*) declare void @llvm.aarch64.sve.st2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i1>, i64*)
declare void @llvm.aarch64.sve.st2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>*) declare void @llvm.aarch64.sve.st2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, half*)
declare void @llvm.aarch64.sve.st2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>*) declare void @llvm.aarch64.sve.st2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i1>, float*)
declare void @llvm.aarch64.sve.st2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>*) declare void @llvm.aarch64.sve.st2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x i1>, double*)
declare void @llvm.aarch64.sve.st3.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>*) declare void @llvm.aarch64.sve.st3.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i1>, i8*)
declare void @llvm.aarch64.sve.st3.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>*) declare void @llvm.aarch64.sve.st3.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i1>, i16*)
declare void @llvm.aarch64.sve.st3.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>*) declare void @llvm.aarch64.sve.st3.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, i32*)
declare void @llvm.aarch64.sve.st3.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>*) declare void @llvm.aarch64.sve.st3.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i1>, i64*)
declare void @llvm.aarch64.sve.st3.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>*) declare void @llvm.aarch64.sve.st3.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, half*)
declare void @llvm.aarch64.sve.st3.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>*) declare void @llvm.aarch64.sve.st3.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i1>, float*)
declare void @llvm.aarch64.sve.st3.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>*) declare void @llvm.aarch64.sve.st3.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x i1>, double*)
declare void @llvm.aarch64.sve.st4.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i1>, <vscale x 16 x i8>*) declare void @llvm.aarch64.sve.st4.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i1>, i8*)
declare void @llvm.aarch64.sve.st4.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x i16>*) declare void @llvm.aarch64.sve.st4.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i1>, i16*)
declare void @llvm.aarch64.sve.st4.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>*) declare void @llvm.aarch64.sve.st4.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, i32*)
declare void @llvm.aarch64.sve.st4.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>*) declare void @llvm.aarch64.sve.st4.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i1>, i64*)
declare void @llvm.aarch64.sve.st4.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, <vscale x 8 x half>*) declare void @llvm.aarch64.sve.st4.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x i1>, half*)
declare void @llvm.aarch64.sve.st4.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 4 x float>*) declare void @llvm.aarch64.sve.st4.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x i1>, float*)
declare void @llvm.aarch64.sve.st4.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x i1>, <vscale x 2 x double>*) declare void @llvm.aarch64.sve.st4.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x i1>, double*)
declare void @llvm.aarch64.sve.stnt1.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, i8*) declare void @llvm.aarch64.sve.stnt1.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, i8*)
declare void @llvm.aarch64.sve.stnt1.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, i16*) declare void @llvm.aarch64.sve.stnt1.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, i16*)
declare void @llvm.aarch64.sve.stnt1.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, i32*) declare void @llvm.aarch64.sve.stnt1.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, i32*)
declare void @llvm.aarch64.sve.stnt1.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, i64*) declare void @llvm.aarch64.sve.stnt1.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, i64*)
declare void @llvm.aarch64.sve.stnt1.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>, half*) declare void @llvm.aarch64.sve.stnt1.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>, half*)
declare void @llvm.aarch64.sve.stnt1.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, float*) declare void @llvm.aarch64.sve.stnt1.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, float*)
declare void @llvm.aarch64.sve.stnt1.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, double*) declare void @llvm.aarch64.sve.stnt1.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, double*)