[mlir][mlir-rocm-runner] Detect HIP version and AMD ISA version.

[whchung]

Summary

Prior to ROCm / HIP 3.5, HSA code object V2 is the default binary format.
Starting from ROCm 3.5, HSA code object V3 becomes default.

Also invoke rocm_agent_enumerator to detect proper AMD ISA version on the
system. Use gfx900 as the fallback value.

[whchung]

Fix build error due to incorrect lint.

[whchung]

Add logic to detech AMD ISA version.

[whchung]

Revise HIP version detection logic to be more descriptive.

[whchung]

Fix typos in the commit log.

[yaxunl]

LGTM

mlir/tools/mlir-rocm-runner/CMakeLists.txt

if(MLIR_ROCM_RUNNER_ENABLED)
 
   add_llvm_tool(mlir-rocm-runner
     mlir-rocm-runner.cpp
 
     DEPENDS
     rocm-runtime-wrappers
     )
   llvm_update_compile_flags(mlir-rocm-runner)
+  target_include_directories(mlir-rocm-runner
+    PRIVATE
+    "${HIP_PATH}/../include"
+    "${HIP_PATH}/include"
+  )
   target_link_libraries(mlir-rocm-runner PRIVATE ${LIBS} ${targets_to_link})
 
 endif()

mlir/tools/mlir-rocm-runner/mlir-rocm-runner.cpp

 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/MC/MCTargetOptionsCommandFlags.h"
 
 // lld headers.
 #include "lld/Common/Driver.h"
 
+// HIP headers.
+#include "hip/hip_version.h"
+
 using namespace mlir;
 using namespace llvm;
 
 using Blob = SmallVector<char, 0>;
 
 static cl::opt<std::string> tripleName("triple", cl::desc("target triple"),
                                        cl::value_desc("triple string"),
                                        cl::init("amdgcn-amd-amdhsa"));
 
 // TODO(whchung): Add feature to automatically detect available AMD GCN ISA
 // version via `rocm-agent-enumerator` utility.
 static cl::opt<std::string> targetChip("target", cl::desc("target chip"),
                                        cl::value_desc("AMDGPU ISA version"),
                                        cl::init("gfx900"));
 
 static cl::opt<std::string> features("feature", cl::desc("target features"),
                                      cl::value_desc("AMDGPU target features"),
-                                     cl::init("-code-object-v3"));
+                                     cl::init(""));
 
 static LogicalResult assembleIsa(const std::string isa, StringRef name,
                                  Blob &result) {
   raw_svector_ostream os(result);
 
   std::string error;
   Triple theTriple(Triple::normalize(tripleName));
   const Target *theTarget =
if (succeeded(assembleIsa(isa, name, isaBlob)) &&
       succeeded(createHsaco(isaBlob, name, hsacoBlob)))
     return std::make_unique<std::vector<char>>(hsacoBlob.begin(),
                                                hsacoBlob.end());
 
   WithColor::error(errs(), name) << "producing HSA code object error.\n";
   return {};
 }
 
+static void configTargetFeatures() {
+  if (features.size() > 0)
+    features += ",";
+  // Before ROCm 3.5, disable HSA code object V3.
+  if (HIP_VERSION_MAJOR >= 3 && HIP_VERSION_MINOR <= 5)
+    features += "-code-object-v3";
+  else
+    features += "+code-object-v3";
+}
+
 static LogicalResult runMLIRPasses(ModuleOp m) {
   PassManager pm(m.getContext());
   applyPassManagerCLOptions(pm);
 
+  // Configure target features per ROCm / HIP version.
+  configTargetFeatures();
+
   pm.addPass(createGpuKernelOutliningPass());
   auto &kernelPm = pm.nest<gpu::GPUModuleOp>();
   kernelPm.addPass(createStripDebugInfoPass());
   kernelPm.addPass(createLowerGpuOpsToROCDLOpsPass());
   kernelPm.addPass(createConvertGPUKernelToBlobPass(
       compileModuleToROCDLIR, compileISAToHsaco, tripleName, targetChip,
       features, /*gpuBinaryAnnotation=*/"rocdl.hsaco"));
   pm.addPass(createLowerToLLVMPass());