[PowerPC] Do not add the relocation addend to the instruction encoding

[stefanp]

Summary

We should not be adding the relocation addend to the instruction encoding.
This patch removes that and sets those bits to zero.

[sfertile]

Do you already have a test which dumps the relocations and verifies the addend on the relocations? (Do the llvm tools support dumping these new relocations?)

llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp

222

I think you are better keeping the return here.

254

ditto.

[stefanp]

I've put the return instructions back in place.
The test in this patch already prints out the addend. The CHECK-O section prints out the relocation and then it has symbol+<addend>. Is that what you are looking for?
For example:

; CHECK-O-NEXT:    0000000000000000:  R_PPC64_PCREL34      array2+0x1c

[sfertile]

LGTM.

The CHECK-O section prints out the relocation and then it has symbol+<addend>. Is that what you are looking for?

Yeah, not sure how I missed that the first time. Sorry.

[NeHuang]

LGTM

llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp

case MCExpr::SymbolRef: {
     // Currently these are the only valid PCRelative Relocations.
     assert((SRE->getKind() == MCSymbolRefExpr::VK_PCREL ||
             SRE->getKind() == MCSymbolRefExpr::VK_PPC_GOT_PCREL) &&
            "VariantKind must be VK_PCREL or VK_PPC_GOT_PCREL");
     // Generate the fixup for the relocation.
     Fixups.push_back(
         MCFixup::create(0, Expr,
                         static_cast<MCFixupKind>(PPC::fixup_ppc_pcrel34)));
-    // There is no offset to return so just return 0.
-    return 0;
+    break;
   }
   case MCExpr::Binary: {
     // Relocation plus some offset.
     const MCBinaryExpr *BE = cast<MCBinaryExpr>(Expr);
     assert(BE->getOpcode() == MCBinaryExpr::Add &&
            "Binary expression opcode must be an add.");
 
     const MCExpr *LHS = BE->getLHS();
     const MCExpr *RHS = BE->getRHS();
 
     // Need to check in both directions. Reloc+Offset and Offset+Reloc.
     if (LHS->getKind() != MCExpr::SymbolRef)
       std::swap(LHS, RHS);
 
     if (LHS->getKind() != MCExpr::SymbolRef ||
         RHS->getKind() != MCExpr::Constant)
       llvm_unreachable("Expecting to have one constant and one relocation.");
 
     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(LHS);
     (void)SRE;
     const MCConstantExpr *CE = cast<MCConstantExpr>(RHS);
+    assert(isInt<34>(CE->getValue()) && "Value must fit in 34 bits.");
 
     // Currently these are the only valid PCRelative Relocations.
     assert((SRE->getKind() == MCSymbolRefExpr::VK_PCREL ||
             SRE->getKind() == MCSymbolRefExpr::VK_PPC_GOT_PCREL) &&
            "VariantKind must be VK_PCREL or VK_PPC_GOT_PCREL");
     // Generate the fixup for the relocation.
     Fixups.push_back(
         MCFixup::create(0, Expr,
                         static_cast<MCFixupKind>(PPC::fixup_ppc_pcrel34)));
-    assert(isInt<34>(CE->getValue()) && "Value must fit in 34 bits.");
-    // Return the offset that should be added to the relocation by the linker.
-    return (CE->getValue() & 0x3FFFFFFFFUL) | RegBits;
-    }
+    break;
   }
+  return 0;
 }
 
 uint64_t
 PPCMCCodeEmitter::getMemRI34Encoding(const MCInst &MI, unsigned OpNo,
                                      SmallVectorImpl<MCFixup> &Fixups,
                                      const MCSubtargetInfo &STI) const {
   // Encode (imm, reg) as a memri34, which has the low 34-bits as the
   // displacement and the next 5 bits as the register #.

llvm/test/CodeGen/PowerPC/pcrel-relocation-plus-offset.ll

 @array2 = common dso_local local_unnamed_addr global [10 x i32] zeroinitializer, align 4
 
 define dso_local signext i32 @getElementLocal7() local_unnamed_addr {
 ; CHECK-S-LABEL: getElementLocal7:
 ; CHECK-S:       # %bb.0: # %entry
 ; CHECK-S-NEXT:    plwa r3, array2@PCREL+28(0), 1
 ; CHECK-S-NEXT:    blr
 ; CHECK-O-LABEL: <getElementLocal7>:
-; CHECK-O:         00 00 10 04 1c 00 60 a4       plwa 3, 28(0), 1
+; CHECK-O:         00 00 10 04 00 00 60 a4       plwa 3, 0(0), 1
 ; CHECK-O-NEXT:    0000000000000000:  R_PPC64_PCREL34      array2+0x1c
 ; CHECK-O-NEXT:    20 00 80 4e                   blr
 entry:
   %0 = load i32, i32* getelementptr inbounds ([10 x i32], [10 x i32]* @array2, i64 0, i64 7), align 4
   ret i32 %0
 }
 
 define dso_local signext i32 @getElementLocalNegative() local_unnamed_addr {
 ; CHECK-S-LABEL: getElementLocalNegative:
 ; CHECK-S:       # %bb.0: # %entry
 ; CHECK-S-NEXT:    plwa r3, array2@PCREL-8(0), 1
 ; CHECK-S-NEXT:    blr
 ; CHECK-O-LABEL: <getElementLocalNegative>:
-; CHECK-O:         ff ff 13 04 f8 ff 60 a4       plwa 3, -8(0), 1
+; CHECK-O:         00 00 10 04 00 00 60 a4       plwa 3, 0(0), 1
 ; CHECK-O-NEXT:    0000000000000020:  R_PPC64_PCREL34      array2-0x8
 ; CHECK-O-NEXT:    20 00 80 4e                   blr
 entry:
   %0 = load i32, i32* getelementptr inbounds ([10 x i32], [10 x i32]* @array2, i64 0, i64 -2), align 4
   ret i32 %0
 }
 
 define dso_local signext i32 @getElementExtern4() local_unnamed_addr {