[XCOFF][AIX] Use 'L..' instead of 'L' for PrivateGlobalPrefix

[jasonliu]

Summary

Without this change, names start with 'L' will get created as temporary symbol in MCContext::createSymbol.
Some other potential prefix considered:
.L, does not work for AIX, as a function start with L will end up with .L as prefix for its function entry point.
..L could work, but it does not play well with the convention on AIX that anything start with '.' are considered as entry point.
L. could work, but not sure if it's safe enough, as it's possible to have suffixes like .something append to a plain L, giving L.something which is not necessarily a temporary.
That's why we picked L.. for now.

[hubert.reinterpretcast]

llvm/lib/MC/MCAsmInfoXCOFF.cpp

18

Since . gets appended for function entry points, .L is not all that "reserved". I am not sure that it makes sense to use .L except for inertia. It seems adding the dot after the L would work better?

[hubert.reinterpretcast]

llvm/lib/MC/MCAsmInfoXCOFF.cpp

18

*"prefixed to"

[jasonliu]

Use L.. as prefix instead.

[daltenty]

LGTM

[hubert.reinterpretcast]

llvm/test/CodeGen/PowerPC/aix-lower-block-address.ll

72

What exactly is a "temporary" in terms of the object file or the assembly? The TOC entry here clearly would have a symbol table entry.

[hubert.reinterpretcast]

llvm/test/CodeGen/PowerPC/aix-xcoff-externL.ll

2

s/symbol name starts/a symbol name that starts/;

4

s/resulted/resulting/;

[jasonliu]

llvm/test/CodeGen/PowerPC/aix-lower-block-address.ll

72

I think LLVM treat the "temporary" as compiler created symbol.
We have the logic in XCOFFObjectFileWriter.cpp to query and skip recording the temporary symbols.
In this particular case, L..tmp0 is a temporary symbol/XCOFF label that we do not want to record in our symbol table. L..tmp0[TC] gets treated as temporary symbol as well, and skipped, but its csect still get registered and recorded. So everything "works".
I do agree it's a bit confusing here. But for our current status on AIX, symbols' "temporary" status does not seem to affect any of the assembly generation. And we actually only care about the symbols's temporary status for external symbols and labels, because those info are coming through MCSymbol (others are from MCSection).

[jasonliu]

llvm/test/CodeGen/PowerPC/aix-lower-block-address.ll

72

In terms of object file generation we actually only care about the correctness of symbols's temporary status for external symbols and labels, because those info are coming through MCSymbol (others are from MCSection) .

[hubert.reinterpretcast]

llvm/test/CodeGen/PowerPC/aix-lower-jump-table.ll

181–182

Maybe as a separate patch, should we update the test cases to use a different "mangling mode" with a matching private global prefix?

[jasonliu]

llvm/test/CodeGen/PowerPC/aix-lower-jump-table.ll

181–182

Yes, we should make it consistent in a separate patch.

[jasonliu]

Modify comments in test case.

[hubert.reinterpretcast]

LGTM.

llvm/lib/MC/MCAsmInfoXCOFF.cpp

 //===- MC/MCAsmInfoXCOFF.cpp - XCOFF asm properties ------------ *- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "llvm/MC/MCAsmInfoXCOFF.h"
 
 using namespace llvm;
 
 void MCAsmInfoXCOFF::anchor() {}
 
 MCAsmInfoXCOFF::MCAsmInfoXCOFF() {
   IsLittleEndian = false;
+  PrivateGlobalPrefix = "L..";
+  PrivateLabelPrefix = "L..";
   SupportsQuotedNames = false;
   UseDotAlignForAlignment = true;
   ZeroDirective = "\t.space\t";
   ZeroDirectiveSupportsNonZeroValue = false;
   AsciiDirective = nullptr; // not supported
   AscizDirective = nullptr; // not supported
 
   // Use .vbyte for data definition to avoid directives that apply an implicit

llvm/test/CodeGen/PowerPC/aix-cc-abi.ll

 ; 32BIT-DAG:  $f12 = COPY renamable $f1
 ; 32BIT-DAG:  $f13 = COPY renamable $f1
 ; 32BIT-NEXT: BL_NOP <mcsymbol .test_fpr_max>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $f1, implicit killed $f2, implicit killed $f3, implicit killed $f4, implicit killed $f5, implicit killed $f6, implicit killed $f7, implicit killed $f8, implicit killed $f9, implicit killed $f10, implicit killed $f11, implicit killed $f12, implicit killed $f13, implicit $r2, implicit-def $r1, implicit-def dead $f1
 ; 32BIT-NEXT: ADJCALLSTACKUP 128, 0, implicit-def dead $r1, implicit $r1
 
 ; CHECKASM-LABEL: .call_test_fpr_max:
 
 ; ASM32PWR4:       stwu 1, -128(1)
-; ASM32PWR4-NEXT:  lwz [[REG:[0-9]+]], LC2(2)
+; ASM32PWR4-NEXT:  lwz [[REG:[0-9]+]], L..C2(2)
 ; ASM32PWR4-NEXT:  lfd 1, 0([[REG]])
 ; ASM32PWR4-DAG:   stfd 1, 56(1)
 ; ASM32PWR4-DAG:   stfd 1, 64(1)
 ; ASM32PWR4-DAG:   stfd 1, 72(1)
 ; ASM32PWR4-DAG:   stfd 1, 80(1)
 ; ASM32PWR4-DAG:   stfd 1, 88(1)
 ; ASM32PWR4-DAG:   stfd 1, 96(1)
 ; ASM32PWR4-DAG:   stfd 1, 104(1)

 ; 64BIT-DAG:  $f10 = COPY renamable $f1
 ; 64BIT-DAG:  $f11 = COPY renamable $f1
 ; 64BIT-DAG:  $f12 = COPY renamable $f1
 ; 64BIT-DAG:  $f13 = COPY renamable $f1
 ; 64BIT-NEXT: BL8_NOP <mcsymbol .test_fpr_max>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $f1, implicit killed $f2, implicit killed $f3, implicit killed $f4, implicit killed $f5, implicit killed $f6, implicit killed $f7, implicit killed $f8, implicit killed $f9, implicit killed $f10, implicit killed $f11, implicit killed $f12, implicit killed $f13, implicit $x2, implicit-def $r1
 ; 64BIT-NEXT: ADJCALLSTACKUP 152, 0, implicit-def dead $r1, implicit $r1
 
 ; ASM64PWR4:       stdu 1, -160(1)
-; ASM64PWR4-NEXT:  ld [[REG:[0-9]+]], LC2(2)
+; ASM64PWR4-NEXT:  ld [[REG:[0-9]+]], L..C2(2)
 ; ASM64PWR4-NEXT:  lfd 1, 0([[REG]])
 ; ASM64PWR4-DAG:   stfd 1, 112(1)
 ; ASM64PWR4-DAG:   stfd 1, 120(1)
 ; ASM64PWR4-DAG:   stfd 1, 128(1)
 ; ASM64PWR4-DAG:   stfd 1, 136(1)
 ; ASM64PWR4-DAG:   stfd 1, 144(1)
 ; ASM64PWR4-DAG:   fmr 2, 1
 ; ASM64PWR4-DAG:   fmr 3, 1

 ; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
 ; 32BIT-NEXT: $r3 = LI 42
 ; 32BIT-NEXT: BL_NOP <mcsymbol .test_vararg>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $f1, implicit $r4, implicit $r5, implicit $f2, implicit $r6, implicit $r7, implicit $r2, implicit-def $r1
 ; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
 
 ; CHECKASM-LABEL: .call_test_vararg:
 
 ; ASM32PWR4:      stwu 1, -80(1)
-; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], LC1(2)
+; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], L..C1(2)
 ; ASM32PWR4-NEXT: lfs 1, 0([[REG]])
-; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], LC2(2)
+; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], L..C2(2)
 ; ASM32PWR4-NEXT: stfd 1, 64(1)
 ; ASM32PWR4-NEXT: lfd 2, 0([[REG]])
 ; ASM32PWR4-NEXT: li 3, 42
 ; ASM32PWR4-NEXT: stfd 2, 72(1)
 ; ASM32PWR4-DAG:  lwz 4, 64(1)
 ; ASM32PWR4-DAG:  lwz 5, 68(1)
 ; ASM32PWR4-DAG:  lwz 6, 72(1)
 ; ASM32PWR4-DAG:  lwz 7, 76(1)

 ; 64BIT-NEXT: STFD renamable $f2, 0, %stack.[[SLOT2:[0-9]+]] :: (store 8 into %stack.[[SLOT2]])
 ; 64BIT-NEXT: renamable $x5 = LD 0, %stack.[[SLOT2]] :: (load 8 from %stack.[[SLOT2]])
 ; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
 ; 64BIT-NEXT: $x3 = LI8 42
 ; 64BIT-NEXT: BL8_NOP <mcsymbol .test_vararg>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit $f2, implicit $x5, implicit $x2, implicit-def $r1
 ; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 ; ASM64PWR4:      stdu 1, -128(1)
-; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], LC1(2)
+; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], L..C1(2)
 ; ASM64PWR4-NEXT: lfs 1, 0([[REG]])
-; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], LC2(2)
+; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], L..C2(2)
 ; ASM64PWR4-NEXT: stfd 1, 112(1)
 ; ASM64PWR4-NEXT: lfd 2, 0([[REG]])
 ; ASM64PWR4-NEXT: li 3, 42
 ; ASM64PWR4-NEXT: stfd 2, 120(1)
 ; ASM64PWR4-NEXT: ld 4, 112(1)
 ; ASM64PWR4-NEXT: ld 5, 120(1)
 ; ASM64PWR4-NEXT: bl .test_vararg
 ; ASM64PWR4-NEXT: nop

 ; 32BIT-NEXT: renamable $r8 = LWZ 4, %stack.[[SLOT2]] :: (load 4 from %stack.[[SLOT2]] + 4)
 ; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
 ; 32BIT-NEXT: $r3 = LI 42
 ; 32BIT-NEXT: $r6 = LI 42
 ; 32BIT-NEXT: BL_NOP <mcsymbol .test_vararg>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $f1, implicit $r4, implicit $r5, implicit killed $r6, implicit $f2, implicit $r7, implicit $r8, implicit $r2, implicit-def $r1
 ; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
 
 ; ASM32PWR4:      stwu 1, -80(1)
-; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], LC1(2)
+; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], L..C1(2)
 ; ASM32PWR4-NEXT: li 6, 42
 ; ASM32PWR4-NEXT: lfs 1, 0([[REG]])
-; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], LC2(2)
+; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], L..C2(2)
 ; ASM32PWR4-NEXT: stfd 1, 64(1)
 ; ASM32PWR4-NEXT: lfd 2, 0([[REG]])
 ; ASM32PWR4-NEXT: li 3, 42
 ; ASM32PWR4-NEXT: stfd 2, 72(1)
 ; ASM32PWR4-DAG: lwz 4, 64(1)
 ; ASM32PWR4-DAG: lwz 5, 68(1)
 ; ASM32PWR4-DAG: lwz 7, 72(1)
 ; ASM32PWR4-DAG: lwz 8, 76(1)

 ; 64BIT-NEXT: renamable $x6 = LD 0, %stack.[[SLOT2]] :: (load 8 from %stack.[[SLOT2]])
 ; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
 ; 64BIT-NEXT: $x3 = LI8 42
 ; 64BIT-NEXT: $x5 = LI8 42
 ; 64BIT-NEXT: BL8_NOP <mcsymbol .test_vararg>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit killed $x5, implicit $f2, implicit $x6, implicit $x2, implicit-def $r1
 ; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 ; ASM64PWR4:      stdu 1, -128(1)
-; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], LC1(2)
+; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], L..C1(2)
 ; ASM64PWR4-NEXT: li 5, 42
 ; ASM64PWR4-NEXT: lfs 1, 0([[REG]])
-; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], LC2(2)
+; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], L..C2(2)
 ; ASM64PWR4-NEXT: stfd 1, 112(1)
 ; ASM64PWR4-NEXT: lfd 2, 0([[REG]])
 ; ASM64PWR4-NEXT: li 3, 42
 ; ASM64PWR4-NEXT: stfd 2, 120(1)
 ; ASM64PWR4-NEXT: ld 4, 112(1)
 ; ASM64PWR4-NEXT: ld 6, 120(1)
 ; ASM64PWR4-NEXT: bl .test_vararg
 ; ASM64PWR4-NEXT: nop

 ; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
 ; 32BIT-NEXT: $r3 = LI 42
 ; 32BIT-NEXT: $r6 = LI 0
 ; 32BIT-NEXT: $r7 = LI 42
 ; 32BIT-NEXT: BL_NOP <mcsymbol .test_vararg>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $f1, implicit $r4, implicit $r5, implicit killed $r6, implicit killed $r7, implicit $f2, implicit $r8, implicit $r9, implicit $r2, implicit-def $r1
 ; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
 
 ; ASM32PWR4:      stwu 1, -80(1)
-; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], LC1(2)
+; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], L..C1(2)
 ; ASM32PWR4-DAG:  li 6, 0
 ; ASM32PWR4-DAG:  li 7, 42
 ; ASM32PWR4-NEXT: lfs 1, 0([[REG]])
-; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], LC2(2)
+; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], L..C2(2)
 ; ASM32PWR4-NEXT: stfd 1, 64(1)
 ; ASM32PWR4-NEXT: lfd 2, 0([[REG]])
 ; ASM32PWR4-NEXT: li 3, 42
 ; ASM32PWR4-NEXT: stfd 2, 72(1)
 ; ASM32PWR4-DAG:  lwz 4, 64(1)
 ; ASM32PWR4-DAG:  lwz 5, 68(1)
 ; ASM32PWR4-DAG:  lwz 8, 72(1)
 ; ASM32PWR4-DAG:  lwz 9, 76(1)

 ; 64BIT-NEXT: renamable $x6 = LD 0, %stack.[[SLOT2]] :: (load 8 from %stack.[[SLOT2]])
 ; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
 ; 64BIT-NEXT: $x3 = LI8 42
 ; 64BIT-NEXT: $x5 = LI8 42
 ; 64BIT-NEXT: BL8_NOP <mcsymbol .test_vararg>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit killed $x5, implicit $f2, implicit $x6, implicit $x2, implicit-def $r1
 ; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 ; ASM64PWR4:      stdu 1, -128(1)
-; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], LC1(2)
+; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], L..C1(2)
 ; ASM64PWR4-NEXT: li 5, 42
 ; ASM64PWR4-NEXT: lfs 1, 0([[REG]])
-; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], LC2(2)
+; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], L..C2(2)
 ; ASM64PWR4-NEXT: stfd 1, 112(1)
 ; ASM64PWR4-NEXT: lfd 2, 0([[REG]])
 ; ASM64PWR4-NEXT: li 3, 42
 ; ASM64PWR4-NEXT: stfd 2, 120(1)
 ; ASM64PWR4-DAG:  ld 4, 112(1)
 ; ASM64PWR4-DAG:  ld 6, 120(1)
 ; ASM64PWR4-NEXT: bl .test_vararg
 ; ASM64PWR4-NEXT: nop

 ; 32BIT-NEXT: STFS renamable $f1, 0, %stack.[[SLOT:[0-9]+]] :: (store 4 into %stack.[[SLOT]])
 ; 32BIT-NEXT: renamable $r4 = LWZ 0, %stack.[[SLOT]] :: (load 4 from %stack.[[SLOT]])
 ; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
 ; 32BIT-NEXT: $r3 = LI 42
 ; 32BIT-NEXT: BL_NOP <mcsymbol .test_vararg>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $f1, implicit $r4, implicit $r2, implicit-def $r1
 ; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
 
 ; ASM32PWR4:      stwu 1, -64(1)
-; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], LC1(2)
+; ASM32PWR4-NEXT: lwz [[REG:[0-9]+]], L..C1(2)
 ; ASM32PWR4-NEXT: lfs 1, 0([[REG]])
 ; ASM32PWR4-NEXT: li 3, 42
 ; ASM32PWR4-NEXT: stfs 1, 60(1)
 ; ASM32PWR4-NEXT: lwz 4, 60(1)
 ; ASM32PWR4-NEXT: bl .test_vararg
 ; ASM32PWR4-NEXT: nop
 
 ; 64BIT:      renamable $x[[REG:[0-9]+]] = LDtoc @f1, $x2 :: (load 8 from got)
 ; 64BIT-NEXT: renamable $f1 = LFS 0, killed renamable $x[[REG]] :: (dereferenceable load 4 from @f1)
 ; 64BIT-NEXT: STFS renamable $f1, 0, %stack.[[SLOT:[0-9]+]] :: (store 4 into %stack.[[SLOT]])
 ; 64BIT-NEXT: renamable $x4 = LWZ8 0, %stack.[[SLOT]] :: (load 4 from %stack.[[SLOT]])
 ; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
 ; 64BIT-NEXT: $x3 = LI8 42
 ; 64BIT-NEXT: BL8_NOP <mcsymbol .test_vararg>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit $x2, implicit-def $r1
 ; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 ; ASM64PWR4:      stdu 1, -128(1)
-; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], LC1(2)
+; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], L..C1(2)
 ; ASM64PWR4-NEXT: lfs 1, 0([[REG]])
 ; ASM64PWR4-NEXT: li 3, 42
 ; ASM64PWR4-NEXT: stfs 1, 124(1)
 ; ASM64PWR4-NEXT: lwz 4, 124(1)
 ; ASM64PWR4-NEXT: bl .test_vararg
 ; ASM64PWR4-NEXT: nop
 
 @c = common global i8 0, align 1

 ; ASM32PWR4-DAG:   li 3, 1
 ; ASM32PWR4-DAG:   li 4, 2
 ; ASM32PWR4-DAG:   li 5, 3
 ; ASM32PWR4-DAG:   li 6, 4
 ; ASM32PWR4-DAG:   li 7, 5
 ; ASM32PWR4-DAG:   li 8, 6
 ; ASM32PWR4-DAG:   li 9, 7
 ; ASM32PWR4-DAG:   li 10, 8
-; ASM32PWR4-DAG:   lwz [[REGCADDR:[0-9]+]], LC6(2)
+; ASM32PWR4-DAG:   lwz [[REGCADDR:[0-9]+]], L..C6(2)
 ; ASM32PWR4-DAG:   lbz [[REGC:[0-9]+]], 0([[REGCADDR]])
 ; ASM32PWR4-DAG:   stw [[REGC]], 56(1)
-; ASM32PWR4-DAG:   lwz [[REGSIADDR:[0-9]+]], LC4(2)
+; ASM32PWR4-DAG:   lwz [[REGSIADDR:[0-9]+]], L..C4(2)
 ; ASM32PWR4-DAG:   lha [[REGSI:[0-9]+]], 0([[REGSIADDR]])
 ; ASM32PWR4-DAG:   stw [[REGSI]], 60(1)
-; ASM32PWR4-DAG:   lwz [[REGIADDR:[0-9]+]], LC5(2)
+; ASM32PWR4-DAG:   lwz [[REGIADDR:[0-9]+]], L..C5(2)
 ; ASM32PWR4-DAG:   lwz [[REGI:[0-9]+]], 0([[REGIADDR]])
 ; ASM32PWR4-DAG:   stw [[REGI]], 64(1)
-; ASM32PWR4-DAG:   lwz [[REGLLIADDR:[0-9]+]], LC7(2)
+; ASM32PWR4-DAG:   lwz [[REGLLIADDR:[0-9]+]], L..C7(2)
 ; ASM32PWR4-DAG:   lwz [[REGLLI1:[0-9]+]], 0([[REGLLIADDR]])
 ; ASM32PWR4-DAG:   stw [[REGLLI1]], 68(1)
 ; ASM32PWR4-DAG:   lwz [[REGLLI2:[0-9]+]], 4([[REGLLIADDR]])
 ; ASM32PWR4-DAG:   stw [[REGLLI2]], 72(1)
 ; ASM32PWR4-DAG:   stw [[REGI]], 76(1)
 ; ASM32PWR4-NEXT:  bl .test_stackarg_int
 ; ASM32PWR4-NEXT:  nop
 

 ; ASM64PWR4-DAG:   li 3, 1
 ; ASM64PWR4-DAG:   li 4, 2
 ; ASM64PWR4-DAG:   li 5, 3
 ; ASM64PWR4-DAG:   li 6, 4
 ; ASM64PWR4-DAG:   li 7, 5
 ; ASM64PWR4-DAG:   li 8, 6
 ; ASM64PWR4-DAG:   li 9, 7
 ; ASM64PWR4-DAG:   li 10, 8
-; ASM64PWR4-DAG:   ld [[REGCADDR:[0-9]+]], LC5(2)
+; ASM64PWR4-DAG:   ld [[REGCADDR:[0-9]+]], L..C5(2)
 ; ASM64PWR4-DAG:   lbz [[REGC:[0-9]+]], 0([[REGCADDR]])
 ; ASM64PWR4-DAG:   std [[REGC]], 112(1)
-; ASM64PWR4-DAG:   ld [[REGSIADDR:[0-9]+]], LC3(2)
+; ASM64PWR4-DAG:   ld [[REGSIADDR:[0-9]+]], L..C3(2)
 ; ASM64PWR4-DAG:   lha [[REGSI:[0-9]+]], 0([[REGSIADDR]])
 ; ASM64PWR4-DAG:   std [[REGSI]], 120(1)
-; ASM64PWR4-DAG:   ld [[REGIADDR:[0-9]+]], LC4(2)
+; ASM64PWR4-DAG:   ld [[REGIADDR:[0-9]+]], L..C4(2)
 ; ASM64PWR4-DAG:   lwz [[REGI:[0-9]+]], 0([[REGIADDR]])
 ; ASM64PWR4-DAG:   std [[REGI]], 128(1)
-; ASM64PWR4-DAG:   ld [[REGLLIADDR:[0-9]+]], LC6(2)
+; ASM64PWR4-DAG:   ld [[REGLLIADDR:[0-9]+]], L..C6(2)
 ; ASM64PWR4-DAG:   ld [[REGLLI:[0-9]+]], 0([[REGLLIADDR]])
 ; ASM64PWR4-DAG:   std [[REGLLI]], 136(1)
 ; ASM64PWR4-DAG:   std [[REGI]], 144(1)
 ; ASM64PWR4-NEXT:  bl .test_stackarg_int
 ; ASM64PWR4-NEXT:  nop
 
 ; Basic saving of floating point type arguments to the parameter save area.
 ; The float and double arguments will pass in both fpr as well as parameter save area.

 ; ASM32PWR4-DAG:  li 3, 1
 ; ASM32PWR4-DAG:  li 4, 2
 ; ASM32PWR4-DAG:  li 5, 3
 ; ASM32PWR4-DAG:  li 6, 4
 ; ASM32PWR4-DAG:  li 7, 5
 ; ASM32PWR4-DAG:  li 8, 6
 ; ASM32PWR4-DAG:  li 9, 7
 ; ASM32PWR4-DAG:  li 10, 8
-; ASM32PWR4-DAG:  lwz [[REGF:[0-9]+]], LC8(2)
+; ASM32PWR4-DAG:  lwz [[REGF:[0-9]+]], L..C8(2)
 ; ASM32PWR4-DAG:  lfs 1, 0([[REGF]])
-; ASM32PWR4-DAG:  lwz [[REGD:[0-9]+]], LC9(2)
+; ASM32PWR4-DAG:  lwz [[REGD:[0-9]+]], L..C9(2)
 ; ASM32PWR4-DAG:  lfd 2, 0([[REGD:[0-9]+]])
 ; ASM32PWR4-DAG:  stfs 1, 56(1)
 ; ASM32PWR4-DAG:  stfd 2, 60(1)
 ; ASM32PWR4-NEXT: bl .test_stackarg_float
 ; ASM32PWR4-NEXT: nop
 ; ASM32PWR4-NEXT: addi 1, 1, 80
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.

 ; ASM64PWR4-DAG:  li 3, 1
 ; ASM64PWR4-DAG:  li 4, 2
 ; ASM64PWR4-DAG:  li 5, 3
 ; ASM64PWR4-DAG:  li 6, 4
 ; ASM64PWR4-DAG:  li 7, 5
 ; ASM64PWR4-DAG:  li 8, 6
 ; ASM64PWR4-DAG:  li 9, 7
 ; ASM64PWR4-DAG:  li 10, 8
-; ASM64PWR4-DAG:  ld [[REGF:[0-9]+]], LC7(2)
+; ASM64PWR4-DAG:  ld [[REGF:[0-9]+]], L..C7(2)
 ; ASM64PWR4-DAG:  lfs 1, 0([[REGF]])
-; ASM64PWR4-DAG:  ld [[REGD:[0-9]+]], LC8(2)
+; ASM64PWR4-DAG:  ld [[REGD:[0-9]+]], L..C8(2)
 ; ASM64PWR4-DAG:  lfd 2, 0([[REGD]])
 ; ASM64PWR4-DAG:  stfs 1, 112(1)
 ; ASM64PWR4-DAG:  stfd 2, 120(1)
 ; ASM64PWR4-NEXT: bl .test_stackarg_float
 ; ASM64PWR4-NEXT: nop
 ; ASM64PWR4-NEXT: addi 1, 1, 128
 
 define void @call_test_stackarg_float2() {

 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; ASM32PWR4:     stwu 1, -64(1)
 ; ASM32PWR4-DAG: li 3, 1
 ; ASM32PWR4-DAG: li 4, 2
 ; ASM32PWR4-DAG: li 5, 3
 ; ASM32PWR4-DAG: li 6, 4
 ; ASM32PWR4-DAG: li 7, 5
 ; ASM32PWR4-DAG: li 8, 6
-; ASM32PWR4-DAG: lwz [[REG:[0-9]+]], LC9(2)
+; ASM32PWR4-DAG: lwz [[REG:[0-9]+]], L..C9(2)
 ; ASM32PWR4-DAG: lfd 1, 0([[REG]])
 ; ASM32PWR4-DAG: stfd 1, 56(1)
 ; ASM32PWR4-DAG: lwz 9, 56(1)
 ; ASM32PWR4-DAG: lwz 10, 60(1)
 ; ASM32PWR4-NEXT: bl .test_stackarg_float2
 ; ASM32PWR4-NEXT: nop
 ; ASM32PWR4-NEXT: addi 1, 1, 64
 

 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; ASM64PWR4:     stdu 1, -128(1)
 ; ASM64PWR4-DAG: li 3, 1
 ; ASM64PWR4-DAG: li 4, 2
 ; ASM64PWR4-DAG: li 5, 3
 ; ASM64PWR4-DAG: li 6, 4
 ; ASM64PWR4-DAG: li 7, 5
 ; ASM64PWR4-DAG: li 8, 6
-; ASM64PWR4-DAG: ld [[REG:[0-9]+]], LC8(2)
+; ASM64PWR4-DAG: ld [[REG:[0-9]+]], L..C8(2)
 ; ASM64PWR4-DAG: lfd 1, 0([[REG]])
 ; ASM64PWR4-DAG: stfd 1, 120(1)
 ; ASM64PWR4-DAG: ld 9, 120(1)
 ; ASM64PWR4-NEXT: bl .test_stackarg_float2
 ; ASM64PWR4-NEXT: nop
 ; ASM64PWR4-NEXT: addi 1, 1, 128
 
 ; A double arg will pass on the stack in PPC32 if there is only one available GPR.

 ; ASM32PWR4:       stwu 1, -80(1)
 ; ASM32PWR4-DAG:   li 3, 1
 ; ASM32PWR4-DAG:   li 4, 2
 ; ASM32PWR4-DAG:   li 5, 3
 ; ASM32PWR4-DAG:   li 6, 4
 ; ASM32PWR4-DAG:   li 7, 5
 ; ASM32PWR4-DAG:   li 8, 6
 ; ASM32PWR4-DAG:   li 9, 7
-; ASM32PWR4-DAG:   lwz [[REGD:[0-9]+]], LC9(2)
+; ASM32PWR4-DAG:   lwz [[REGD:[0-9]+]], L..C9(2)
 ; ASM32PWR4-DAG:   lfd 1, 0([[REGD]])
-; ASM32PWR4-DAG:   lwz [[REGF:[0-9]+]], LC8(2)
+; ASM32PWR4-DAG:   lwz [[REGF:[0-9]+]], L..C8(2)
 ; ASM32PWR4-DAG:   lfs 2, 0([[REGF]])
 ; ASM32PWR4-DAG:   stfd 1, 52(1)
 ; ASM32PWR4-DAG:   stfs 2, 60(1)
 ; ASM32PWR4-DAG:   stfd 1, 72(1)
 ; ASM32PWR4-DAG:   lwz 10, 72(1)
 ; ASM32PWR4-NEXT:  bl .test_stackarg_float3
 ; ASM32PWR4-NEXT:  nop
 ; ASM32PWR4-NEXT:  addi 1, 1, 80

 ; ASM64PWR4:       stdu 1, -128(1)
 ; ASM64PWR4-DAG:   li 3, 1
 ; ASM64PWR4-DAG:   li 4, 2
 ; ASM64PWR4-DAG:   li 5, 3
 ; ASM64PWR4-DAG:   li 6, 4
 ; ASM64PWR4-DAG:   li 7, 5
 ; ASM64PWR4-DAG:   li 8, 6
 ; ASM64PWR4-DAG:   li 9, 7
-; ASM64PWR4-DAG:   ld [[REGD:[0-9]+]], LC8(2)
+; ASM64PWR4-DAG:   ld [[REGD:[0-9]+]], L..C8(2)
 ; ASM64PWR4-DAG:   lfd 1, 0([[REGD]])
-; ASM64PWR4-DAG:   ld [[REGF:[0-9]+]], LC7(2)
+; ASM64PWR4-DAG:   ld [[REGF:[0-9]+]], L..C7(2)
 ; ASM64PWR4-DAG:   lfs 2, 0([[REGF]])
 ; ASM64PWR4-DAG:   stfs 2, 112(1)
 ; ASM64PWR4-DAG:   stfd 1, 120(1)
 ; ASM64PWR4-DAG:   ld 10, 120(1)
 ; ASM64PWR4-NEXT:  bl .test_stackarg_float3
 ; ASM64PWR4-NEXT:  nop
 ; ASM64PWR4-NEXT:  addi 1, 1, 128
 

 ; ASM32PWR4-DAG:    li 3, 1
 ; ASM32PWR4-DAG:    li 4, 2
 ; ASM32PWR4-DAG:    li 5, 3
 ; ASM32PWR4-DAG:    li 6, 4
 ; ASM32PWR4-DAG:    li 7, 5
 ; ASM32PWR4-DAG:    li 9, 7
 ; ASM32PWR4-DAG:    li 8, 6
 ; ASM32PWR4-DAG:    li 10, 8
-; ASM32PWR4-DAG:    lwz [[REG1:[0-9]+]], LC10(2)
-; ASM32PWR4-DAG:    lwz [[REG2:[0-9]+]], LC11(2)
-; ASM32PWR4-DAG:    lwz [[REG3:[0-9]+]], LC12(2)
-; ASM32PWR4-DAG:    lwz [[REG4:[0-9]+]], LC13(2)
-; ASM32PWR4-DAG:    lwz [[REG5:[0-9]+]], LC14(2)
-; ASM32PWR4-DAG:    lwz [[REG6:[0-9]+]], LC15(2)
-; ASM32PWR4-DAG:    lwz [[REG7:[0-9]+]], LC16(2)
-; ASM32PWR4-DAG:    lwz [[REG8:[0-9]+]], LC17(2)
+; ASM32PWR4-DAG:    lwz [[REG1:[0-9]+]], L..C10(2)
+; ASM32PWR4-DAG:    lwz [[REG2:[0-9]+]], L..C11(2)
+; ASM32PWR4-DAG:    lwz [[REG3:[0-9]+]], L..C12(2)
+; ASM32PWR4-DAG:    lwz [[REG4:[0-9]+]], L..C13(2)
+; ASM32PWR4-DAG:    lwz [[REG5:[0-9]+]], L..C14(2)
+; ASM32PWR4-DAG:    lwz [[REG6:[0-9]+]], L..C15(2)
+; ASM32PWR4-DAG:    lwz [[REG7:[0-9]+]], L..C16(2)
+; ASM32PWR4-DAG:    lwz [[REG8:[0-9]+]], L..C17(2)
 ; ASM32PWR4-DAG:    lha 5, 0([[REG1]])
 ; ASM32PWR4-DAG:    lwz 11, 0([[REG7]])
 ; ASM32PWR4-DAG:    lwz 7, 4([[REG7]])
 ; ASM32PWR4-DAG:    lbz 4, 0([[REG2]])
 ; ASM32PWR4-DAG:    lwz 3, 0([[REG8]])
 ; ASM32PWR4-DAG:    lwz 6, 0([[REG3]])
 ; ASM32PWR4-DAG:    lwz 9, 0([[REG4]])
 ; ASM32PWR4-DAG:    lwz 8, 4([[REG4]])

 ; ASM64PWR4-DAG:    li 3, 1
 ; ASM64PWR4-DAG:    li 4, 2
 ; ASM64PWR4-DAG:    li 5, 3
 ; ASM64PWR4-DAG:    li 6, 4
 ; ASM64PWR4-DAG:    li 7, 5
 ; ASM64PWR4-DAG:    li 8, 6
 ; ASM64PWR4-DAG:    li 9, 7
 ; ASM64PWR4-DAG:    li 10, 8
-; ASM64PWR4-DAG:    ld [[REG1:[0-9]+]], LC9(2)
-; ASM64PWR4-DAG:    ld [[REG2:[0-9]+]], LC10(2)
-; ASM64PWR4-DAG:    ld [[REG3:[0-9]+]], LC11(2)
-; ASM64PWR4-DAG:    ld [[REG4:[0-9]+]], LC12(2)
-; ASM64PWR4-DAG:    ld [[REG5:[0-9]+]], LC13(2)
-; ASM64PWR4-DAG:    ld [[REG6:[0-9]+]], LC14(2)
-; ASM64PWR4-DAG:    ld [[REG7:[0-9]+]], LC15(2)
-; ASM64PWR4-DAG:    ld [[REG8:[0-9]+]], LC16(2)
+; ASM64PWR4-DAG:    ld [[REG1:[0-9]+]], L..C9(2)
+; ASM64PWR4-DAG:    ld [[REG2:[0-9]+]], L..C10(2)
+; ASM64PWR4-DAG:    ld [[REG3:[0-9]+]], L..C11(2)
+; ASM64PWR4-DAG:    ld [[REG4:[0-9]+]], L..C12(2)
+; ASM64PWR4-DAG:    ld [[REG5:[0-9]+]], L..C13(2)
+; ASM64PWR4-DAG:    ld [[REG6:[0-9]+]], L..C14(2)
+; ASM64PWR4-DAG:    ld [[REG7:[0-9]+]], L..C15(2)
+; ASM64PWR4-DAG:    ld [[REG8:[0-9]+]], L..C16(2)
 ; ASM64PWR4-DAG:    lha 7, 0([[REG1]])
 ; ASM64PWR4-DAG:    lbz 5, 0([[REG2]])
 ; ASM64PWR4-DAG:    ld 6, 0([[REG3]])
 ; ASM64PWR4-DAG:    lbz 8, 0([[REG4]])
 ; ASM64PWR4-DAG:    lwz 9, 0([[REG5]])
 ; ASM64PWR4-DAG:    ld 11, 0([[REG6]])
 ; ASM64PWR4-DAG:    lwz 3, 0([[REG7]])
 ; ASM64PWR4-DAG:    lwz 4, 0([[REG8]])

 ; 64BIT-DAG:       renamable $r[[REGB:[0-9]+]] = LBZ 0, %fixed-stack.0 :: (load 1 from %fixed-stack.0)
 ; 64BIT-DAG:       renamable $x[[REGBTOC:[0-9]+]] = LDtoc @globali1, $x2 :: (load 8 from got)
 ; 64BIT-DAG:       STB killed renamable $r[[SCRATCHREG:[0-9]+]], 0, killed renamable $x[[REGBTOC]] :: (store 1 into @globali1)
 ; 64BIT-DAG:       BLR8 implicit $lr8, implicit $rm
 
 ; CHECKASM-LABEL:  test_i1_stack:
 
 ; ASM32PWR4-DAG:   lbz [[REGB:[0-9]+]], 59(1)
-; ASM32PWR4-DAG:   lwz [[REGBTOC:[0-9]+]], LC18(2)
+; ASM32PWR4-DAG:   lwz [[REGBTOC:[0-9]+]], L..C18(2)
 ; ASM32PWR4-DAG:   stb [[SCRATCHREG:[0-9]+]], 0([[REGBTOC]])
 ; ASM32PWR4-DAG:   blr
 
 ; ASM64PWR4-DAG:   lbz [[REGB:[0-9]+]], 119(1)
-; ASM64PWR4-DAG:   ld [[REGBTOC:[0-9]+]], LC17(2)
+; ASM64PWR4-DAG:   ld [[REGBTOC:[0-9]+]], L..C17(2)
 ; ASM64PWR4-DAG:   stb [[SCRATCHREG:[0-9]+]], 0([[REGBTOC]])
 ; ASM64PWR4-DAG:   blr
 
 define void @call_test_i1_stack() {
   entry:
     call void @test_i1_stack(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i1 true)
     ret void
 }

 ; 64BIT-NEXT:   ADJCALLSTACKUP 176, 0, implicit-def dead $r1, implicit $r1
 ; 64BIT-NEXT:   BLR8 implicit $lr8, implicit $rm
 
 ; CHECKASM-LABEL:  .caller_fpr_stack:
 
 ; ASM32PWR4:       mflr 0
 ; ASM32PWR4-DAG:   stw 0, 8(1)
 ; ASM32PWR4-DAG:   stwu 1, -144(1)
-; ASM32PWR4-DAG:   lwz [[REGF1ADDR:[0-9]+]], LC20(2)
+; ASM32PWR4-DAG:   lwz [[REGF1ADDR:[0-9]+]], L..C20(2)
 ; ASM32PWR4-DAG:   lwz [[REGF1:[0-9]+]], 0([[REGF1ADDR]])
-; ASM32PWR4-DAG:   lwz [[REGDADDR:[0-9]+]], LC19(2)
+; ASM32PWR4-DAG:   lwz [[REGDADDR:[0-9]+]], L..C19(2)
 ; ASM32PWR4-DAG:   lfd [[REGD:[0-9]+]], 0([[REGDADDR]])
-; ASM32PWR4-DAG:   lwz [[REGF2ADDR:[0-9]+]], LC21(2)
+; ASM32PWR4-DAG:   lwz [[REGF2ADDR:[0-9]+]], L..C21(2)
 ; ASM32PWR4-DAG:   lwz [[REGF2:[0-9]+]], 0([[REGF2ADDR]])
 ; ASM32PWR4-DAG:   stw [[SCRATCHREG:[0-9]+]], 56(1)
 ; ASM32PWR4-DAG:   stw [[SCRATCHREG:[0-9]+]], 60(1)
 ; ASM32PWR4-DAG:   stw [[SCRATCHREG:[0-9]+]], 64(1)
 ; ASM32PWR4-DAG:   stw [[SCRATCHREG:[0-9]+]], 68(1)
 ; ASM32PWR4-DAG:   stw [[SCRATCHREG:[0-9]+]], 72(1)
 ; ASM32PWR4-DAG:   stw [[SCRATCHREG:[0-9]+]], 76(1)
 ; ASM32PWR4-DAG:   stw [[SCRATCHREG:[0-9]+]], 80(1)

 ; ASM32PWR4-DAG:   stw [[REGF1]], 128(1)
 ; ASM32PWR4-DAG:   stfd [[REGD]], 132(1)
 ; ASM32PWR4-DAG:   stw [[REGF2]], 140(1)
 ; ASM32PWR4-NEXT:  bl .test_fpr_stack
 
 ; ASM64PWR4:       mflr 0
 ; ASM64PWR4-DAG:   std 0, 16(1)
 ; ASM64PWR4-DAG:   stdu 1, -176(1)
-; ASM64PWR4-DAG:   ld [[REGF1ADDR:[0-9]+]], LC18(2)
+; ASM64PWR4-DAG:   ld [[REGF1ADDR:[0-9]+]], L..C18(2)
 ; ASM64PWR4-DAG:   lwz [[REGF1:[0-9]+]], 0([[REGF1ADDR]])
-; ASM64PWR4-DAG:   ld [[REGDADDR:[0-9]+]], LC19(2)
+; ASM64PWR4-DAG:   ld [[REGDADDR:[0-9]+]], L..C19(2)
 ; ASM64PWR4-DAG:   ld [[REGD:[0-9]+]], 0([[REGDADDR]])
-; ASM64PWR4-DAG:   ld [[REGF2ADDR:[0-9]+]], LC20(2)
+; ASM64PWR4-DAG:   ld [[REGF2ADDR:[0-9]+]], L..C20(2)
 ; ASM64PWR4-DAG:   lwz [[REGF2:[0-9]+]], 0([[REGF2ADDR]])
 ; ASM64PWR4-DAG:   std [[SCRATCHREG:[0-9]+]], 112(1)
 ; ASM64PWR4-DAG:   std [[SCRATCHREG:[0-9]+]], 120(1)
 ; ASM64PWR4-DAG:   std [[SCRATCHREG:[0-9]+]], 128(1)
 ; ASM64PWR4-DAG:   std [[SCRATCHREG:[0-9]+]], 136(1)
 ; ASM64PWR4-DAG:   std [[SCRATCHREG:[0-9]+]], 144(1)
 ; ASM64PWR4-DAG:   stw [[REGF1]], 152(1)
 ; ASM64PWR4-DAG:   std [[REGD]], 160(1)

llvm/test/CodeGen/PowerPC/aix-cc-byval-mem.ll

entry:
   %call = call zeroext i8 @test_byval_mem1(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, %struct_S1* byval(%struct_S1) align 1 @gS1)
   ret void
 }
 
 
 ; CHECKASM-LABEL: .call_test_byval_mem1:
 
 ; ASM32BIT:       stwu 1, -64(1)
-; ASM32BIT:       lwz [[REG1:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM32BIT:       lwz [[REG1:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM32BIT:       lbz [[REG2:[0-9]+]], 0([[REG1]])
 ; ASM32BIT:       stb [[REG2]], 56(1)
 ; ASM32BIT:       bl .test_byval_mem1
 ; ASM32BIT:       addi 1, 1, 64
 
 ; ASM64BIT:       stdu 1, -128(1)
-; ASM64BIT:       ld [[REG1:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM64BIT:       ld [[REG1:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM64BIT:       lbz [[REG2:[0-9]+]], 0([[REG1]])
 ; ASM64BIT:       stb [[REG2]], 112(1)
 ; ASM64BIT:       bl .test_byval_mem1
 ; ASM64BIT:       addi 1, 1, 128
 
 define zeroext  i8 @test_byval_mem1(i32, i32, i32, i32, i32, i32, i32, i32, %struct_S1* byval(%struct_S1) align 1 %s) {
 entry:
   %gep = getelementptr inbounds %struct_S1, %struct_S1* %s, i32 0, i32 0

 ; 32BIT-DAG:      $r10 = COPY %{{[0-9]+}}
 ; 32BIT-NEXT:     BL_NOP <mcsymbol .test_byval_mem2>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r6, implicit $r7, implicit $r8, implicit $r9, implicit $r10, implicit $r2, implicit-def $r1
 ; 32BIT-NEXT:     ADJCALLSTACKUP 312, 0, implicit-def dead $r1, implicit $r1
 
 ; CHECKASM-LABEL: .call_test_byval_mem2:
 
 ; ASM32BIT:       stwu 1, -320(1)
 ; ASM32BIT-DAG:   addi 3, 1, 56
-; ASM32BIT-DAG:   lwz 4, LC{{[0-9]+}}(2)
+; ASM32BIT-DAG:   lwz 4, L..C{{[0-9]+}}(2)
 ; ASM32BIT-DAG:   li 5, 256
 ; ASM32BIT-NEXT:  bl .memcpy
 ; ASM32BIT:       bl .test_byval_mem2
 ; ASM32BIT:       addi 1, 1, 320
 
 ; Confirm the expected memcpy call is independent of the call to test_byval_mem2.
 ; 64BIT:          ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
 ; 64BIT-NEXT:     %0:g8rc = nuw ADDI8 $x1, 112

 ; 64BIT-DAG:      $x8 = COPY %{{[0-9]+}}
 ; 64BIT-DAG:      $x9 = COPY %{{[0-9]+}}
 ; 64BIT-DAG:      $x10 = COPY %{{[0-9]+}}
 ; 64BIT-NEXT:     BL8_NOP <mcsymbol .test_byval_mem2>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit $x8, implicit $x9, implicit $x10, implicit $x2, implicit-def $r1
 ; 64BIT-NEXT:     ADJCALLSTACKUP 368, 0, implicit-def dead $r1, implicit $r1
 
 ; ASM64BIT:       stdu 1, -368(1)
 ; ASM64BIT-DAG:   addi 3, 1, 112
-; ASM64BIT-DAG:   ld 4, LC{{[0-9]+}}(2)
+; ASM64BIT-DAG:   ld 4, L..C{{[0-9]+}}(2)
 ; ASM64BIT-DAG:   li 5, 256
 ; ASM64BIT-NEXT:  bl .memcpy
 ; ASM64BIT:       bl .test_byval_mem2
 ; ASM64BIT:       addi 1, 1, 368
 
 
 define zeroext i8 @test_byval_mem2(i32, i32, i32, i32, i32, i32, i32, i32, %struct_S256* byval(%struct_S256) align 1 %s) {
 entry:

 ; 32BIT-DAG:      $r9 = COPY %{{[0-9]+}}
 ; 32BIT-DAG:      $r10 = COPY %{{[0-9]+}}
 ; 32BIT-NEXT:     BL_NOP <mcsymbol .test_byval_mem3>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $f1, implicit $r5, implicit $r6, implicit $r7, implicit $r8, implicit $r9, implicit $r10, implicit $r2, implicit-def $r1
 ; 32BIT-NEXT:     ADJCALLSTACKUP 92, 0, implicit-def dead $r1, implicit $r1
 
 ; CHECKASM-LABEL: .call_test_byval_mem3:
 
 ; ASM32BIT:       stwu 1, -112(1)
-; ASM32BIT-DAG:   lwz [[REG:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM32BIT-DAG:   lwz [[REG:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM32BIT-DAG:   addi 3, 1, 56
 ; ASM32BIT-DAG:   addi 4, [[REG]], 24
 ; ASM32BIT-DAG:   li 5, 33
 ; ASM32BIT-NEXT:  bl .memcpy
 ; ASM32BIT-DAG:   lwz 5, 0([[REG]])
 ; ASM32BIT-DAG:   lwz 6, 4([[REG]])
 ; ASM32BIT-DAG:   lwz 7, 8([[REG]])
 ; ASM32BIT-DAG:   lwz 8, 12([[REG]])
 ; ASM32BIT-DAG:   lwz 9, 16([[REG]])
 ; ASM32BIT-DAG:   lwz 10, 20([[REG]])
 ; ASM32BIT:       bl .test_byval_mem3
 ; ASM32BIT:       addi 1, 1, 112
 
 ; The memcpy call was inlined in 64-bit so MIR test is redundant and omitted.
 ; ASM64BIT:       stdu 1, -128(1)
-; ASM64BIT-DAG:   ld [[REG1:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM64BIT-DAG:   ld [[REG1:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM64BIT-DAG:   ld [[REG2:[0-9]+]], 48([[REG1]])
 ; ASM64BIT-DAG:   std [[REG2]], 112(1)
 ; ASM64BIT-DAG:   lbz [[REG3:[0-9]+]], 56([[REG1]])
 ; ASM64BIT-DAG:   stb [[REG3]], 120(1)
 ; ASM64BIT-DAG:   ld 5, 0([[REG1]])
 ; ASM64BIT-DAG:   ld 6, 8([[REG1]])
 ; ASM64BIT-DAG:   ld 7, 16([[REG1]])
 ; ASM64BIT-DAG:   ld 8, 24([[REG1]])

 ; 32BIT-DAG:      $r8 = COPY %{{[0-9]+}}
 ; 32BIT-DAG:      $r9 = COPY %{{[0-9]+}}
 ; 32BIT-DAG:      $r10 = COPY %{{[0-9]+}}
 ; 32BIT-NEXT:     BL_NOP <mcsymbol .test_byval_mem4>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r6, implicit $r7, implicit $r8, implicit $r9, implicit $r10, implicit $r2, implicit-def $r1
 ; 32BIT-NEXT:     ADJCALLSTACKUP 316, 0, implicit-def dead $r1, implicit $r1
 
 ; ASM32BIT:       stwu 1, -336(1)
 ; ASM32BIT-NEXT:  stw [[REG1:[0-9]+]], {{[0-9]+}}(1)
-; ASM32BIT:       lwz [[REG1]], LC{{[0-9]+}}(2)
+; ASM32BIT:       lwz [[REG1]], L..C{{[0-9]+}}(2)
 ; ASM32BIT-DAG:   lhz [[REG2:[0-9]+]], 28([[REG1]])
 ; ASM32BIT-DAG:   sth [[REG2]], 56(1)
 ; ASM32BIT-DAG:   lbz [[REG3:[0-9]+]], 30([[REG1]])
 ; ASM32BIT-DAG:   stb [[REG3]], 58(1)
 ; ASM32BIT-DAG:   addi 3, 1, 60
-; ASM32BIT-DAG:   lwz 4, LC{{[0-9]+}}(2)
+; ASM32BIT-DAG:   lwz 4, L..C{{[0-9]+}}(2)
 ; ASM32BIT-DAG:   li 5, 256
 ; ASM32BIT-NEXT:  bl .memcpy
 ; ASM32BIT-DAG:   lwz 4, 0([[REG1]])
 ; ASM32BIT-DAG:   lwz 5, 4([[REG1]])
 ; ASM32BIT-DAG:   lwz 6, 8([[REG1]])
 ; ASM32BIT-DAG:   lwz 7, 12([[REG1]])
 ; ASM32BIT-DAG:   lwz 8, 16([[REG1]])
 ; ASM32BIT-DAG:   lwz 9, 20([[REG1]])

 ; 64BIT-DAG:      $x7 = COPY %{{[0-9]+}}
 ; 64BIT-DAG:      $x8 = COPY %{{[0-9]+}}
 ; 64BIT-DAG:      $x9 = COPY %{{[0-9]+}}
 ; 64BIT-DAG:      $x10 = COPY %{{[0-9]+}}
 ; 64BIT-NEXT:     BL8_NOP <mcsymbol .test_byval_mem4>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit $x8, implicit $x9, implicit $x10, implicit $x2, implicit-def $r1
 ; 64BIT-NEXT:     ADJCALLSTACKUP 344, 0, implicit-def dead $r1, implicit $r1
 
 ; ASM64BIT:       stdu 1, -368(1)
-; ASM64BIT-DAG:   ld [[REG1:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM64BIT-DAG:   ld [[REG1:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM64BIT-DAG:   addi 3, 1, 112
 ; ASM64BIT-DAG:   addi 4, [[REG1]], 24
 ; ASM64BIT-DAG:   li 5, 232
 ; ASM64BIT-NEXT:  bl .memcpy
-; ASM64BIT-DAG:   ld [[REG2:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM64BIT-DAG:   ld [[REG2:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM64BIT-DAG:   ld 4, 0([[REG2]])
 ; ASM64BIT-DAG:   ld 5, 8([[REG2]])
 ; ASM64BIT-DAG:   ld 6, 16([[REG2]])
 ; ASM64BIT-DAG:   lwz [[REG3:[0-9]+]], 24([[REG2]])
 ; ASM64BIT-DAG:   lhz [[REG4:[0-9]+]], 28([[REG2]])
 ; ASM64BIT-DAG:   lbz 7, 30([[REG2]])
 ; ASM64BIT-DAG:   rlwinm 7, 7, 8, 16, 23
 ; ASM64BIT-DAG:   rlwimi 7, [[REG4]], 16, 0, 15

llvm/test/CodeGen/PowerPC/aix-cc-byval.ll

 ; 32BIT-NEXT:  renamable $r3 = LBZ 0, killed renamable $r[[REG]] :: (load 1)
 ; 32BIT-NEXT:  renamable $r3 = RLWINM killed renamable $r3, 24, 0, 7
 ; 32BIT-NEXT:  BL_NOP <mcsymbol .test_byval_1Byte>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r2, implicit-def $r1
 ; 32BIT-NEXT:  ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
 
 ; CHECKASM-LABEL: .call_test_byval_1Byte:
 
 ; ASM32:       stwu 1, -64(1)
-; ASM32-NEXT:  lwz [[REG:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM32-NEXT:  lwz [[REG:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM32-NEXT:  lbz 3, 0([[REG]])
 ; ASM32-NEXT:  slwi 3, 3, 24
 ; ASM32-NEXT:  bl .test_byval_1Byte
 ; ASM32-NEXT:  nop
 ; ASM32-NEXT:  addi 1, 1, 64
 
 ; 64BIT:       ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
 ; 64BIT-NEXT:  renamable $x[[REG:[0-9]+]] = LDtoc @gS1, $x2 :: (load 8 from got)
 ; 64BIT-NEXT:  renamable $x3 = LBZ8 0, killed renamable $x[[REG]] :: (load 1)
 ; 64BIT-NEXT:  renamable $x3 = RLDICR killed renamable $x3, 56, 7
 ; 64BIT-NEXT:  BL8_NOP <mcsymbol .test_byval_1Byte>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
 ; 64BIT-NEXT:  ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 ; ASM64:       std 0, 16(1)
 ; ASM64-NEXT:  stdu 1, -128(1)
-; ASM64-NEXT:  ld [[REG:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM64-NEXT:  ld [[REG:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM64-NEXT:  lbz 3, 0([[REG]])
 ; ASM64-NEXT:  sldi 3, 3, 56
 ; ASM64-NEXT:  bl .test_byval_1Byte
 ; ASM64-NEXT:  nop
 ; ASM64-NEXT:  addi 1, 1, 128
 
 
 define zeroext i8 @test_byval_1Byte(%struct.S0* byval(%struct.S0) align 1 %s0, %struct.S1* byval(%struct.S1) align 1 %s) {

 ; 32BIT-NEXT:  BL_NOP <mcsymbol .test_byval_2Byte>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $f1, implicit $r5, implicit killed $f2, implicit killed $r7, implicit $r2, implicit-def $r1
 ; 32BIT-NEXT:  ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
 
 ; CHECKASM-LABEL: .call_test_byval_2Byte:
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; ASM32:       stwu 1, -64(1)
 ; ASM32-DAG:   li 3, 42
-; ASM32-DAG:   lwz [[REG1:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM32-DAG:   lwz [[REG1:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM32-DAG:   lfs 1, 0([[REG1]])
-; ASM32-DAG:   lwz [[REG2:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM32-DAG:   lwz [[REG2:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM32-DAG:   lhz [[REG3:[0-9]+]], 0([[REG2]])
 ; ASM32-DAG:   slwi 5, [[REG3]], 16
 ; ASM32-DAG:   fmr 2, 1
 ; ASM32-DAG:   li 7, 43
 ; ASM32-NEXT:  bl .test_byval_2Byte
 ; ASM32-NEXT:  nop
 ; ASM32-NEXT:  addi 1, 1, 64
 

 ; 64BIT-DAG:   $x7 = LI8 43
 ; 64BIT-NEXT:  BL8_NOP <mcsymbol .test_byval_2Byte>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x5, implicit killed $f2, implicit killed $x7, implicit $x2, implicit-def $r1
 ; 64BIT-NEXT:  ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; ASM64:       std 0, 16(1)
 ; ASM64-NEXT:  stdu 1, -112(1)
 ; ASM64-DAG:   li 3, 42
-; ASM64-DAG:   ld [[REG1:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM64-DAG:   ld [[REG1:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM64-DAG:   lfs 1, 0([[REG1]])
-; ASM64-DAG:   ld [[REG2:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM64-DAG:   ld [[REG2:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM64-DAG:   lhz [[REG3:[0-9]+]], 0([[REG2]])
 ; ASM64-DAG:   sldi 5, [[REG3]], 48
 ; ASM64-DAG:   fmr 2, 1
 ; ASM64-DAG:   li 7, 43
 ; ASM64-NEXT:  bl .test_byval_2Byte
 ; ASM64-NEXT:  nop
 ; ASM64-NEXT:  addi 1, 1, 112
 

 ; ASM32:       stwu 1, -64(1)
 ; ASM32-DAG:   li 3, 1
 ; ASM32-DAG:   li 4, 2
 ; ASM32-DAG:   li 5, 3
 ; ASM32-DAG:   li 6, 4
 ; ASM32-DAG:   li 7, 5
 ; ASM32-DAG:   li 8, 6
 ; ASM32-DAG:   li 9, 7
-; ASM32-DAG:   lwz [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM32-DAG:   lwz [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM32-DAG:   lhz [[REG1:[0-9]+]], 0([[REGADDR]])
 ; ASM32-DAG:   lbz [[REG2:[0-9]+]], 2([[REGADDR]])
 ; ASM32-DAG:   rlwinm 10, [[REG2]], 8, 16, 23
 ; ASM32-DAG:   rlwimi 10, [[REG1]], 16, 0, 15
 ; ASM32-DAG:   li [[REG3:[0-9]+]], 42
 ; ASM32-DAG:   stw [[REG3]], 56(1)
 ; ASM32-NEXT:  bl .test_byval_3Byte
 ; ASM32-NEXT:  nop

 ; ASM64:       stdu 1, -128(1)
 ; ASM64-DAG:   li 3, 1
 ; ASM64-DAG:   li 4, 2
 ; ASM64-DAG:   li 5, 3
 ; ASM64-DAG:   li 6, 4
 ; ASM64-DAG:   li 7, 5
 ; ASM64-DAG:   li 8, 6
 ; ASM64-DAG:   li 9, 7
-; ASM64-DAG:   ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM64-DAG:   ld [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM64-DAG:   lhz [[REG1:[0-9]+]], 0([[REGADDR]])
 ; ASM64-DAG:   lbz [[REG2:[0-9]+]], 2([[REGADDR]])
 ; ASM64-DAG:   rldic 10, [[REG2]], 40, 16
 ; ASM64-DAG:   rldimi 10, [[REG1]], 48, 0
 ; ASM64-DAG:   li [[REG3:[0-9]+]], 42
 ; ASM64-DAG:   std [[REG3]], 112(1)
 ; ASM64-NEXT:  bl .test_byval_3Byte
 ; ASM64-NEXT:  nop

 ; 32BIT-DAG:   renamable $r3 = LWZ 0, killed renamable $r[[REG]] :: (load 4)
 ; 32BIT-DAG:   renamable $r4 = LWZ 0, %stack.1.s4a :: (load 4 from %stack.1.s4a, align 8)
 ; 32BIT-NEXT:  BL_NOP <mcsymbol .test_byval_4Byte>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3,  implicit $r4, implicit $r2, implicit-def $r1
 ; 32BIT-NEXT:  ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
 
 ; CHECKASM-LABEL: .call_test_byval_4Byte:
 
 ; ASM32:       stwu 1, -80(1)
-; ASM32-NEXT:  lwz [[REG:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM32-NEXT:  lwz [[REG:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM32-DAG:   lwz 3, 0([[REG]])
 ; ASM32-DAG:   lwz 4, 64(1)
 ; ASM32-NEXT:  bl .test_byval_4Byte
 ; ASM32-NEXT:  nop
 ; ASM32-NEXT:  addi 1, 1, 80
 
 ; 64BIT:       ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
 ; 64BIT-NEXT:  renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS4, $x2 :: (load 8 from got)
 ; 64BIT-DAG:   renamable $x[[LD1:[0-9]+]] = LWZ8 0, killed renamable $x[[REGADDR]] :: (load 4)
 ; 64BIT-DAG:   renamable $x[[LD2:[0-9]+]] = LWZ8 0, %stack.1.s4a :: (load 4 from %stack.1.s4a, align 8)
 ; 64BIT-DAG:   renamable $x3 = RLDICR killed renamable $x[[LD1]], 32, 31
 ; 64BIT-DAG:   renamable $x4 = RLDICR killed renamable $x[[LD2]], 32, 31
 ; 64BIT-NEXT:  BL8_NOP <mcsymbol .test_byval_4Byte>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3,  implicit $x4, implicit $x2, implicit-def $r1
 ; 64BIT-NEXT:  ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 ; ASM64:       stdu 1, -128(1)
-; ASM64-NEXT:  ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM64-NEXT:  ld [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM64-DAG:   lwz [[LD1:[0-9]+]], 0([[REGADDR]])
 ; ASM64-DAG:   lwz [[LD2:[0-9]+]], 112(1)
 ; ASM64-DAG:   sldi 3, [[LD1]], 32
 ; ASM64-DAG:   sldi 4, [[LD2]], 32
 ; ASM64-NEXT:  bl .test_byval_4Byte
 ; ASM64-NEXT:  nop
 ; ASM64-NEXT:  addi 1, 1, 128
 

 ; 32BIT-DAG:   renamable $r4 = RLWINM killed renamable $r[[REG1]], 24, 0, 7
 ; 32BIT-NEXT:  BL_NOP <mcsymbol .test_byval_5Byte>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r2, implicit-def $r1
 ; 32BIT-NEXT:   ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
 
 ; CHECKASM-LABEL: .call_test_byval_5Byte:
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; ASM32:       stwu 1, -64(1)
-; ASM32-NEXT:  lwz [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM32-NEXT:  lwz [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM32-DAG:   lbz [[REG1:[0-9]+]], 4([[REGADDR]])
 ; ASM32-DAG:   lwz 3, 0([[REGADDR]])
 ; ASM32-DAG:   slwi 4, [[REG1]], 24
 ; ASM32-NEXT:  bl .test_byval_5Byte
 ; ASM32-NEXT:  nop
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; 64BIT:       ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
 ; 64BIT-NEXT:  renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS5, $x2 :: (load 8 from got)
 ; 64BIT-DAG:   renamable $x[[REG1:[0-9]+]] = LWZ8 0, killed renamable $x[[REGADDR]] :: (load 4)
 ; 64BIT-DAG:   renamable $x[[REG2:[0-9]+]] = LBZ8 4, renamable $x[[REGADDR]] :: (load 1)
 ; 64BIT-DAG:   renamable $x3 = RLWINM8 killed renamable $x[[REG2]], 24, 0, 7
 ; 64BIT-DAG:   renamable $x3 = RLDIMI killed renamable $x3, killed renamable $x[[REG1]], 32, 0
 ; 64BIT-NEXT:  BL8_NOP <mcsymbol .test_byval_5Byte>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
 ; 64BIT-NEXT:  ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; ASM64:       stdu 1, -112(1)
-; ASM64-NEXT:  ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM64-NEXT:  ld [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM64-DAG:   lwz [[REG1:[0-9]+]], 0([[REGADDR]])
 ; ASM64-DAG:   lbz [[REG2:[0-9]+]], 4([[REGADDR]])
 ; ASM64-DAG:   rlwinm 3, [[REG2]], 24, 0, 7
 ; ASM64-DAG:   rldimi 3, [[REG1]], 32, 0
 ; ASM64-NEXT:  bl .test_byval_5Byte
 ; ASM64-NEXT:  nop
 
 

 ; 32BIT-DAG:   renamable $r4 = RLWINM killed renamable $r[[REG1]], 16, 0, 15
 ; 32BIT-NEXT:  BL_NOP <mcsymbol .test_byval_6Byte>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r2, implicit-def $r1
 ; 32BIT-NEXT:  ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
 
 ; CHECKASM-LABEL: .call_test_byval_6Byte:
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; ASM32:       stwu 1, -64(1)
-; ASM32-NEXT:  lwz [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM32-NEXT:  lwz [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM32-DAG:   lhz [[REG1:[0-9]+]], 4([[REGADDR]])
 ; ASM32-DAG:   lwz 3, 0([[REGADDR]])
 ; ASM32-DAG:   slwi 4, [[REG1]], 16
 ; ASM32-NEXT:  bl .test_byval_6Byte
 ; ASM32-NEXT:  nop
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; 64BIT:       ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
 ; 64BIT-NEXT:  renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS6, $x2 :: (load 8 from got)
 ; 64BIT-DAG:   renamable $x[[REG1:[0-9]+]] = LWZ8 0, killed renamable $x[[REGADDR]] :: (load 4)
 ; 64BIT-DAG:   renamable $x[[REG2:[0-9]+]] = LHZ8 4, renamable $x[[REGADDR]] :: (load 2)
 ; 64BIT-DAG:   renamable $x3 = RLWINM8 killed renamable $x[[REG2]], 16, 0, 15
 ; 64BIT-DAG:   renamable $x3 = RLDIMI killed renamable $x3, killed renamable $x[[REG1]], 32, 0
 ; 64BIT-NEXT:  BL8_NOP <mcsymbol .test_byval_6Byte>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
 ; 64BIT-NEXT:  ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; ASM64:       stdu 1, -112(1)
-; ASM64-NEXT:  ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM64-NEXT:  ld [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM64-DAG:   lwz [[REG1:[0-9]+]], 0([[REGADDR]])
 ; ASM64-DAG:   lhz [[REG2:[0-9]+]], 4([[REGADDR]])
 ; ASM64-DAG:   rlwinm 3, [[REG2]], 16, 0, 15
 ; ASM64-DAG:   rldimi 3, [[REG1]], 32, 0
 ; ASM64-NEXT:  bl .test_byval_6Byte
 ; ASM64-NEXT:  nop
 
 

 ; 32BIT-DAG:   renamable $r4 = RLWIMI killed renamable $r4, killed renamable $r[[REG1]], 16, 0, 15
 ; 32BIT-NEXT:  BL_NOP <mcsymbol .test_byval_7Byte>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r2, implicit-def $r1
 ; 32BIT-NEXT:  ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
 
 ; CHECKASM-LABEL: .call_test_byval_7Byte:
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; ASM32:       stwu 1, -64(1)
-; ASM32-NEXT:  lwz [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM32-NEXT:  lwz [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM32-DAG:   lwz 3, 0([[REGADDR]])
 ; ASM32-DAG:   lhz [[REG1:[0-9]+]], 4([[REGADDR]])
 ; ASM32-DAG:   lbz [[REG2:[0-9]+]], 6([[REGADDR]])
 ; ASM32-DAG:   rlwinm 4, [[REG2]], 8, 16, 23
 ; ASM32-DAG:   rlwimi 4, [[REG1]], 16, 0, 15
 ; ASM32-NEXT:  bl .test_byval_7Byte
 ; ASM32-NEXT:  nop
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; 64BIT:       ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
 ; 64BIT-NEXT:  renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS7, $x2 :: (load 8 from got)
 ; 64BIT-DAG:   renamable $x[[REG1:[0-9]+]] = LWZ8 0, killed renamable $x[[REGADDR]] :: (load 4)
 ; 64BIT-DAG:   renamable $x[[REG2:[0-9]+]] = LHZ8 4, renamable $x[[REGADDR]] :: (load 2)
 ; 64BIT-DAG:   renamable $x[[REG3:[0-9]+]] = LBZ8 6, renamable $x[[REGADDR]] :: (load 1)
 ; 64BIT-DAG:   renamable $x3 = RLWINM8 killed renamable $x[[REG3]], 8, 16, 23
 ; 64BIT-DAG:   renamable $x3 = RLWIMI8 killed renamable $x3, killed renamable $x[[REG2]], 16, 0, 15
 ; 64BIT-DAG:   renamable $x3 = RLDIMI killed renamable $x3, killed renamable $x[[REG1]], 32, 0
 ; 64BIT-NEXT:  BL8_NOP <mcsymbol .test_byval_7Byte>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
 ; 64BIT-NEXT:  ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; ASM64:       stdu 1, -112(1)
-; ASM64-NEXT:  ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM64-NEXT:  ld [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM64-DAG:   lwz [[REG1:[0-9]+]], 0([[REGADDR]])
 ; ASM64-DAG:   lhz [[REG2:[0-9]+]], 4([[REGADDR]])
 ; ASM64-DAG:   lbz [[REG3:[0-9]+]], 6([[REGADDR]])
 ; ASM64-DAG:   rlwinm 3, [[REG3]], 8, 16, 23
 ; ASM64-DAG:   rlwimi 3, [[REG2]], 16, 0, 15
 ; ASM64-DAG:   rldimi 3, [[REG1]], 32, 0
 ; ASM64-NEXT:  bl .test_byval_7Byte
 ; ASM64-NEXT:  nop

 ; 32BIT-DAG:   renamable $r4 = LWZ 4, renamable $r[[REGADDR]] :: (load 4)
 ; 32BIT-NEXT:  BL_NOP <mcsymbol .test_byval_8Byte>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r2, implicit-def $r1
 ; 32BIT-NEXT:  ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
 
 ; CHECKASM-LABEL: .call_test_byval_8Byte:
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; ASM32:       stwu 1, -64(1)
-; ASM32-NEXT:  lwz [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM32-NEXT:  lwz [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM32-DAG:   lwz 3, 0([[REGADDR]])
 ; ASM32-DAG:   lwz 4, 4([[REGADDR]])
 ; ASM32-NEXT:  bl .test_byval_8Byte
 ; ASM32-NEXT:  nop
 
 ; 64BIT:       ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
 ; 64BIT-NEXT:  renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS8, $x2 :: (load 8 from got)
 ; 64BIT-NEXT:  renamable $x3 = LD 0, killed renamable $x[[REGADDR]] :: (load 8)
 ; 64BIT-NEXT:  BL8_NOP <mcsymbol .test_byval_8Byte>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
 ; 64BIT-NEXT:  ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 ; ASM64:       stdu 1, -112(1)
-; ASM64-NEXT:  ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM64-NEXT:  ld [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM64-NEXT:  ld 3, 0([[REGADDR]])
 ; ASM64-NEXT:  bl .test_byval_8Byte
 ; ASM64-NEXT:  nop
 
 
 %struct.S32 = type { [32 x i8] }
 
 @gS32 = external global %struct.S32, align 1

 ; 32BIT-DAG:   renamable $r10 = LWZ 28, renamable $r[[REGADDR]] :: (load 4)
 ; 32BIT-NEXT:  BL_NOP <mcsymbol .test_byval_32Byte>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r6, implicit $r7, implicit $r8, implicit $r9, implicit $r10, implicit $r2, implicit-def $r1
 ; 32BIT-NEXT:  ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
 
 ; CHECKASM-LABEL: .call_test_byval_32Byte:
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; ASM32:       stwu 1, -64(1)
-; ASM32-NEXT:  lwz [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM32-NEXT:  lwz [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM32-DAG:   lwz 3, 0([[REGADDR]])
 ; ASM32-DAG:   lwz 4, 4([[REGADDR]])
 ; ASM32-DAG:   lwz 5, 8([[REGADDR]])
 ; ASM32-DAG:   lwz 6, 12([[REGADDR]])
 ; ASM32-DAG:   lwz 7, 16([[REGADDR]])
 ; ASM32-DAG:   lwz 8, 20([[REGADDR]])
 ; ASM32-DAG:   lwz 9, 24([[REGADDR]])
 ; ASM32-DAG:   lwz 10, 28([[REGADDR]])
 ; ASM32-NEXT:  bl .test_byval_32Byte
 ; ASM32-NEXT:  nop
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; 64BIT:       ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
 ; 64BIT-NEXT:  renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS32, $x2 :: (load 8 from got)
 ; 64BIT-DAG:   renamable $x3 = LD 0, killed renamable $x[[REGADDR]] :: (load 8)
 ; 64BIT-DAG:   renamable $x4 = LD 8, renamable $x[[REGADDR]] :: (load 8)
 ; 64BIT-DAG:   renamable $x5 = LD 16, renamable $x[[REGADDR]] :: (load 8)
 ; 64BIT-DAG:   renamable $x6 = LD 24, renamable $x[[REGADDR]] :: (load 8)
 ; 64BIT-NEXT:  BL8_NOP <mcsymbol .test_byval_32Byte>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x2, implicit-def $r1
 ; 64BIT-NEXT:  ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 ; ASM64:       stdu 1, -112(1)
-; ASM64-NEXT:  ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM64-NEXT:  ld [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM64-DAG:   ld 3, 0([[REGADDR]])
 ; ASM64-DAG:   ld 4, 8([[REGADDR]])
 ; ASM64-DAG:   ld 5, 16([[REGADDR]])
 ; ASM64-DAG:   ld 6, 24([[REGADDR]])
 ; ASM64-NEXT:  bl .test_byval_32Byte
 ; ASM64-NEXT:  nop
 
 define zeroext i8 @test_byval_32Byte(%struct.S32* byval(%struct.S32) align 1 %s) {

 ; 32BIT-DAG:   renamable $r10 = RLWIMI killed renamable $r10, killed renamable $r[[REG]], 16, 0, 15
 ; 32BIT-NEXT:  BL_NOP <mcsymbol .test_byval_31Byte>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r6, implicit $r7, implicit $r8, implicit $r9, implicit $r10, implicit $r2, implicit-def $r1
 ; 32BIT-NEXT:  ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
 
 ; CHECKASM-LABEL: .call_test_byval_31Byte:
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; ASM32:       stwu 1, -64(1)
-; ASM32-NEXT:  lwz [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM32-NEXT:  lwz [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM32-DAG:   lwz 3, 0([[REGADDR]])
 ; ASM32-DAG:   lwz 4, 4([[REGADDR]])
 ; ASM32-DAG:   lwz 5, 8([[REGADDR]])
 ; ASM32-DAG:   lwz 6, 12([[REGADDR]])
 ; ASM32-DAG:   lwz 7, 16([[REGADDR]])
 ; ASM32-DAG:   lwz 8, 20([[REGADDR]])
 ; ASM32-DAG:   lwz 9, 24([[REGADDR]])
 ; ASM32-DAG:   lbz 10, 30([[REGADDR]])

 ; 64BIT-DAG:   renamable $x[[REG3:[0-9]+]] = LBZ8 30, renamable $x[[REGADDR]] :: (load 1)
 ; 64BIT-DAG:   renamable $x6 = RLWINM8 killed renamable $x[[REG3]], 8, 16, 23
 ; 64BIT-DAG:   renamable $x6 = RLWIMI8 killed renamable $x6, killed renamable $x[[REG2]], 16, 0, 15
 ; 64BIT-DAG:   renamable $x6 = RLDIMI killed renamable $x6, killed renamable $x[[REG1]], 32, 0
 ; 64BIT-NEXT:  BL8_NOP <mcsymbol .test_byval_31Byte>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x2, implicit-def $r1
 ; 64BIT-NEXT:  ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 ; ASM64:       stdu 1, -112(1)
-; ASM64-NEXT:  ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM64-NEXT:  ld [[REGADDR:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM64-DAG:   ld 3, 0([[REGADDR]])
 ; ASM64-DAG:   ld 4, 8([[REGADDR]])
 ; ASM64-DAG:   ld 5, 16([[REGADDR]])
 ; ASM64-DAG:   lwz [[REG1:[0-9]+]], 24([[REGADDR]])
 ; ASM64-DAG:   lhz [[REG2:[0-9]+]], 28([[REGADDR]])
 ; ASM64-DAG:   lbz [[REG3:[0-9]+]], 30([[REGADDR]])
 ; ASM64-DAG:   rlwinm 6, [[REG3]], 8, 16, 23
 ; ASM64-DAG:   rlwimi 6, [[REG2]], 16, 0, 15

llvm/test/CodeGen/PowerPC/aix-extern-weak.ll

 ; COMMON-NEXT: foo_ext_weak_p:
 ; BIT32-NEXT:     .vbyte  4, foo_ext_weak_ref[DS]
 ; BIT64-NEXT:     .vbyte  8, foo_ext_weak_ref[DS]
 ; COMMON-NEXT:    .weak   b_w[UA]
 ; COMMON-NEXT:    .weak   foo_ext_weak_ref[DS]
 ; COMMON-NEXT:    .weak   .foo_ext_weak
 ; COMMON-NEXT:    .weak   foo_ext_weak[DS]
 ; COMMON-NEXT:    .toc
-; COMMON-NEXT: LC0:
+; COMMON-NEXT: L..C0:
 ; COMMON-NEXT:    .tc foo_ext_weak_p[TC],foo_ext_weak_p
-; COMMON-NEXT: LC1:
+; COMMON-NEXT: L..C1:
 ; COMMON-NEXT:    .tc b_w[TC],b_w[UA]
 
 ; CHECK-NOT:      .weak   .foo_ext_weak_ref
 
 ; CHECKSYM:      Symbols [
 ; CHECKSYM-NEXT:   Symbol {
 ; CHECKSYM-NEXT:     Index: [[#Index:]]
 ; CHECKSYM-NEXT:     Name: .foo_ext_weak

llvm/test/CodeGen/PowerPC/aix-extern.ll

 ; BIT32-NEXT:       .vbyte  4, bar_ref[DS]
 ; BIT64-NEXT:       .vbyte  8, bar_ref[DS]
 ; COMMON-NEXT:      .extern b_e[UA]
 ; COMMON-NEXT:      .extern .bar_ref
 ; COMMON-NEXT:      .extern bar_ref[DS]
 ; COMMON-NEXT:      .extern .bar_extern
 ; COMMON-NEXT:      .extern     bar_extern[DS]
 ; COMMON-NEXT:      .toc
-; COMMON-NEXT: LC0:
+; COMMON-NEXT: L..C0:
 ; COMMON-NEXT:      .tc b_e[TC],b_e[UA]
-; COMMON-NEXT: LC1:
+; COMMON-NEXT: L..C1:
 ; COMMON-NEXT:      .tc bar_p[TC],bar_p
 
 ; CHECKSYM:       Symbols [
 ; CHECKSYM-NEXT:   Symbol {
 ; CHECKSYM-NEXT:     Index: [[#Index:]]
 ; CHECKSYM-NEXT:     Name: .bar_extern
 ; CHECKSYM-NEXT:     Value (RelocatableAddress): 0x0
 ; CHECKSYM-NEXT:     Section: N_UNDEF

llvm/test/CodeGen/PowerPC/aix-lower-block-address.ll

 
 ; 64SMALL-MIR: renamable $x[[REG1:[0-9]+]] = LDtocBA blockaddress(@foo, %ir-block.__here), $x2 :: (load 8 from got)
 
 ; 64LARGE-MIR: renamable $x[[REG1:[0-9]+]] = ADDIStocHA8 $x2, blockaddress(@foo, %ir-block.__here)
 ; 64LARGE-MIR: renamable $x[[REG2:[0-9]+]] = LDtocL blockaddress(@foo, %ir-block.__here), killed renamable $x[[REG1]], implicit $x2 :: (load 8 from got)
 
 ; 32SMALL-ASM-LABEL: foo
 ; 32SMALL-ASM: .foo:
-; 32SMALL-ASM: Ltmp0:
-; 32SMALL-ASM:         lwz [[REG1:[0-9]+]], LC0(2)
+; 32SMALL-ASM: L..tmp0:
+; 32SMALL-ASM:         lwz [[REG1:[0-9]+]], L..C0(2)
 
 ; 32LARGE-ASM-LABEL: foo
 ; 32LARGE-ASM: .foo:
-; 32LARGE-ASM: Ltmp0:
-; 32LARGE-ASM:         addis [[REG1:[0-9]+]], LC0@u(2)
-; 32LARGE-ASM:         lwz [[REG2:[0-9]+]], LC0@l([[REG1]])
+; 32LARGE-ASM: L..tmp0:
+; 32LARGE-ASM:         addis [[REG1:[0-9]+]], L..C0@u(2)
+; 32LARGE-ASM:         lwz [[REG2:[0-9]+]], L..C0@l([[REG1]])
 
 ; 64SMALL-ASM-LABEL: foo
 ; 64SMALL-ASM: .foo:
-; 64SMALL-ASM: Ltmp0:
-; 64SMALL-ASM:         ld [[REG1:[0-9]+]], LC0(2)
+; 64SMALL-ASM: L..tmp0:
+; 64SMALL-ASM:         ld [[REG1:[0-9]+]], L..C0(2)
 
 ; 64LARGE-ASM-LABEL: foo
 ; 64LARGE-ASM: .foo:
-; 64LARGE-ASM: Ltmp0:
-; 64LARGE-ASM:         addis [[REG1:[0-9]+]], LC0@u(2)
-; 64LARGE-ASM:         ld [[REG2:[0-9]+]], LC0@l([[REG1]])
+; 64LARGE-ASM: L..tmp0:
+; 64LARGE-ASM:         addis [[REG1:[0-9]+]], L..C0@u(2)
+; 64LARGE-ASM:         ld [[REG2:[0-9]+]], L..C0@l([[REG1]])
 
 ; CHECK: .toc
-; CHECK: .tc Ltmp0[TC],Ltmp0
+; CHECK: .tc L..tmp0[TC],L..tmp0

llvm/test/CodeGen/PowerPC/aix-lower-constant-pool-index.ll

 ; 64LARGE-MIR: renamable $x[[REG2:[0-9]+]] = LDtocL %const.0, killed renamable $x[[REG1]], implicit $x2 :: (load 8 from got)
 ; 64LARGE-MIR: renamable $f[[REG3:[0-9]+]] = LFS 0, killed renamable $x[[REG2]] :: (load 4 from constant-pool)
 
 ; 32SMALL-ASM:         .csect .rodata[RO],2
 ; 32SMALL-ASM:         .align  2
 ; 32SMALL-ASM: .LCPI0_0:
 ; 32SMALL-ASM:         .vbyte 4, 0x40b00000
 ; 32SMALL-ASM: .test_float:
-; 32SMALL-ASM:         lwz [[REG1:[0-9]+]], LC0(2)
+; 32SMALL-ASM:         lwz [[REG1:[0-9]+]], L..C0(2)
 ; 32SMALL-ASM:         lfs 1, 0([[REG1]])
 ; 32SMALL-ASM:         blr
 
 ; 32LARGE-ASM:         .csect .rodata[RO],2
 ; 32LARGE-ASM:         .align  2
 ; 32LARGE-ASM: .LCPI0_0:
 ; 32LARGE-ASM:         .vbyte 4, 0x40b00000
 ; 32LARGE-ASM: .test_float:
-; 32LARGE-ASM:         addis [[REG1:[0-9]+]], LC0@u(2)
-; 32LARGE-ASM:         lwz [[REG2:[0-9]+]], LC0@l([[REG1]])
+; 32LARGE-ASM:         addis [[REG1:[0-9]+]], L..C0@u(2)
+; 32LARGE-ASM:         lwz [[REG2:[0-9]+]], L..C0@l([[REG1]])
 ; 32LARGE-ASM:         lfs 1, 0([[REG2]])
 ; 32LARGE-ASM:         blr
 
 ; 64SMALL-ASM:         .csect .rodata[RO],2
 ; 64SMALL-ASM:         .align  2
 ; 64SMALL-ASM: .LCPI0_0:
 ; 64SMALL-ASM:         .vbyte 4, 0x40b00000
 ; 64SMALL-ASM: .test_float:
-; 64SMALL-ASM:         ld [[REG1:[0-9]+]], LC0(2)
+; 64SMALL-ASM:         ld [[REG1:[0-9]+]], L..C0(2)
 ; 64SMALL-ASM:         lfs 1, 0([[REG1]])
 ; 64SMALL-ASM:         blr
 
 ; 64LARGE-ASM:         .csect .rodata[RO],2
 ; 64LARGE-ASM:         .align  2
 ; 64LARGE-ASM: .LCPI0_0:
 ; 64LARGE-ASM:         .vbyte 4, 0x40b00000
 ; 64LARGE-ASM: .test_float:
-; 64LARGE-ASM:         addis [[REG1:[0-9]+]], LC0@u(2)
-; 64LARGE-ASM:         ld [[REG2:[0-9]+]], LC0@l([[REG1]])
+; 64LARGE-ASM:         addis [[REG1:[0-9]+]], L..C0@u(2)
+; 64LARGE-ASM:         ld [[REG2:[0-9]+]], L..C0@l([[REG1]])
 ; 64LARGE-ASM:         lfs 1, 0([[REG2]])
 ; 64LARGE-ASM:         blr
 
 ; CHECK: .toc
 ; CHECK: .tc .LCPI0_0[TC],.LCPI0_0

llvm/test/CodeGen/PowerPC/aix-lower-jump-table.ll

 ; 64LARGE-MIR: renamable $x[[REG4:[0-9]+]] = RLDIC killed renamable $x[[REG3:[0-9]+]], 2, 30
 ; 64LARGE-MIR: renamable $x[[REG5:[0-9]+]] = LWAX killed renamable $x[[REG4]], renamable $x[[REG2]] :: (load 4 from jump-table)
 ; 64LARGE-MIR: renamable $x[[REG6:[0-9]+]] = ADD8 killed renamable $x[[REG5]], killed renamable $x[[REG2]]
 
 ; 32SMALL-ASM-LABEL: jump_table
 ; 32SMALL-ASM: .jump_table:
 ; 32SMALL-ASM:      addi 3, 3, -1
 ; 32SMALL-ASM:      cmplwi 3, 3
-; 32SMALL-ASM:      bgt 0, LBB0_6
-; 32SMALL-ASM:      lwz 4, LC0(2)
+; 32SMALL-ASM:      bgt 0, L..BB0_6
+; 32SMALL-ASM:      lwz 4, L..C0(2)
 ; 32SMALL-ASM:      slwi 3, 3, 2
 ; 32SMALL-ASM:      lwzx 3, 3, 4
 ; 32SMALL-ASM:      add 3, 3, 4
 ; 32SMALL-ASM:      mtctr 3
 ; 32SMALL-ASM:      bctr
-; 32SMALL-ASM: LBB0_2:
-; 32SMALL-ASM: LBB0_3:
-; 32SMALL-ASM: LBB0_4:
-; 32SMALL-ASM: LBB0_5:
-; 32SMALL-ASM: LBB0_6:
+; 32SMALL-ASM: L..BB0_2:
+; 32SMALL-ASM: L..BB0_3:
+; 32SMALL-ASM: L..BB0_4:
+; 32SMALL-ASM: L..BB0_5:
+; 32SMALL-ASM: L..BB0_6:
 ; 32SMALL-ASM:      li 3, 0
 ; 32SMALL-ASM:      blr
 ; 32SMALL-ASM:      .csect .rodata[RO],2
 ; 32SMALL-ASM:      .align  2
 ; 32SMALL-ASM: .LJTI0_0:
-; 32SMALL-ASM:      .vbyte  4, LBB0_2-.LJTI0_0
-; 32SMALL-ASM:      .vbyte  4, LBB0_3-.LJTI0_0
-; 32SMALL-ASM:      .vbyte  4, LBB0_4-.LJTI0_0
-; 32SMALL-ASM:      .vbyte  4, LBB0_5-.LJTI0_0
+; 32SMALL-ASM:      .vbyte  4, L..BB0_2-.LJTI0_0
+; 32SMALL-ASM:      .vbyte  4, L..BB0_3-.LJTI0_0
+; 32SMALL-ASM:      .vbyte  4, L..BB0_4-.LJTI0_0
+; 32SMALL-ASM:      .vbyte  4, L..BB0_5-.LJTI0_0
 
 ; 32LARGE-ASM-LABEL: jump_table
 ; 32LARGE-ASM: .jump_table:
 ; 32LARGE-ASM:      addi 3, 3, -1
 ; 32LARGE-ASM:      cmplwi  3, 3
-; 32LARGE-ASM:      bgt     0, LBB0_6
-; 32LARGE-ASM:      addis 4, LC0@u(2)
+; 32LARGE-ASM:      bgt     0, L..BB0_6
+; 32LARGE-ASM:      addis 4, L..C0@u(2)
 ; 32LARGE-ASM:      slwi 3, 3, 2
-; 32LARGE-ASM:      lwz 4, LC0@l(4)
+; 32LARGE-ASM:      lwz 4, L..C0@l(4)
 ; 32LARGE-ASM:      lwzx 3, 3, 4
 ; 32LARGE-ASM:      add 3, 3, 4
 ; 32LARGE-ASM:      mtctr 3
 ; 32LARGE-ASM:      bctr
-; 32LARGE-ASM: LBB0_2:
-; 32LARGE-ASM: LBB0_3:
-; 32LARGE-ASM: LBB0_4:
-; 32LARGE-ASM: LBB0_5:
-; 32LARGE-ASM: LBB0_6:
+; 32LARGE-ASM: L..BB0_2:
+; 32LARGE-ASM: L..BB0_3:
+; 32LARGE-ASM: L..BB0_4:
+; 32LARGE-ASM: L..BB0_5:
+; 32LARGE-ASM: L..BB0_6:
 ; 32LARGE-ASM:      li 3, 0
 ; 32LARGE-ASM:      blr
 ; 32LARGE-ASM:      .csect .rodata[RO],2
 ; 32LARGE-ASM:      .align  2
 ; 32LARGE-ASM: .LJTI0_0:
-; 32LARGE-ASM:      .vbyte  4, LBB0_2-.LJTI0_0
-; 32LARGE-ASM:      .vbyte  4, LBB0_3-.LJTI0_0
-; 32LARGE-ASM:      .vbyte  4, LBB0_4-.LJTI0_0
-; 32LARGE-ASM:      .vbyte  4, LBB0_5-.LJTI0_0
+; 32LARGE-ASM:      .vbyte  4, L..BB0_2-.LJTI0_0
+; 32LARGE-ASM:      .vbyte  4, L..BB0_3-.LJTI0_0
+; 32LARGE-ASM:      .vbyte  4, L..BB0_4-.LJTI0_0
+; 32LARGE-ASM:      .vbyte  4, L..BB0_5-.LJTI0_0
 
 ; 64SMALL-ASM-LABEL: jump_table
 ; 64SMALL-ASM: .jump_table:
 ; 64SMALL-ASM:      addi 3, 3, -1
 ; 64SMALL-ASM:      cmplwi  3, 3
-; 64SMALL-ASM:      bgt     0, LBB0_6
-; 64SMALL-ASM:      ld 4, LC0(2)
+; 64SMALL-ASM:      bgt     0, L..BB0_6
+; 64SMALL-ASM:      ld 4, L..C0(2)
 ; 64SMALL-ASM:      rldic 3, 3, 2, 30
 ; 64SMALL-ASM:      lwax 3, 3, 4
 ; 64SMALL-ASM:      add 3, 3, 4
 ; 64SMALL-ASM:      mtctr 3
 ; 64SMALL-ASM:      bctr
-; 64SMALL-ASM: LBB0_2:
-; 64SMALL-ASM: LBB0_3:
-; 64SMALL-ASM: LBB0_4:
-; 64SMALL-ASM: LBB0_5:
-; 64SMALL-ASM: LBB0_6:
+; 64SMALL-ASM: L..BB0_2:
+; 64SMALL-ASM: L..BB0_3:
+; 64SMALL-ASM: L..BB0_4:
+; 64SMALL-ASM: L..BB0_5:
+; 64SMALL-ASM: L..BB0_6:
 ; 64SMALL-ASM:      li 3, 0
 ; 64SMALL-ASM:      blr
 ; 64SMALL-ASM:      .csect .rodata[RO],2
 ; 64SMALL-ASM:      .align  2
 ; 64SMALL-ASM: .LJTI0_0:
-; 64SMALL-ASM:      .vbyte  4, LBB0_2-.LJTI0_0
-; 64SMALL-ASM:      .vbyte  4, LBB0_3-.LJTI0_0
-; 64SMALL-ASM:      .vbyte  4, LBB0_4-.LJTI0_0
-; 64SMALL-ASM:      .vbyte  4, LBB0_5-.LJTI0_0
+; 64SMALL-ASM:      .vbyte  4, L..BB0_2-.LJTI0_0
+; 64SMALL-ASM:      .vbyte  4, L..BB0_3-.LJTI0_0
+; 64SMALL-ASM:      .vbyte  4, L..BB0_4-.LJTI0_0
+; 64SMALL-ASM:      .vbyte  4, L..BB0_5-.LJTI0_0
 
 ; 64LARGE-ASM-LABEL: jump_table
 ; 64LARGE-ASM: .jump_table:
 ; 64LARGE-ASM:      addi 3, 3, -1
 ; 64LARGE-ASM:      cmplwi  3, 3
-; 64LARGE-ASM:      bgt     0, LBB0_6
-; 64LARGE-ASM:      addis 4, LC0@u(2)
+; 64LARGE-ASM:      bgt     0, L..BB0_6
+; 64LARGE-ASM:      addis 4, L..C0@u(2)
 ; 64LARGE-ASM:      rldic 3, 3, 2, 30
-; 64LARGE-ASM:      ld 4, LC0@l(4)
+; 64LARGE-ASM:      ld 4, L..C0@l(4)
 ; 64LARGE-ASM:      lwax 3, 3, 4
 ; 64LARGE-ASM:      add 3, 3, 4
 ; 64LARGE-ASM:      mtctr 3
 ; 64LARGE-ASM:      bctr
-; 64LARGE-ASM: LBB0_2:
-; 64LARGE-ASM: LBB0_3:
-; 64LARGE-ASM: LBB0_4:
-; 64LARGE-ASM: LBB0_5:
-; 64LARGE-ASM: LBB0_6:
+; 64LARGE-ASM: L..BB0_2:
+; 64LARGE-ASM: L..BB0_3:
+; 64LARGE-ASM: L..BB0_4:
+; 64LARGE-ASM: L..BB0_5:
+; 64LARGE-ASM: L..BB0_6:
 ; 64LARGE-ASM:      li 3, 0
 ; 64LARGE-ASM:      blr
 ; 64LARGE-ASM:      .csect .rodata[RO],2
 ; 64LARGE-ASM:      .align  2
 ; 64LARGE-ASM: .LJTI0_0:
-; 64LARGE-ASM:      .vbyte  4, LBB0_2-.LJTI0_0
-; 64LARGE-ASM:      .vbyte  4, LBB0_3-.LJTI0_0
-; 64LARGE-ASM:      .vbyte  4, LBB0_4-.LJTI0_0
-; 64LARGE-ASM:      .vbyte  4, LBB0_5-.LJTI0_0
+; 64LARGE-ASM:      .vbyte  4, L..BB0_2-.LJTI0_0
+; 64LARGE-ASM:      .vbyte  4, L..BB0_3-.LJTI0_0
+; 64LARGE-ASM:      .vbyte  4, L..BB0_4-.LJTI0_0
+; 64LARGE-ASM:      .vbyte  4, L..BB0_5-.LJTI0_0
 
 ; CHECK: .toc
 ; CHECK: .tc .LJTI0_0[TC],.LJTI0_0

llvm/test/CodeGen/PowerPC/aix-weak.ll

 ; COMMON-NEXT:  foo_weak_p:
 ; BIT32-NEXT:           .vbyte  4, foo_ref_weak[DS]
 ; BIT64-NEXT:           .vbyte  8, foo_ref_weak[DS]
 ; COMMON-NEXT:          .weak b
 ; COMMON-NEXT:          .align  2
 ; COMMON-NEXT:  b:
 ; COMMON-NEXT:          .vbyte  4, 0                       # 0x0
 ; COMMON-NEXT:          .toc
-; COMMON-NEXT:  LC0:
+; COMMON-NEXT:  L..C0:
 ; COMMON-NEXT:          .tc foo_weak_p[TC],foo_weak_p
-; COMMON-NEXT:  LC1:
+; COMMON-NEXT:  L..C1:
 ; COMMON-NEXT:          .tc b[TC],b
 
 
 ; CHECKSYM:      Symbols [
 ; CHECKSYM-NEXT:   Symbol {
 ; CHECKSYM-NEXT:     Index: [[#Index:]]
 ; CHECKSYM-NEXT:     Name: .text
 ; CHECKSYM-NEXT:     Value (RelocatableAddress): 0x0

llvm/test/CodeGen/PowerPC/aix-xcoff-externL.ll

+;; Test to make sure a symbol name that starts with an 'L' could be succesfully
+;; consumed. Note that this could fail if PrivateGlobalPrefix returns
+;; 'L'/'.L' instead of 'L..' because the resulting symbol gets created as
+;; a temporary symbol.
+
+; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr4 \
+; RUN:     -mattr=-altivec -filetype=obj -o %t.o < %s
+; RUN: llvm-readobj --symbols %t.o | \
+; RUN:   FileCheck --check-prefix=XCOFF32 %s
+
+; RUN: not --crash llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff \
+; RUN:     -mcpu=pwr4 -mattr=-altivec -filetype=obj -o %t.o 2>&1 < %s | \
+; RUN:   FileCheck --check-prefix=XCOFF64 %s
+; XCOFF64: LLVM ERROR: 64-bit XCOFF object files are not supported yet.
+
+@La = external global i32, align 4
+
+declare i32 @Lb(...)
+
+define void @foo() {
+entry:
+  store i32 1, i32* @La, align 4
+  call i32 bitcast (i32 (...)* @Lb to i32 ()*)()
+  ret void
+}
+
+; XCOFF32:         Index: [[#IND:]]{{.*}}{{[[:space:]] *}}Name: .Lb
+; XCOFF32-NEXT:    Value (RelocatableAddress): 0x0
+; XCOFF32-NEXT:    Section: N_UNDEF
+; XCOFF32-NEXT:    Type: 0x0
+; XCOFF32-NEXT:    StorageClass: C_EXT (0x2)
+; XCOFF32-NEXT:    NumberOfAuxEntries: 1
+; XCOFF32-NEXT:    CSECT Auxiliary Entry {
+; XCOFF32-NEXT:      Index: [[#IND+1]]
+; XCOFF32-NEXT:      SectionLen: 0
+; XCOFF32-NEXT:      ParameterHashIndex: 0x0
+; XCOFF32-NEXT:      TypeChkSectNum: 0x0
+; XCOFF32-NEXT:      SymbolAlignmentLog2: 0
+; XCOFF32-NEXT:      SymbolType: XTY_ER (0x0)
+; XCOFF32-NEXT:      StorageMappingClass: XMC_PR (0x0)
+; XCOFF32-NEXT:      StabInfoIndex: 0x0
+; XCOFF32-NEXT:      StabSectNum: 0x0
+; XCOFF32-NEXT:    }
+; XCOFF32-NEXT:  }
+; XCOFF32-NEXT:  Symbol {
+; XCOFF32-NEXT:    Index: [[#IND+2]]
+; XCOFF32-NEXT:    Name: La
+; XCOFF32-NEXT:    Value (RelocatableAddress): 0x0
+; XCOFF32-NEXT:    Section: N_UNDEF
+; XCOFF32-NEXT:    Type: 0x0
+; XCOFF32-NEXT:    StorageClass: C_EXT (0x2)
+; XCOFF32-NEXT:    NumberOfAuxEntries: 1
+; XCOFF32-NEXT:    CSECT Auxiliary Entry {
+; XCOFF32-NEXT:      Index: [[#IND+3]]
+; XCOFF32-NEXT:      SectionLen: 0
+; XCOFF32-NEXT:      ParameterHashIndex: 0x0
+; XCOFF32-NEXT:      TypeChkSectNum: 0x0
+; XCOFF32-NEXT:      SymbolAlignmentLog2: 0
+; XCOFF32-NEXT:      SymbolType: XTY_ER (0x0)
+; XCOFF32-NEXT:      StorageMappingClass: XMC_UA (0x4)
+; XCOFF32-NEXT:      StabInfoIndex: 0x0
+; XCOFF32-NEXT:      StabSectNum: 0x0
+; XCOFF32-NEXT:    }
+; XCOFF32-NEXT:  }

llvm/test/CodeGen/PowerPC/aix-xcoff-toc.ll

 ; CHECK-NOT: .comm b
 ; CHECK-NOT: .lcomm b
 ; CHECK-NOT: .comm c
 ; CHECK-NOT: .lcomm c
 ; CHECK: .comm globa[RW],4,2
 ; CHECK32: .lcomm ptr,4,ptr[BS],2
 ; CHECK64: .lcomm ptr,8,ptr[BS],2
 ; CHECK:      .toc
-; CHECK-NEXT: LC0:
+; CHECK-NEXT: L..C0:
 ; CHECK-NEXT: .tc   a[TC],a[UA]
-; CHECK-NEXT: LC1:
+; CHECK-NEXT: L..C1:
 ; CHECK-NEXT: .tc   b[TC],b[UA]
-; CHECK-NEXT: LC2:
+; CHECK-NEXT: L..C2:
 ; CHECK-NEXT: .tc   c[TC],c[UA]
-; CHECK-NEXT: LC3:
+; CHECK-NEXT: L..C3:
 ; CHECK-NEXT: .tc   globa[TC],globa[RW]
-; CHECK-NEXT: LC4:
+; CHECK-NEXT: L..C4:
 ; CHECK-NEXT: .tc   ptr[TC],ptr[BS]
-; CHECK-NEXT: LC5:
+; CHECK-NEXT: L..C5:
 ; CHECK-NEXT: .tc   bar[TC],bar[DS]
-; CHECK-NEXT: LC6:
+; CHECK-NEXT: L..C6:
 ; CHECK-NEXT: .tc   foo[TC],foo[DS]
-; CHECK-NEXT: LC7:
+; CHECK-NEXT: L..C7:
 ; CHECK-NEXT: .tc   foobar[TC],foobar[DS]
 
 
 ; Test undefined symbol generation.
 
 ; SYM:       File: {{.*}}aix-xcoff-toc.ll.tmp.o
 ; SYM:       Symbol {{[{][[:space:]] *}}Index: [[#UNDEF_INDX:]]{{[[:space:]] *}}Name: a
 ; SYM-NEXT:   Value (RelocatableAddress): 0x0

llvm/test/CodeGen/PowerPC/aix64-cc-byval.ll

 ; CHECK-DAG:   renamable $x9 = LD 48, renamable $x[[REGADDR]] :: (load 8)
 ; CHECK-DAG:   renamable $x10 = LD 56, renamable $x[[REGADDR]] :: (load 8)
 ; CHECK-NEXT:  BL8_NOP <mcsymbol .test_byval_64Byte>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit $x8, implicit $x9, implicit $x10, implicit $x2, implicit-def $r1
 ; CHECK-NEXT:  ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 ; CHECKASM-LABEL: .test_byval_64Byte:
 
 ; ASM:         stdu 1, -112(1)
-; ASM-NEXT:    ld [[REG:[0-9]+]], LC{{[0-9]+}}(2)
+; ASM-NEXT:    ld [[REG:[0-9]+]], L..C{{[0-9]+}}(2)
 ; ASM-DAG:     ld 3, 0([[REG]])
 ; ASM-DAG:     ld 4, 8([[REG]])
 ; ASM-DAG:     ld 5, 16([[REG]])
 ; ASM-DAG:     ld 6, 24([[REG]])
 ; ASM-DAG:     ld 7, 32([[REG]])
 ; ASM-DAG:     ld 8, 40([[REG]])
 ; ASM-DAG:     ld 9, 48([[REG]])
 ; ASM-DAG:     ld 10, 56([[REG]])
 ; ASM-NEXT:    bl .test_byval_64Byte
 ; ASM-NEXT:    nop

llvm/test/CodeGen/PowerPC/lower-globaladdr32-aix-asm.ll

 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
 ; RUN: -code-model=small < %s | FileCheck %s --check-prefixes=CHECK,SMALL
 
 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
 ; RUN: -code-model=large < %s | FileCheck %s --check-prefixes=CHECK,LARGE
 
 @a = common global i32 0
 
 define i32 @test_load() {
 entry:
   %0 = load i32, i32* @a
   ret i32 %0
 }
 
 ; SMALL-LABEL: .test_load:{{$}}
-; SMALL: lwz [[REG1:[0-9]+]], LC0(2)
+; SMALL: lwz [[REG1:[0-9]+]], L..C0(2)
 ; SMALL: lwz [[REG2:[0-9]+]], 0([[REG1]])
 ; SMALL: blr
 
 ; LARGE-LABEL: .test_load:{{$}}
-; LARGE: addis [[REG1:[0-9]+]], LC0@u(2)
-; LARGE: lwz [[REG2:[0-9]+]], LC0@l([[REG1]])
+; LARGE: addis [[REG1:[0-9]+]], L..C0@u(2)
+; LARGE: lwz [[REG2:[0-9]+]], L..C0@l([[REG1]])
 ; LARGE: lwz [[REG3:[0-9]+]], 0([[REG2]])
 ; LARGE: blr
 
 @b = common global i32 0
 
 define void @test_store(i32 %0) {
   store i32 %0, i32* @b
   ret void
 }
 
 ; SMALL-LABEL: .test_store:{{$}}
-; SMALL: lwz [[REG1:[0-9]+]], LC1(2)
+; SMALL: lwz [[REG1:[0-9]+]], L..C1(2)
 ; SMALL: stw [[REG2:[0-9]+]], 0([[REG1]])
 ; SMALL: blr
 
 ; LARGE-LABEL: .test_store:{{$}}
-; LARGE: addis [[REG1:[0-9]+]], LC1@u(2)
-; LARGE: lwz [[REG2:[0-9]+]], LC1@l([[REG1]])
+; LARGE: addis [[REG1:[0-9]+]], L..C1@u(2)
+; LARGE: lwz [[REG2:[0-9]+]], L..C1@l([[REG1]])
 ; LARGE: stw [[REG3:[0-9]+]], 0([[REG2]])
 ; LARGE: blr
 
 ; CHECK: .tc a[TC],a
 ; CHECK: .tc b[TC],b

llvm/test/CodeGen/PowerPC/lower-globaladdr64-aix-asm.ll

 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
 ; RUN: -code-model=small < %s | FileCheck %s --check-prefixes=CHECK,SMALL
 
 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
 ; RUN: -code-model=large < %s | FileCheck %s --check-prefixes=CHECK,LARGE
 
 @a = common global i32 0
 
 define zeroext i32 @test_load() {
 entry:
   %0 = load i32, i32* @a
   ret i32 %0
 }
 
 ; SMALL-LABEL: .test_load:{{$}}
-; SMALL: ld [[REG1:[0-9]+]], LC0(2)
+; SMALL: ld [[REG1:[0-9]+]], L..C0(2)
 ; SMALL: lwz [[REG2:[0-9]+]], 0([[REG1]])
 ; SMALL: blr
 
 ; LARGE-LABEL: .test_load:{{$}}
-; LARGE: addis [[REG1:[0-9]+]], LC0@u(2)
-; LARGE: ld [[REG2:[0-9]+]], LC0@l([[REG1]])
+; LARGE: addis [[REG1:[0-9]+]], L..C0@u(2)
+; LARGE: ld [[REG2:[0-9]+]], L..C0@l([[REG1]])
 ; LARGE: lwz [[REG3:[0-9]+]], 0([[REG2]])
 ; LARGE: blr
 
 @b = common global i32 0
 
 define void @test_store(i32 zeroext %0) {
   store i32 %0, i32* @b
   ret void
 }
 
 ; SMALL-LABEL: .test_store:{{$}}
-; SMALL: ld [[REG1:[0-9]+]], LC1(2)
+; SMALL: ld [[REG1:[0-9]+]], L..C1(2)
 ; SMALL: stw [[REG2:[0-9]+]], 0([[REG1]])
 ; SMALL: blr
 
 ; LARGE-LABEL: .test_store:{{$}}
-; LARGE: addis [[REG1:[0-9]+]], LC1@u(2)
-; LARGE: ld [[REG2:[0-9]+]], LC1@l([[REG1]])
+; LARGE: addis [[REG1:[0-9]+]], L..C1@u(2)
+; LARGE: ld [[REG2:[0-9]+]], L..C1@l([[REG1]])
 ; LARGE: stw [[REG3:[0-9]+]], 0([[REG2]])
 ; LARGE: blr
 
 ; CHECK: .tc a[TC],a
 ; CHECK: .tc b[TC],b