[CodeGen] Fix warnings in getZeroExtendInReg

[david-arm]

Summary

We should be using getVectorElementCount() to assert that two types
have the same numbers of elements. I encountered the warnings while
compiling this test:

CodeGen/AArch64/sve-intrinsics-ld1.ll

[c-rhodes]

LGTM!

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

 SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT VT) {
   EVT OpVT = Op.getValueType();
   assert(VT.isInteger() && OpVT.isInteger() &&
          "Cannot getZeroExtendInReg FP types");
   assert(VT.isVector() == OpVT.isVector() &&
          "getZeroExtendInReg type should be vector iff the operand "
          "type is vector!");
   assert((!VT.isVector() ||
-          VT.getVectorNumElements() == OpVT.getVectorNumElements()) &&
+          VT.getVectorElementCount() == OpVT.getVectorElementCount()) &&
          "Vector element counts must match in getZeroExtendInReg");
   assert(VT.bitsLE(OpVT) && "Not extending!");
   if (OpVT == VT)
     return Op;
   APInt Imm = APInt::getLowBitsSet(OpVT.getScalarSizeInBits(),
                                    VT.getScalarSizeInBits());
   return getNode(ISD::AND, DL, OpVT, Op, getConstant(Imm, DL, OpVT));
 }