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[x86] favor vector constant load to avoid GPR to XMM transfer
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Authored by spatel on Fri, May 15, 8:18 AM.

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Summary

This build vector lowering pattern came up in D79886. I've tried to limit the improvement to cases where it looks clearly better to load, but we could remove the 'TODO' predicates already if we are willing to overlook some corner cases.

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Event Timeline

spatel created this revision.Fri, May 15, 8:18 AM
Herald added a project: Restricted Project. · View Herald TranscriptFri, May 15, 8:18 AM
spatel marked 5 inline comments as done.Fri, May 15, 8:30 AM
spatel added inline comments.
llvm/test/CodeGen/X86/combine-udiv.ll
602

This would improve without the -1 restriction.

681–682

No change for AVX2 is probably caused by the 128-bit limit.

llvm/test/CodeGen/X86/sad.ll
547–548

This would improve without the -1 restriction.

1019–1020

No change for AVX2/AXV512 is probably caused by the 128-bit limit.

llvm/test/CodeGen/X86/vec_shift2.ll
13

This is a regression, but I'm assuming it does not matter because we have been using standard IR for vector shifts for at least 5 years. If it does matter, then I think the next test shows an existing failure of constant analysis. Also, if the high part of the shift amount is undef, then can't we fold both of these tests to constant 0 (no shift needed)?

This revision is now accepted and ready to land.Sat, May 16, 3:47 PM
This revision was automatically updated to reflect the committed changes.