[AArch64] Don't promote constants with float ConstantExpr.

[fhahn]

Summary

Currently the AsmPrinter cannot emit some floating point constant
expressions in global initializers. Avoid generating them.

[fhahn]

Simplify code.

[efriedma]

llvm/lib/Target/AArch64/AArch64PromoteConstant.cpp

578

I would rather extend the check here to make it recursive: in addition to restricting ConstantExprs, restrict ConstantAggregates that contain a ConstantExpr or GlobalValue. Or just call Constant::needsRelocation().

[fhahn]

Update to disallow any constant expressions, global values or blockvalues.

[fhahn]

llvm/lib/Target/AArch64/AArch64PromoteConstant.cpp

578

Done, I've changed containsFloatConstantExpr to containsOnlyConstantData which traverses ConstantAggregates.

[efriedma]

LGTM

[fhahn]

Thanks Eli!

llvm/lib/Target/AArch64/AArch64PromoteConstant.cpp

for (unsigned EltIdx = 0, EndEltIdx = CstTy->getStructNumElements();
          EltIdx < EndEltIdx; ++EltIdx)
       if (isConstantUsingVectorTy(CstTy->getStructElementType(EltIdx)))
         return true;
   } else if (CstTy->isArrayTy())
     return isConstantUsingVectorTy(CstTy->getArrayElementType());
   return false;
 }
 
+// Returns true if \p C contains a floating point constant expressions. Such
+// constant expressions are not supported in initializers by AsmPrinter.
+static bool containsFloatConstantExpr(const Constant *C) {
+  Type *T = C->getType();
+
+  if (auto *ArrayTy = dyn_cast<ArrayType>(T))
+    T = ArrayTy->getElementType();
+  else if (auto *VecTy = dyn_cast<VectorType>(T))
+    T = VecTy->getElementType();
+
+  if (T->isFloatingPointTy() && isa<ConstantExpr>(C))
+    return true;
+
+  return any_of(C->operands(), [](const Use &U) {
+    return containsFloatConstantExpr(cast<Constant>(&U));
+  });
+}
+
 /// Check if the given use (Instruction + OpIdx) of Cst should be converted into
 /// a load of a global variable initialized with Cst.
 /// A use should be converted if it is legal to do so.
 /// For instance, it is not legal to turn the mask operand of a shuffle vector
 /// into a load of a global variable.
 static bool shouldConvertUse(const Constant *Cst, const Instruction *Instr,
                              unsigned OpIdx) {
+  // AsmPrinter cannot lower floating point constant expressions in
+  // initializers.
+  if (containsFloatConstantExpr(Cst))
+    return false;
+
   // shufflevector instruction expects a const for the mask argument, i.e., the
   // third argument. Do not promote this use in that case.
   if (isa<const ShuffleVectorInst>(Instr) && OpIdx == 2)
     return false;
 
   // extractvalue instruction expects a const idx.
   if (isa<const ExtractValueInst>(Instr) && OpIdx > 0)
     return false;
bool AArch64PromoteConstant::runOnFunction(Function &F,
   for (Instruction &I : instructions(&F)) {
     // Traverse the operand, looking for constant vectors. Replace them by a
     // load of a global variable of constant vector type.
     for (Use &U : I.operands()) {
       Constant *Cst = dyn_cast<Constant>(U);
       // There is no point in promoting global values as they are already
       // global. Do not promote constant expressions either, as they may
       // require some code expansion.
       if (!Cst || isa<GlobalValue>(Cst) || isa<ConstantExpr>(Cst))
         continue;
 
       // Check if this constant is worth promoting.
       if (!shouldConvert(*Cst, PromotionCache))
         continue;
 
       // Check if this use should be promoted.
       unsigned OpNo = &U - I.op_begin();

llvm/test/CodeGen/AArch64/arm64-promote-const-complex-initializers.ll

+; RUN: llc -o - %s | FileCheck %s
+
+; AsmPrinter cannot lower floating point constant expressions in global
+; initializers. Check that we do not create new globals with float constant
+; expressions in initializers.
+
+target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+target triple = "arm64-apple-ios14.0.0"
+
+define [1 x <4 x float>] @test1() {
+; CHECK-LABEL:    .p2align    4               ; -- Begin function test1
+; CHECK-NEXT: lCPI0_0:
+; CHECK-NEXT:     .quad   0                       ; 0x0
+; CHECK-NEXT:     .quad   4575657221408423936     ; 0x3f80000000000000
+; CHECK-NEXT:     .section    __TEXT,__text,regular,pure_instructions
+; CHECK-NEXT:     .globl  _test1
+; CHECK-NEXT:     .p2align    2
+; CHECK-NEXT: _test1:                                 ; @test1
+; CHECK-NEXT:     .cfi_startproc
+; CHECK-NEXT: ; %bb.0:
+; CHECK-NEXT: Lloh0:
+; CHECK-NEXT:     adrp    x8, lCPI0_0@PAGE
+; CHECK-NEXT: Lloh1:
+; CHECK-NEXT:     ldr q0, [x8, lCPI0_0@PAGEOFF]
+; CHECK-NEXT:     ret
+
+  ret [1 x <4 x float>] [<4 x float> bitcast (<1 x i128> <i128 84405977732342157929391748327801880576> to <4 x float>)]
+}
+
+define [1 x <4 x float>] @test2() {
+; CHECK-LABEL:    .p2align    4               ; -- Begin function test2
+; CHECK-NEXT: lCPI1_0:
+; CHECK-NEXT:     .long   0x00000000              ; float 0
+; CHECK-NEXT:     .long   0x00000000              ; float 0
+; CHECK-NEXT:     .long   0x00000000              ; float 0
+; CHECK-NEXT:     .long   0x3f800000              ; float 1
+; CHECK-NEXT:     .section    __TEXT,__text,regular,pure_instructions
+; CHECK-NEXT:     .globl  _test2
+; CHECK-NEXT:     .p2align    2
+; CHECK-NEXT: _test2:                                 ; @test2
+; CHECK-NEXT:     .cfi_startproc
+; CHECK-NEXT: ; %bb.0:
+; CHECK-NEXT: Lloh2:
+; CHECK-NEXT:     adrp    x8, lCPI1_0@PAGE
+; CHECK-NEXT: Lloh3:
+; CHECK-NEXT:     ldr q1, [x8, lCPI1_0@PAGEOFF]
+; CHECK-NEXT:     mov s2, v1[1]
+; CHECK-NEXT:     fneg    s0, s1
+; CHECK-NEXT:     mov s3, v1[2]
+; CHECK-NEXT:     fneg    s2, s2
+; CHECK-NEXT:     mov s1, v1[3]
+; CHECK-NEXT:     fneg    s3, s3
+; CHECK-NEXT:     mov.s   v0[1], v2[0]
+; CHECK-NEXT:     mov.s   v0[2], v3[0]
+; CHECK-NEXT:     fneg    s1, s1
+; CHECK-NEXT:     mov.s   v0[3], v1[0]
+; CHECK-NEXT:     ret
+;
+  ret [1 x <4 x float>] [<4 x float>
+    <float fneg (float extractelement (<4 x float> bitcast (<1 x i128> <i128 84405977732342157929391748327801880576> to <4 x float>), i32 0)),
+     float fneg (float extractelement (<4 x float> bitcast (<1 x i128> <i128 84405977732342157929391748327801880576> to <4 x float>), i32 1)),
+     float fneg (float extractelement (<4 x float> bitcast (<1 x i128> <i128 84405977732342157929391748327801880576> to <4 x float>), i32 2)),
+     float fneg (float extractelement (<4 x float> bitcast (<1 x i128> <i128 84405977732342157929391748327801880576> to <4 x float>), i32 3))>]
+}