[SveEmitter] Builtins for SVE matrix multiply `mmla`.

[fpetrogalli]

Summary

Guarded by __ARM_FEATURE_SVE_MATMUL_INT8:

• svmmla_u32
• svmmla_s32
• svusmmla_s32

Guarded by __ARM_FEATURE_SVE_MATMUL_FP32:

• svmmla_f32

Guarded by __ARM_FEATURE_SVE_MATMUL_FP64:

• svmmla_f64

[fpetrogalli]

I replaced the lines Signed = !Signed in the tablegen emitter with Signed = false.

[sdesmalen]

clang/include/clang/Basic/arm_sve.td

74

Can you phrase this like e and move it below e as well:

1/4 width unsigned elements, 4 x element count

1228

nit: please fix the alignment like how this is done for the other definitions.

clang/lib/CodeGen/CGBuiltin.cpp

7988

unnecessary change, please remove.

clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_matmul_fp32.c

1

nit: These RUN lines no longer match all the other ACLE tests (with the added newlines)

[fpetrogalli]

Thank you for the review @sdesmalen, I have addressed all your comments.

Francesco

[fpetrogalli]

Adding some text here as phabricator refuses to submit with an empty comment...

[sdesmalen]

LGTM!

clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mmla.c

18

nit: please remove the whitespace between the commas (to make it similar to the other tests)

[fpetrogalli]

Thank you for the review @sdesmalen!

Francesco

[fpetrogalli]

clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mmla.c

18

Done. May I ask the reason why this formatting is preferred? The command git clang-format prefers the one with spaces...

clang/include/clang/Basic/arm_sve.td

 // P: predicate type
 // s: scalar of element type
 // a: scalar of element type (splat to vector type)
 // R: scalar of 1/2 width element type (splat to vector type)
 // r: scalar of 1/4 width element type (splat to vector type)
 // e: 1/2 width unsigned elements, 2x element count
 // h: 1/2 width elements, 2x element count
 // q: 1/4 width elements, 4x element count
+// b: 1/4 width elements, 4x element count, integer, unsigned
 // o: 4x width elements, 1/4 element count
 //
 // w: vector of element type promoted to 64bits, vector maintains
 //    signedness of its element type.
 // f: element type promoted to uint64_t (splat to vector type)
 // j: element type promoted to 64bits (splat to vector type)
 // K: element type bitcast to a signed integer (splat to vector type)
 // L: element type bitcast to an unsigned integer (splat to vector type)

 def SVQDECP_N_S64 : SInst<"svqdecp[_n_s64]_{d}", "llP", "PcPsPiPl", MergeNone, "aarch64_sve_sqdecp_n64">;
 def SVQDECP_N_U32 : SInst<"svqdecp[_n_u32]_{d}", "mmP", "PcPsPiPl", MergeNone, "aarch64_sve_uqdecp_n32">;
 def SVQDECP_N_U64 : SInst<"svqdecp[_n_u64]_{d}", "nnP", "PcPsPiPl", MergeNone, "aarch64_sve_uqdecp_n64">;
 def SVQINCP_N_S32 : SInst<"svqincp[_n_s32]_{d}", "kkP", "PcPsPiPl", MergeNone, "aarch64_sve_sqincp_n32">;
 def SVQINCP_N_S64 : SInst<"svqincp[_n_s64]_{d}", "llP", "PcPsPiPl", MergeNone, "aarch64_sve_sqincp_n64">;
 def SVQINCP_N_U32 : SInst<"svqincp[_n_u32]_{d}", "mmP", "PcPsPiPl", MergeNone, "aarch64_sve_uqincp_n32">;
 def SVQINCP_N_U64 : SInst<"svqincp[_n_u64]_{d}", "nnP", "PcPsPiPl", MergeNone, "aarch64_sve_uqincp_n64">;
 
+let ArchGuard = "defined(__ARM_FEATURE_SVE_MATMUL_INT8)" in {
+def SVMLLA_S32 : SInst<"svmmla[_s32]", "ddqq","i", MergeNone, "aarch64_sve_smmla">;
+def SVMLLA_U32 : SInst<"svmmla[_u32]", "ddqq","Ui", MergeNone, "aarch64_sve_ummla">;
+def SVUSMLLA_S32 : SInst<"svusmmla[_s32]", "ddbq","i", MergeNone, "aarch64_sve_usmmla">;
+}
+
+let ArchGuard = "defined(__ARM_FEATURE_SVE_MATMUL_FP32)" in {
+def SVMLLA_F32 : SInst<"svmmla[_f32]", "dddd","f", MergeNone, "aarch64_sve_mmla">;
+}
+
+let ArchGuard = "defined(__ARM_FEATURE_SVE_MATMUL_FP64)" in {
+def SVMLLA_F64 : SInst<"svmmla[_f64]", "dddd","d", MergeNone, "aarch64_sve_mmla">;
+}
+
+
 ////////////////////////////////////////////////////////////////////////////////
 // SVE2 WhileGE/GT
 let ArchGuard = "defined(__ARM_FEATURE_SVE2)" in {
 def SVWHILEGE_S32 : SInst<"svwhilege_{d}[_{1}]", "Pkk", "PcPsPiPl",     MergeNone, "aarch64_sve_whilege", [IsOverloadWhile]>;
 def SVWHILEGE_S64 : SInst<"svwhilege_{d}[_{1}]", "Pll", "PcPsPiPl",     MergeNone, "aarch64_sve_whilege", [IsOverloadWhile]>;
 def SVWHILEGT_S32 : SInst<"svwhilegt_{d}[_{1}]", "Pkk", "PcPsPiPl",     MergeNone, "aarch64_sve_whilegt", [IsOverloadWhile]>;
 def SVWHILEGT_S64 : SInst<"svwhilegt_{d}[_{1}]", "Pll", "PcPsPiPl",     MergeNone, "aarch64_sve_whilegt", [IsOverloadWhile]>;
 def SVWHILEHI_U32 : SInst<"svwhilegt_{d}[_{1}]", "Pmm", "PUcPUsPUiPUl", MergeNone, "aarch64_sve_whilehi", [IsOverloadWhile]>;

clang/lib/CodeGen/CGBuiltin.cpp

else {
       // Immediates for SVE llvm intrinsics are always 32bit.  We can safely
       // truncate because the immediate has been range checked and no valid
       // immediate requires more than a handful of bits.
       Result = Result.extOrTrunc(32);
       Ops.push_back(llvm::ConstantInt::get(getLLVMContext(), Result));
     }
   }
 
-  auto *Builtin = findARMVectorIntrinsicInMap(AArch64SVEIntrinsicMap, BuiltinID,
-                                              AArch64SVEIntrinsicsProvenSorted);
+  const ARMVectorIntrinsicInfo *Builtin = findARMVectorIntrinsicInMap(
+      AArch64SVEIntrinsicMap, BuiltinID, AArch64SVEIntrinsicsProvenSorted);
   SVETypeFlags TypeFlags(Builtin->TypeModifier);
   if (TypeFlags.isLoad())
     return EmitSVEMaskedLoad(E, Ty, Ops, Builtin->LLVMIntrinsic,
                              TypeFlags.isZExtReturn());
   else if (TypeFlags.isStore())
     return EmitSVEMaskedStore(E, Ops, Builtin->LLVMIntrinsic);
   else if (TypeFlags.isGatherLoad())
     return EmitSVEGatherLoad(TypeFlags, Ops, Builtin->LLVMIntrinsic);

clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_matmul_fp32.c

+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE_MATMUL_FP32 \
+// RUN:            -triple aarch64-none-linux-gnu -target-feature +sve \
+// RUN:            -fallow-half-arguments-and-returns -S -O1 -Werror -Wall \
+// RUN:            -emit-llvm -o - %s | FileCheck %s
+
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE_MATMUL_FP32 \
+// RUN:            -triple aarch64-none-linux-gnu -target-feature +sve \
+// RUN:            -fallow-half-arguments-and-returns -S -O1 -Werror -Wall \
+// RUN:            -emit-llvm -o - %s -DSVE_OVERLOADED_FORMS | FileCheck %s
+
+#include <arm_sve.h>
+
+#ifdef SVE_OVERLOADED_FORMS
+// A simple used,unused... macro, long enough to represent any SVE builtin.
+#define SVE_ACLE_FUNC(A1, A2_UNUSED, A3, A4_UNUSED) A1##A3
+#else
+#define SVE_ACLE_FUNC(A1, A2, A3, A4) A1##A2##A3##A4
+#endif
+
+svfloat32_t test_svmmla_f32(svfloat32_t x, svfloat32_t y, svfloat32_t z) {
+  // CHECK-LABEL: test_svmmla_f32
+  // CHECK: %[[RET:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.mmla.nxv4f32(<vscale x 4 x float> %x, <vscale x 4 x float> %y, <vscale x 4 x float> %z)
+  // CHECK: ret <vscale x 4 x float> %[[RET]]
+  return SVE_ACLE_FUNC(svmmla, _f32, , )(x, y, z);
+}

clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_matmul_fp64.c

+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE_MATMUL_FP64 \
+// RUN:            -triple aarch64-none-linux-gnu -target-feature +sve \
+// RUN:            -fallow-half-arguments-and-returns -S -O1 -Werror -Wall \
+// RUN:            -emit-llvm -o - %s | FileCheck %s
+
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE_MATMUL_FP64 \
+// RUN:            -triple aarch64-none-linux-gnu -target-feature +sve \
+// RUN:            -fallow-half-arguments-and-returns -S -O1 -Werror -Wall \
+// RUN:            -emit-llvm -o - %s -DSVE_OVERLOADED_FORMS | FileCheck %s
+
+#include <arm_sve.h>
+
+#ifdef SVE_OVERLOADED_FORMS
+// A simple used,unused... macro, long enough to represent any SVE builtin.
+#define SVE_ACLE_FUNC(A1, A2_UNUSED, A3, A4_UNUSED) A1##A3
+#else
+#define SVE_ACLE_FUNC(A1, A2, A3, A4) A1##A2##A3##A4
+#endif
+
+svfloat64_t test_svmmla_f64(svfloat64_t x, svfloat64_t y, svfloat64_t z) {
+  // CHECK-LABEL: test_svmmla_f64
+  // CHECK: %[[RET:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.mmla.nxv2f64(<vscale x 2 x double> %x, <vscale x 2 x double> %y, <vscale x 2 x double> %z)
+  // CHECK: ret <vscale x 2 x double> %[[RET]]
+  return SVE_ACLE_FUNC(svmmla, _f64, , )(x, y, z);
+}

clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mmla.c

+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE_MATMUL_INT8 \
+// RUN:            -triple aarch64-none-linux-gnu -target-feature +sve \
+// RUN:            -fallow-half-arguments-and-returns -S -O1 -Werror -Wall \
+// RUN:            -emit-llvm -o - %s | FileCheck %s
+
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE_MATMUL_INT8 \
+// RUN:            -triple aarch64-none-linux-gnu -target-feature +sve \
+// RUN:            -fallow-half-arguments-and-returns -S -O1 -Werror -Wall \
+// RUN:            -emit-llvm -o - %s -DSVE_OVERLOADED_FORMS| FileCheck %s
+
+#include <arm_sve.h>
+
+#ifdef SVE_OVERLOADED_FORMS
+// A simple used,unused... macro, long enough to represent any SVE builtin.
+#define SVE_ACLE_FUNC(A1, A2_UNUSED, A3, A4_UNUSED) A1##A3
+#else
+#define SVE_ACLE_FUNC(A1, A2, A3, A4) A1##A2##A3##A4
+#endif
+
+svint32_t test_svmmla_s32(svint32_t x, svint8_t y, svint8_t z) {
+  // CHECK-LABEL: test_svmmla_s32
+  // CHECK: %[[RET:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.smmla.nxv4i32(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z)
+  // CHECK: ret <vscale x 4 x i32> %[[RET]]
+  return SVE_ACLE_FUNC(svmmla, _s32, , )(x, y, z);
+}
+
+svuint32_t test_svmmla_u32(svuint32_t x, svuint8_t y, svuint8_t z) {
+  // CHECK-LABEL: test_svmmla_u32
+  // CHECK: %[[RET:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.ummla.nxv4i32(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z)
+  // CHECK: ret <vscale x 4 x i32> %[[RET]]
+  return SVE_ACLE_FUNC(svmmla, _u32, , )(x, y, z);
+}
+
+svint32_t test_svusmmla_s32(svint32_t x, svuint8_t y, svint8_t z) {
+  // CHECK-LABEL: test_svusmmla_s32
+  // CHECK: %[[RET:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.usmmla.nxv4i32(<vscale x 4 x i32> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %z)
+  // CHECK: ret <vscale x 4 x i32> %[[RET]]
+  return SVE_ACLE_FUNC(svusmmla, _s32, , )(x, y, z);
+}

clang/utils/TableGen/SveEmitter.cpp

case 'e':
     ElementBitwidth /= 2;
     break;
   case 'h':
     ElementBitwidth /= 2;
     break;
   case 'q':
     ElementBitwidth /= 4;
     break;
+  case 'b':
+    Signed = false;
+    Float = false;
+    ElementBitwidth /= 4;
+    break;
   case 'o':
     ElementBitwidth *= 4;
     break;
   case 'P':
     Signed = true;
     Float = false;
     Predicate = true;
     Bitwidth = 16;