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Differential D79606

[ARM] Convert VDUPLANE to VDUP under MVE
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Authored by dmgreen on May 7 2020, 3:31 PM.

Details

Reviewers
efriedma
SjoerdMeijer
simon_tatham
ostannard
samparker
Commits
rG6eee2d9b5bdd: [ARM] Convert VDUPLANE to VDUP under MVE
Summary

Unlike Neon, MVE does not have a way of duplicating from a vector lane, so a VDUPLANE currently selects to a VDUP(move_from_lane(..)). This forces that to be done earlier as a dag combine to allow other folds to happen.

It converts to a VDUP(EXTRACT). On FP16 this is then folded to a VGETLANEu to prevent it from creating a vmovx;vmovhr pair, using a single move_from_reg instead.

Diff Detail

Event Timeline

dmgreen created this revision.May 7 2020, 3:31 PM
Herald added a project: Restricted Project. · View Herald TranscriptMay 7 2020, 3:31 PM
Herald added subscribers: danielkiss, hiraditya, kristof.beyls. · View Herald Transcript
efriedma added a comment.May 7 2020, 4:08 PM

Some of the code differences here make me suspect we're missing combines for VDUPLANE. But that's not really something you need to concern yourself with here, I guess.

If you never want VDUPLANE, it doesn't seem like there's much point to generating it in the first place; I guess you want to continue supporting it just to make it easier to share code between NEON and MVE?

llvm/lib/Target/ARM/ARMISelLowering.cpp
13853

I guess if you didn't have a special case for f16 here, you could still eventually get to the same place, but it would take some extra steps?

dmgreen marked an inline comment as done.May 8 2020, 12:45 AM
In D79606#2026276, @efriedma wrote:

If you never want VDUPLANE, it doesn't seem like there's much point to generating it in the first place; I guess you want to continue supporting it just to make it easier to share code between NEON and MVE?

Yep. They can be generate in a few different place, and although it would be possible to stop them being created, it complicates the logic. I agree it's strange on it's own to create a node only to convert it into something else, but if it keeps the buildvector/vectorshuffle code simpler and helps them be shared between neon and mve, I think this is probably simpler overall.

llvm/lib/Target/ARM/ARMISelLowering.cpp
13853

I was originally thinking this would need to look at the demanded bits of the VMOVrh which complicate things, but yeah it's simpler than that. With VGETLANEu we can add a fold easily enough and still get the top lanes correct. I can change things around to do it that way.

dmgreen updated this revision to Diff 262828.May 8 2020, 12:56 AM

Now with an extra VMOVrh(extract(..)) -> VGETLANEu fold.

dmgreen edited the summary of this revision. (Show Details)May 8 2020, 12:57 AM
efriedma accepted this revision.May 8 2020, 10:29 AM

LGTM

This revision is now accepted and ready to land.May 8 2020, 10:29 AM
Closed by commit rG6eee2d9b5bdd: [ARM] Convert VDUPLANE to VDUP under MVE (authored by dmgreen). · Explain WhyMay 9 2020, 11:09 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
lib/
Target/
ARM/
27 lines
2 lines
18 lines
test/
CodeGen/
Thumb2/
LowOverheadLoops/
10 lines
2 lines
4 lines
80 lines
203 lines
21 lines
562 lines

Diff 262776

llvm/lib/Target/ARM/ARMISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 13,835 Lines • ▼ Show 20 Linesstatic bool CombineVLDDUP(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
DCI.CombineTo(VLD, VLDDupResults); DCI.CombineTo(VLD, VLDDupResults);
return true; return true;
} }
/// PerformVDUPLANECombine - Target-specific dag combine xforms for /// PerformVDUPLANECombine - Target-specific dag combine xforms for
/// ARMISD::VDUPLANE. /// ARMISD::VDUPLANE.
static SDValue PerformVDUPLANECombine(SDNode *N, static SDValue PerformVDUPLANECombine(SDNode *N,
TargetLowering::DAGCombinerInfo &DCI) { TargetLowering::DAGCombinerInfo &DCI,
const ARMSubtarget *Subtarget) {
SDValue Op = N->getOperand(0); SDValue Op = N->getOperand(0);
EVT VT = N->getValueType(0);
// On MVE, we just convert the VDUPLANE to a VDUP with an extract.
if (Subtarget->hasMVEIntegerOps()) {
EVT ExtractVT = VT.getVectorElementType();
SDValue Extract;
if (ExtractVT == MVT::f16) {
efriedmaUnsubmitted
Not Done
ReplyInline Actions

I guess if you didn't have a special case for f16 here, you could still eventually get to the same place, but it would take some extra steps?

efriedma: I guess if you didn't have a special case for f16 here, you could still eventually get to the…
dmgreenAuthorUnsubmitted
Done
ReplyInline Actions

I was originally thinking this would need to look at the demanded bits of the VMOVrh which complicate things, but yeah it's simpler than that. With VGETLANEu we can add a fold easily enough and still get the top lanes correct. I can change things around to do it that way.

dmgreen: I was originally thinking this would need to look at the demanded bits of the VMOVrh which…
// FP16 are always a little special and go via a VGETLANEu to stop it
// using a vmovx;vmovhr pair.
Extract = DCI.DAG.getNode(ARMISD::VGETLANEu, SDLoc(N), MVT::i32,
N->getOperand(0), N->getOperand(1));
}
else {
// Otherwise we need to ensure we are creating a legal type.
if (!DCI.DAG.getTargetLoweringInfo().isTypeLegal(ExtractVT))
ExtractVT = MVT::i32;
Extract = DCI.DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), ExtractVT,
N->getOperand(0), N->getOperand(1));
}
return DCI.DAG.getNode(ARMISD::VDUP, SDLoc(N), VT, Extract);
}
// If the source is a vldN-lane (N > 1) intrinsic, and all the other uses // If the source is a vldN-lane (N > 1) intrinsic, and all the other uses
// of that intrinsic are also VDUPLANEs, combine them to a vldN-dup operation. // of that intrinsic are also VDUPLANEs, combine them to a vldN-dup operation.
if (CombineVLDDUP(N, DCI)) if (CombineVLDDUP(N, DCI))
return SDValue(N, 0); return SDValue(N, 0);
// If the source is already a VMOVIMM or VMVNIMM splat, the VDUPLANE is // If the source is already a VMOVIMM or VMVNIMM splat, the VDUPLANE is
// redundant. Ignore bit_converts for now; element sizes are checked below. // redundant. Ignore bit_converts for now; element sizes are checked below.
while (Op.getOpcode() == ISD::BITCAST) while (Op.getOpcode() == ISD::BITCAST)
Op = Op.getOperand(0); Op = Op.getOperand(0);
if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM) if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM)
return SDValue(); return SDValue();
// Make sure the VMOV element size is not bigger than the VDUPLANE elements. // Make sure the VMOV element size is not bigger than the VDUPLANE elements.
unsigned EltSize = Op.getScalarValueSizeInBits(); unsigned EltSize = Op.getScalarValueSizeInBits();
// The canonical VMOV for a zero vector uses a 32-bit element size. // The canonical VMOV for a zero vector uses a 32-bit element size.
unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
unsigned EltBits; unsigned EltBits;
if (ARM_AM::decodeVMOVModImm(Imm, EltBits) == 0) if (ARM_AM::decodeVMOVModImm(Imm, EltBits) == 0)
EltSize = 8; EltSize = 8;
EVT VT = N->getValueType(0);
if (EltSize > VT.getScalarSizeInBits()) if (EltSize > VT.getScalarSizeInBits())
return SDValue(); return SDValue();
return DCI.DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op); return DCI.DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
} }
/// PerformVDUPCombine - Target-specific dag combine xforms for ARMISD::VDUP. /// PerformVDUPCombine - Target-specific dag combine xforms for ARMISD::VDUP.
static SDValue PerformVDUPCombine(SDNode *N, static SDValue PerformVDUPCombine(SDNode *N,
▲ Show 20 Lines • Show All 1,464 Lines • ▼ Show 20 LinesSDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG); case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG);
case ARMISD::VMOVhr: return PerformVMOVhrCombine(N, DCI); case ARMISD::VMOVhr: return PerformVMOVhrCombine(N, DCI);
case ARMISD::VMOVrh: return PerformVMOVrhCombine(N, DCI); case ARMISD::VMOVrh: return PerformVMOVrhCombine(N, DCI);
case ISD::STORE: return PerformSTORECombine(N, DCI, Subtarget); case ISD::STORE: return PerformSTORECombine(N, DCI, Subtarget);
case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI, Subtarget); case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI, Subtarget);
case ISD::INSERT_VECTOR_ELT: return PerformInsertEltCombine(N, DCI); case ISD::INSERT_VECTOR_ELT: return PerformInsertEltCombine(N, DCI);
case ISD::EXTRACT_VECTOR_ELT: return PerformExtractEltCombine(N, DCI); case ISD::EXTRACT_VECTOR_ELT: return PerformExtractEltCombine(N, DCI);
case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG); case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG);
case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI); case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI, Subtarget);
case ARMISD::VDUP: return PerformVDUPCombine(N, DCI, Subtarget); case ARMISD::VDUP: return PerformVDUPCombine(N, DCI, Subtarget);
case ISD::FP_TO_SINT: case ISD::FP_TO_SINT:
case ISD::FP_TO_UINT: case ISD::FP_TO_UINT:
return PerformVCVTCombine(N, DCI.DAG, Subtarget); return PerformVCVTCombine(N, DCI.DAG, Subtarget);
case ISD::FDIV: case ISD::FDIV:
return PerformVDIVCombine(N, DCI.DAG, Subtarget); return PerformVDIVCombine(N, DCI.DAG, Subtarget);
case ISD::INTRINSIC_WO_CHAIN: case ISD::INTRINSIC_WO_CHAIN:
return PerformIntrinsicCombine(N, DCI); return PerformIntrinsicCombine(N, DCI);
▲ Show 20 Lines • Show All 2,964 Lines • Show Last 20 Lines

llvm/lib/Target/ARM/ARMInstrInfo.td

Show First 20 Lines • Show All 258 Lines • ▼ Show 20 Linesdef ARMvduplane : SDNode<"ARMISD::VDUPLANE",
SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
SDTCisVT<2, i32>]>>; SDTCisVT<2, i32>]>>;
def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>; def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
def ARMvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>; def ARMvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
def ARMvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>; def ARMvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
def ARMvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>; def ARMvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>, def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVec<1>,
SDTCisVT<2, i32>]>; SDTCisVT<2, i32>]>;
def ARMvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>; def ARMvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
def ARMvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>; def ARMvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
def SDTARMVMOVIMM : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>; def SDTARMVMOVIMM : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
def ARMvmovImm : SDNode<"ARMISD::VMOVIMM", SDTARMVMOVIMM>; def ARMvmovImm : SDNode<"ARMISD::VMOVIMM", SDTARMVMOVIMM>;
def ARMvmvnImm : SDNode<"ARMISD::VMVNIMM", SDTARMVMOVIMM>; def ARMvmvnImm : SDNode<"ARMISD::VMVNIMM", SDTARMVMOVIMM>;
def ARMvmovFPImm : SDNode<"ARMISD::VMOVFPIMM", SDTARMVMOVIMM>; def ARMvmovFPImm : SDNode<"ARMISD::VMOVFPIMM", SDTARMVMOVIMM>;
▲ Show 20 Lines • Show All 6,044 Lines • Show Last 20 Lines

llvm/lib/Target/ARM/ARMInstrMVE.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 1,684 Lines • ▼ Show 20 Lines def : Pat<(vector_insert (v16i8 MQPR:$src1), rGPR:$src2, imm:$lane),
(MVE_VMOV_to_lane_8 MQPR:$src1, rGPR:$src2, imm:$lane)>; (MVE_VMOV_to_lane_8 MQPR:$src1, rGPR:$src2, imm:$lane)>;
def : Pat<(vector_insert (v8i16 MQPR:$src1), rGPR:$src2, imm:$lane), def : Pat<(vector_insert (v8i16 MQPR:$src1), rGPR:$src2, imm:$lane),
(MVE_VMOV_to_lane_16 MQPR:$src1, rGPR:$src2, imm:$lane)>; (MVE_VMOV_to_lane_16 MQPR:$src1, rGPR:$src2, imm:$lane)>;
def : Pat<(ARMvgetlanes (v16i8 MQPR:$src), imm:$lane), def : Pat<(ARMvgetlanes (v16i8 MQPR:$src), imm:$lane),
(MVE_VMOV_from_lane_s8 MQPR:$src, imm:$lane)>; (MVE_VMOV_from_lane_s8 MQPR:$src, imm:$lane)>;
def : Pat<(ARMvgetlanes (v8i16 MQPR:$src), imm:$lane), def : Pat<(ARMvgetlanes (v8i16 MQPR:$src), imm:$lane),
(MVE_VMOV_from_lane_s16 MQPR:$src, imm:$lane)>; (MVE_VMOV_from_lane_s16 MQPR:$src, imm:$lane)>;
def : Pat<(ARMvgetlanes (v8f16 MQPR:$src), imm:$lane),
(MVE_VMOV_from_lane_s16 MQPR:$src, imm:$lane)>;
def : Pat<(ARMvgetlaneu (v16i8 MQPR:$src), imm:$lane), def : Pat<(ARMvgetlaneu (v16i8 MQPR:$src), imm:$lane),
(MVE_VMOV_from_lane_u8 MQPR:$src, imm:$lane)>; (MVE_VMOV_from_lane_u8 MQPR:$src, imm:$lane)>;
def : Pat<(ARMvgetlaneu (v8i16 MQPR:$src), imm:$lane), def : Pat<(ARMvgetlaneu (v8i16 MQPR:$src), imm:$lane),
(MVE_VMOV_from_lane_u16 MQPR:$src, imm:$lane)>; (MVE_VMOV_from_lane_u16 MQPR:$src, imm:$lane)>;
def : Pat<(ARMvgetlaneu (v8f16 MQPR:$src), imm:$lane),
(MVE_VMOV_from_lane_u16 MQPR:$src, imm:$lane)>;
def : Pat<(v16i8 (scalar_to_vector GPR:$src)), def : Pat<(v16i8 (scalar_to_vector GPR:$src)),
(MVE_VMOV_to_lane_8 (v16i8 (IMPLICIT_DEF)), rGPR:$src, (i32 0))>; (MVE_VMOV_to_lane_8 (v16i8 (IMPLICIT_DEF)), rGPR:$src, (i32 0))>;
def : Pat<(v8i16 (scalar_to_vector GPR:$src)), def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
(MVE_VMOV_to_lane_16 (v8i16 (IMPLICIT_DEF)), rGPR:$src, (i32 0))>; (MVE_VMOV_to_lane_16 (v8i16 (IMPLICIT_DEF)), rGPR:$src, (i32 0))>;
def : Pat<(v4i32 (scalar_to_vector GPR:$src)), def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
(MVE_VMOV_to_lane_32 (v4i32 (IMPLICIT_DEF)), rGPR:$src, (i32 0))>; (MVE_VMOV_to_lane_32 (v4i32 (IMPLICIT_DEF)), rGPR:$src, (i32 0))>;
▲ Show 20 Lines • Show All 517 Lines • ▼ Show 20 Lines
let Predicates = [HasMVEInt] in { let Predicates = [HasMVEInt] in {
def : Pat<(v16i8 (ARMvdup (i32 rGPR:$elem))), def : Pat<(v16i8 (ARMvdup (i32 rGPR:$elem))),
(MVE_VDUP8 rGPR:$elem)>; (MVE_VDUP8 rGPR:$elem)>;
def : Pat<(v8i16 (ARMvdup (i32 rGPR:$elem))), def : Pat<(v8i16 (ARMvdup (i32 rGPR:$elem))),
(MVE_VDUP16 rGPR:$elem)>; (MVE_VDUP16 rGPR:$elem)>;
def : Pat<(v4i32 (ARMvdup (i32 rGPR:$elem))), def : Pat<(v4i32 (ARMvdup (i32 rGPR:$elem))),
(MVE_VDUP32 rGPR:$elem)>; (MVE_VDUP32 rGPR:$elem)>;
def : Pat<(v4i32 (ARMvduplane (v4i32 MQPR:$src), imm:$lane)),
(MVE_VDUP32 (MVE_VMOV_from_lane_32 MQPR:$src, imm:$lane))>;
// For the 16-bit and 8-bit vduplanes we don't care about the signedness
// of the lane move operation as we only want the lowest 8/16 bits anyway.
def : Pat<(v8i16 (ARMvduplane (v8i16 MQPR:$src), imm:$lane)),
(MVE_VDUP16 (MVE_VMOV_from_lane_u16 MQPR:$src, imm:$lane))>;
def : Pat<(v16i8 (ARMvduplane (v16i8 MQPR:$src), imm:$lane)),
(MVE_VDUP8 (MVE_VMOV_from_lane_u8 MQPR:$src, imm:$lane))>;
def : Pat<(v8f16 (ARMvdup (i32 rGPR:$elem))), def : Pat<(v8f16 (ARMvdup (i32 rGPR:$elem))),
(MVE_VDUP16 rGPR:$elem)>; (MVE_VDUP16 rGPR:$elem)>;
def : Pat<(v4f32 (ARMvdup (i32 rGPR:$elem))), def : Pat<(v4f32 (ARMvdup (i32 rGPR:$elem))),
(MVE_VDUP32 rGPR:$elem)>; (MVE_VDUP32 rGPR:$elem)>;
def : Pat<(v4f32 (ARMvduplane (v4f32 MQPR:$src), imm:$lane)),
(MVE_VDUP32 (MVE_VMOV_from_lane_32 MQPR:$src, imm:$lane))>;
def : Pat<(v8f16 (ARMvduplane (v8f16 MQPR:$src), imm:$lane)),
(MVE_VDUP16 (MVE_VMOV_from_lane_u16 MQPR:$src, imm:$lane))>;
// Match a vselect with an ARMvdup as a predicated MVE_VDUP // Match a vselect with an ARMvdup as a predicated MVE_VDUP
def : Pat<(v16i8 (vselect (v16i1 VCCR:$pred), def : Pat<(v16i8 (vselect (v16i1 VCCR:$pred),
(v16i8 (ARMvdup (i32 rGPR:$elem))), (v16i8 (ARMvdup (i32 rGPR:$elem))),
(v16i8 MQPR:$inactive))), (v16i8 MQPR:$inactive))),
(MVE_VDUP8 rGPR:$elem, ARMVCCThen, (v16i1 VCCR:$pred), (MVE_VDUP8 rGPR:$elem, ARMVCCThen, (v16i1 VCCR:$pred),
(v16i8 MQPR:$inactive))>; (v16i8 MQPR:$inactive))>;
def : Pat<(v8i16 (vselect (v8i1 VCCR:$pred), def : Pat<(v8i16 (vselect (v8i1 VCCR:$pred),
(v8i16 (ARMvdup (i32 rGPR:$elem))), (v8i16 (ARMvdup (i32 rGPR:$elem))),
▲ Show 20 Lines • Show All 4,914 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll

Show First 20 Lines • Show All 235 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vfma.f32 q0, q3, q2 ; CHECK-NEXT: vfma.f32 q0, q3, q2
; CHECK-NEXT: le lr, .LBB1_2 ; CHECK-NEXT: le lr, .LBB1_2
; CHECK-NEXT: @ %bb.3: @ %middle.block ; CHECK-NEXT: @ %bb.3: @ %middle.block
; CHECK-NEXT: vctp.32 r3 ; CHECK-NEXT: vctp.32 r3
; CHECK-NEXT: vpsel q0, q0, q1 ; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: vmov.f32 s4, s2 ; CHECK-NEXT: vmov.f32 s4, s2
; CHECK-NEXT: vmov.f32 s5, s3 ; CHECK-NEXT: vmov.f32 s5, s3
; CHECK-NEXT: vadd.f32 q0, q0, q1 ; CHECK-NEXT: vadd.f32 q0, q0, q1
; CHECK-NEXT: vmov.32 r0, q0[1] ; CHECK-NEXT: vmov r0, s1
; CHECK-NEXT: vdup.32 q1, r0 ; CHECK-NEXT: vadd.f32 q0, q0, r0
; CHECK-NEXT: vadd.f32 q0, q0, q1
; CHECK-NEXT: @ kill: def $s0 killed $s0 killed $q0 ; CHECK-NEXT: @ kill: def $s0 killed $s0 killed $q0
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: pop {r7, pc}
; CHECK-NEXT: .LBB1_4: ; CHECK-NEXT: .LBB1_4:
; CHECK-NEXT: vldr s0, .LCPI1_0 ; CHECK-NEXT: vldr s0, .LCPI1_0
; CHECK-NEXT: @ kill: def $s0 killed $s0 killed $q0 ; CHECK-NEXT: @ kill: def $s0 killed $s0 killed $q0
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: pop {r7, pc}
; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: .p2align 2
; CHECK-NEXT: @ %bb.5: ; CHECK-NEXT: @ %bb.5:
▲ Show 20 Lines • Show All 251 Lines • ▼ Show 20 Lines
; CHECK-NEXT: b .LBB2_3 ; CHECK-NEXT: b .LBB2_3
; CHECK-NEXT: .LBB2_21: @ %middle.block ; CHECK-NEXT: .LBB2_21: @ %middle.block
; CHECK-NEXT: vdup.32 q0, r12 ; CHECK-NEXT: vdup.32 q0, r12
; CHECK-NEXT: vcmp.u32 cs, q0, q4 ; CHECK-NEXT: vcmp.u32 cs, q0, q4
; CHECK-NEXT: vpsel q0, q5, q3 ; CHECK-NEXT: vpsel q0, q5, q3
; CHECK-NEXT: vmov.f32 s4, s2 ; CHECK-NEXT: vmov.f32 s4, s2
; CHECK-NEXT: vmov.f32 s5, s3 ; CHECK-NEXT: vmov.f32 s5, s3
; CHECK-NEXT: vadd.f32 q0, q0, q1 ; CHECK-NEXT: vadd.f32 q0, q0, q1
; CHECK-NEXT: vmov.32 r0, q0[1] ; CHECK-NEXT: vmov r0, s1
; CHECK-NEXT: vdup.32 q1, r0 ; CHECK-NEXT: vadd.f32 q0, q0, r0
; CHECK-NEXT: vadd.f32 q0, q0, q1
; CHECK-NEXT: b .LBB2_23 ; CHECK-NEXT: b .LBB2_23
; CHECK-NEXT: .LBB2_22: ; CHECK-NEXT: .LBB2_22:
; CHECK-NEXT: vldr s0, .LCPI2_0 ; CHECK-NEXT: vldr s0, .LCPI2_0
; CHECK-NEXT: .LBB2_23: @ %for.cond.cleanup ; CHECK-NEXT: .LBB2_23: @ %for.cond.cleanup
; CHECK-NEXT: @ kill: def $s0 killed $s0 killed $q0 ; CHECK-NEXT: @ kill: def $s0 killed $s0 killed $q0
; CHECK-NEXT: add sp, #32 ; CHECK-NEXT: add sp, #32
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: pop {r4, r5, r7, pc} ; CHECK-NEXT: pop {r4, r5, r7, pc}
▲ Show 20 Lines • Show All 64 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-pred-shuffle.ll

Show First 20 Lines • Show All 142 Lines • ▼ Show 20 Lines
; CHECK-LABEL: shuffle3_v4i32: ; CHECK-LABEL: shuffle3_v4i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov d1, r2, r3 ; CHECK-NEXT: vmov d1, r2, r3
; CHECK-NEXT: vmov.i8 q1, #0xff ; CHECK-NEXT: vmov.i8 q1, #0xff
; CHECK-NEXT: vmov d0, r0, r1 ; CHECK-NEXT: vmov d0, r0, r1
; CHECK-NEXT: vcmp.i32 eq, q0, zr ; CHECK-NEXT: vcmp.i32 eq, q0, zr
; CHECK-NEXT: vmov.i8 q0, #0x0 ; CHECK-NEXT: vmov.i8 q0, #0x0
; CHECK-NEXT: vpsel q0, q1, q0 ; CHECK-NEXT: vpsel q0, q1, q0
; CHECK-NEXT: vmov.32 r0, q0[0] ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vdup.32 q0, r0 ; CHECK-NEXT: vdup.32 q0, r0
; CHECK-NEXT: add r0, sp, #16 ; CHECK-NEXT: add r0, sp, #16
; CHECK-NEXT: vcmp.i32 ne, q0, zr ; CHECK-NEXT: vcmp.i32 ne, q0, zr
; CHECK-NEXT: vldrw.u32 q0, [r0] ; CHECK-NEXT: vldrw.u32 q0, [r0]
; CHECK-NEXT: mov r0, sp ; CHECK-NEXT: mov r0, sp
; CHECK-NEXT: vldrw.u32 q1, [r0] ; CHECK-NEXT: vldrw.u32 q1, [r0]
; CHECK-NEXT: vpsel q0, q1, q0 ; CHECK-NEXT: vpsel q0, q1, q0
; CHECK-NEXT: vmov r0, r1, d0 ; CHECK-NEXT: vmov r0, r1, d0
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llvm/test/CodeGen/Thumb2/mve-vdup.ll

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ret <2 x double> %out ret <2 x double> %out
} }
define arm_aapcs_vfpcc <4 x i32> @vduplane_i32(<4 x i32> %src) { define arm_aapcs_vfpcc <4 x i32> @vduplane_i32(<4 x i32> %src) {
; CHECK-LABEL: vduplane_i32: ; CHECK-LABEL: vduplane_i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.32 r0, q0[3] ; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: vdup.32 q0, r0 ; CHECK-NEXT: vdup.32 q0, r0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%out = shufflevector <4 x i32> %src, <4 x i32> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3> %out = shufflevector <4 x i32> %src, <4 x i32> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
ret <4 x i32> %out ret <4 x i32> %out
} }
define arm_aapcs_vfpcc <8 x i16> @vduplane_i16(<8 x i16> %src) { define arm_aapcs_vfpcc <8 x i16> @vduplane_i16(<8 x i16> %src) {
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entry: entry:
%out = shufflevector <2 x i64> %src, <2 x i64> undef, <2 x i32> <i32 1, i32 1> %out = shufflevector <2 x i64> %src, <2 x i64> undef, <2 x i32> <i32 1, i32 1>
ret <2 x i64> %out ret <2 x i64> %out
} }
define arm_aapcs_vfpcc <4 x float> @vduplane_f32(<4 x float> %src) { define arm_aapcs_vfpcc <4 x float> @vduplane_f32(<4 x float> %src) {
; CHECK-LABEL: vduplane_f32: ; CHECK-LABEL: vduplane_f32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.32 r0, q0[3] ; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: vdup.32 q0, r0 ; CHECK-NEXT: vdup.32 q0, r0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%out = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3> %out = shufflevector <4 x float> %src, <4 x float> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
ret <4 x float> %out ret <4 x float> %out
} }
define arm_aapcs_vfpcc <8 x half> @vduplane_f16(<8 x half> %src) { define arm_aapcs_vfpcc <8 x half> @vduplane_f16(<8 x half> %src) {
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llvm/test/CodeGen/Thumb2/mve-vecreduce-fminmax.ll

Show First 20 Lines • Show All 210 Lines • ▼ Show 20 Linesentry:
ret double %z ret double %z
} }
; FIXME should not be vminnm ; FIXME should not be vminnm
; FIXME better reductions (no vmovs/vdups) ; FIXME better reductions (no vmovs/vdups)
define arm_aapcs_vfpcc float @fmin_v2f32_nofast(<2 x float> %x) { define arm_aapcs_vfpcc float @fmin_v2f32_nofast(<2 x float> %x) {
; CHECK-FP-LABEL: fmin_v2f32_nofast: ; CHECK-FP-LABEL: fmin_v2f32_nofast:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vmov.32 r0, q0[1] ; CHECK-FP-NEXT: vmov r0, s1
; CHECK-FP-NEXT: vdup.32 q1, r0 ; CHECK-FP-NEXT: vdup.32 q1, r0
; CHECK-FP-NEXT: vminnm.f32 q0, q0, q1 ; CHECK-FP-NEXT: vminnm.f32 q0, q0, q1
; CHECK-FP-NEXT: @ kill: def $s0 killed $s0 killed $q0 ; CHECK-FP-NEXT: @ kill: def $s0 killed $s0 killed $q0
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fmin_v2f32_nofast: ; CHECK-NOFP-LABEL: fmin_v2f32_nofast:
; CHECK-NOFP: @ %bb.0: @ %entry ; CHECK-NOFP: @ %bb.0: @ %entry
; CHECK-NOFP-NEXT: vmov.32 r0, q0[1] ; CHECK-NOFP-NEXT: vcmp.f32 s1, s0
; CHECK-NOFP-NEXT: vdup.32 q1, r0
; CHECK-NOFP-NEXT: vcmp.f32 s4, s0
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vselgt.f32 s0, s0, s4 ; CHECK-NOFP-NEXT: vselgt.f32 s0, s0, s1
; CHECK-NOFP-NEXT: bx lr ; CHECK-NOFP-NEXT: bx lr
entry: entry:
%z = call float @llvm.experimental.vector.reduce.fmin.v2f32(<2 x float> %x) %z = call float @llvm.experimental.vector.reduce.fmin.v2f32(<2 x float> %x)
ret float %z ret float %z
} }
define arm_aapcs_vfpcc float @fmin_v4f32_nofast(<4 x float> %x) { define arm_aapcs_vfpcc float @fmin_v4f32_nofast(<4 x float> %x) {
; CHECK-FP-LABEL: fmin_v4f32_nofast: ; CHECK-FP-LABEL: fmin_v4f32_nofast:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vmov.f64 d2, d1 ; CHECK-FP-NEXT: vmov.f64 d2, d1
; CHECK-FP-NEXT: vmov.f32 s5, s3 ; CHECK-FP-NEXT: vmov.f32 s5, s3
; CHECK-FP-NEXT: vminnm.f32 q0, q0, q1 ; CHECK-FP-NEXT: vminnm.f32 q0, q0, q1
; CHECK-FP-NEXT: vmov.32 r0, q0[1] ; CHECK-FP-NEXT: vmov r0, s1
; CHECK-FP-NEXT: vdup.32 q1, r0 ; CHECK-FP-NEXT: vdup.32 q1, r0
; CHECK-FP-NEXT: vminnm.f32 q0, q0, q1 ; CHECK-FP-NEXT: vminnm.f32 q0, q0, q1
; CHECK-FP-NEXT: @ kill: def $s0 killed $s0 killed $q0 ; CHECK-FP-NEXT: @ kill: def $s0 killed $s0 killed $q0
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fmin_v4f32_nofast: ; CHECK-NOFP-LABEL: fmin_v4f32_nofast:
; CHECK-NOFP: @ %bb.0: @ %entry ; CHECK-NOFP: @ %bb.0: @ %entry
; CHECK-NOFP-NEXT: vcmp.f32 s3, s1 ; CHECK-NOFP-NEXT: vcmp.f32 s3, s1
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define arm_aapcs_vfpcc float @fmin_v8f32_nofast(<8 x float> %x) { define arm_aapcs_vfpcc float @fmin_v8f32_nofast(<8 x float> %x) {
; CHECK-FP-LABEL: fmin_v8f32_nofast: ; CHECK-FP-LABEL: fmin_v8f32_nofast:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vminnm.f32 q0, q0, q1 ; CHECK-FP-NEXT: vminnm.f32 q0, q0, q1
; CHECK-FP-NEXT: vmov.f64 d2, d1 ; CHECK-FP-NEXT: vmov.f64 d2, d1
; CHECK-FP-NEXT: vmov.f32 s5, s3 ; CHECK-FP-NEXT: vmov.f32 s5, s3
; CHECK-FP-NEXT: vminnm.f32 q0, q0, q1 ; CHECK-FP-NEXT: vminnm.f32 q0, q0, q1
; CHECK-FP-NEXT: vmov.32 r0, q0[1] ; CHECK-FP-NEXT: vmov r0, s1
; CHECK-FP-NEXT: vdup.32 q1, r0 ; CHECK-FP-NEXT: vdup.32 q1, r0
; CHECK-FP-NEXT: vminnm.f32 q0, q0, q1 ; CHECK-FP-NEXT: vminnm.f32 q0, q0, q1
; CHECK-FP-NEXT: @ kill: def $s0 killed $s0 killed $q0 ; CHECK-FP-NEXT: @ kill: def $s0 killed $s0 killed $q0
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fmin_v8f32_nofast: ; CHECK-NOFP-LABEL: fmin_v8f32_nofast:
; CHECK-NOFP: @ %bb.0: @ %entry ; CHECK-NOFP: @ %bb.0: @ %entry
; CHECK-NOFP-NEXT: vcmp.f32 s7, s3 ; CHECK-NOFP-NEXT: vcmp.f32 s7, s3
Show All 21 Lines
entry: entry:
%z = call float @llvm.experimental.vector.reduce.fmin.v8f32(<8 x float> %x) %z = call float @llvm.experimental.vector.reduce.fmin.v8f32(<8 x float> %x)
ret float %z ret float %z
} }
define arm_aapcs_vfpcc half @fmin_v4f16_nofast(<4 x half> %x) { define arm_aapcs_vfpcc half @fmin_v4f16_nofast(<4 x half> %x) {
; CHECK-FP-LABEL: fmin_v4f16_nofast: ; CHECK-FP-LABEL: fmin_v4f16_nofast:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vmov.32 r1, q0[1] ; CHECK-FP-NEXT: vmov r1, s1
; CHECK-FP-NEXT: vdup.32 q1, r1 ; CHECK-FP-NEXT: vdup.32 q1, r1
; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1 ; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1
; CHECK-FP-NEXT: vmov.u16 r1, q0[1] ; CHECK-FP-NEXT: vmov.u16 r1, q0[1]
; CHECK-FP-NEXT: vdup.16 q1, r1 ; CHECK-FP-NEXT: vdup.16 q1, r1
; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1 ; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1
; CHECK-FP-NEXT: vstr.16 s0, [r0] ; CHECK-FP-NEXT: vstr.16 s0, [r0]
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fmin_v4f16_nofast: ; CHECK-NOFP-LABEL: fmin_v4f16_nofast:
; CHECK-NOFP: @ %bb.0: @ %entry ; CHECK-NOFP: @ %bb.0: @ %entry
; CHECK-NOFP-NEXT: vmov.32 r1, q0[1] ; CHECK-NOFP-NEXT: vmov r1, s1
; CHECK-NOFP-NEXT: vmovx.f16 s10, s0 ; CHECK-NOFP-NEXT: vmovx.f16 s10, s0
; CHECK-NOFP-NEXT: vdup.32 q1, r1 ; CHECK-NOFP-NEXT: vdup.32 q1, r1
; CHECK-NOFP-NEXT: vmovx.f16 s8, s4 ; CHECK-NOFP-NEXT: vmovx.f16 s8, s4
; CHECK-NOFP-NEXT: vcmp.f16 s8, s10 ; CHECK-NOFP-NEXT: vcmp.f16 s8, s10
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vcmp.f16 s4, s0 ; CHECK-NOFP-NEXT: vcmp.f16 s4, s0
; CHECK-NOFP-NEXT: vselgt.f16 s8, s10, s8 ; CHECK-NOFP-NEXT: vselgt.f16 s8, s10, s8
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
Show All 9 Lines
} }
define arm_aapcs_vfpcc half @fmin_v8f16_nofast(<8 x half> %x) { define arm_aapcs_vfpcc half @fmin_v8f16_nofast(<8 x half> %x) {
; CHECK-FP-LABEL: fmin_v8f16_nofast: ; CHECK-FP-LABEL: fmin_v8f16_nofast:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vmov.f64 d2, d1 ; CHECK-FP-NEXT: vmov.f64 d2, d1
; CHECK-FP-NEXT: vmov.f32 s5, s3 ; CHECK-FP-NEXT: vmov.f32 s5, s3
; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1 ; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1
; CHECK-FP-NEXT: vmov.32 r1, q0[1] ; CHECK-FP-NEXT: vmov r1, s1
; CHECK-FP-NEXT: vdup.32 q1, r1 ; CHECK-FP-NEXT: vdup.32 q1, r1
; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1 ; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1
; CHECK-FP-NEXT: vmov.u16 r1, q0[1] ; CHECK-FP-NEXT: vmov.u16 r1, q0[1]
; CHECK-FP-NEXT: vdup.16 q1, r1 ; CHECK-FP-NEXT: vdup.16 q1, r1
; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1 ; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1
; CHECK-FP-NEXT: vstr.16 s0, [r0] ; CHECK-FP-NEXT: vstr.16 s0, [r0]
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
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define arm_aapcs_vfpcc half @fmin_v16f16_nofast(<16 x half> %x) { define arm_aapcs_vfpcc half @fmin_v16f16_nofast(<16 x half> %x) {
; CHECK-FP-LABEL: fmin_v16f16_nofast: ; CHECK-FP-LABEL: fmin_v16f16_nofast:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1 ; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1
; CHECK-FP-NEXT: vmov.f64 d2, d1 ; CHECK-FP-NEXT: vmov.f64 d2, d1
; CHECK-FP-NEXT: vmov.f32 s5, s3 ; CHECK-FP-NEXT: vmov.f32 s5, s3
; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1 ; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1
; CHECK-FP-NEXT: vmov.32 r1, q0[1] ; CHECK-FP-NEXT: vmov r1, s1
; CHECK-FP-NEXT: vdup.32 q1, r1 ; CHECK-FP-NEXT: vdup.32 q1, r1
; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1 ; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1
; CHECK-FP-NEXT: vmov.u16 r1, q0[1] ; CHECK-FP-NEXT: vmov.u16 r1, q0[1]
; CHECK-FP-NEXT: vdup.16 q1, r1 ; CHECK-FP-NEXT: vdup.16 q1, r1
; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1 ; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1
; CHECK-FP-NEXT: vstr.16 s0, [r0] ; CHECK-FP-NEXT: vstr.16 s0, [r0]
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
▲ Show 20 Lines • Show All 342 Lines • ▼ Show 20 Linesentry:
%c = fcmp fast olt double %y, %z %c = fcmp fast olt double %y, %z
%r = select i1 %c, double %y, double %z %r = select i1 %c, double %y, double %z
ret double %r ret double %r
} }
define arm_aapcs_vfpcc float @fmin_v2f32_acc_nofast(<2 x float> %x, float %y) { define arm_aapcs_vfpcc float @fmin_v2f32_acc_nofast(<2 x float> %x, float %y) {
; CHECK-FP-LABEL: fmin_v2f32_acc_nofast: ; CHECK-FP-LABEL: fmin_v2f32_acc_nofast:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vmov.32 r0, q0[1] ; CHECK-FP-NEXT: vmov r0, s1
; CHECK-FP-NEXT: vdup.32 q2, r0 ; CHECK-FP-NEXT: vdup.32 q2, r0
; CHECK-FP-NEXT: vminnm.f32 q0, q0, q2 ; CHECK-FP-NEXT: vminnm.f32 q0, q0, q2
; CHECK-FP-NEXT: vcmp.f32 s0, s4 ; CHECK-FP-NEXT: vcmp.f32 s0, s4
; CHECK-FP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-FP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-FP-NEXT: vselgt.f32 s0, s4, s0 ; CHECK-FP-NEXT: vselgt.f32 s0, s4, s0
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fmin_v2f32_acc_nofast: ; CHECK-NOFP-LABEL: fmin_v2f32_acc_nofast:
; CHECK-NOFP: @ %bb.0: @ %entry ; CHECK-NOFP: @ %bb.0: @ %entry
; CHECK-NOFP-NEXT: vmov.32 r0, q0[1] ; CHECK-NOFP-NEXT: vcmp.f32 s1, s0
; CHECK-NOFP-NEXT: vdup.32 q2, r0
; CHECK-NOFP-NEXT: vcmp.f32 s8, s0
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vselgt.f32 s0, s0, s8 ; CHECK-NOFP-NEXT: vselgt.f32 s0, s0, s1
; CHECK-NOFP-NEXT: vcmp.f32 s0, s4 ; CHECK-NOFP-NEXT: vcmp.f32 s0, s4
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vselgt.f32 s0, s4, s0 ; CHECK-NOFP-NEXT: vselgt.f32 s0, s4, s0
; CHECK-NOFP-NEXT: bx lr ; CHECK-NOFP-NEXT: bx lr
entry: entry:
%z = call float @llvm.experimental.vector.reduce.fmin.v2f32(<2 x float> %x) %z = call float @llvm.experimental.vector.reduce.fmin.v2f32(<2 x float> %x)
%c = fcmp olt float %y, %z %c = fcmp olt float %y, %z
%r = select i1 %c, float %y, float %z %r = select i1 %c, float %y, float %z
ret float %r ret float %r
} }
define arm_aapcs_vfpcc float @fmin_v4f32_acc_nofast(<4 x float> %x, float %y) { define arm_aapcs_vfpcc float @fmin_v4f32_acc_nofast(<4 x float> %x, float %y) {
; CHECK-FP-LABEL: fmin_v4f32_acc_nofast: ; CHECK-FP-LABEL: fmin_v4f32_acc_nofast:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vmov.f64 d4, d1 ; CHECK-FP-NEXT: vmov.f64 d4, d1
; CHECK-FP-NEXT: vmov.f32 s9, s3 ; CHECK-FP-NEXT: vmov.f32 s9, s3
; CHECK-FP-NEXT: vminnm.f32 q0, q0, q2 ; CHECK-FP-NEXT: vminnm.f32 q0, q0, q2
; CHECK-FP-NEXT: vmov.32 r0, q0[1] ; CHECK-FP-NEXT: vmov r0, s1
; CHECK-FP-NEXT: vdup.32 q2, r0 ; CHECK-FP-NEXT: vdup.32 q2, r0
; CHECK-FP-NEXT: vminnm.f32 q0, q0, q2 ; CHECK-FP-NEXT: vminnm.f32 q0, q0, q2
; CHECK-FP-NEXT: vcmp.f32 s0, s4 ; CHECK-FP-NEXT: vcmp.f32 s0, s4
; CHECK-FP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-FP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-FP-NEXT: vselgt.f32 s0, s4, s0 ; CHECK-FP-NEXT: vselgt.f32 s0, s4, s0
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fmin_v4f32_acc_nofast: ; CHECK-NOFP-LABEL: fmin_v4f32_acc_nofast:
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define arm_aapcs_vfpcc float @fmin_v8f32_acc_nofast(<8 x float> %x, float %y) { define arm_aapcs_vfpcc float @fmin_v8f32_acc_nofast(<8 x float> %x, float %y) {
; CHECK-FP-LABEL: fmin_v8f32_acc_nofast: ; CHECK-FP-LABEL: fmin_v8f32_acc_nofast:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vminnm.f32 q0, q0, q1 ; CHECK-FP-NEXT: vminnm.f32 q0, q0, q1
; CHECK-FP-NEXT: vmov.f64 d2, d1 ; CHECK-FP-NEXT: vmov.f64 d2, d1
; CHECK-FP-NEXT: vmov.f32 s5, s3 ; CHECK-FP-NEXT: vmov.f32 s5, s3
; CHECK-FP-NEXT: vminnm.f32 q0, q0, q1 ; CHECK-FP-NEXT: vminnm.f32 q0, q0, q1
; CHECK-FP-NEXT: vmov.32 r0, q0[1] ; CHECK-FP-NEXT: vmov r0, s1
; CHECK-FP-NEXT: vdup.32 q1, r0 ; CHECK-FP-NEXT: vdup.32 q1, r0
; CHECK-FP-NEXT: vminnm.f32 q0, q0, q1 ; CHECK-FP-NEXT: vminnm.f32 q0, q0, q1
; CHECK-FP-NEXT: vcmp.f32 s0, s8 ; CHECK-FP-NEXT: vcmp.f32 s0, s8
; CHECK-FP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-FP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-FP-NEXT: vselgt.f32 s0, s8, s0 ; CHECK-FP-NEXT: vselgt.f32 s0, s8, s0
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fmin_v8f32_acc_nofast: ; CHECK-NOFP-LABEL: fmin_v8f32_acc_nofast:
Show All 28 Linesentry:
%c = fcmp olt float %y, %z %c = fcmp olt float %y, %z
%r = select i1 %c, float %y, float %z %r = select i1 %c, float %y, float %z
ret float %r ret float %r
} }
define arm_aapcs_vfpcc void @fmin_v4f16_acc_nofast(<4 x half> %x, half* %yy) { define arm_aapcs_vfpcc void @fmin_v4f16_acc_nofast(<4 x half> %x, half* %yy) {
; CHECK-FP-LABEL: fmin_v4f16_acc_nofast: ; CHECK-FP-LABEL: fmin_v4f16_acc_nofast:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vmov.32 r1, q0[1] ; CHECK-FP-NEXT: vmov r1, s1
; CHECK-FP-NEXT: vdup.32 q1, r1 ; CHECK-FP-NEXT: vdup.32 q1, r1
; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1 ; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1
; CHECK-FP-NEXT: vmov.u16 r1, q0[1] ; CHECK-FP-NEXT: vmov.u16 r1, q0[1]
; CHECK-FP-NEXT: vdup.16 q1, r1 ; CHECK-FP-NEXT: vdup.16 q1, r1
; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1 ; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1
; CHECK-FP-NEXT: vldr.16 s4, [r0] ; CHECK-FP-NEXT: vldr.16 s4, [r0]
; CHECK-FP-NEXT: vcmp.f16 s0, s4 ; CHECK-FP-NEXT: vcmp.f16 s0, s4
; CHECK-FP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-FP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-FP-NEXT: vselgt.f16 s0, s4, s0 ; CHECK-FP-NEXT: vselgt.f16 s0, s4, s0
; CHECK-FP-NEXT: vstr.16 s0, [r0] ; CHECK-FP-NEXT: vstr.16 s0, [r0]
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fmin_v4f16_acc_nofast: ; CHECK-NOFP-LABEL: fmin_v4f16_acc_nofast:
; CHECK-NOFP: @ %bb.0: @ %entry ; CHECK-NOFP: @ %bb.0: @ %entry
; CHECK-NOFP-NEXT: vmov.32 r1, q0[1] ; CHECK-NOFP-NEXT: vmov r1, s1
; CHECK-NOFP-NEXT: vmovx.f16 s10, s0 ; CHECK-NOFP-NEXT: vmovx.f16 s10, s0
; CHECK-NOFP-NEXT: vdup.32 q1, r1 ; CHECK-NOFP-NEXT: vdup.32 q1, r1
; CHECK-NOFP-NEXT: vmovx.f16 s8, s4 ; CHECK-NOFP-NEXT: vmovx.f16 s8, s4
; CHECK-NOFP-NEXT: vcmp.f16 s8, s10 ; CHECK-NOFP-NEXT: vcmp.f16 s8, s10
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vcmp.f16 s4, s0 ; CHECK-NOFP-NEXT: vcmp.f16 s4, s0
; CHECK-NOFP-NEXT: vselgt.f16 s8, s10, s8 ; CHECK-NOFP-NEXT: vselgt.f16 s8, s10, s8
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
Show All 17 Lines
} }
define arm_aapcs_vfpcc void @fmin_v8f16_acc_nofast(<8 x half> %x, half* %yy) { define arm_aapcs_vfpcc void @fmin_v8f16_acc_nofast(<8 x half> %x, half* %yy) {
; CHECK-FP-LABEL: fmin_v8f16_acc_nofast: ; CHECK-FP-LABEL: fmin_v8f16_acc_nofast:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vmov.f64 d2, d1 ; CHECK-FP-NEXT: vmov.f64 d2, d1
; CHECK-FP-NEXT: vmov.f32 s5, s3 ; CHECK-FP-NEXT: vmov.f32 s5, s3
; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1 ; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1
; CHECK-FP-NEXT: vmov.32 r1, q0[1] ; CHECK-FP-NEXT: vmov r1, s1
; CHECK-FP-NEXT: vdup.32 q1, r1 ; CHECK-FP-NEXT: vdup.32 q1, r1
; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1 ; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1
; CHECK-FP-NEXT: vmov.u16 r1, q0[1] ; CHECK-FP-NEXT: vmov.u16 r1, q0[1]
; CHECK-FP-NEXT: vdup.16 q1, r1 ; CHECK-FP-NEXT: vdup.16 q1, r1
; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1 ; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1
; CHECK-FP-NEXT: vldr.16 s4, [r0] ; CHECK-FP-NEXT: vldr.16 s4, [r0]
; CHECK-FP-NEXT: vcmp.f16 s0, s4 ; CHECK-FP-NEXT: vcmp.f16 s0, s4
; CHECK-FP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-FP-NEXT: vmrs APSR_nzcv, fpscr
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define arm_aapcs_vfpcc void @fmin_v16f16_acc_nofast(<16 x half> %x, half* %yy) { define arm_aapcs_vfpcc void @fmin_v16f16_acc_nofast(<16 x half> %x, half* %yy) {
; CHECK-FP-LABEL: fmin_v16f16_acc_nofast: ; CHECK-FP-LABEL: fmin_v16f16_acc_nofast:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1 ; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1
; CHECK-FP-NEXT: vmov.f64 d2, d1 ; CHECK-FP-NEXT: vmov.f64 d2, d1
; CHECK-FP-NEXT: vmov.f32 s5, s3 ; CHECK-FP-NEXT: vmov.f32 s5, s3
; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1 ; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1
; CHECK-FP-NEXT: vmov.32 r1, q0[1] ; CHECK-FP-NEXT: vmov r1, s1
; CHECK-FP-NEXT: vdup.32 q1, r1 ; CHECK-FP-NEXT: vdup.32 q1, r1
; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1 ; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1
; CHECK-FP-NEXT: vmov.u16 r1, q0[1] ; CHECK-FP-NEXT: vmov.u16 r1, q0[1]
; CHECK-FP-NEXT: vdup.16 q1, r1 ; CHECK-FP-NEXT: vdup.16 q1, r1
; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1 ; CHECK-FP-NEXT: vminnm.f16 q0, q0, q1
; CHECK-FP-NEXT: vldr.16 s4, [r0] ; CHECK-FP-NEXT: vldr.16 s4, [r0]
; CHECK-FP-NEXT: vcmp.f16 s0, s4 ; CHECK-FP-NEXT: vcmp.f16 s0, s4
; CHECK-FP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-FP-NEXT: vmrs APSR_nzcv, fpscr
▲ Show 20 Lines • Show All 330 Lines • ▼ Show 20 Lines
entry: entry:
%z = call fast double @llvm.experimental.vector.reduce.fmax.v4f64(<4 x double> %x) %z = call fast double @llvm.experimental.vector.reduce.fmax.v4f64(<4 x double> %x)
ret double %z ret double %z
} }
define arm_aapcs_vfpcc float @fmax_v2f32_nofast(<2 x float> %x) { define arm_aapcs_vfpcc float @fmax_v2f32_nofast(<2 x float> %x) {
; CHECK-FP-LABEL: fmax_v2f32_nofast: ; CHECK-FP-LABEL: fmax_v2f32_nofast:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vmov.32 r0, q0[1] ; CHECK-FP-NEXT: vmov r0, s1
; CHECK-FP-NEXT: vdup.32 q1, r0 ; CHECK-FP-NEXT: vdup.32 q1, r0
; CHECK-FP-NEXT: vmaxnm.f32 q0, q0, q1 ; CHECK-FP-NEXT: vmaxnm.f32 q0, q0, q1
; CHECK-FP-NEXT: @ kill: def $s0 killed $s0 killed $q0 ; CHECK-FP-NEXT: @ kill: def $s0 killed $s0 killed $q0
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fmax_v2f32_nofast: ; CHECK-NOFP-LABEL: fmax_v2f32_nofast:
; CHECK-NOFP: @ %bb.0: @ %entry ; CHECK-NOFP: @ %bb.0: @ %entry
; CHECK-NOFP-NEXT: vmov.32 r0, q0[1] ; CHECK-NOFP-NEXT: vcmp.f32 s0, s1
; CHECK-NOFP-NEXT: vdup.32 q1, r0
; CHECK-NOFP-NEXT: vcmp.f32 s0, s4
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vselgt.f32 s0, s0, s4 ; CHECK-NOFP-NEXT: vselgt.f32 s0, s0, s1
; CHECK-NOFP-NEXT: bx lr ; CHECK-NOFP-NEXT: bx lr
entry: entry:
%z = call float @llvm.experimental.vector.reduce.fmax.v2f32(<2 x float> %x) %z = call float @llvm.experimental.vector.reduce.fmax.v2f32(<2 x float> %x)
ret float %z ret float %z
} }
define arm_aapcs_vfpcc float @fmax_v4f32_nofast(<4 x float> %x) { define arm_aapcs_vfpcc float @fmax_v4f32_nofast(<4 x float> %x) {
; CHECK-FP-LABEL: fmax_v4f32_nofast: ; CHECK-FP-LABEL: fmax_v4f32_nofast:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vmov.f64 d2, d1 ; CHECK-FP-NEXT: vmov.f64 d2, d1
; CHECK-FP-NEXT: vmov.f32 s5, s3 ; CHECK-FP-NEXT: vmov.f32 s5, s3
; CHECK-FP-NEXT: vmaxnm.f32 q0, q0, q1 ; CHECK-FP-NEXT: vmaxnm.f32 q0, q0, q1
; CHECK-FP-NEXT: vmov.32 r0, q0[1] ; CHECK-FP-NEXT: vmov r0, s1
; CHECK-FP-NEXT: vdup.32 q1, r0 ; CHECK-FP-NEXT: vdup.32 q1, r0
; CHECK-FP-NEXT: vmaxnm.f32 q0, q0, q1 ; CHECK-FP-NEXT: vmaxnm.f32 q0, q0, q1
; CHECK-FP-NEXT: @ kill: def $s0 killed $s0 killed $q0 ; CHECK-FP-NEXT: @ kill: def $s0 killed $s0 killed $q0
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fmax_v4f32_nofast: ; CHECK-NOFP-LABEL: fmax_v4f32_nofast:
; CHECK-NOFP: @ %bb.0: @ %entry ; CHECK-NOFP: @ %bb.0: @ %entry
; CHECK-NOFP-NEXT: vcmp.f32 s1, s3 ; CHECK-NOFP-NEXT: vcmp.f32 s1, s3
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define arm_aapcs_vfpcc float @fmax_v8f32_nofast(<8 x float> %x) { define arm_aapcs_vfpcc float @fmax_v8f32_nofast(<8 x float> %x) {
; CHECK-FP-LABEL: fmax_v8f32_nofast: ; CHECK-FP-LABEL: fmax_v8f32_nofast:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vmaxnm.f32 q0, q0, q1 ; CHECK-FP-NEXT: vmaxnm.f32 q0, q0, q1
; CHECK-FP-NEXT: vmov.f64 d2, d1 ; CHECK-FP-NEXT: vmov.f64 d2, d1
; CHECK-FP-NEXT: vmov.f32 s5, s3 ; CHECK-FP-NEXT: vmov.f32 s5, s3
; CHECK-FP-NEXT: vmaxnm.f32 q0, q0, q1 ; CHECK-FP-NEXT: vmaxnm.f32 q0, q0, q1
; CHECK-FP-NEXT: vmov.32 r0, q0[1] ; CHECK-FP-NEXT: vmov r0, s1
; CHECK-FP-NEXT: vdup.32 q1, r0 ; CHECK-FP-NEXT: vdup.32 q1, r0
; CHECK-FP-NEXT: vmaxnm.f32 q0, q0, q1 ; CHECK-FP-NEXT: vmaxnm.f32 q0, q0, q1
; CHECK-FP-NEXT: @ kill: def $s0 killed $s0 killed $q0 ; CHECK-FP-NEXT: @ kill: def $s0 killed $s0 killed $q0
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fmax_v8f32_nofast: ; CHECK-NOFP-LABEL: fmax_v8f32_nofast:
; CHECK-NOFP: @ %bb.0: @ %entry ; CHECK-NOFP: @ %bb.0: @ %entry
; CHECK-NOFP-NEXT: vcmp.f32 s3, s7 ; CHECK-NOFP-NEXT: vcmp.f32 s3, s7
Show All 21 Lines
entry: entry:
%z = call float @llvm.experimental.vector.reduce.fmax.v8f32(<8 x float> %x) %z = call float @llvm.experimental.vector.reduce.fmax.v8f32(<8 x float> %x)
ret float %z ret float %z
} }
define arm_aapcs_vfpcc half @fmax_v4f16_nofast(<4 x half> %x) { define arm_aapcs_vfpcc half @fmax_v4f16_nofast(<4 x half> %x) {
; CHECK-FP-LABEL: fmax_v4f16_nofast: ; CHECK-FP-LABEL: fmax_v4f16_nofast:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vmov.32 r1, q0[1] ; CHECK-FP-NEXT: vmov r1, s1
; CHECK-FP-NEXT: vdup.32 q1, r1 ; CHECK-FP-NEXT: vdup.32 q1, r1
; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q1 ; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q1
; CHECK-FP-NEXT: vmov.u16 r1, q0[1] ; CHECK-FP-NEXT: vmov.u16 r1, q0[1]
; CHECK-FP-NEXT: vdup.16 q1, r1 ; CHECK-FP-NEXT: vdup.16 q1, r1
; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q1 ; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q1
; CHECK-FP-NEXT: vstr.16 s0, [r0] ; CHECK-FP-NEXT: vstr.16 s0, [r0]
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fmax_v4f16_nofast: ; CHECK-NOFP-LABEL: fmax_v4f16_nofast:
; CHECK-NOFP: @ %bb.0: @ %entry ; CHECK-NOFP: @ %bb.0: @ %entry
; CHECK-NOFP-NEXT: vmov.32 r1, q0[1] ; CHECK-NOFP-NEXT: vmov r1, s1
; CHECK-NOFP-NEXT: vmovx.f16 s10, s0 ; CHECK-NOFP-NEXT: vmovx.f16 s10, s0
; CHECK-NOFP-NEXT: vdup.32 q1, r1 ; CHECK-NOFP-NEXT: vdup.32 q1, r1
; CHECK-NOFP-NEXT: vmovx.f16 s8, s4 ; CHECK-NOFP-NEXT: vmovx.f16 s8, s4
; CHECK-NOFP-NEXT: vcmp.f16 s10, s8 ; CHECK-NOFP-NEXT: vcmp.f16 s10, s8
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vcmp.f16 s0, s4 ; CHECK-NOFP-NEXT: vcmp.f16 s0, s4
; CHECK-NOFP-NEXT: vselgt.f16 s8, s10, s8 ; CHECK-NOFP-NEXT: vselgt.f16 s8, s10, s8
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
Show All 9 Lines
} }
define arm_aapcs_vfpcc half @fmax_v8f16_nofast(<8 x half> %x) { define arm_aapcs_vfpcc half @fmax_v8f16_nofast(<8 x half> %x) {
; CHECK-FP-LABEL: fmax_v8f16_nofast: ; CHECK-FP-LABEL: fmax_v8f16_nofast:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vmov.f64 d2, d1 ; CHECK-FP-NEXT: vmov.f64 d2, d1
; CHECK-FP-NEXT: vmov.f32 s5, s3 ; CHECK-FP-NEXT: vmov.f32 s5, s3
; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q1 ; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q1
; CHECK-FP-NEXT: vmov.32 r1, q0[1] ; CHECK-FP-NEXT: vmov r1, s1
; CHECK-FP-NEXT: vdup.32 q1, r1 ; CHECK-FP-NEXT: vdup.32 q1, r1
; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q1 ; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q1
; CHECK-FP-NEXT: vmov.u16 r1, q0[1] ; CHECK-FP-NEXT: vmov.u16 r1, q0[1]
; CHECK-FP-NEXT: vdup.16 q1, r1 ; CHECK-FP-NEXT: vdup.16 q1, r1
; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q1 ; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q1
; CHECK-FP-NEXT: vstr.16 s0, [r0] ; CHECK-FP-NEXT: vstr.16 s0, [r0]
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
Show All 35 Lines
define arm_aapcs_vfpcc half @fmax_v16f16_nofast(<16 x half> %x) { define arm_aapcs_vfpcc half @fmax_v16f16_nofast(<16 x half> %x) {
; CHECK-FP-LABEL: fmax_v16f16_nofast: ; CHECK-FP-LABEL: fmax_v16f16_nofast:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q1 ; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q1
; CHECK-FP-NEXT: vmov.f64 d2, d1 ; CHECK-FP-NEXT: vmov.f64 d2, d1
; CHECK-FP-NEXT: vmov.f32 s5, s3 ; CHECK-FP-NEXT: vmov.f32 s5, s3
; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q1 ; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q1
; CHECK-FP-NEXT: vmov.32 r1, q0[1] ; CHECK-FP-NEXT: vmov r1, s1
; CHECK-FP-NEXT: vdup.32 q1, r1 ; CHECK-FP-NEXT: vdup.32 q1, r1
; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q1 ; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q1
; CHECK-FP-NEXT: vmov.u16 r1, q0[1] ; CHECK-FP-NEXT: vmov.u16 r1, q0[1]
; CHECK-FP-NEXT: vdup.16 q1, r1 ; CHECK-FP-NEXT: vdup.16 q1, r1
; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q1 ; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q1
; CHECK-FP-NEXT: vstr.16 s0, [r0] ; CHECK-FP-NEXT: vstr.16 s0, [r0]
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
▲ Show 20 Lines • Show All 342 Lines • ▼ Show 20 Linesentry:
%c = fcmp fast ogt double %y, %z %c = fcmp fast ogt double %y, %z
%r = select i1 %c, double %y, double %z %r = select i1 %c, double %y, double %z
ret double %r ret double %r
} }
define arm_aapcs_vfpcc float @fmax_v2f32_acc_nofast(<2 x float> %x, float %y) { define arm_aapcs_vfpcc float @fmax_v2f32_acc_nofast(<2 x float> %x, float %y) {
; CHECK-FP-LABEL: fmax_v2f32_acc_nofast: ; CHECK-FP-LABEL: fmax_v2f32_acc_nofast:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vmov.32 r0, q0[1] ; CHECK-FP-NEXT: vmov r0, s1
; CHECK-FP-NEXT: vdup.32 q2, r0 ; CHECK-FP-NEXT: vdup.32 q2, r0
; CHECK-FP-NEXT: vmaxnm.f32 q0, q0, q2 ; CHECK-FP-NEXT: vmaxnm.f32 q0, q0, q2
; CHECK-FP-NEXT: vcmp.f32 s4, s0 ; CHECK-FP-NEXT: vcmp.f32 s4, s0
; CHECK-FP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-FP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-FP-NEXT: vselgt.f32 s0, s4, s0 ; CHECK-FP-NEXT: vselgt.f32 s0, s4, s0
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fmax_v2f32_acc_nofast: ; CHECK-NOFP-LABEL: fmax_v2f32_acc_nofast:
; CHECK-NOFP: @ %bb.0: @ %entry ; CHECK-NOFP: @ %bb.0: @ %entry
; CHECK-NOFP-NEXT: vmov.32 r0, q0[1] ; CHECK-NOFP-NEXT: vcmp.f32 s0, s1
; CHECK-NOFP-NEXT: vdup.32 q2, r0
; CHECK-NOFP-NEXT: vcmp.f32 s0, s8
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vselgt.f32 s0, s0, s8 ; CHECK-NOFP-NEXT: vselgt.f32 s0, s0, s1
; CHECK-NOFP-NEXT: vcmp.f32 s4, s0 ; CHECK-NOFP-NEXT: vcmp.f32 s4, s0
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vselgt.f32 s0, s4, s0 ; CHECK-NOFP-NEXT: vselgt.f32 s0, s4, s0
; CHECK-NOFP-NEXT: bx lr ; CHECK-NOFP-NEXT: bx lr
entry: entry:
%z = call float @llvm.experimental.vector.reduce.fmax.v2f32(<2 x float> %x) %z = call float @llvm.experimental.vector.reduce.fmax.v2f32(<2 x float> %x)
%c = fcmp ogt float %y, %z %c = fcmp ogt float %y, %z
%r = select i1 %c, float %y, float %z %r = select i1 %c, float %y, float %z
ret float %r ret float %r
} }
define arm_aapcs_vfpcc float @fmax_v4f32_acc_nofast(<4 x float> %x, float %y) { define arm_aapcs_vfpcc float @fmax_v4f32_acc_nofast(<4 x float> %x, float %y) {
; CHECK-FP-LABEL: fmax_v4f32_acc_nofast: ; CHECK-FP-LABEL: fmax_v4f32_acc_nofast:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vmov.f64 d4, d1 ; CHECK-FP-NEXT: vmov.f64 d4, d1
; CHECK-FP-NEXT: vmov.f32 s9, s3 ; CHECK-FP-NEXT: vmov.f32 s9, s3
; CHECK-FP-NEXT: vmaxnm.f32 q0, q0, q2 ; CHECK-FP-NEXT: vmaxnm.f32 q0, q0, q2
; CHECK-FP-NEXT: vmov.32 r0, q0[1] ; CHECK-FP-NEXT: vmov r0, s1
; CHECK-FP-NEXT: vdup.32 q2, r0 ; CHECK-FP-NEXT: vdup.32 q2, r0
; CHECK-FP-NEXT: vmaxnm.f32 q0, q0, q2 ; CHECK-FP-NEXT: vmaxnm.f32 q0, q0, q2
; CHECK-FP-NEXT: vcmp.f32 s4, s0 ; CHECK-FP-NEXT: vcmp.f32 s4, s0
; CHECK-FP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-FP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-FP-NEXT: vselgt.f32 s0, s4, s0 ; CHECK-FP-NEXT: vselgt.f32 s0, s4, s0
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fmax_v4f32_acc_nofast: ; CHECK-NOFP-LABEL: fmax_v4f32_acc_nofast:
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define arm_aapcs_vfpcc float @fmax_v8f32_acc_nofast(<8 x float> %x, float %y) { define arm_aapcs_vfpcc float @fmax_v8f32_acc_nofast(<8 x float> %x, float %y) {
; CHECK-FP-LABEL: fmax_v8f32_acc_nofast: ; CHECK-FP-LABEL: fmax_v8f32_acc_nofast:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vmaxnm.f32 q0, q0, q1 ; CHECK-FP-NEXT: vmaxnm.f32 q0, q0, q1
; CHECK-FP-NEXT: vmov.f64 d2, d1 ; CHECK-FP-NEXT: vmov.f64 d2, d1
; CHECK-FP-NEXT: vmov.f32 s5, s3 ; CHECK-FP-NEXT: vmov.f32 s5, s3
; CHECK-FP-NEXT: vmaxnm.f32 q0, q0, q1 ; CHECK-FP-NEXT: vmaxnm.f32 q0, q0, q1
; CHECK-FP-NEXT: vmov.32 r0, q0[1] ; CHECK-FP-NEXT: vmov r0, s1
; CHECK-FP-NEXT: vdup.32 q1, r0 ; CHECK-FP-NEXT: vdup.32 q1, r0
; CHECK-FP-NEXT: vmaxnm.f32 q0, q0, q1 ; CHECK-FP-NEXT: vmaxnm.f32 q0, q0, q1
; CHECK-FP-NEXT: vcmp.f32 s8, s0 ; CHECK-FP-NEXT: vcmp.f32 s8, s0
; CHECK-FP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-FP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-FP-NEXT: vselgt.f32 s0, s8, s0 ; CHECK-FP-NEXT: vselgt.f32 s0, s8, s0
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fmax_v8f32_acc_nofast: ; CHECK-NOFP-LABEL: fmax_v8f32_acc_nofast:
Show All 28 Linesentry:
%c = fcmp ogt float %y, %z %c = fcmp ogt float %y, %z
%r = select i1 %c, float %y, float %z %r = select i1 %c, float %y, float %z
ret float %r ret float %r
} }
define arm_aapcs_vfpcc void @fmax_v4f16_acc_nofast(<4 x half> %x, half* %yy) { define arm_aapcs_vfpcc void @fmax_v4f16_acc_nofast(<4 x half> %x, half* %yy) {
; CHECK-FP-LABEL: fmax_v4f16_acc_nofast: ; CHECK-FP-LABEL: fmax_v4f16_acc_nofast:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vmov.32 r1, q0[1] ; CHECK-FP-NEXT: vmov r1, s1
; CHECK-FP-NEXT: vdup.32 q1, r1 ; CHECK-FP-NEXT: vdup.32 q1, r1
; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q1 ; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q1
; CHECK-FP-NEXT: vmov.u16 r1, q0[1] ; CHECK-FP-NEXT: vmov.u16 r1, q0[1]
; CHECK-FP-NEXT: vdup.16 q1, r1 ; CHECK-FP-NEXT: vdup.16 q1, r1
; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q1 ; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q1
; CHECK-FP-NEXT: vldr.16 s4, [r0] ; CHECK-FP-NEXT: vldr.16 s4, [r0]
; CHECK-FP-NEXT: vcmp.f16 s4, s0 ; CHECK-FP-NEXT: vcmp.f16 s4, s0
; CHECK-FP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-FP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-FP-NEXT: vselgt.f16 s0, s4, s0 ; CHECK-FP-NEXT: vselgt.f16 s0, s4, s0
; CHECK-FP-NEXT: vstr.16 s0, [r0] ; CHECK-FP-NEXT: vstr.16 s0, [r0]
; CHECK-FP-NEXT: bx lr ; CHECK-FP-NEXT: bx lr
; ;
; CHECK-NOFP-LABEL: fmax_v4f16_acc_nofast: ; CHECK-NOFP-LABEL: fmax_v4f16_acc_nofast:
; CHECK-NOFP: @ %bb.0: @ %entry ; CHECK-NOFP: @ %bb.0: @ %entry
; CHECK-NOFP-NEXT: vmov.32 r1, q0[1] ; CHECK-NOFP-NEXT: vmov r1, s1
; CHECK-NOFP-NEXT: vmovx.f16 s10, s0 ; CHECK-NOFP-NEXT: vmovx.f16 s10, s0
; CHECK-NOFP-NEXT: vdup.32 q1, r1 ; CHECK-NOFP-NEXT: vdup.32 q1, r1
; CHECK-NOFP-NEXT: vmovx.f16 s8, s4 ; CHECK-NOFP-NEXT: vmovx.f16 s8, s4
; CHECK-NOFP-NEXT: vcmp.f16 s10, s8 ; CHECK-NOFP-NEXT: vcmp.f16 s10, s8
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NOFP-NEXT: vcmp.f16 s0, s4 ; CHECK-NOFP-NEXT: vcmp.f16 s0, s4
; CHECK-NOFP-NEXT: vselgt.f16 s8, s10, s8 ; CHECK-NOFP-NEXT: vselgt.f16 s8, s10, s8
; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-NOFP-NEXT: vmrs APSR_nzcv, fpscr
Show All 17 Lines
} }
define arm_aapcs_vfpcc void @fmax_v8f16_acc_nofast(<8 x half> %x, half* %yy) { define arm_aapcs_vfpcc void @fmax_v8f16_acc_nofast(<8 x half> %x, half* %yy) {
; CHECK-FP-LABEL: fmax_v8f16_acc_nofast: ; CHECK-FP-LABEL: fmax_v8f16_acc_nofast:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vmov.f64 d2, d1 ; CHECK-FP-NEXT: vmov.f64 d2, d1
; CHECK-FP-NEXT: vmov.f32 s5, s3 ; CHECK-FP-NEXT: vmov.f32 s5, s3
; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q1 ; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q1
; CHECK-FP-NEXT: vmov.32 r1, q0[1] ; CHECK-FP-NEXT: vmov r1, s1
; CHECK-FP-NEXT: vdup.32 q1, r1 ; CHECK-FP-NEXT: vdup.32 q1, r1
; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q1 ; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q1
; CHECK-FP-NEXT: vmov.u16 r1, q0[1] ; CHECK-FP-NEXT: vmov.u16 r1, q0[1]
; CHECK-FP-NEXT: vdup.16 q1, r1 ; CHECK-FP-NEXT: vdup.16 q1, r1
; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q1 ; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q1
; CHECK-FP-NEXT: vldr.16 s4, [r0] ; CHECK-FP-NEXT: vldr.16 s4, [r0]
; CHECK-FP-NEXT: vcmp.f16 s4, s0 ; CHECK-FP-NEXT: vcmp.f16 s4, s0
; CHECK-FP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-FP-NEXT: vmrs APSR_nzcv, fpscr
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
define arm_aapcs_vfpcc void @fmax_v16f16_acc_nofast(<16 x half> %x, half* %yy) { define arm_aapcs_vfpcc void @fmax_v16f16_acc_nofast(<16 x half> %x, half* %yy) {
; CHECK-FP-LABEL: fmax_v16f16_acc_nofast: ; CHECK-FP-LABEL: fmax_v16f16_acc_nofast:
; CHECK-FP: @ %bb.0: @ %entry ; CHECK-FP: @ %bb.0: @ %entry
; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q1 ; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q1
; CHECK-FP-NEXT: vmov.f64 d2, d1 ; CHECK-FP-NEXT: vmov.f64 d2, d1
; CHECK-FP-NEXT: vmov.f32 s5, s3 ; CHECK-FP-NEXT: vmov.f32 s5, s3
; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q1 ; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q1
; CHECK-FP-NEXT: vmov.32 r1, q0[1] ; CHECK-FP-NEXT: vmov r1, s1
; CHECK-FP-NEXT: vdup.32 q1, r1 ; CHECK-FP-NEXT: vdup.32 q1, r1
; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q1 ; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q1
; CHECK-FP-NEXT: vmov.u16 r1, q0[1] ; CHECK-FP-NEXT: vmov.u16 r1, q0[1]
; CHECK-FP-NEXT: vdup.16 q1, r1 ; CHECK-FP-NEXT: vdup.16 q1, r1
; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q1 ; CHECK-FP-NEXT: vmaxnm.f16 q0, q0, q1
; CHECK-FP-NEXT: vldr.16 s4, [r0] ; CHECK-FP-NEXT: vldr.16 s4, [r0]
; CHECK-FP-NEXT: vcmp.f16 s4, s0 ; CHECK-FP-NEXT: vcmp.f16 s4, s0
; CHECK-FP-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-FP-NEXT: vmrs APSR_nzcv, fpscr
▲ Show 20 Lines • Show All 146 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-vld3.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp,+fp64 -verify-machineinstrs %s -o - | FileCheck %s ; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp,+fp64 -verify-machineinstrs %s -o - | FileCheck %s
; i32 ; i32
define void @vld3_v2i32(<6 x i32> *%src, <2 x i32> *%dst) { define void @vld3_v2i32(<6 x i32> *%src, <2 x i32> *%dst) {
; CHECK-LABEL: vld3_v2i32: ; CHECK-LABEL: vld3_v2i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrd r2, r3, [r0, #16]
; CHECK-NEXT: vldrw.u32 q0, [r0] ; CHECK-NEXT: vldrw.u32 q0, [r0]
; CHECK-NEXT: vmov.32 q2[0], r2 ; CHECK-NEXT: ldrd r2, r3, [r0, #16]
; CHECK-NEXT: vmov.f64 d2, d0 ; CHECK-NEXT: vmov.f64 d2, d0
; CHECK-NEXT: vmov.32 q2[2], r3
; CHECK-NEXT: vmov.32 r0, q0[2]
; CHECK-NEXT: vmov.f32 s12, s1
; CHECK-NEXT: vmov.f32 s6, s3 ; CHECK-NEXT: vmov.f32 s6, s3
; CHECK-NEXT: vmov.f32 s14, s8 ; CHECK-NEXT: vmov.f32 s8, s1
; CHECK-NEXT: vmov r2, s12 ; CHECK-NEXT: vmov r0, s6
; CHECK-NEXT: vmov r12, s6 ; CHECK-NEXT: vmov.32 q1[0], r2
; CHECK-NEXT: vdup.32 q1, r0 ; CHECK-NEXT: vmov.32 q1[2], r3
; CHECK-NEXT: vmov r0, s14 ; CHECK-NEXT: vmov.f32 s10, s4
; CHECK-NEXT: add r0, r12 ; CHECK-NEXT: vmov r2, s10
; CHECK-NEXT: add r0, r2
; CHECK-NEXT: vmov r2, s8
; CHECK-NEXT: add r0, r3 ; CHECK-NEXT: add r0, r3
; CHECK-NEXT: vmov r3, s0 ; CHECK-NEXT: vmov r3, s0
; CHECK-NEXT: add r2, r3 ; CHECK-NEXT: add r2, r3
; CHECK-NEXT: vmov r3, s4 ; CHECK-NEXT: vmov r3, s2
; CHECK-NEXT: add r2, r3 ; CHECK-NEXT: add r2, r3
; CHECK-NEXT: strd r2, r0, [r1] ; CHECK-NEXT: strd r2, r0, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <6 x i32>, <6 x i32>* %src, align 4 %l1 = load <6 x i32>, <6 x i32>* %src, align 4
%s1 = shufflevector <6 x i32> %l1, <6 x i32> undef, <2 x i32> <i32 0, i32 3> %s1 = shufflevector <6 x i32> %l1, <6 x i32> undef, <2 x i32> <i32 0, i32 3>
%s2 = shufflevector <6 x i32> %l1, <6 x i32> undef, <2 x i32> <i32 1, i32 4> %s2 = shufflevector <6 x i32> %l1, <6 x i32> undef, <2 x i32> <i32 1, i32 4>
%s3 = shufflevector <6 x i32> %l1, <6 x i32> undef, <2 x i32> <i32 2, i32 5> %s3 = shufflevector <6 x i32> %l1, <6 x i32> undef, <2 x i32> <i32 2, i32 5>
%a1 = add <2 x i32> %s1, %s2 %a1 = add <2 x i32> %s1, %s2
%a = add <2 x i32> %a1, %s3 %a = add <2 x i32> %a1, %s3
store <2 x i32> %a, <2 x i32> *%dst store <2 x i32> %a, <2 x i32> *%dst
ret void ret void
} }
define void @vld3_v4i32(<12 x i32> *%src, <4 x i32> *%dst) { define void @vld3_v4i32(<12 x i32> *%src, <4 x i32> *%dst) {
; CHECK-LABEL: vld3_v4i32: ; CHECK-LABEL: vld3_v4i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-NEXT: vpush {d8, d9, d10, d11} ; CHECK-NEXT: vpush {d8, d9, d10, d11}
; CHECK-NEXT: vldrw.u32 q1, [r0] ; CHECK-NEXT: vldrw.u32 q1, [r0]
; CHECK-NEXT: vldrw.u32 q0, [r0, #16] ; CHECK-NEXT: vldrw.u32 q0, [r0, #16]
; CHECK-NEXT: vldrw.u32 q2, [r0, #32] ; CHECK-NEXT: vldrw.u32 q2, [r0, #32]
; CHECK-NEXT: vmov.f32 s12, s5 ; CHECK-NEXT: vmov.f32 s12, s5
; CHECK-NEXT: vmov.f32 s13, s0 ; CHECK-NEXT: vmov.f32 s13, s0
; CHECK-NEXT: vmov.32 r0, q2[2] ; CHECK-NEXT: vmov r0, s10
; CHECK-NEXT: vdup.32 q4, r0 ; CHECK-NEXT: vdup.32 q4, r0
; CHECK-NEXT: vmov.f32 s14, s3 ; CHECK-NEXT: vmov.f32 s14, s3
; CHECK-NEXT: vmov.f32 s15, s19 ; CHECK-NEXT: vmov.f32 s15, s19
; CHECK-NEXT: vmov.32 r0, q2[1]
; CHECK-NEXT: vmov.f64 d8, d2 ; CHECK-NEXT: vmov.f64 d8, d2
; CHECK-NEXT: vdup.32 q5, r0
; CHECK-NEXT: vmov.f32 s17, s7 ; CHECK-NEXT: vmov.f32 s17, s7
; CHECK-NEXT: vmov r0, s9
; CHECK-NEXT: vmov.f32 s18, s2 ; CHECK-NEXT: vmov.f32 s18, s2
; CHECK-NEXT: vdup.32 q5, r0
; CHECK-NEXT: vmov.f32 s0, s6 ; CHECK-NEXT: vmov.f32 s0, s6
; CHECK-NEXT: vmov.f32 s19, s23 ; CHECK-NEXT: vmov.f32 s19, s23
; CHECK-NEXT: vmov.f32 s10, s8 ; CHECK-NEXT: vmov.f32 s10, s8
; CHECK-NEXT: vadd.i32 q3, q4, q3 ; CHECK-NEXT: vadd.i32 q3, q4, q3
; CHECK-NEXT: vmov.f32 s2, s8 ; CHECK-NEXT: vmov.f32 s2, s8
; CHECK-NEXT: vmov.f32 s3, s11 ; CHECK-NEXT: vmov.f32 s3, s11
; CHECK-NEXT: vadd.i32 q0, q3, q0 ; CHECK-NEXT: vadd.i32 q0, q3, q0
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
Show All 14 Lines
; CHECK-LABEL: vld3_v8i32: ; CHECK-LABEL: vld3_v8i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: vldrw.u32 q1, [r0, #48] ; CHECK-NEXT: vldrw.u32 q1, [r0, #48]
; CHECK-NEXT: vldrw.u32 q2, [r0, #80] ; CHECK-NEXT: vldrw.u32 q2, [r0, #80]
; CHECK-NEXT: vldrw.u32 q0, [r0, #64] ; CHECK-NEXT: vldrw.u32 q0, [r0, #64]
; CHECK-NEXT: vmov.f32 s12, s5 ; CHECK-NEXT: vmov.f32 s12, s5
; CHECK-NEXT: vmov.32 r2, q2[2]
; CHECK-NEXT: vmov.f32 s13, s0 ; CHECK-NEXT: vmov.f32 s13, s0
; CHECK-NEXT: vmov r2, s10
; CHECK-NEXT: vdup.32 q4, r2 ; CHECK-NEXT: vdup.32 q4, r2
; CHECK-NEXT: vmov.f32 s14, s3 ; CHECK-NEXT: vmov.f32 s14, s3
; CHECK-NEXT: vmov.32 r2, q2[1]
; CHECK-NEXT: vmov.f32 s15, s19 ; CHECK-NEXT: vmov.f32 s15, s19
; CHECK-NEXT: vdup.32 q5, r2
; CHECK-NEXT: vmov.f64 d8, d2 ; CHECK-NEXT: vmov.f64 d8, d2
; CHECK-NEXT: vmov.f32 s17, s7 ; CHECK-NEXT: vmov.f32 s17, s7
; CHECK-NEXT: vmov r2, s9
; CHECK-NEXT: vmov.f32 s18, s2 ; CHECK-NEXT: vmov.f32 s18, s2
; CHECK-NEXT: vdup.32 q5, r2
; CHECK-NEXT: vmov.f32 s0, s6 ; CHECK-NEXT: vmov.f32 s0, s6
; CHECK-NEXT: vldrw.u32 q1, [r0, #16] ; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
; CHECK-NEXT: vmov.f32 s19, s23 ; CHECK-NEXT: vmov.f32 s19, s23
; CHECK-NEXT: vmov.f32 s10, s8 ; CHECK-NEXT: vmov.f32 s10, s8
; CHECK-NEXT: vadd.i32 q3, q4, q3 ; CHECK-NEXT: vadd.i32 q3, q4, q3
; CHECK-NEXT: vmov.f32 s2, s8 ; CHECK-NEXT: vmov.f32 s2, s8
; CHECK-NEXT: vmov.f32 s3, s11 ; CHECK-NEXT: vmov.f32 s3, s11
; CHECK-NEXT: vldrw.u32 q2, [r0] ; CHECK-NEXT: vldrw.u32 q2, [r0]
; CHECK-NEXT: vadd.i32 q0, q3, q0 ; CHECK-NEXT: vadd.i32 q0, q3, q0
; CHECK-NEXT: vldrw.u32 q3, [r0, #32] ; CHECK-NEXT: vldrw.u32 q3, [r0, #32]
; CHECK-NEXT: vmov.f32 s16, s9 ; CHECK-NEXT: vmov.f32 s16, s9
; CHECK-NEXT: vstrw.32 q0, [r1, #16] ; CHECK-NEXT: vstrw.32 q0, [r1, #16]
; CHECK-NEXT: vmov.f32 s17, s4 ; CHECK-NEXT: vmov.f32 s17, s4
; CHECK-NEXT: vmov.32 r0, q3[2] ; CHECK-NEXT: vmov r0, s14
; CHECK-NEXT: vdup.32 q5, r0 ; CHECK-NEXT: vdup.32 q5, r0
; CHECK-NEXT: vmov.f32 s18, s7 ; CHECK-NEXT: vmov.f32 s18, s7
; CHECK-NEXT: vmov.f32 s19, s23 ; CHECK-NEXT: vmov.f32 s19, s23
; CHECK-NEXT: vmov.32 r0, q3[1]
; CHECK-NEXT: vmov.f64 d10, d4 ; CHECK-NEXT: vmov.f64 d10, d4
; CHECK-NEXT: vdup.32 q6, r0
; CHECK-NEXT: vmov.f32 s21, s11 ; CHECK-NEXT: vmov.f32 s21, s11
; CHECK-NEXT: vmov r0, s13
; CHECK-NEXT: vmov.f32 s22, s6 ; CHECK-NEXT: vmov.f32 s22, s6
; CHECK-NEXT: vdup.32 q6, r0
; CHECK-NEXT: vmov.f32 s4, s10 ; CHECK-NEXT: vmov.f32 s4, s10
; CHECK-NEXT: vmov.f32 s23, s27 ; CHECK-NEXT: vmov.f32 s23, s27
; CHECK-NEXT: vmov.f32 s14, s12 ; CHECK-NEXT: vmov.f32 s14, s12
; CHECK-NEXT: vadd.i32 q4, q5, q4 ; CHECK-NEXT: vadd.i32 q4, q5, q4
; CHECK-NEXT: vmov.f32 s6, s12 ; CHECK-NEXT: vmov.f32 s6, s12
; CHECK-NEXT: vmov.f32 s7, s15 ; CHECK-NEXT: vmov.f32 s7, s15
; CHECK-NEXT: vadd.i32 q1, q4, q1 ; CHECK-NEXT: vadd.i32 q1, q4, q1
; CHECK-NEXT: vstrw.32 q1, [r1] ; CHECK-NEXT: vstrw.32 q1, [r1]
Show All 16 Lines
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: .pad #16 ; CHECK-NEXT: .pad #16
; CHECK-NEXT: sub sp, #16 ; CHECK-NEXT: sub sp, #16
; CHECK-NEXT: vldrw.u32 q1, [r0, #48] ; CHECK-NEXT: vldrw.u32 q1, [r0, #48]
; CHECK-NEXT: vldrw.u32 q2, [r0, #80] ; CHECK-NEXT: vldrw.u32 q2, [r0, #80]
; CHECK-NEXT: vldrw.u32 q0, [r0, #64] ; CHECK-NEXT: vldrw.u32 q0, [r0, #64]
; CHECK-NEXT: vmov.f32 s12, s5 ; CHECK-NEXT: vmov.f32 s12, s5
; CHECK-NEXT: vmov.32 r2, q2[2]
; CHECK-NEXT: vmov.f32 s13, s0 ; CHECK-NEXT: vmov.f32 s13, s0
; CHECK-NEXT: vmov r2, s10
; CHECK-NEXT: vdup.32 q4, r2 ; CHECK-NEXT: vdup.32 q4, r2
; CHECK-NEXT: vmov.f32 s14, s3 ; CHECK-NEXT: vmov.f32 s14, s3
; CHECK-NEXT: vmov.32 r2, q2[1]
; CHECK-NEXT: vmov.f32 s15, s19 ; CHECK-NEXT: vmov.f32 s15, s19
; CHECK-NEXT: vdup.32 q5, r2
; CHECK-NEXT: vmov.f64 d8, d2 ; CHECK-NEXT: vmov.f64 d8, d2
; CHECK-NEXT: vmov.f32 s17, s7 ; CHECK-NEXT: vmov.f32 s17, s7
; CHECK-NEXT: vmov r2, s9
; CHECK-NEXT: vmov.f32 s18, s2 ; CHECK-NEXT: vmov.f32 s18, s2
; CHECK-NEXT: vdup.32 q5, r2
; CHECK-NEXT: vmov.f32 s0, s6 ; CHECK-NEXT: vmov.f32 s0, s6
; CHECK-NEXT: vldrw.u32 q1, [r0, #16] ; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
; CHECK-NEXT: vmov.f32 s19, s23 ; CHECK-NEXT: vmov.f32 s19, s23
; CHECK-NEXT: vmov.f32 s10, s8 ; CHECK-NEXT: vmov.f32 s10, s8
; CHECK-NEXT: vadd.i32 q3, q4, q3 ; CHECK-NEXT: vadd.i32 q3, q4, q3
; CHECK-NEXT: vmov.f32 s2, s8 ; CHECK-NEXT: vmov.f32 s2, s8
; CHECK-NEXT: vmov.f32 s3, s11 ; CHECK-NEXT: vmov.f32 s3, s11
; CHECK-NEXT: vldrw.u32 q2, [r0] ; CHECK-NEXT: vldrw.u32 q2, [r0]
; CHECK-NEXT: vadd.i32 q0, q3, q0 ; CHECK-NEXT: vadd.i32 q0, q3, q0
; CHECK-NEXT: vldrw.u32 q3, [r0, #32] ; CHECK-NEXT: vldrw.u32 q3, [r0, #32]
; CHECK-NEXT: vmov.f32 s16, s9 ; CHECK-NEXT: vmov.f32 s16, s9
; CHECK-NEXT: vstrw.32 q0, [sp] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q0, [sp] @ 16-byte Spill
; CHECK-NEXT: vmov.f32 s17, s4 ; CHECK-NEXT: vmov.f32 s17, s4
; CHECK-NEXT: vmov.32 r2, q3[2] ; CHECK-NEXT: vldrw.u32 q0, [r0, #128]
; CHECK-NEXT: vmov r2, s14
; CHECK-NEXT: vdup.32 q5, r2 ; CHECK-NEXT: vdup.32 q5, r2
; CHECK-NEXT: vmov.f32 s18, s7 ; CHECK-NEXT: vmov.f32 s18, s7
; CHECK-NEXT: vmov.f32 s19, s23 ; CHECK-NEXT: vmov.f32 s19, s23
; CHECK-NEXT: vmov.32 r2, q3[1]
; CHECK-NEXT: vmov.f64 d10, d4 ; CHECK-NEXT: vmov.f64 d10, d4
; CHECK-NEXT: vdup.32 q6, r2
; CHECK-NEXT: vldrw.u32 q0, [r0, #128]
; CHECK-NEXT: vmov.f32 s21, s11 ; CHECK-NEXT: vmov.f32 s21, s11
; CHECK-NEXT: vmov r2, s13
; CHECK-NEXT: vmov.f32 s22, s6 ; CHECK-NEXT: vmov.f32 s22, s6
; CHECK-NEXT: vdup.32 q6, r2
; CHECK-NEXT: vmov.f32 s4, s10 ; CHECK-NEXT: vmov.f32 s4, s10
; CHECK-NEXT: vldrw.u32 q2, [r0, #160] ; CHECK-NEXT: vldrw.u32 q2, [r0, #160]
; CHECK-NEXT: vmov.f32 s23, s27 ; CHECK-NEXT: vmov.f32 s23, s27
; CHECK-NEXT: vmov.f32 s14, s12 ; CHECK-NEXT: vmov.f32 s14, s12
; CHECK-NEXT: vadd.i32 q4, q5, q4 ; CHECK-NEXT: vadd.i32 q4, q5, q4
; CHECK-NEXT: vmov.f32 s6, s12 ; CHECK-NEXT: vmov.f32 s6, s12
; CHECK-NEXT: vmov.f32 s7, s15 ; CHECK-NEXT: vmov.f32 s7, s15
; CHECK-NEXT: vldrw.u32 q3, [r0, #144] ; CHECK-NEXT: vldrw.u32 q3, [r0, #144]
; CHECK-NEXT: vadd.i32 q1, q4, q1 ; CHECK-NEXT: vadd.i32 q1, q4, q1
; CHECK-NEXT: vldrw.u32 q4, [r0, #176] ; CHECK-NEXT: vldrw.u32 q4, [r0, #176]
; CHECK-NEXT: vmov.f32 s20, s13 ; CHECK-NEXT: vmov.f32 s20, s13
; CHECK-NEXT: vmov.f32 s21, s8 ; CHECK-NEXT: vmov.f32 s21, s8
; CHECK-NEXT: vmov.32 r2, q4[2] ; CHECK-NEXT: vmov r2, s18
; CHECK-NEXT: vdup.32 q6, r2 ; CHECK-NEXT: vdup.32 q6, r2
; CHECK-NEXT: vmov.f32 s22, s11 ; CHECK-NEXT: vmov.f32 s22, s11
; CHECK-NEXT: vmov.f32 s23, s27 ; CHECK-NEXT: vmov.f32 s23, s27
; CHECK-NEXT: vmov.32 r2, q4[1]
; CHECK-NEXT: vmov.f64 d12, d6 ; CHECK-NEXT: vmov.f64 d12, d6
; CHECK-NEXT: vdup.32 q7, r2
; CHECK-NEXT: vmov.f32 s25, s15 ; CHECK-NEXT: vmov.f32 s25, s15
; CHECK-NEXT: vmov r2, s17
; CHECK-NEXT: vmov.f32 s26, s10 ; CHECK-NEXT: vmov.f32 s26, s10
; CHECK-NEXT: vdup.32 q7, r2
; CHECK-NEXT: vmov.f32 s8, s14 ; CHECK-NEXT: vmov.f32 s8, s14
; CHECK-NEXT: vmov.f32 s27, s31 ; CHECK-NEXT: vmov.f32 s27, s31
; CHECK-NEXT: vmov.f32 s18, s16 ; CHECK-NEXT: vmov.f32 s18, s16
; CHECK-NEXT: vadd.i32 q5, q6, q5 ; CHECK-NEXT: vadd.i32 q5, q6, q5
; CHECK-NEXT: vmov.f32 s10, s16 ; CHECK-NEXT: vmov.f32 s10, s16
; CHECK-NEXT: vmov.f32 s11, s19 ; CHECK-NEXT: vmov.f32 s11, s19
; CHECK-NEXT: vldrw.u32 q4, [r0, #96] ; CHECK-NEXT: vldrw.u32 q4, [r0, #96]
; CHECK-NEXT: vadd.i32 q2, q5, q2 ; CHECK-NEXT: vadd.i32 q2, q5, q2
; CHECK-NEXT: vldrw.u32 q5, [r0, #112] ; CHECK-NEXT: vldrw.u32 q5, [r0, #112]
; CHECK-NEXT: vmov.f32 s24, s17 ; CHECK-NEXT: vmov.f32 s24, s17
; CHECK-NEXT: vmov.32 r0, q0[2]
; CHECK-NEXT: vmov.f32 s25, s20
; CHECK-NEXT: vdup.32 q7, r0
; CHECK-NEXT: vmov.f64 d6, d8
; CHECK-NEXT: vmov.32 r0, q0[1]
; CHECK-NEXT: vstrw.32 q2, [r1, #48] ; CHECK-NEXT: vstrw.32 q2, [r1, #48]
; CHECK-NEXT: vmov.f32 s25, s20
; CHECK-NEXT: vstrw.32 q1, [r1] ; CHECK-NEXT: vstrw.32 q1, [r1]
; CHECK-NEXT: vmov.f32 s26, s23 ; CHECK-NEXT: vmov.f64 d6, d8
; CHECK-NEXT: vmov r0, s2
; CHECK-NEXT: vmov.f32 s13, s19 ; CHECK-NEXT: vmov.f32 s13, s19
; CHECK-NEXT: vdup.32 q7, r0
; CHECK-NEXT: vmov.f32 s26, s23
; CHECK-NEXT: vmov r0, s1
; CHECK-NEXT: vmov.f32 s27, s31 ; CHECK-NEXT: vmov.f32 s27, s31
; CHECK-NEXT: vdup.32 q7, r0 ; CHECK-NEXT: vdup.32 q7, r0
; CHECK-NEXT: vmov.f32 s14, s22 ; CHECK-NEXT: vmov.f32 s14, s22
; CHECK-NEXT: vmov.f32 s20, s18 ; CHECK-NEXT: vmov.f32 s20, s18
; CHECK-NEXT: vmov.f32 s15, s31 ; CHECK-NEXT: vmov.f32 s15, s31
; CHECK-NEXT: vmov.f32 s2, s0 ; CHECK-NEXT: vmov.f32 s2, s0
; CHECK-NEXT: vadd.i32 q6, q3, q6 ; CHECK-NEXT: vadd.i32 q6, q3, q6
; CHECK-NEXT: vmov.f32 s22, s0 ; CHECK-NEXT: vmov.f32 s22, s0
▲ Show 20 Lines • Show All 842 Lines • ▼ Show 20 Linesentry:
%a = fadd <2 x float> %a1, %s3 %a = fadd <2 x float> %a1, %s3
store <2 x float> %a, <2 x float> *%dst store <2 x float> %a, <2 x float> *%dst
ret void ret void
} }
define void @vld3_v4f32(<12 x float> *%src, <4 x float> *%dst) { define void @vld3_v4f32(<12 x float> *%src, <4 x float> *%dst) {
; CHECK-LABEL: vld3_v4f32: ; CHECK-LABEL: vld3_v4f32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9, d10, d11} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vldrw.u32 q1, [r0] ; CHECK-NEXT: vldrw.u32 q1, [r0]
; CHECK-NEXT: vldrw.u32 q0, [r0, #16] ; CHECK-NEXT: vldrw.u32 q0, [r0, #16]
; CHECK-NEXT: vldrw.u32 q2, [r0, #32] ; CHECK-NEXT: vldrw.u32 q2, [r0, #32]
; CHECK-NEXT: vmov.f32 s12, s5 ; CHECK-NEXT: vmov.f32 s12, s5
; CHECK-NEXT: vmov.f32 s13, s0
; CHECK-NEXT: vmov.32 r0, q2[2]
; CHECK-NEXT: vdup.32 q4, r0
; CHECK-NEXT: vmov.f32 s14, s3
; CHECK-NEXT: vmov.f32 s15, s19
; CHECK-NEXT: vmov.32 r0, q2[1]
; CHECK-NEXT: vmov.f64 d8, d2 ; CHECK-NEXT: vmov.f64 d8, d2
; CHECK-NEXT: vdup.32 q5, r0 ; CHECK-NEXT: vmov.f32 s13, s0
; CHECK-NEXT: vmov.f32 s17, s7 ; CHECK-NEXT: vmov.f32 s17, s7
; CHECK-NEXT: vmov.f32 s14, s3
; CHECK-NEXT: vmov.f32 s18, s2 ; CHECK-NEXT: vmov.f32 s18, s2
; CHECK-NEXT: vmov.f32 s0, s6 ; CHECK-NEXT: vmov.f32 s0, s6
; CHECK-NEXT: vmov.f32 s19, s23 ; CHECK-NEXT: vmov.f32 s15, s10
; CHECK-NEXT: vmov.f32 s19, s9
; CHECK-NEXT: vmov.f32 s10, s8 ; CHECK-NEXT: vmov.f32 s10, s8
; CHECK-NEXT: vadd.f32 q3, q4, q3 ; CHECK-NEXT: vadd.f32 q3, q4, q3
; CHECK-NEXT: vmov.f32 s2, s8 ; CHECK-NEXT: vmov.f32 s2, s8
; CHECK-NEXT: vmov.f32 s3, s11 ; CHECK-NEXT: vmov.f32 s3, s11
; CHECK-NEXT: vadd.f32 q0, q3, q0 ; CHECK-NEXT: vadd.f32 q0, q3, q0
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: vpop {d8, d9, d10, d11} ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <12 x float>, <12 x float>* %src, align 4 %l1 = load <12 x float>, <12 x float>* %src, align 4
%s1 = shufflevector <12 x float> %l1, <12 x float> undef, <4 x i32> <i32 0, i32 3, i32 6, i32 9> %s1 = shufflevector <12 x float> %l1, <12 x float> undef, <4 x i32> <i32 0, i32 3, i32 6, i32 9>
%s2 = shufflevector <12 x float> %l1, <12 x float> undef, <4 x i32> <i32 1, i32 4, i32 7, i32 10> %s2 = shufflevector <12 x float> %l1, <12 x float> undef, <4 x i32> <i32 1, i32 4, i32 7, i32 10>
%s3 = shufflevector <12 x float> %l1, <12 x float> undef, <4 x i32> <i32 2, i32 5, i32 8, i32 11> %s3 = shufflevector <12 x float> %l1, <12 x float> undef, <4 x i32> <i32 2, i32 5, i32 8, i32 11>
%a1 = fadd <4 x float> %s1, %s2 %a1 = fadd <4 x float> %s1, %s2
%a = fadd <4 x float> %a1, %s3 %a = fadd <4 x float> %a1, %s3
store <4 x float> %a, <4 x float> *%dst store <4 x float> %a, <4 x float> *%dst
ret void ret void
} }
define void @vld3_v8f32(<24 x float> *%src, <8 x float> *%dst) { define void @vld3_v8f32(<24 x float> *%src, <8 x float> *%dst) {
; CHECK-LABEL: vld3_v8f32: ; CHECK-LABEL: vld3_v8f32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: vpush {d8, d9, d10, d11}
; CHECK-NEXT: vldrw.u32 q1, [r0, #48] ; CHECK-NEXT: vldrw.u32 q1, [r0, #48]
; CHECK-NEXT: vldrw.u32 q2, [r0, #80]
; CHECK-NEXT: vldrw.u32 q0, [r0, #64] ; CHECK-NEXT: vldrw.u32 q0, [r0, #64]
; CHECK-NEXT: vldrw.u32 q2, [r0, #80]
; CHECK-NEXT: vmov.f32 s12, s5 ; CHECK-NEXT: vmov.f32 s12, s5
; CHECK-NEXT: vmov.32 r2, q2[2]
; CHECK-NEXT: vmov.f32 s13, s0
; CHECK-NEXT: vdup.32 q4, r2
; CHECK-NEXT: vmov.f32 s14, s3
; CHECK-NEXT: vmov.32 r2, q2[1]
; CHECK-NEXT: vmov.f32 s15, s19
; CHECK-NEXT: vdup.32 q5, r2
; CHECK-NEXT: vmov.f64 d8, d2 ; CHECK-NEXT: vmov.f64 d8, d2
; CHECK-NEXT: vmov.f32 s13, s0
; CHECK-NEXT: vmov.f32 s17, s7 ; CHECK-NEXT: vmov.f32 s17, s7
; CHECK-NEXT: vmov.f32 s14, s3
; CHECK-NEXT: vmov.f32 s18, s2 ; CHECK-NEXT: vmov.f32 s18, s2
; CHECK-NEXT: vmov.f32 s0, s6 ; CHECK-NEXT: vmov.f32 s0, s6
; CHECK-NEXT: vldrw.u32 q1, [r0, #16] ; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
; CHECK-NEXT: vmov.f32 s19, s23 ; CHECK-NEXT: vmov.f32 s15, s10
; CHECK-NEXT: vmov.f32 s19, s9
; CHECK-NEXT: vmov.f32 s10, s8 ; CHECK-NEXT: vmov.f32 s10, s8
; CHECK-NEXT: vadd.f32 q3, q4, q3 ; CHECK-NEXT: vadd.f32 q3, q4, q3
; CHECK-NEXT: vmov.f32 s2, s8 ; CHECK-NEXT: vmov.f32 s2, s8
; CHECK-NEXT: vmov.f32 s3, s11 ; CHECK-NEXT: vmov.f32 s3, s11
; CHECK-NEXT: vldrw.u32 q2, [r0] ; CHECK-NEXT: vldrw.u32 q2, [r0]
; CHECK-NEXT: vadd.f32 q0, q3, q0 ; CHECK-NEXT: vadd.f32 q0, q3, q0
; CHECK-NEXT: vldrw.u32 q3, [r0, #32] ; CHECK-NEXT: vldrw.u32 q3, [r0, #32]
; CHECK-NEXT: vmov.f32 s16, s9 ; CHECK-NEXT: vmov.f32 s16, s9
; CHECK-NEXT: vstrw.32 q0, [r1, #16] ; CHECK-NEXT: vstrw.32 q0, [r1, #16]
; CHECK-NEXT: vmov.f32 s17, s4
; CHECK-NEXT: vmov.32 r0, q3[2]
; CHECK-NEXT: vdup.32 q5, r0
; CHECK-NEXT: vmov.f32 s18, s7
; CHECK-NEXT: vmov.f32 s19, s23
; CHECK-NEXT: vmov.32 r0, q3[1]
; CHECK-NEXT: vmov.f64 d10, d4 ; CHECK-NEXT: vmov.f64 d10, d4
; CHECK-NEXT: vdup.32 q6, r0 ; CHECK-NEXT: vmov.f32 s17, s4
; CHECK-NEXT: vmov.f32 s21, s11 ; CHECK-NEXT: vmov.f32 s21, s11
; CHECK-NEXT: vmov.f32 s18, s7
; CHECK-NEXT: vmov.f32 s22, s6 ; CHECK-NEXT: vmov.f32 s22, s6
; CHECK-NEXT: vmov.f32 s4, s10 ; CHECK-NEXT: vmov.f32 s4, s10
; CHECK-NEXT: vmov.f32 s23, s27 ; CHECK-NEXT: vmov.f32 s19, s14
; CHECK-NEXT: vmov.f32 s23, s13
; CHECK-NEXT: vmov.f32 s14, s12 ; CHECK-NEXT: vmov.f32 s14, s12
; CHECK-NEXT: vadd.f32 q4, q5, q4 ; CHECK-NEXT: vadd.f32 q4, q5, q4
; CHECK-NEXT: vmov.f32 s6, s12 ; CHECK-NEXT: vmov.f32 s6, s12
; CHECK-NEXT: vmov.f32 s7, s15 ; CHECK-NEXT: vmov.f32 s7, s15
; CHECK-NEXT: vadd.f32 q1, q4, q1 ; CHECK-NEXT: vadd.f32 q1, q4, q1
; CHECK-NEXT: vstrw.32 q1, [r1] ; CHECK-NEXT: vstrw.32 q1, [r1]
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13} ; CHECK-NEXT: vpop {d8, d9, d10, d11}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <24 x float>, <24 x float>* %src, align 4 %l1 = load <24 x float>, <24 x float>* %src, align 4
%s1 = shufflevector <24 x float> %l1, <24 x float> undef, <8 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21> %s1 = shufflevector <24 x float> %l1, <24 x float> undef, <8 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21>
%s2 = shufflevector <24 x float> %l1, <24 x float> undef, <8 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22> %s2 = shufflevector <24 x float> %l1, <24 x float> undef, <8 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22>
%s3 = shufflevector <24 x float> %l1, <24 x float> undef, <8 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23> %s3 = shufflevector <24 x float> %l1, <24 x float> undef, <8 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23>
%a1 = fadd <8 x float> %s1, %s2 %a1 = fadd <8 x float> %s1, %s2
%a = fadd <8 x float> %a1, %s3 %a = fadd <8 x float> %a1, %s3
store <8 x float> %a, <8 x float> *%dst store <8 x float> %a, <8 x float> *%dst
ret void ret void
} }
define void @vld3_v16f32(<48 x float> *%src, <16 x float> *%dst) { define void @vld3_v16f32(<48 x float> *%src, <16 x float> *%dst) {
; CHECK-LABEL: vld3_v16f32: ; CHECK-LABEL: vld3_v16f32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: .pad #16
; CHECK-NEXT: sub sp, #16
; CHECK-NEXT: vldrw.u32 q1, [r0, #48] ; CHECK-NEXT: vldrw.u32 q1, [r0, #48]
; CHECK-NEXT: vldrw.u32 q2, [r0, #80]
; CHECK-NEXT: vldrw.u32 q0, [r0, #64] ; CHECK-NEXT: vldrw.u32 q0, [r0, #64]
; CHECK-NEXT: vldrw.u32 q2, [r0, #80]
; CHECK-NEXT: vmov.f32 s12, s5 ; CHECK-NEXT: vmov.f32 s12, s5
; CHECK-NEXT: vmov.32 r2, q2[2]
; CHECK-NEXT: vmov.f32 s13, s0
; CHECK-NEXT: vdup.32 q4, r2
; CHECK-NEXT: vmov.f32 s14, s3
; CHECK-NEXT: vmov.32 r2, q2[1]
; CHECK-NEXT: vmov.f32 s15, s19
; CHECK-NEXT: vdup.32 q5, r2
; CHECK-NEXT: vmov.f64 d8, d2 ; CHECK-NEXT: vmov.f64 d8, d2
; CHECK-NEXT: vmov.f32 s13, s0
; CHECK-NEXT: vmov.f32 s17, s7 ; CHECK-NEXT: vmov.f32 s17, s7
; CHECK-NEXT: vmov.f32 s14, s3
; CHECK-NEXT: vmov.f32 s18, s2 ; CHECK-NEXT: vmov.f32 s18, s2
; CHECK-NEXT: vmov.f32 s0, s6 ; CHECK-NEXT: vmov.f32 s0, s6
; CHECK-NEXT: vldrw.u32 q1, [r0, #16] ; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
; CHECK-NEXT: vmov.f32 s19, s23 ; CHECK-NEXT: vmov.f32 s15, s10
; CHECK-NEXT: vmov.f32 s19, s9
; CHECK-NEXT: vmov.f32 s10, s8 ; CHECK-NEXT: vmov.f32 s10, s8
; CHECK-NEXT: vadd.f32 q3, q4, q3 ; CHECK-NEXT: vadd.f32 q3, q4, q3
; CHECK-NEXT: vmov.f32 s2, s8 ; CHECK-NEXT: vmov.f32 s2, s8
; CHECK-NEXT: vmov.f32 s3, s11 ; CHECK-NEXT: vmov.f32 s3, s11
; CHECK-NEXT: vldrw.u32 q2, [r0] ; CHECK-NEXT: vldrw.u32 q2, [r0]
; CHECK-NEXT: vadd.f32 q0, q3, q0 ; CHECK-NEXT: vadd.f32 q0, q3, q0
; CHECK-NEXT: vldrw.u32 q3, [r0, #32] ; CHECK-NEXT: vldrw.u32 q3, [r0, #32]
; CHECK-NEXT: vmov.f32 s16, s9 ; CHECK-NEXT: vmov.f32 s16, s9
; CHECK-NEXT: vstrw.32 q0, [sp] @ 16-byte Spill
; CHECK-NEXT: vmov.f32 s17, s4
; CHECK-NEXT: vmov.32 r2, q3[2]
; CHECK-NEXT: vdup.32 q5, r2
; CHECK-NEXT: vmov.f32 s18, s7
; CHECK-NEXT: vmov.f32 s19, s23
; CHECK-NEXT: vmov.32 r2, q3[1]
; CHECK-NEXT: vmov.f64 d10, d4 ; CHECK-NEXT: vmov.f64 d10, d4
; CHECK-NEXT: vdup.32 q6, r2 ; CHECK-NEXT: vmov.f32 s17, s4
; CHECK-NEXT: vldrw.u32 q0, [r0, #128]
; CHECK-NEXT: vmov.f32 s21, s11 ; CHECK-NEXT: vmov.f32 s21, s11
; CHECK-NEXT: vmov.f32 s18, s7
; CHECK-NEXT: vmov.f32 s22, s6 ; CHECK-NEXT: vmov.f32 s22, s6
; CHECK-NEXT: vmov.f32 s4, s10 ; CHECK-NEXT: vmov.f32 s4, s10
; CHECK-NEXT: vldrw.u32 q2, [r0, #160] ; CHECK-NEXT: vldrw.u32 q2, [r0, #160]
; CHECK-NEXT: vmov.f32 s23, s27 ; CHECK-NEXT: vmov.f32 s19, s14
; CHECK-NEXT: vmov.f32 s23, s13
; CHECK-NEXT: vmov.f32 s14, s12 ; CHECK-NEXT: vmov.f32 s14, s12
; CHECK-NEXT: vadd.f32 q4, q5, q4 ; CHECK-NEXT: vadd.f32 q4, q5, q4
; CHECK-NEXT: vmov.f32 s6, s12 ; CHECK-NEXT: vmov.f32 s6, s12
; CHECK-NEXT: vmov.f32 s7, s15 ; CHECK-NEXT: vmov.f32 s7, s15
; CHECK-NEXT: vldrw.u32 q3, [r0, #144] ; CHECK-NEXT: vldrw.u32 q3, [r0, #144]
; CHECK-NEXT: vadd.f32 q1, q4, q1 ; CHECK-NEXT: vadd.f32 q1, q4, q1
; CHECK-NEXT: vldrw.u32 q4, [r0, #176] ; CHECK-NEXT: vldrw.u32 q4, [r0, #176]
; CHECK-NEXT: vmov.f32 s20, s13 ; CHECK-NEXT: vmov.f32 s20, s13
; CHECK-NEXT: vmov.f32 s21, s8
; CHECK-NEXT: vmov.32 r2, q4[2]
; CHECK-NEXT: vdup.32 q6, r2
; CHECK-NEXT: vmov.f32 s22, s11
; CHECK-NEXT: vmov.f32 s23, s27
; CHECK-NEXT: vmov.32 r2, q4[1]
; CHECK-NEXT: vmov.f64 d12, d6 ; CHECK-NEXT: vmov.f64 d12, d6
; CHECK-NEXT: vdup.32 q7, r2 ; CHECK-NEXT: vmov.f32 s21, s8
; CHECK-NEXT: vmov.f32 s25, s15 ; CHECK-NEXT: vmov.f32 s25, s15
; CHECK-NEXT: vmov.f32 s22, s11
; CHECK-NEXT: vmov.f32 s26, s10 ; CHECK-NEXT: vmov.f32 s26, s10
; CHECK-NEXT: vmov.f32 s8, s14 ; CHECK-NEXT: vmov.f32 s8, s14
; CHECK-NEXT: vmov.f32 s27, s31 ; CHECK-NEXT: vldrw.u32 q3, [r0, #112]
; CHECK-NEXT: vmov.f32 s23, s18
; CHECK-NEXT: vmov.f32 s27, s17
; CHECK-NEXT: vmov.f32 s18, s16 ; CHECK-NEXT: vmov.f32 s18, s16
; CHECK-NEXT: vadd.f32 q5, q6, q5 ; CHECK-NEXT: vadd.f32 q5, q6, q5
; CHECK-NEXT: vmov.f32 s10, s16 ; CHECK-NEXT: vmov.f32 s10, s16
; CHECK-NEXT: vmov.f32 s11, s19 ; CHECK-NEXT: vmov.f32 s11, s19
; CHECK-NEXT: vldrw.u32 q4, [r0, #96] ; CHECK-NEXT: vldrw.u32 q4, [r0, #96]
; CHECK-NEXT: vadd.f32 q2, q5, q2 ; CHECK-NEXT: vadd.f32 q2, q5, q2
; CHECK-NEXT: vldrw.u32 q5, [r0, #112] ; CHECK-NEXT: vldrw.u32 q5, [r0, #128]
; CHECK-NEXT: vmov.f32 s24, s17 ; CHECK-NEXT: vmov.f32 s24, s17
; CHECK-NEXT: vmov.32 r0, q0[2]
; CHECK-NEXT: vmov.f32 s25, s20
; CHECK-NEXT: vdup.32 q7, r0
; CHECK-NEXT: vmov.f64 d6, d8
; CHECK-NEXT: vmov.32 r0, q0[1]
; CHECK-NEXT: vstrw.32 q2, [r1, #48] ; CHECK-NEXT: vstrw.32 q2, [r1, #48]
; CHECK-NEXT: vstrw.32 q1, [r1] ; CHECK-NEXT: vmov.f64 d14, d8
; CHECK-NEXT: vmov.f32 s26, s23
; CHECK-NEXT: vmov.f32 s13, s19
; CHECK-NEXT: vmov.f32 s27, s31
; CHECK-NEXT: vdup.32 q7, r0
; CHECK-NEXT: vmov.f32 s14, s22
; CHECK-NEXT: vmov.f32 s20, s18
; CHECK-NEXT: vmov.f32 s15, s31
; CHECK-NEXT: vmov.f32 s2, s0
; CHECK-NEXT: vadd.f32 q6, q3, q6
; CHECK-NEXT: vmov.f32 s22, s0
; CHECK-NEXT: vmov.f32 s23, s3
; CHECK-NEXT: vadd.f32 q0, q6, q5
; CHECK-NEXT: vstrw.32 q0, [r1, #32]
; CHECK-NEXT: vldrw.u32 q0, [sp] @ 16-byte Reload
; CHECK-NEXT: vstrw.32 q0, [r1, #16] ; CHECK-NEXT: vstrw.32 q0, [r1, #16]
; CHECK-NEXT: add sp, #16 ; CHECK-NEXT: vstrw.32 q1, [r1]
; CHECK-NEXT: vmov.f32 s25, s12
; CHECK-NEXT: vmov.f32 s29, s19
; CHECK-NEXT: vmov.f32 s26, s15
; CHECK-NEXT: vmov.f32 s30, s14
; CHECK-NEXT: vmov.f32 s12, s18
; CHECK-NEXT: vmov.f32 s27, s22
; CHECK-NEXT: vmov.f32 s31, s21
; CHECK-NEXT: vmov.f32 s22, s20
; CHECK-NEXT: vadd.f32 q6, q7, q6
; CHECK-NEXT: vmov.f32 s14, s20
; CHECK-NEXT: vmov.f32 s15, s23
; CHECK-NEXT: vadd.f32 q3, q6, q3
; CHECK-NEXT: vstrw.32 q3, [r1, #32]
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <48 x float>, <48 x float>* %src, align 4 %l1 = load <48 x float>, <48 x float>* %src, align 4
%s1 = shufflevector <48 x float> %l1, <48 x float> undef, <16 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21, i32 24, i32 27, i32 30, i32 33, i32 36, i32 39, i32 42, i32 45> %s1 = shufflevector <48 x float> %l1, <48 x float> undef, <16 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21, i32 24, i32 27, i32 30, i32 33, i32 36, i32 39, i32 42, i32 45>
%s2 = shufflevector <48 x float> %l1, <48 x float> undef, <16 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22, i32 25, i32 28, i32 31, i32 34, i32 37, i32 40, i32 43, i32 46> %s2 = shufflevector <48 x float> %l1, <48 x float> undef, <16 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22, i32 25, i32 28, i32 31, i32 34, i32 37, i32 40, i32 43, i32 46>
%s3 = shufflevector <48 x float> %l1, <48 x float> undef, <16 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23, i32 26, i32 29, i32 32, i32 35, i32 38, i32 41, i32 44, i32 47> %s3 = shufflevector <48 x float> %l1, <48 x float> undef, <16 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23, i32 26, i32 29, i32 32, i32 35, i32 38, i32 41, i32 44, i32 47>
%a1 = fadd <16 x float> %s1, %s2 %a1 = fadd <16 x float> %s1, %s2
▲ Show 20 Lines • Show All 456 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-vld4.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp,+fp64 -mve-max-interleave-factor=4 -verify-machineinstrs %s -o - | FileCheck %s ; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp,+fp64 -mve-max-interleave-factor=4 -verify-machineinstrs %s -o - | FileCheck %s
; i32 ; i32
define void @vld4_v2i32(<8 x i32> *%src, <2 x i32> *%dst) { define void @vld4_v2i32(<8 x i32> *%src, <2 x i32> *%dst) {
; CHECK-LABEL: vld4_v2i32: ; CHECK-LABEL: vld4_v2i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vldrw.u32 q0, [r0] ; CHECK-NEXT: vldrw.u32 q0, [r0]
; CHECK-NEXT: vldrw.u32 q1, [r0, #16] ; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
; CHECK-NEXT: vmov.f32 s8, s3 ; CHECK-NEXT: vmov.f32 s8, s3
; CHECK-NEXT: vmov.32 r3, q1[0]
; CHECK-NEXT: vmov.f32 s10, s7 ; CHECK-NEXT: vmov.f32 s10, s7
; CHECK-NEXT: vmov r2, s6 ; CHECK-NEXT: vmov r2, s6
; CHECK-NEXT: vmov.f32 s12, s1 ; CHECK-NEXT: vmov.f32 s12, s1
; CHECK-NEXT: vmov.f32 s14, s5 ; CHECK-NEXT: vmov.f32 s14, s5
; CHECK-NEXT: vdup.32 q1, r3 ; CHECK-NEXT: vmov r3, s4
; CHECK-NEXT: vmov r3, s6
; CHECK-NEXT: vmov r0, s10 ; CHECK-NEXT: vmov r0, s10
; CHECK-NEXT: add r0, r2 ; CHECK-NEXT: add r0, r2
; CHECK-NEXT: vmov r2, s14 ; CHECK-NEXT: vmov r2, s14
; CHECK-NEXT: add r2, r3 ; CHECK-NEXT: add r2, r3
; CHECK-NEXT: vmov r3, s0 ; CHECK-NEXT: vmov r3, s2
; CHECK-NEXT: add r0, r2 ; CHECK-NEXT: add.w r12, r2, r0
; CHECK-NEXT: vmov.32 r2, q0[2] ; CHECK-NEXT: vmov r2, s8
; CHECK-NEXT: vdup.32 q1, r2 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: str r0, [r1, #4]
; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vmov r2, s4
; CHECK-NEXT: add r0, r2
; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: add r2, r3 ; CHECK-NEXT: add r2, r3
; CHECK-NEXT: vmov r3, s12
; CHECK-NEXT: add r0, r3
; CHECK-NEXT: add r0, r2 ; CHECK-NEXT: add r0, r2
; CHECK-NEXT: str r0, [r1] ; CHECK-NEXT: strd r0, r12, [r1]
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%l1 = load <8 x i32>, <8 x i32>* %src, align 4 %l1 = load <8 x i32>, <8 x i32>* %src, align 4
%s1 = shufflevector <8 x i32> %l1, <8 x i32> undef, <2 x i32> <i32 0, i32 4> %s1 = shufflevector <8 x i32> %l1, <8 x i32> undef, <2 x i32> <i32 0, i32 4>
%s2 = shufflevector <8 x i32> %l1, <8 x i32> undef, <2 x i32> <i32 1, i32 5> %s2 = shufflevector <8 x i32> %l1, <8 x i32> undef, <2 x i32> <i32 1, i32 5>
%s3 = shufflevector <8 x i32> %l1, <8 x i32> undef, <2 x i32> <i32 2, i32 6> %s3 = shufflevector <8 x i32> %l1, <8 x i32> undef, <2 x i32> <i32 2, i32 6>
%s4 = shufflevector <8 x i32> %l1, <8 x i32> undef, <2 x i32> <i32 3, i32 7> %s4 = shufflevector <8 x i32> %l1, <8 x i32> undef, <2 x i32> <i32 3, i32 7>
%a1 = add <2 x i32> %s1, %s2 %a1 = add <2 x i32> %s1, %s2
▲ Show 20 Lines • Show All 1,147 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-vst3.ll

Show First 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-NEXT: vpush {d8, d9, d10, d11} ; CHECK-NEXT: vpush {d8, d9, d10, d11}
; CHECK-NEXT: vldrw.u32 q4, [r0] ; CHECK-NEXT: vldrw.u32 q4, [r0]
; CHECK-NEXT: vldrw.u32 q2, [r0, #16] ; CHECK-NEXT: vldrw.u32 q2, [r0, #16]
; CHECK-NEXT: vldrw.u32 q0, [r0, #32] ; CHECK-NEXT: vldrw.u32 q0, [r0, #32]
; CHECK-NEXT: vmov.f32 s4, s9 ; CHECK-NEXT: vmov.f32 s4, s9
; CHECK-NEXT: vmov.f64 d6, d8 ; CHECK-NEXT: vmov.f64 d6, d8
; CHECK-NEXT: vmov.32 r0, q0[0] ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vdup.32 q5, r0
; CHECK-NEXT: vmov.32 r0, q2[3]
; CHECK-NEXT: vmov.f32 s5, s1 ; CHECK-NEXT: vmov.f32 s5, s1
; CHECK-NEXT: vdup.32 q5, r0
; CHECK-NEXT: vmov.f32 s13, s8 ; CHECK-NEXT: vmov.f32 s13, s8
; CHECK-NEXT: vmov.f32 s0, s2 ; CHECK-NEXT: vmov.f32 s0, s2
; CHECK-NEXT: vmov r0, s11
; CHECK-NEXT: vmov.f32 s7, s10 ; CHECK-NEXT: vmov.f32 s7, s10
; CHECK-NEXT: vdup.32 q2, r0 ; CHECK-NEXT: vdup.32 q2, r0
; CHECK-NEXT: vmov.f32 s15, s17 ; CHECK-NEXT: vmov.f32 s15, s17
; CHECK-NEXT: vmov.f32 s1, s19 ; CHECK-NEXT: vmov.f32 s1, s19
; CHECK-NEXT: vmov.f32 s6, s18 ; CHECK-NEXT: vmov.f32 s6, s18
; CHECK-NEXT: vmov.f32 s14, s22 ; CHECK-NEXT: vmov.f32 s14, s22
; CHECK-NEXT: vstrw.32 q1, [r1, #16] ; CHECK-NEXT: vstrw.32 q1, [r1, #16]
; CHECK-NEXT: vmov.f32 s2, s10 ; CHECK-NEXT: vmov.f32 s2, s10
Show All 23 Lines
; CHECK-NEXT: .pad #48 ; CHECK-NEXT: .pad #48
; CHECK-NEXT: sub sp, #48 ; CHECK-NEXT: sub sp, #48
; CHECK-NEXT: vldrw.u32 q0, [r0, #80] ; CHECK-NEXT: vldrw.u32 q0, [r0, #80]
; CHECK-NEXT: vldrw.u32 q5, [r0, #16] ; CHECK-NEXT: vldrw.u32 q5, [r0, #16]
; CHECK-NEXT: vldrw.u32 q1, [r0, #48] ; CHECK-NEXT: vldrw.u32 q1, [r0, #48]
; CHECK-NEXT: vldrw.u32 q4, [r0] ; CHECK-NEXT: vldrw.u32 q4, [r0]
; CHECK-NEXT: vmov.f64 d6, d1 ; CHECK-NEXT: vmov.f64 d6, d1
; CHECK-NEXT: vldrw.u32 q6, [r0, #32] ; CHECK-NEXT: vldrw.u32 q6, [r0, #32]
; CHECK-NEXT: vmov.32 r2, q1[3]
; CHECK-NEXT: vldrw.u32 q7, [r0, #64] ; CHECK-NEXT: vldrw.u32 q7, [r0, #64]
; CHECK-NEXT: vdup.32 q2, r2
; CHECK-NEXT: vstrw.32 q4, [sp, #32] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q4, [sp, #32] @ 16-byte Spill
; CHECK-NEXT: vstrw.32 q5, [sp] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q5, [sp] @ 16-byte Spill
; CHECK-NEXT: vmov.32 r0, q7[0]
; CHECK-NEXT: vmov.f32 s13, s23
; CHECK-NEXT: vstrw.32 q6, [sp, #16] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q6, [sp, #16] @ 16-byte Spill
; CHECK-NEXT: vmov.f32 s13, s23
; CHECK-NEXT: vmov r2, s7
; CHECK-NEXT: vmov.f32 s15, s3 ; CHECK-NEXT: vmov.f32 s15, s3
; CHECK-NEXT: vdup.32 q2, r2
; CHECK-NEXT: vmov.f32 s14, s10 ; CHECK-NEXT: vmov.f32 s14, s10
; CHECK-NEXT: vmov.f64 d4, d8 ; CHECK-NEXT: vmov.f64 d4, d8
; CHECK-NEXT: vstrw.32 q3, [r1, #80] ; CHECK-NEXT: vstrw.32 q3, [r1, #80]
; CHECK-NEXT: vmov.f32 s9, s24 ; CHECK-NEXT: vmov.f32 s9, s24
; CHECK-NEXT: vmov.f32 s11, s17 ; CHECK-NEXT: vmov.f32 s11, s17
; CHECK-NEXT: vmov q4, q5 ; CHECK-NEXT: vmov q4, q5
; CHECK-NEXT: vmov.f32 s21, s4 ; CHECK-NEXT: vmov.f32 s21, s4
; CHECK-NEXT: vmov r0, s28
; CHECK-NEXT: vmov.f32 s23, s17 ; CHECK-NEXT: vmov.f32 s23, s17
; CHECK-NEXT: vdup.32 q4, r0 ; CHECK-NEXT: vdup.32 q4, r0
; CHECK-NEXT: vmov.32 r0, q0[0] ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.f32 s0, s5 ; CHECK-NEXT: vmov.f32 s0, s5
; CHECK-NEXT: vdup.32 q6, r0
; CHECK-NEXT: vmov.f32 s10, s18 ; CHECK-NEXT: vmov.f32 s10, s18
; CHECK-NEXT: vldrw.u32 q4, [sp, #16] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q4, [sp, #16] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s3, s6 ; CHECK-NEXT: vmov.f32 s3, s6
; CHECK-NEXT: vldrw.u32 q1, [sp] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q1, [sp] @ 16-byte Reload
; CHECK-NEXT: vdup.32 q6, r0
; CHECK-NEXT: vmov.32 r0, q4[3]
; CHECK-NEXT: vmov.f32 s22, s26 ; CHECK-NEXT: vmov.f32 s22, s26
; CHECK-NEXT: vldrw.u32 q6, [sp, #32] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q6, [sp, #32] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s2, s6 ; CHECK-NEXT: vmov.f32 s2, s6
; CHECK-NEXT: vstrw.32 q5, [r1, #48] ; CHECK-NEXT: vstrw.32 q5, [r1, #48]
; CHECK-NEXT: vmov.f32 s4, s17 ; CHECK-NEXT: vmov.f32 s4, s17
; CHECK-NEXT: vstrw.32 q0, [r1, #64] ; CHECK-NEXT: vstrw.32 q0, [r1, #64]
; CHECK-NEXT: vmov.f32 s5, s29 ; CHECK-NEXT: vmov.f32 s5, s29
; CHECK-NEXT: vstrw.32 q2, [r1] ; CHECK-NEXT: vstrw.32 q2, [r1]
; CHECK-NEXT: vmov.f32 s28, s30 ; CHECK-NEXT: vmov.f32 s28, s30
; CHECK-NEXT: vmov r0, s19
; CHECK-NEXT: vmov.f32 s7, s18 ; CHECK-NEXT: vmov.f32 s7, s18
; CHECK-NEXT: vdup.32 q4, r0 ; CHECK-NEXT: vdup.32 q4, r0
; CHECK-NEXT: vmov.f32 s29, s27 ; CHECK-NEXT: vmov.f32 s29, s27
; CHECK-NEXT: vmov.f32 s6, s26 ; CHECK-NEXT: vmov.f32 s6, s26
; CHECK-NEXT: vmov.f32 s30, s18 ; CHECK-NEXT: vmov.f32 s30, s18
; CHECK-NEXT: vstrw.32 q1, [r1, #16] ; CHECK-NEXT: vstrw.32 q1, [r1, #16]
; CHECK-NEXT: vstrw.32 q7, [r1, #32] ; CHECK-NEXT: vstrw.32 q7, [r1, #32]
; CHECK-NEXT: add sp, #48 ; CHECK-NEXT: add sp, #48
Show All 15 Lines
define void @vst3_v16i32(<16 x i32> *%src, <48 x i32> *%dst) { define void @vst3_v16i32(<16 x i32> *%src, <48 x i32> *%dst) {
; CHECK-LABEL: vst3_v16i32: ; CHECK-LABEL: vst3_v16i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: .pad #160 ; CHECK-NEXT: .pad #160
; CHECK-NEXT: sub sp, #160 ; CHECK-NEXT: sub sp, #160
; CHECK-NEXT: vldrw.u32 q2, [r0, #80] ; CHECK-NEXT: vldrw.u32 q1, [r0, #144]
; CHECK-NEXT: vldrw.u32 q6, [r0, #64] ; CHECK-NEXT: vldrw.u32 q0, [r0, #64]
; CHECK-NEXT: vldrw.u32 q7, [r0, #128] ; CHECK-NEXT: vldrw.u32 q3, [r0, #128]
; CHECK-NEXT: vldrw.u32 q0, [r0, #144]
; CHECK-NEXT: vstrw.32 q2, [sp, #144] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q2, [r0, #16]
; CHECK-NEXT: vmov.f32 s4, s25
; CHECK-NEXT: vldrw.u32 q5, [r0] ; CHECK-NEXT: vldrw.u32 q5, [r0]
; CHECK-NEXT: vstrw.32 q2, [sp, #128] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q1, [sp, #48] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q2, [r0, #160] ; CHECK-NEXT: vldrw.u32 q1, [r0, #80]
; CHECK-NEXT: vmov.f32 s5, s29 ; CHECK-NEXT: vmov.f32 s8, s1
; CHECK-NEXT: vstrw.32 q0, [sp] @ 16-byte Spill
; CHECK-NEXT: vstrw.32 q2, [sp, #112] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q2, [r0, #96]
; CHECK-NEXT: vmov.f32 s7, s26
; CHECK-NEXT: vldrw.u32 q0, [r0, #48]
; CHECK-NEXT: vstrw.32 q2, [sp, #96] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q2, [r0, #32]
; CHECK-NEXT: vmov.f32 s6, s22
; CHECK-NEXT: vldrw.u32 q3, [r0, #112]
; CHECK-NEXT: vstrw.32 q2, [sp, #16] @ 16-byte Spill
; CHECK-NEXT: vmov.f64 d4, d15
; CHECK-NEXT: vldrw.u32 q4, [r0, #176] ; CHECK-NEXT: vldrw.u32 q4, [r0, #176]
; CHECK-NEXT: vmov.32 r0, q6[3] ; CHECK-NEXT: vstrw.32 q1, [sp, #144] @ 16-byte Spill
; CHECK-NEXT: vstrw.32 q1, [r1, #16] ; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
; CHECK-NEXT: vdup.32 q1, r0 ; CHECK-NEXT: vmov.f32 s9, s13
; CHECK-NEXT: vmov.32 r0, q3[3] ; CHECK-NEXT: vldrw.u32 q6, [r0, #112]
; CHECK-NEXT: vstrw.32 q0, [sp, #32] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q1, [sp, #128] @ 16-byte Spill
; CHECK-NEXT: vmov.f32 s9, s23 ; CHECK-NEXT: vldrw.u32 q1, [r0, #160]
; CHECK-NEXT: vmov.f32 s11, s31 ; CHECK-NEXT: vmov.f32 s11, s2
; CHECK-NEXT: vmov.f32 s10, s6 ; CHECK-NEXT: vldrw.u32 q7, [r0, #48]
; CHECK-NEXT: vstrw.32 q1, [sp, #112] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q1, [r0, #96]
; CHECK-NEXT: vmov.f32 s10, s22
; CHECK-NEXT: vstrw.32 q1, [sp, #96] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q1, [r0, #32]
; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: vstrw.32 q2, [r1, #16]
; CHECK-NEXT: vstrw.32 q1, [sp] @ 16-byte Spill
; CHECK-NEXT: vmov.f64 d2, d7
; CHECK-NEXT: vdup.32 q2, r0
; CHECK-NEXT: vmov.f32 s5, s23
; CHECK-NEXT: vmov.f32 s7, s15
; CHECK-NEXT: vmov.f32 s6, s10
; CHECK-NEXT: vstrw.32 q1, [r1, #32]
; CHECK-NEXT: vmov.f64 d2, d9 ; CHECK-NEXT: vmov.f64 d2, d9
; CHECK-NEXT: vstrw.32 q2, [r1, #32] ; CHECK-NEXT: vmov.f32 s5, s31
; CHECK-NEXT: vmov.f32 s5, s3
; CHECK-NEXT: vmov.f32 s7, s19 ; CHECK-NEXT: vmov.f32 s7, s19
; CHECK-NEXT: vmov r0, s27
; CHECK-NEXT: vmov q2, q1 ; CHECK-NEXT: vmov q2, q1
; CHECK-NEXT: vdup.32 q1, r0 ; CHECK-NEXT: vdup.32 q1, r0
; CHECK-NEXT: vmov r0, s12
; CHECK-NEXT: vmov.f32 s10, s6 ; CHECK-NEXT: vmov.f32 s10, s6
; CHECK-NEXT: vmov.32 r0, q7[0]
; CHECK-NEXT: vmov.f64 d2, d10 ; CHECK-NEXT: vmov.f64 d2, d10
; CHECK-NEXT: vstrw.32 q2, [sp, #80] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q2, [sp, #80] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q2, [sp, #32] @ 16-byte Reload ; CHECK-NEXT: vmov.f32 s5, s0
; CHECK-NEXT: vdup.32 q0, r0 ; CHECK-NEXT: vdup.32 q0, r0
; CHECK-NEXT: vmov.32 r0, q4[0]
; CHECK-NEXT: vmov.f32 s5, s24
; CHECK-NEXT: vmov.f32 s7, s21 ; CHECK-NEXT: vmov.f32 s7, s21
; CHECK-NEXT: vmov.f32 s6, s2 ; CHECK-NEXT: vmov.f32 s6, s2
; CHECK-NEXT: vmov.f64 d0, d4 ; CHECK-NEXT: vmov.f64 d0, d14
; CHECK-NEXT: vstrw.32 q1, [sp, #64] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q1, [sp, #64] @ 16-byte Spill
; CHECK-NEXT: vmov.f32 s1, s12 ; CHECK-NEXT: vmov.f32 s1, s24
; CHECK-NEXT: vmov.f32 s3, s9 ; CHECK-NEXT: vmov.f32 s3, s29
; CHECK-NEXT: vmov r0, s16
; CHECK-NEXT: vmov q1, q0 ; CHECK-NEXT: vmov q1, q0
; CHECK-NEXT: vdup.32 q0, r0 ; CHECK-NEXT: vdup.32 q0, r0
; CHECK-NEXT: vmov.f32 s16, s25
; CHECK-NEXT: vmov.f32 s6, s2 ; CHECK-NEXT: vmov.f32 s6, s2
; CHECK-NEXT: vldrw.u32 q0, [sp, #112] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q0, [sp, #112] @ 16-byte Reload
; CHECK-NEXT: vstrw.32 q1, [sp, #48] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q1, [sp, #32] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q1, [sp, #96] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q1, [sp, #96] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s16, s13 ; CHECK-NEXT: vmov.f32 s19, s26
; CHECK-NEXT: vmov.f32 s24, s5 ; CHECK-NEXT: vldrw.u32 q6, [sp, #144] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s25, s1 ; CHECK-NEXT: vmov.f32 s18, s30
; CHECK-NEXT: vmov.f32 s19, s14 ; CHECK-NEXT: vmov q2, q1
; CHECK-NEXT: vmov q3, q1 ; CHECK-NEXT: vmov.f32 s28, s5
; CHECK-NEXT: vmov.f32 s27, s6 ; CHECK-NEXT: vstrw.32 q4, [sp, #16] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q1, [sp, #16] @ 16-byte Reload ; CHECK-NEXT: vmov.f32 s29, s1
; CHECK-NEXT: vmov.f32 s18, s10 ; CHECK-NEXT: vmov.f32 s31, s6
; CHECK-NEXT: vmov.32 r0, q3[3] ; CHECK-NEXT: vldrw.u32 q1, [sp] @ 16-byte Reload
; CHECK-NEXT: vmov.f64 d4, d1 ; CHECK-NEXT: vmov.f64 d8, d1
; CHECK-NEXT: vstrw.32 q4, [sp, #32] @ 16-byte Spill
; CHECK-NEXT: vmov q5, q1 ; CHECK-NEXT: vmov q5, q1
; CHECK-NEXT: vldrw.u32 q4, [sp, #144] @ 16-byte Reload ; CHECK-NEXT: vmov r0, s11
; CHECK-NEXT: vmov.f32 s9, s7 ; CHECK-NEXT: vldrw.u32 q2, [sp, #48] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s11, s3 ; CHECK-NEXT: vmov.f32 s17, s7
; CHECK-NEXT: vdup.32 q0, r0 ; CHECK-NEXT: vmov.f32 s30, s6
; CHECK-NEXT: vmov.f32 s10, s2
; CHECK-NEXT: vldrw.u32 q0, [sp] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s26, s6
; CHECK-NEXT: vldrw.u32 q1, [sp, #128] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q1, [sp, #128] @ 16-byte Reload
; CHECK-NEXT: vmov.f64 d6, d1 ; CHECK-NEXT: vmov.f64 d6, d5
; CHECK-NEXT: vmov.32 r0, q4[3] ; CHECK-NEXT: vstrw.32 q7, [r1, #112]
; CHECK-NEXT: vmov q7, q0
; CHECK-NEXT: vstrw.32 q6, [r1, #112]
; CHECK-NEXT: vstrw.32 q2, [r1, #128]
; CHECK-NEXT: vmov.f32 s13, s7 ; CHECK-NEXT: vmov.f32 s13, s7
; CHECK-NEXT: vldrw.u32 q1, [sp, #96] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q1, [sp, #96] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s15, s3 ; CHECK-NEXT: vmov.f32 s19, s3
; CHECK-NEXT: vdup.32 q0, r0
; CHECK-NEXT: vmov r0, s27
; CHECK-NEXT: vmov.f32 s18, s2
; CHECK-NEXT: vdup.32 q0, r0 ; CHECK-NEXT: vdup.32 q0, r0
; CHECK-NEXT: vmov.f32 s15, s11
; CHECK-NEXT: vstrw.32 q4, [r1, #128]
; CHECK-NEXT: vmov.f32 s14, s2 ; CHECK-NEXT: vmov.f32 s14, s2
; CHECK-NEXT: vmov q0, q5 ; CHECK-NEXT: vmov q0, q5
; CHECK-NEXT: vmov.f32 s21, s4 ; CHECK-NEXT: vmov.f32 s21, s4
; CHECK-NEXT: vstrw.32 q3, [r1, #80] ; CHECK-NEXT: vstrw.32 q3, [r1, #80]
; CHECK-NEXT: vmov.f32 s23, s1 ; CHECK-NEXT: vmov.f32 s23, s1
; CHECK-NEXT: vldrw.u32 q0, [sp, #112] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q0, [sp, #112] @ 16-byte Reload
; CHECK-NEXT: vmov.32 r0, q0[0] ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vdup.32 q0, r0 ; CHECK-NEXT: vdup.32 q0, r0
; CHECK-NEXT: vmov.32 r0, q7[0] ; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vmov.f32 s22, s2 ; CHECK-NEXT: vmov.f32 s22, s2
; CHECK-NEXT: vldrw.u32 q0, [sp, #128] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q0, [sp, #128] @ 16-byte Reload
; CHECK-NEXT: vstrw.32 q5, [r1, #96] ; CHECK-NEXT: vstrw.32 q5, [r1, #96]
; CHECK-NEXT: vmov.f64 d2, d0 ; CHECK-NEXT: vmov.f64 d2, d0
; CHECK-NEXT: vmov.f32 s5, s16 ; CHECK-NEXT: vmov.f32 s5, s24
; CHECK-NEXT: vmov q4, q0 ; CHECK-NEXT: vmov q6, q0
; CHECK-NEXT: vmov.f32 s7, s1 ; CHECK-NEXT: vmov.f32 s7, s1
; CHECK-NEXT: vdup.32 q0, r0 ; CHECK-NEXT: vdup.32 q0, r0
; CHECK-NEXT: vmov.f32 s6, s2 ; CHECK-NEXT: vmov.f32 s6, s2
; CHECK-NEXT: vldrw.u32 q0, [sp, #144] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q0, [sp, #144] @ 16-byte Reload
; CHECK-NEXT: vstrw.32 q1, [r1, #48] ; CHECK-NEXT: vstrw.32 q1, [r1, #48]
; CHECK-NEXT: vmov.f32 s28, s1 ; CHECK-NEXT: vmov.f32 s8, s1
; CHECK-NEXT: vmov.f32 s31, s2 ; CHECK-NEXT: vmov.f32 s11, s2
; CHECK-NEXT: vldrw.u32 q0, [sp, #48] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s30, s18
; CHECK-NEXT: vstrw.32 q0, [r1, #144]
; CHECK-NEXT: vldrw.u32 q0, [sp, #32] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q0, [sp, #32] @ 16-byte Reload
; CHECK-NEXT: vstrw.32 q7, [r1, #64] ; CHECK-NEXT: vmov.f32 s10, s26
; CHECK-NEXT: vstrw.32 q0, [r1, #144]
; CHECK-NEXT: vldrw.u32 q0, [sp, #16] @ 16-byte Reload
; CHECK-NEXT: vstrw.32 q2, [r1, #64]
; CHECK-NEXT: vstrw.32 q0, [r1, #160] ; CHECK-NEXT: vstrw.32 q0, [r1, #160]
; CHECK-NEXT: vldrw.u32 q0, [sp, #80] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q0, [sp, #80] @ 16-byte Reload
; CHECK-NEXT: vstrw.32 q0, [r1, #176] ; CHECK-NEXT: vstrw.32 q0, [r1, #176]
; CHECK-NEXT: vldrw.u32 q0, [sp, #64] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q0, [sp, #64] @ 16-byte Reload
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: add sp, #160 ; CHECK-NEXT: add sp, #160
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
; CHECK-LABEL: vst3_v4i16: ; CHECK-LABEL: vst3_v4i16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9} ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vldrh.u32 q2, [r0, #16] ; CHECK-NEXT: vldrh.u32 q2, [r0, #16]
; CHECK-NEXT: vldrh.u32 q1, [r0] ; CHECK-NEXT: vldrh.u32 q1, [r0]
; CHECK-NEXT: vldrh.u32 q3, [r0, #8] ; CHECK-NEXT: vldrh.u32 q3, [r0, #8]
; CHECK-NEXT: vmov.f64 d0, d5 ; CHECK-NEXT: vmov.f64 d0, d5
; CHECK-NEXT: vmov.32 r0, q3[3]
; CHECK-NEXT: vdup.32 q4, r0
; CHECK-NEXT: vmov.f32 s1, s7 ; CHECK-NEXT: vmov.f32 s1, s7
; CHECK-NEXT: vmov r0, s15
; CHECK-NEXT: vdup.32 q4, r0
; CHECK-NEXT: vmov.f32 s3, s11 ; CHECK-NEXT: vmov.f32 s3, s11
; CHECK-NEXT: vmov r0, s4 ; CHECK-NEXT: vmov r0, s4
; CHECK-NEXT: vmov.f32 s2, s18 ; CHECK-NEXT: vmov.f32 s2, s18
; CHECK-NEXT: vmov.16 q4[0], r0 ; CHECK-NEXT: vmov.16 q4[0], r0
; CHECK-NEXT: vmov r0, s12 ; CHECK-NEXT: vmov r0, s12
; CHECK-NEXT: vstrh.32 q0, [r1, #16] ; CHECK-NEXT: vstrh.32 q0, [r1, #16]
; CHECK-NEXT: vmov.16 q4[1], r0 ; CHECK-NEXT: vmov.16 q4[1], r0
; CHECK-NEXT: vmov r0, s8 ; CHECK-NEXT: vmov r0, s8
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vmov.16 q3[0], r2 ; CHECK-NEXT: vmov.16 q3[0], r2
; CHECK-NEXT: vmov.u16 r0, q4[0] ; CHECK-NEXT: vmov.u16 r0, q4[0]
; CHECK-NEXT: vmov.16 q3[1], r0 ; CHECK-NEXT: vmov.16 q3[1], r0
; CHECK-NEXT: vmov.u16 r0, q4[1] ; CHECK-NEXT: vmov.u16 r0, q4[1]
; CHECK-NEXT: vmov.16 q3[4], r0 ; CHECK-NEXT: vmov.16 q3[4], r0
; CHECK-NEXT: vmov.u16 r0, q2[2] ; CHECK-NEXT: vmov.u16 r0, q2[2]
; CHECK-NEXT: vmov.16 q3[6], r0 ; CHECK-NEXT: vmov.16 q3[6], r0
; CHECK-NEXT: vmov.u16 r0, q4[2] ; CHECK-NEXT: vmov.u16 r0, q4[2]
; CHECK-NEXT: vmov.32 r2, q1[0] ; CHECK-NEXT: vmov r2, s4
; CHECK-NEXT: vmov.16 q3[7], r0 ; CHECK-NEXT: vmov.16 q3[7], r0
; CHECK-NEXT: vdup.32 q5, r2 ; CHECK-NEXT: vdup.32 q5, r2
; CHECK-NEXT: vmov.f32 s13, s8 ; CHECK-NEXT: vmov.f32 s13, s8
; CHECK-NEXT: vmov.u16 r2, q5[2] ; CHECK-NEXT: vmov.u16 r2, q5[2]
; CHECK-NEXT: vmov.u16 r0, q3[3] ; CHECK-NEXT: vmov.u16 r0, q3[3]
; CHECK-NEXT: vmov.16 q6[2], r2 ; CHECK-NEXT: vmov.16 q6[2], r2
; CHECK-NEXT: vmov.32 r2, q2[3] ; CHECK-NEXT: vmov r2, s11
; CHECK-NEXT: vmov.16 q6[3], r0 ; CHECK-NEXT: vmov.16 q6[3], r0
; CHECK-NEXT: vmov.u16 r0, q3[4] ; CHECK-NEXT: vmov.u16 r0, q3[4]
; CHECK-NEXT: vmov.16 q6[4], r0 ; CHECK-NEXT: vmov.16 q6[4], r0
; CHECK-NEXT: vmov.u16 r0, q5[5] ; CHECK-NEXT: vmov.u16 r0, q5[5]
; CHECK-NEXT: vmov.16 q6[5], r0 ; CHECK-NEXT: vmov.16 q6[5], r0
; CHECK-NEXT: vmov.u16 r0, q4[5] ; CHECK-NEXT: vmov.u16 r0, q4[5]
; CHECK-NEXT: vmov.16 q5[0], r0 ; CHECK-NEXT: vmov.16 q5[0], r0
; CHECK-NEXT: vmov.u16 r0, q1[5] ; CHECK-NEXT: vmov.u16 r0, q1[5]
▲ Show 20 Lines • Show All 70 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vmov.16 q2[6], r2 ; CHECK-NEXT: vmov.16 q2[6], r2
; CHECK-NEXT: vmov.u16 r2, q1[2] ; CHECK-NEXT: vmov.u16 r2, q1[2]
; CHECK-NEXT: vmov.16 q2[7], r2 ; CHECK-NEXT: vmov.16 q2[7], r2
; CHECK-NEXT: vmov q7, q1 ; CHECK-NEXT: vmov q7, q1
; CHECK-NEXT: vmov.f32 s9, s0 ; CHECK-NEXT: vmov.f32 s9, s0
; CHECK-NEXT: vldrw.u32 q0, [r0, #80] ; CHECK-NEXT: vldrw.u32 q0, [r0, #80]
; CHECK-NEXT: vmov.u16 r2, q2[3] ; CHECK-NEXT: vmov.u16 r2, q2[3]
; CHECK-NEXT: vmov q3, q2 ; CHECK-NEXT: vmov q3, q2
; CHECK-NEXT: vmov.32 r3, q0[0] ; CHECK-NEXT: vmov r3, s0
; CHECK-NEXT: vmov q1, q0 ; CHECK-NEXT: vmov q1, q0
; CHECK-NEXT: vdup.32 q0, r3 ; CHECK-NEXT: vdup.32 q0, r3
; CHECK-NEXT: vstrw.32 q2, [sp, #96] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q2, [sp, #96] @ 16-byte Spill
; CHECK-NEXT: vmov.u16 r3, q0[2] ; CHECK-NEXT: vmov.u16 r3, q0[2]
; CHECK-NEXT: vstrw.32 q7, [sp, #32] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q7, [sp, #32] @ 16-byte Spill
; CHECK-NEXT: vmov.16 q2[2], r3 ; CHECK-NEXT: vmov.16 q2[2], r3
; CHECK-NEXT: vmov.16 q2[3], r2 ; CHECK-NEXT: vmov.16 q2[3], r2
; CHECK-NEXT: vmov.u16 r2, q3[4] ; CHECK-NEXT: vmov.u16 r2, q3[4]
Show All 12 Lines
; CHECK-NEXT: vmov.16 q5[6], r2 ; CHECK-NEXT: vmov.16 q5[6], r2
; CHECK-NEXT: vmov.u16 r2, q0[7] ; CHECK-NEXT: vmov.u16 r2, q0[7]
; CHECK-NEXT: vmov.16 q5[7], r2 ; CHECK-NEXT: vmov.16 q5[7], r2
; CHECK-NEXT: vstrw.32 q0, [sp, #144] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q0, [sp, #144] @ 16-byte Spill
; CHECK-NEXT: vmov.f32 s22, s3 ; CHECK-NEXT: vmov.f32 s22, s3
; CHECK-NEXT: vldrw.u32 q0, [r0] ; CHECK-NEXT: vldrw.u32 q0, [r0]
; CHECK-NEXT: vstrw.32 q2, [sp, #112] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q2, [sp, #112] @ 16-byte Spill
; CHECK-NEXT: vmov.u16 r2, q5[3] ; CHECK-NEXT: vmov.u16 r2, q5[3]
; CHECK-NEXT: vmov.32 r0, q0[3] ; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: vmov q2, q0 ; CHECK-NEXT: vmov q2, q0
; CHECK-NEXT: vdup.32 q0, r0 ; CHECK-NEXT: vdup.32 q0, r0
; CHECK-NEXT: vstrw.32 q2, [sp, #48] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q2, [sp, #48] @ 16-byte Spill
; CHECK-NEXT: vmov.u16 r0, q0[2] ; CHECK-NEXT: vmov.u16 r0, q0[2]
; CHECK-NEXT: vmov.16 q4[2], r0 ; CHECK-NEXT: vmov.16 q4[2], r0
; CHECK-NEXT: vmov.u16 r0, q5[4] ; CHECK-NEXT: vmov.u16 r0, q5[4]
; CHECK-NEXT: vmov.16 q4[3], r2 ; CHECK-NEXT: vmov.16 q4[3], r2
; CHECK-NEXT: vmov.16 q4[4], r0 ; CHECK-NEXT: vmov.16 q4[4], r0
; CHECK-NEXT: vmov.u16 r0, q0[5] ; CHECK-NEXT: vmov.u16 r0, q0[5]
; CHECK-NEXT: vmov.16 q4[5], r0 ; CHECK-NEXT: vmov.16 q4[5], r0
; CHECK-NEXT: vmov.u16 r0, q2[0] ; CHECK-NEXT: vmov.u16 r0, q2[0]
; CHECK-NEXT: vmov.16 q6[0], r0 ; CHECK-NEXT: vmov.16 q6[0], r0
; CHECK-NEXT: vmov.u16 r0, q3[0] ; CHECK-NEXT: vmov.u16 r0, q3[0]
; CHECK-NEXT: vldrw.u32 q0, [sp, #144] @ 16-byte Reload
; CHECK-NEXT: vmov.16 q6[1], r0 ; CHECK-NEXT: vmov.16 q6[1], r0
; CHECK-NEXT: vmov.u16 r0, q3[1] ; CHECK-NEXT: vmov.u16 r0, q3[1]
; CHECK-NEXT: vldrw.u32 q0, [sp, #144] @ 16-byte Reload ; CHECK-NEXT: vstrw.32 q4, [sp, #80] @ 16-byte Spill
; CHECK-NEXT: vmov.16 q6[4], r0 ; CHECK-NEXT: vmov.16 q6[4], r0
; CHECK-NEXT: vmov.u16 r0, q2[2] ; CHECK-NEXT: vmov.u16 r0, q2[2]
; CHECK-NEXT: vstrw.32 q4, [sp, #80] @ 16-byte Spill ; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: vmov.32 r2, q0[0]
; CHECK-NEXT: vmov.16 q6[6], r0 ; CHECK-NEXT: vmov.16 q6[6], r0
; CHECK-NEXT: vmov.u16 r0, q3[2] ; CHECK-NEXT: vmov.u16 r0, q3[2]
; CHECK-NEXT: vdup.32 q0, r2 ; CHECK-NEXT: vdup.32 q0, r2
; CHECK-NEXT: vmov.16 q6[7], r0 ; CHECK-NEXT: vmov.16 q6[7], r0
; CHECK-NEXT: vmov.u16 r2, q0[2] ; CHECK-NEXT: vmov.u16 r2, q0[2]
; CHECK-NEXT: vmov.f32 s25, s8 ; CHECK-NEXT: vmov.f32 s25, s8
; CHECK-NEXT: vmov.16 q2[2], r2 ; CHECK-NEXT: vmov.16 q2[2], r2
; CHECK-NEXT: vmov.u16 r0, q6[3] ; CHECK-NEXT: vmov.u16 r0, q6[3]
Show All 11 Lines
; CHECK-NEXT: vmov.16 q0[3], r0 ; CHECK-NEXT: vmov.16 q0[3], r0
; CHECK-NEXT: vmov.u16 r0, q7[7] ; CHECK-NEXT: vmov.u16 r0, q7[7]
; CHECK-NEXT: vmov.16 q0[6], r0 ; CHECK-NEXT: vmov.16 q0[6], r0
; CHECK-NEXT: vmov.u16 r0, q1[7] ; CHECK-NEXT: vmov.u16 r0, q1[7]
; CHECK-NEXT: vldrw.u32 q1, [sp, #128] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q1, [sp, #128] @ 16-byte Reload
; CHECK-NEXT: vmov.16 q0[7], r0 ; CHECK-NEXT: vmov.16 q0[7], r0
; CHECK-NEXT: vmov.f32 s2, s19 ; CHECK-NEXT: vmov.f32 s2, s19
; CHECK-NEXT: vstrw.32 q2, [sp, #64] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q2, [sp, #64] @ 16-byte Spill
; CHECK-NEXT: vmov.32 r2, q1[3] ; CHECK-NEXT: vmov r2, s7
; CHECK-NEXT: vmov.u16 r0, q0[3] ; CHECK-NEXT: vmov.u16 r0, q0[3]
; CHECK-NEXT: vdup.32 q7, r2 ; CHECK-NEXT: vdup.32 q7, r2
; CHECK-NEXT: vrev32.16 q3, q3 ; CHECK-NEXT: vrev32.16 q3, q3
; CHECK-NEXT: vmov.u16 r2, q7[2] ; CHECK-NEXT: vmov.u16 r2, q7[2]
; CHECK-NEXT: vstrw.32 q3, [sp] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q3, [sp] @ 16-byte Spill
; CHECK-NEXT: vmov.16 q2[2], r2 ; CHECK-NEXT: vmov.16 q2[2], r2
; CHECK-NEXT: vstrw.32 q4, [sp, #16] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q4, [sp, #16] @ 16-byte Spill
; CHECK-NEXT: vmov.16 q2[3], r0 ; CHECK-NEXT: vmov.16 q2[3], r0
▲ Show 20 Lines • Show All 201 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vmov.16 q0[0], r2 ; CHECK-NEXT: vmov.16 q0[0], r2
; CHECK-NEXT: vmov.u16 r2, q2[5] ; CHECK-NEXT: vmov.u16 r2, q2[5]
; CHECK-NEXT: vmov.16 q0[1], r2 ; CHECK-NEXT: vmov.16 q0[1], r2
; CHECK-NEXT: vmov.u16 r2, q1[6] ; CHECK-NEXT: vmov.u16 r2, q1[6]
; CHECK-NEXT: vmov.16 q0[3], r2 ; CHECK-NEXT: vmov.16 q0[3], r2
; CHECK-NEXT: vmov.u16 r2, q1[7] ; CHECK-NEXT: vmov.u16 r2, q1[7]
; CHECK-NEXT: vmov.16 q0[6], r2 ; CHECK-NEXT: vmov.16 q0[6], r2
; CHECK-NEXT: vmov.u16 r2, q2[7] ; CHECK-NEXT: vmov.u16 r2, q2[7]
; CHECK-NEXT: vmov.32 r0, q3[3] ; CHECK-NEXT: vmov r0, s15
; CHECK-NEXT: vmov.16 q0[7], r2 ; CHECK-NEXT: vmov.16 q0[7], r2
; CHECK-NEXT: vdup.32 q4, r0 ; CHECK-NEXT: vdup.32 q4, r0
; CHECK-NEXT: vmov.f32 s2, s11 ; CHECK-NEXT: vmov.f32 s2, s11
; CHECK-NEXT: vmov.u16 r0, q4[2] ; CHECK-NEXT: vmov.u16 r0, q4[2]
; CHECK-NEXT: vmov.u16 r2, q0[3] ; CHECK-NEXT: vmov.u16 r2, q0[3]
; CHECK-NEXT: vmov.16 q5[2], r0 ; CHECK-NEXT: vmov.16 q5[2], r0
; CHECK-NEXT: vmov.u16 r0, q0[4] ; CHECK-NEXT: vmov.u16 r0, q0[4]
; CHECK-NEXT: vmov.16 q5[3], r2 ; CHECK-NEXT: vmov.16 q5[3], r2
▲ Show 20 Lines • Show All 385 Lines • ▼ Show 20 Linesentry:
%s = shufflevector <4 x float> %t1, <4 x float> %t2, <6 x i32> <i32 0, i32 2, i32 4, i32 1, i32 3, i32 5> %s = shufflevector <4 x float> %t1, <4 x float> %t2, <6 x i32> <i32 0, i32 2, i32 4, i32 1, i32 3, i32 5>
store <6 x float> %s, <6 x float> *%dst store <6 x float> %s, <6 x float> *%dst
ret void ret void
} }
define void @vst3_v4f32(<4 x float> *%src, <12 x float> *%dst) { define void @vst3_v4f32(<4 x float> *%src, <12 x float> *%dst) {
; CHECK-LABEL: vst3_v4f32: ; CHECK-LABEL: vst3_v4f32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9, d10, d11} ; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vldrw.u32 q4, [r0] ; CHECK-NEXT: vldrw.u32 q3, [r0]
; CHECK-NEXT: vldrw.u32 q2, [r0, #16] ; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
; CHECK-NEXT: vldrw.u32 q0, [r0, #32] ; CHECK-NEXT: vldrw.u32 q0, [r0, #32]
; CHECK-NEXT: vmov.f32 s4, s9 ; CHECK-NEXT: vmov.f64 d8, d6
; CHECK-NEXT: vmov.f64 d6, d8 ; CHECK-NEXT: vmov.f32 s17, s4
; CHECK-NEXT: vmov.32 r0, q0[0] ; CHECK-NEXT: vmov.f32 s8, s5
; CHECK-NEXT: vdup.32 q5, r0 ; CHECK-NEXT: vmov.f32 s19, s13
; CHECK-NEXT: vmov.32 r0, q2[3] ; CHECK-NEXT: vmov.f32 s9, s1
; CHECK-NEXT: vmov.f32 s5, s1 ; CHECK-NEXT: vmov.f32 s18, s0
; CHECK-NEXT: vmov.f32 s13, s8
; CHECK-NEXT: vmov.f32 s0, s2 ; CHECK-NEXT: vmov.f32 s0, s2
; CHECK-NEXT: vmov.f32 s7, s10 ; CHECK-NEXT: vstrw.32 q4, [r1]
; CHECK-NEXT: vdup.32 q2, r0 ; CHECK-NEXT: vmov.f32 s11, s6
; CHECK-NEXT: vmov.f32 s15, s17 ; CHECK-NEXT: vmov.f32 s1, s15
; CHECK-NEXT: vmov.f32 s1, s19 ; CHECK-NEXT: vmov.f32 s10, s14
; CHECK-NEXT: vmov.f32 s6, s18 ; CHECK-NEXT: vmov.f32 s2, s7
; CHECK-NEXT: vmov.f32 s14, s22 ; CHECK-NEXT: vstrw.32 q2, [r1, #16]
; CHECK-NEXT: vstrw.32 q1, [r1, #16]
; CHECK-NEXT: vmov.f32 s2, s10
; CHECK-NEXT: vstrw.32 q3, [r1]
; CHECK-NEXT: vstrw.32 q0, [r1, #32] ; CHECK-NEXT: vstrw.32 q0, [r1, #32]
; CHECK-NEXT: vpop {d8, d9, d10, d11} ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <4 x float>, <4 x float>* %src, i32 0 %s1 = getelementptr <4 x float>, <4 x float>* %src, i32 0
%l1 = load <4 x float>, <4 x float>* %s1, align 4 %l1 = load <4 x float>, <4 x float>* %s1, align 4
%s2 = getelementptr <4 x float>, <4 x float>* %src, i32 1 %s2 = getelementptr <4 x float>, <4 x float>* %src, i32 1
%l2 = load <4 x float>, <4 x float>* %s2, align 4 %l2 = load <4 x float>, <4 x float>* %s2, align 4
%s3 = getelementptr <4 x float>, <4 x float>* %src, i32 2 %s3 = getelementptr <4 x float>, <4 x float>* %src, i32 2
%l3 = load <4 x float>, <4 x float>* %s3, align 4 %l3 = load <4 x float>, <4 x float>* %s3, align 4
%t1 = shufflevector <4 x float> %l1, <4 x float> %l2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %t1 = shufflevector <4 x float> %l1, <4 x float> %l2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%t2 = shufflevector <4 x float> %l3, <4 x float> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef> %t2 = shufflevector <4 x float> %l3, <4 x float> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
%s = shufflevector <8 x float> %t1, <8 x float> %t2, <12 x i32> <i32 0, i32 4, i32 8, i32 1, i32 5, i32 9, i32 2, i32 6, i32 10, i32 3, i32 7, i32 11> %s = shufflevector <8 x float> %t1, <8 x float> %t2, <12 x i32> <i32 0, i32 4, i32 8, i32 1, i32 5, i32 9, i32 2, i32 6, i32 10, i32 3, i32 7, i32 11>
store <12 x float> %s, <12 x float> *%dst store <12 x float> %s, <12 x float> *%dst
ret void ret void
} }
define void @vst3_v8f32(<8 x float> *%src, <24 x float> *%dst) { define void @vst3_v8f32(<8 x float> *%src, <24 x float> *%dst) {
; CHECK-LABEL: vst3_v8f32: ; CHECK-LABEL: vst3_v8f32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: .pad #48 ; CHECK-NEXT: .pad #16
; CHECK-NEXT: sub sp, #48 ; CHECK-NEXT: sub sp, #16
; CHECK-NEXT: vldrw.u32 q0, [r0, #80]
; CHECK-NEXT: vldrw.u32 q5, [r0, #16]
; CHECK-NEXT: vldrw.u32 q1, [r0, #48]
; CHECK-NEXT: vldrw.u32 q4, [r0] ; CHECK-NEXT: vldrw.u32 q4, [r0]
; CHECK-NEXT: vmov.f64 d6, d1 ; CHECK-NEXT: vldrw.u32 q7, [r0, #32]
; CHECK-NEXT: vldrw.u32 q6, [r0, #32] ; CHECK-NEXT: vldrw.u32 q6, [r0, #16]
; CHECK-NEXT: vmov.32 r2, q1[3] ; CHECK-NEXT: vldrw.u32 q0, [r0, #80]
; CHECK-NEXT: vldrw.u32 q7, [r0, #64] ; CHECK-NEXT: vmov.f64 d10, d8
; CHECK-NEXT: vdup.32 q2, r2 ; CHECK-NEXT: vldrw.u32 q3, [r0, #48]
; CHECK-NEXT: vstrw.32 q4, [sp, #32] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q7, [sp] @ 16-byte Spill
; CHECK-NEXT: vstrw.32 q5, [sp] @ 16-byte Spill ; CHECK-NEXT: vldrw.u32 q1, [r0, #64]
; CHECK-NEXT: vmov.32 r0, q7[0] ; CHECK-NEXT: vmov.f32 s21, s28
; CHECK-NEXT: vmov.f32 s13, s23 ; CHECK-NEXT: vmov.f64 d14, d12
; CHECK-NEXT: vstrw.32 q6, [sp, #16] @ 16-byte Spill ; CHECK-NEXT: vmov.f64 d4, d1
; CHECK-NEXT: vmov.f32 s15, s3 ; CHECK-NEXT: vmov.f32 s29, s12
; CHECK-NEXT: vmov.f32 s14, s10 ; CHECK-NEXT: vmov.f32 s9, s27
; CHECK-NEXT: vmov.f64 d4, d8 ; CHECK-NEXT: vmov.f32 s31, s25
; CHECK-NEXT: vstrw.32 q3, [r1, #80] ; CHECK-NEXT: vmov.f32 s11, s3
; CHECK-NEXT: vmov.f32 s9, s24 ; CHECK-NEXT: vmov.f32 s30, s0
; CHECK-NEXT: vmov.f32 s11, s17 ; CHECK-NEXT: vmov.f32 s0, s13
; CHECK-NEXT: vmov q4, q5 ; CHECK-NEXT: vstrw.32 q7, [r1, #48]
; CHECK-NEXT: vmov.f32 s21, s4 ; CHECK-NEXT: vmov.f32 s3, s14
; CHECK-NEXT: vmov.f32 s23, s17 ; CHECK-NEXT: vmov.f32 s2, s26
; CHECK-NEXT: vdup.32 q4, r0 ; CHECK-NEXT: vldrw.u32 q6, [sp] @ 16-byte Reload
; CHECK-NEXT: vmov.32 r0, q0[0] ; CHECK-NEXT: vmov.f32 s10, s15
; CHECK-NEXT: vmov.f32 s0, s5
; CHECK-NEXT: vmov.f32 s10, s18
; CHECK-NEXT: vldrw.u32 q4, [sp, #16] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s3, s6
; CHECK-NEXT: vldrw.u32 q1, [sp] @ 16-byte Reload
; CHECK-NEXT: vdup.32 q6, r0
; CHECK-NEXT: vmov.32 r0, q4[3]
; CHECK-NEXT: vmov.f32 s22, s26
; CHECK-NEXT: vldrw.u32 q6, [sp, #32] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s2, s6
; CHECK-NEXT: vstrw.32 q5, [r1, #48]
; CHECK-NEXT: vmov.f32 s4, s17
; CHECK-NEXT: vstrw.32 q0, [r1, #64] ; CHECK-NEXT: vstrw.32 q0, [r1, #64]
; CHECK-NEXT: vmov.f32 s5, s29 ; CHECK-NEXT: vmov.f32 s23, s17
; CHECK-NEXT: vstrw.32 q2, [r1] ; CHECK-NEXT: vstrw.32 q2, [r1, #80]
; CHECK-NEXT: vmov.f32 s28, s30 ; CHECK-NEXT: vmov.f32 s12, s25
; CHECK-NEXT: vmov.f32 s7, s18 ; CHECK-NEXT: vmov.f32 s13, s5
; CHECK-NEXT: vdup.32 q4, r0 ; CHECK-NEXT: vmov.f32 s22, s4
; CHECK-NEXT: vmov.f32 s29, s27 ; CHECK-NEXT: vmov.f32 s4, s6
; CHECK-NEXT: vmov.f32 s6, s26 ; CHECK-NEXT: vstrw.32 q5, [r1]
; CHECK-NEXT: vmov.f32 s30, s18 ; CHECK-NEXT: vmov.f32 s15, s26
; CHECK-NEXT: vstrw.32 q1, [r1, #16] ; CHECK-NEXT: vmov.f32 s5, s19
; CHECK-NEXT: vstrw.32 q7, [r1, #32] ; CHECK-NEXT: vmov.f32 s14, s18
; CHECK-NEXT: add sp, #48 ; CHECK-NEXT: vmov.f32 s6, s27
; CHECK-NEXT: vstrw.32 q3, [r1, #16]
; CHECK-NEXT: vstrw.32 q1, [r1, #32]
; CHECK-NEXT: add sp, #16
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <8 x float>, <8 x float>* %src, i32 0 %s1 = getelementptr <8 x float>, <8 x float>* %src, i32 0
%l1 = load <8 x float>, <8 x float>* %s1, align 4 %l1 = load <8 x float>, <8 x float>* %s1, align 4
%s2 = getelementptr <8 x float>, <8 x float>* %src, i32 1 %s2 = getelementptr <8 x float>, <8 x float>* %src, i32 1
%l2 = load <8 x float>, <8 x float>* %s2, align 4 %l2 = load <8 x float>, <8 x float>* %s2, align 4
%s3 = getelementptr <8 x float>, <8 x float>* %src, i32 2 %s3 = getelementptr <8 x float>, <8 x float>* %src, i32 2
%l3 = load <8 x float>, <8 x float>* %s3, align 4 %l3 = load <8 x float>, <8 x float>* %s3, align 4
%t1 = shufflevector <8 x float> %l1, <8 x float> %l2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %t1 = shufflevector <8 x float> %l1, <8 x float> %l2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
%t2 = shufflevector <8 x float> %l3, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> %t2 = shufflevector <8 x float> %l3, <8 x float> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%s = shufflevector <16 x float> %t1, <16 x float> %t2, <24 x i32> <i32 0, i32 8, i32 16, i32 1, i32 9, i32 17, i32 2, i32 10, i32 18, i32 3, i32 11, i32 19, i32 4, i32 12, i32 20, i32 5, i32 13, i32 21, i32 6, i32 14, i32 22, i32 7, i32 15, i32 23> %s = shufflevector <16 x float> %t1, <16 x float> %t2, <24 x i32> <i32 0, i32 8, i32 16, i32 1, i32 9, i32 17, i32 2, i32 10, i32 18, i32 3, i32 11, i32 19, i32 4, i32 12, i32 20, i32 5, i32 13, i32 21, i32 6, i32 14, i32 22, i32 7, i32 15, i32 23>
store <24 x float> %s, <24 x float> *%dst store <24 x float> %s, <24 x float> *%dst
ret void ret void
} }
define void @vst3_v16f32(<16 x float> *%src, <48 x float> *%dst) { define void @vst3_v16f32(<16 x float> *%src, <48 x float> *%dst) {
; CHECK-LABEL: vst3_v16f32: ; CHECK-LABEL: vst3_v16f32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: .pad #160 ; CHECK-NEXT: .pad #160
; CHECK-NEXT: sub sp, #160 ; CHECK-NEXT: sub sp, #160
; CHECK-NEXT: vldrw.u32 q2, [r0, #80] ; CHECK-NEXT: vldrw.u32 q5, [r0, #96]
; CHECK-NEXT: vldrw.u32 q6, [r0, #64] ; CHECK-NEXT: vldrw.u32 q0, [r0, #64]
; CHECK-NEXT: vldrw.u32 q7, [r0, #128] ; CHECK-NEXT: vldrw.u32 q1, [r0, #128]
; CHECK-NEXT: vldrw.u32 q0, [r0, #144] ; CHECK-NEXT: vldrw.u32 q6, [r0]
; CHECK-NEXT: vstrw.32 q2, [sp, #144] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q5, [sp, #112] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q2, [r0, #16] ; CHECK-NEXT: vldrw.u32 q5, [r0, #80]
; CHECK-NEXT: vmov.f32 s4, s25 ; CHECK-NEXT: vmov.f32 s16, s1
; CHECK-NEXT: vldrw.u32 q5, [r0] ; CHECK-NEXT: vldrw.u32 q3, [r0, #160]
; CHECK-NEXT: vstrw.32 q2, [sp, #128] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q5, [sp, #144] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q2, [r0, #160] ; CHECK-NEXT: vldrw.u32 q5, [r0, #48]
; CHECK-NEXT: vmov.f32 s5, s29 ; CHECK-NEXT: vmov.f32 s17, s5
; CHECK-NEXT: vstrw.32 q0, [sp] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q3, [sp, #128] @ 16-byte Spill
; CHECK-NEXT: vstrw.32 q2, [sp, #112] @ 16-byte Spill ; CHECK-NEXT: vmov.f32 s19, s2
; CHECK-NEXT: vldrw.u32 q2, [r0, #96] ; CHECK-NEXT: vstrw.32 q5, [sp, #32] @ 16-byte Spill
; CHECK-NEXT: vmov.f32 s7, s26 ; CHECK-NEXT: vldrw.u32 q5, [r0, #32]
; CHECK-NEXT: vldrw.u32 q0, [r0, #48] ; CHECK-NEXT: vmov.f32 s18, s26
; CHECK-NEXT: vstrw.32 q2, [sp, #96] @ 16-byte Spill ; CHECK-NEXT: vldrw.u32 q7, [r0, #144]
; CHECK-NEXT: vldrw.u32 q2, [r0, #32] ; CHECK-NEXT: vldrw.u32 q2, [r0, #176]
; CHECK-NEXT: vmov.f32 s6, s22 ; CHECK-NEXT: vstrw.32 q5, [sp, #16] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q5, [r0, #16]
; CHECK-NEXT: vldrw.u32 q3, [r0, #112] ; CHECK-NEXT: vldrw.u32 q3, [r0, #112]
; CHECK-NEXT: vstrw.32 q2, [sp, #16] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q4, [r1, #16]
; CHECK-NEXT: vmov.f64 d4, d15 ; CHECK-NEXT: vmov.f64 d8, d3
; CHECK-NEXT: vldrw.u32 q4, [r0, #176] ; CHECK-NEXT: vstrw.32 q5, [sp, #48] @ 16-byte Spill
; CHECK-NEXT: vmov.32 r0, q6[3] ; CHECK-NEXT: vldrw.u32 q5, [sp, #32] @ 16-byte Reload
; CHECK-NEXT: vstrw.32 q1, [r1, #16] ; CHECK-NEXT: vstrw.32 q7, [sp] @ 16-byte Spill
; CHECK-NEXT: vdup.32 q1, r0 ; CHECK-NEXT: vmov.f32 s17, s27
; CHECK-NEXT: vmov.32 r0, q3[3] ; CHECK-NEXT: vmov.f32 s19, s7
; CHECK-NEXT: vstrw.32 q0, [sp, #32] @ 16-byte Spill ; CHECK-NEXT: vmov.f32 s18, s3
; CHECK-NEXT: vmov.f32 s9, s23 ; CHECK-NEXT: vstrw.32 q4, [r1, #32]
; CHECK-NEXT: vmov.f32 s11, s31 ; CHECK-NEXT: vmov.f64 d8, d5
; CHECK-NEXT: vmov.f32 s17, s23
; CHECK-NEXT: vmov.f32 s19, s11
; CHECK-NEXT: vmov.f32 s18, s15
; CHECK-NEXT: vstrw.32 q4, [sp, #96] @ 16-byte Spill
; CHECK-NEXT: vmov.f64 d8, d12
; CHECK-NEXT: vmov.f32 s17, s0
; CHECK-NEXT: vmov.f32 s19, s25
; CHECK-NEXT: vmov.f32 s18, s4
; CHECK-NEXT: vmov q1, q5
; CHECK-NEXT: vmov.f64 d0, d2
; CHECK-NEXT: vstrw.32 q4, [sp, #80] @ 16-byte Spill
; CHECK-NEXT: vmov.f32 s1, s12
; CHECK-NEXT: vmov.f32 s3, s5
; CHECK-NEXT: vmov.f32 s2, s8
; CHECK-NEXT: vmov.f32 s8, s13
; CHECK-NEXT: vstrw.32 q0, [sp, #64] @ 16-byte Spill
; CHECK-NEXT: vmov.f32 s11, s14
; CHECK-NEXT: vldrw.u32 q0, [sp, #128] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s10, s6 ; CHECK-NEXT: vmov.f32 s10, s6
; CHECK-NEXT: vmov.f64 d2, d9 ; CHECK-NEXT: vldrw.u32 q1, [sp, #112] @ 16-byte Reload
; CHECK-NEXT: vstrw.32 q2, [r1, #32] ; CHECK-NEXT: vstrw.32 q2, [sp, #32] @ 16-byte Spill
; CHECK-NEXT: vmov.f32 s5, s3 ; CHECK-NEXT: vmov.f64 d8, d1
; CHECK-NEXT: vmov.f32 s7, s19
; CHECK-NEXT: vmov q2, q1 ; CHECK-NEXT: vmov q2, q1
; CHECK-NEXT: vdup.32 q1, r0 ; CHECK-NEXT: vmov.f32 s20, s5
; CHECK-NEXT: vmov.f32 s10, s6 ; CHECK-NEXT: vmov.f32 s21, s1
; CHECK-NEXT: vmov.32 r0, q7[0] ; CHECK-NEXT: vmov.f32 s23, s6
; CHECK-NEXT: vmov.f64 d2, d10
; CHECK-NEXT: vstrw.32 q2, [sp, #80] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q2, [sp, #32] @ 16-byte Reload
; CHECK-NEXT: vdup.32 q0, r0
; CHECK-NEXT: vmov.32 r0, q4[0]
; CHECK-NEXT: vmov.f32 s5, s24
; CHECK-NEXT: vmov.f32 s7, s21
; CHECK-NEXT: vmov.f32 s6, s2
; CHECK-NEXT: vmov.f64 d0, d4
; CHECK-NEXT: vstrw.32 q1, [sp, #64] @ 16-byte Spill
; CHECK-NEXT: vmov.f32 s1, s12
; CHECK-NEXT: vmov.f32 s3, s9
; CHECK-NEXT: vmov q1, q0
; CHECK-NEXT: vdup.32 q0, r0
; CHECK-NEXT: vmov.f32 s6, s2
; CHECK-NEXT: vldrw.u32 q0, [sp, #112] @ 16-byte Reload
; CHECK-NEXT: vstrw.32 q1, [sp, #48] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q1, [sp, #96] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s16, s13
; CHECK-NEXT: vmov.f32 s24, s5
; CHECK-NEXT: vmov.f32 s25, s1
; CHECK-NEXT: vmov.f32 s19, s14
; CHECK-NEXT: vmov q3, q1
; CHECK-NEXT: vmov.f32 s27, s6
; CHECK-NEXT: vldrw.u32 q1, [sp, #16] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q1, [sp, #16] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s18, s10 ; CHECK-NEXT: vmov.f64 d6, d15
; CHECK-NEXT: vmov.32 r0, q3[3] ; CHECK-NEXT: vmov q6, q1
; CHECK-NEXT: vmov.f64 d4, d1 ; CHECK-NEXT: vmov.f32 s17, s7
; CHECK-NEXT: vstrw.32 q4, [sp, #32] @ 16-byte Spill ; CHECK-NEXT: vmov.f32 s22, s6
; CHECK-NEXT: vmov q5, q1 ; CHECK-NEXT: vldrw.u32 q1, [sp, #48] @ 16-byte Reload
; CHECK-NEXT: vldrw.u32 q4, [sp, #144] @ 16-byte Reload ; CHECK-NEXT: vmov.f32 s19, s3
; CHECK-NEXT: vmov.f32 s9, s7 ; CHECK-NEXT: vmov q0, q6
; CHECK-NEXT: vmov.f32 s11, s3
; CHECK-NEXT: vdup.32 q0, r0
; CHECK-NEXT: vmov.f32 s10, s2
; CHECK-NEXT: vldrw.u32 q0, [sp] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s26, s6
; CHECK-NEXT: vldrw.u32 q1, [sp, #128] @ 16-byte Reload
; CHECK-NEXT: vmov.f64 d6, d1
; CHECK-NEXT: vmov.32 r0, q4[3]
; CHECK-NEXT: vmov q7, q0
; CHECK-NEXT: vstrw.32 q6, [r1, #112]
; CHECK-NEXT: vstrw.32 q2, [r1, #128]
; CHECK-NEXT: vmov.f32 s13, s7 ; CHECK-NEXT: vmov.f32 s13, s7
; CHECK-NEXT: vldrw.u32 q1, [sp, #96] @ 16-byte Reload ; CHECK-NEXT: vstrw.32 q5, [r1, #112]
; CHECK-NEXT: vmov.f32 s15, s3 ; CHECK-NEXT: vmov.f32 s15, s31
; CHECK-NEXT: vdup.32 q0, r0 ; CHECK-NEXT: vldrw.u32 q7, [sp, #112] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s14, s2 ; CHECK-NEXT: vmov.f32 s18, s11
; CHECK-NEXT: vmov q0, q5 ; CHECK-NEXT: vldrw.u32 q2, [sp, #144] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s21, s4 ; CHECK-NEXT: vmov.f32 s25, s28
; CHECK-NEXT: vstrw.32 q3, [r1, #80] ; CHECK-NEXT: vldrw.u32 q7, [sp] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s23, s1 ; CHECK-NEXT: vmov.f32 s27, s1
; CHECK-NEXT: vldrw.u32 q0, [sp, #112] @ 16-byte Reload
; CHECK-NEXT: vmov.32 r0, q0[0]
; CHECK-NEXT: vdup.32 q0, r0
; CHECK-NEXT: vmov.32 r0, q7[0]
; CHECK-NEXT: vmov.f32 s22, s2
; CHECK-NEXT: vldrw.u32 q0, [sp, #128] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q0, [sp, #128] @ 16-byte Reload
; CHECK-NEXT: vstrw.32 q5, [r1, #96] ; CHECK-NEXT: vmov.f32 s14, s11
; CHECK-NEXT: vmov.f64 d2, d0 ; CHECK-NEXT: vstrw.32 q4, [r1, #128]
; CHECK-NEXT: vmov.f32 s5, s16 ; CHECK-NEXT: vmov.f32 s26, s0
; CHECK-NEXT: vmov q4, q0 ; CHECK-NEXT: vstrw.32 q3, [r1, #80]
; CHECK-NEXT: vmov.f32 s7, s1 ; CHECK-NEXT: vmov.f64 d0, d2
; CHECK-NEXT: vdup.32 q0, r0 ; CHECK-NEXT: vstrw.32 q6, [r1, #96]
; CHECK-NEXT: vmov.f32 s6, s2 ; CHECK-NEXT: vmov.f32 s1, s8
; CHECK-NEXT: vldrw.u32 q0, [sp, #144] @ 16-byte Reload ; CHECK-NEXT: vmov q2, q1
; CHECK-NEXT: vstrw.32 q1, [r1, #48] ; CHECK-NEXT: vmov.f32 s3, s5
; CHECK-NEXT: vmov.f32 s28, s1 ; CHECK-NEXT: vldrw.u32 q1, [sp, #144] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s31, s2 ; CHECK-NEXT: vmov.f32 s2, s28
; CHECK-NEXT: vldrw.u32 q0, [sp, #48] @ 16-byte Reload ; CHECK-NEXT: vstrw.32 q0, [r1, #48]
; CHECK-NEXT: vmov.f32 s30, s18 ; CHECK-NEXT: vldrw.u32 q0, [sp, #64] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s28, s5
; CHECK-NEXT: vstrw.32 q0, [r1, #144] ; CHECK-NEXT: vstrw.32 q0, [r1, #144]
; CHECK-NEXT: vldrw.u32 q0, [sp, #32] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q0, [sp, #32] @ 16-byte Reload
; CHECK-NEXT: vstrw.32 q7, [r1, #64] ; CHECK-NEXT: vmov.f32 s31, s6
; CHECK-NEXT: vstrw.32 q0, [r1, #160] ; CHECK-NEXT: vstrw.32 q0, [r1, #160]
; CHECK-NEXT: vldrw.u32 q0, [sp, #80] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q0, [sp, #96] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s30, s10
; CHECK-NEXT: vstrw.32 q0, [r1, #176] ; CHECK-NEXT: vstrw.32 q0, [r1, #176]
; CHECK-NEXT: vldrw.u32 q0, [sp, #64] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q0, [sp, #80] @ 16-byte Reload
; CHECK-NEXT: vstrw.32 q7, [r1, #64]
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: add sp, #160 ; CHECK-NEXT: add sp, #160
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s1 = getelementptr <16 x float>, <16 x float>* %src, i32 0 %s1 = getelementptr <16 x float>, <16 x float>* %src, i32 0
%l1 = load <16 x float>, <16 x float>* %s1, align 4 %l1 = load <16 x float>, <16 x float>* %s1, align 4
%s2 = getelementptr <16 x float>, <16 x float>* %src, i32 1 %s2 = getelementptr <16 x float>, <16 x float>* %src, i32 1
▲ Show 20 Lines • Show All 122 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vldrw.u32 q1, [r0, #16] ; CHECK-NEXT: vldrw.u32 q1, [r0, #16]
; CHECK-NEXT: vldrw.u32 q5, [r0, #32] ; CHECK-NEXT: vldrw.u32 q5, [r0, #32]
; CHECK-NEXT: vmov r3, s8 ; CHECK-NEXT: vmov r3, s8
; CHECK-NEXT: vmovx.f16 s12, s4 ; CHECK-NEXT: vmovx.f16 s12, s4
; CHECK-NEXT: vmov r2, s4 ; CHECK-NEXT: vmov r2, s4
; CHECK-NEXT: vmov.16 q0[0], r3 ; CHECK-NEXT: vmov.16 q0[0], r3
; CHECK-NEXT: vmov.16 q0[1], r2 ; CHECK-NEXT: vmov.16 q0[1], r2
; CHECK-NEXT: vmov r2, s12 ; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: vmov.32 r0, q5[0] ; CHECK-NEXT: vmov r0, s20
; CHECK-NEXT: vmov.16 q0[4], r2 ; CHECK-NEXT: vmov.16 q0[4], r2
; CHECK-NEXT: vdup.32 q4, r0 ; CHECK-NEXT: vdup.32 q4, r0
; CHECK-NEXT: vmov r2, s9 ; CHECK-NEXT: vmov r2, s9
; CHECK-NEXT: vmov.16 q0[6], r2 ; CHECK-NEXT: vmov.16 q0[6], r2
; CHECK-NEXT: vmov r2, s5 ; CHECK-NEXT: vmov r2, s5
; CHECK-NEXT: vmovx.f16 s12, s8 ; CHECK-NEXT: vmovx.f16 s12, s8
; CHECK-NEXT: vmov r0, s17 ; CHECK-NEXT: vmov r0, s17
; CHECK-NEXT: vmov.16 q0[7], r2 ; CHECK-NEXT: vmov.16 q0[7], r2
; CHECK-NEXT: vmov r2, s12 ; CHECK-NEXT: vmov r2, s12
; CHECK-NEXT: vmov.16 q3[2], r0 ; CHECK-NEXT: vmov.16 q3[2], r0
; CHECK-NEXT: vmov.f32 s1, s8 ; CHECK-NEXT: vmov.f32 s1, s8
; CHECK-NEXT: vmov.16 q3[3], r2 ; CHECK-NEXT: vmov.16 q3[3], r2
; CHECK-NEXT: vmov r0, s2 ; CHECK-NEXT: vmov r0, s2
; CHECK-NEXT: vmovx.f16 s16, s18 ; CHECK-NEXT: vmovx.f16 s16, s18
; CHECK-NEXT: vmov.16 q3[4], r0 ; CHECK-NEXT: vmov.16 q3[4], r0
; CHECK-NEXT: vmov r0, s16 ; CHECK-NEXT: vmov r0, s16
; CHECK-NEXT: vmovx.f16 s16, s6 ; CHECK-NEXT: vmovx.f16 s16, s22
; CHECK-NEXT: vmov.16 q3[5], r0 ; CHECK-NEXT: vmov.16 q3[5], r0
; CHECK-NEXT: vmov r0, s16 ; CHECK-NEXT: vmov r0, s16
; CHECK-NEXT: vmovx.f16 s16, s22 ; CHECK-NEXT: vmovx.f16 s16, s6
; CHECK-NEXT: vmovx.f16 s24, s7 ; CHECK-NEXT: vmovx.f16 s24, s7
; CHECK-NEXT: vmov r2, s16 ; CHECK-NEXT: vmov r2, s16
; CHECK-NEXT: vmov.16 q4[0], r0 ; CHECK-NEXT: vstrw.32 q1, [sp] @ 16-byte Spill
; CHECK-NEXT: vmov.16 q4[1], r2 ; CHECK-NEXT: vmov.16 q4[0], r2
; CHECK-NEXT: vmov r2, s11
; CHECK-NEXT: vmov.16 q4[1], r0
; CHECK-NEXT: vmov r0, s7 ; CHECK-NEXT: vmov r0, s7
; CHECK-NEXT: vmov.16 q4[3], r0 ; CHECK-NEXT: vmov.16 q4[3], r0
; CHECK-NEXT: vmov r0, s24 ; CHECK-NEXT: vmov r0, s24
; CHECK-NEXT: vmovx.f16 s24, s23 ; CHECK-NEXT: vmovx.f16 s24, s23
; CHECK-NEXT: vmov.16 q4[6], r0 ; CHECK-NEXT: vmov.16 q4[6], r0
; CHECK-NEXT: vmov r0, s24 ; CHECK-NEXT: vmov r0, s24
; CHECK-NEXT: vmov.32 r2, q2[3]
; CHECK-NEXT: vmov.16 q4[7], r0
; CHECK-NEXT: vdup.32 q7, r2 ; CHECK-NEXT: vdup.32 q7, r2
; CHECK-NEXT: vmov.16 q4[7], r0
; CHECK-NEXT: vmov r2, s29
; CHECK-NEXT: vmov.f32 s18, s23 ; CHECK-NEXT: vmov.f32 s18, s23
; CHECK-NEXT: vmovx.f16 s24, s17 ; CHECK-NEXT: vmovx.f16 s24, s17
; CHECK-NEXT: vmov r2, s29
; CHECK-NEXT: vmovx.f16 s28, s30
; CHECK-NEXT: vmov r0, s24 ; CHECK-NEXT: vmov r0, s24
; CHECK-NEXT: vmov.16 q6[2], r2 ; CHECK-NEXT: vmov.16 q6[2], r2
; CHECK-NEXT: vmov.16 q6[3], r0 ; CHECK-NEXT: vmov.16 q6[3], r0
; CHECK-NEXT: vstrw.32 q1, [sp] @ 16-byte Spill ; CHECK-NEXT: vmovx.f16 s28, s30
; CHECK-NEXT: vmovx.f16 s4, s10 ; CHECK-NEXT: vmovx.f16 s4, s10
; CHECK-NEXT: vmov.f32 s1, s13 ; CHECK-NEXT: vmov.f32 s1, s13
; CHECK-NEXT: vmov.f32 s2, s14 ; CHECK-NEXT: vmov.f32 s2, s14
; CHECK-NEXT: vstrw.32 q0, [r1] ; CHECK-NEXT: vstrw.32 q0, [r1]
; CHECK-NEXT: vmov r0, s18 ; CHECK-NEXT: vmov r0, s18
; CHECK-NEXT: vmov.16 q6[4], r0 ; CHECK-NEXT: vmov.16 q6[4], r0
; CHECK-NEXT: vmov r0, s28 ; CHECK-NEXT: vmov r0, s28
; CHECK-NEXT: vmov.16 q6[5], r0 ; CHECK-NEXT: vmov.16 q6[5], r0
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vmov.16 q1[6], r2 ; CHECK-NEXT: vmov.16 q1[6], r2
; CHECK-NEXT: vmov r2, s9 ; CHECK-NEXT: vmov r2, s9
; CHECK-NEXT: vmov.16 q1[7], r2 ; CHECK-NEXT: vmov.16 q1[7], r2
; CHECK-NEXT: vmov r2, s0 ; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: vldrw.u32 q0, [r0, #64] ; CHECK-NEXT: vldrw.u32 q0, [r0, #64]
; CHECK-NEXT: vmov.f32 s5, s12 ; CHECK-NEXT: vmov.f32 s5, s12
; CHECK-NEXT: vmov q5, q3 ; CHECK-NEXT: vmov q5, q3
; CHECK-NEXT: vstrw.32 q3, [sp, #32] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q3, [sp, #32] @ 16-byte Spill
; CHECK-NEXT: vmov.32 r3, q0[0] ; CHECK-NEXT: vmov r3, s0
; CHECK-NEXT: vmov q4, q0 ; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vdup.32 q0, r3 ; CHECK-NEXT: vdup.32 q0, r3
; CHECK-NEXT: vstrw.32 q1, [sp, #128] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q1, [sp, #128] @ 16-byte Spill
; CHECK-NEXT: vmov r3, s1 ; CHECK-NEXT: vmov r3, s1
; CHECK-NEXT: vmovx.f16 s0, s2 ; CHECK-NEXT: vmovx.f16 s0, s2
; CHECK-NEXT: vmov.16 q3[2], r3 ; CHECK-NEXT: vmov.16 q3[2], r3
; CHECK-NEXT: vstrw.32 q2, [sp, #80] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q2, [sp, #80] @ 16-byte Spill
; CHECK-NEXT: vmov.16 q3[3], r2 ; CHECK-NEXT: vmov.16 q3[3], r2
; CHECK-NEXT: vmov r2, s6 ; CHECK-NEXT: vmov r2, s6
; CHECK-NEXT: vmov.16 q3[4], r2 ; CHECK-NEXT: vmov.16 q3[4], r2
; CHECK-NEXT: vmov r2, s0 ; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: vmovx.f16 s0, s10 ; CHECK-NEXT: vmovx.f16 s0, s18
; CHECK-NEXT: vmov.16 q3[5], r2 ; CHECK-NEXT: vmov.16 q3[5], r2
; CHECK-NEXT: vmov r2, s0 ; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: vmovx.f16 s0, s18 ; CHECK-NEXT: vmovx.f16 s0, s10
; CHECK-NEXT: vmov r3, s0 ; CHECK-NEXT: vmov r3, s0
; CHECK-NEXT: vmov.16 q1[0], r2
; CHECK-NEXT: vmov.16 q1[1], r3
; CHECK-NEXT: vmov r2, s11
; CHECK-NEXT: vmovx.f16 s0, s11 ; CHECK-NEXT: vmovx.f16 s0, s11
; CHECK-NEXT: vmov.16 q1[0], r3
; CHECK-NEXT: vmov r3, s23
; CHECK-NEXT: vmov.16 q1[1], r2
; CHECK-NEXT: vmov r2, s11
; CHECK-NEXT: vmov.16 q1[3], r2 ; CHECK-NEXT: vmov.16 q1[3], r2
; CHECK-NEXT: vmov r2, s0 ; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: vmovx.f16 s0, s19 ; CHECK-NEXT: vmovx.f16 s0, s19
; CHECK-NEXT: vmov.16 q1[6], r2 ; CHECK-NEXT: vmov.16 q1[6], r2
; CHECK-NEXT: vmov r2, s0 ; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: vldrw.u32 q5, [r0, #16]
; CHECK-NEXT: vmov.16 q1[7], r2 ; CHECK-NEXT: vmov.16 q1[7], r2
; CHECK-NEXT: vmov.32 r3, q5[3] ; CHECK-NEXT: vstrw.32 q3, [sp, #112] @ 16-byte Spill
; CHECK-NEXT: vmov.f32 s6, s19 ; CHECK-NEXT: vmov.f32 s6, s19
; CHECK-NEXT: vmovx.f16 s0, s5 ; CHECK-NEXT: vmovx.f16 s0, s5
; CHECK-NEXT: vmov r2, s0 ; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: vdup.32 q0, r3 ; CHECK-NEXT: vdup.32 q0, r3
; CHECK-NEXT: vmov r3, s1 ; CHECK-NEXT: vmov r3, s1
; CHECK-NEXT: vmovx.f16 s0, s2 ; CHECK-NEXT: vmovx.f16 s0, s2
; CHECK-NEXT: vmov.16 q2[2], r3 ; CHECK-NEXT: vmov.16 q2[2], r3
; CHECK-NEXT: vldrw.u32 q5, [r0, #16]
; CHECK-NEXT: vmov.16 q2[3], r2
; CHECK-NEXT: vstrw.32 q3, [sp, #112] @ 16-byte Spill
; CHECK-NEXT: vmov r3, s20 ; CHECK-NEXT: vmov r3, s20
; CHECK-NEXT: vldrw.u32 q3, [r0, #80] ; CHECK-NEXT: vmov.16 q2[3], r2
; CHECK-NEXT: vmov.16 q7[0], r3 ; CHECK-NEXT: vmov.16 q7[0], r3
; CHECK-NEXT: vldrw.u32 q3, [r0, #80]
; CHECK-NEXT: vstrw.32 q1, [sp, #96] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q1, [sp, #96] @ 16-byte Spill
; CHECK-NEXT: vmov r2, s6
; CHECK-NEXT: vstrw.32 q4, [sp, #48] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q4, [sp, #48] @ 16-byte Spill
; CHECK-NEXT: vmov r2, s6
; CHECK-NEXT: vmov.16 q2[4], r2 ; CHECK-NEXT: vmov.16 q2[4], r2
; CHECK-NEXT: vmov r2, s0 ; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: vmov.16 q2[5], r2 ; CHECK-NEXT: vmov.16 q2[5], r2
; CHECK-NEXT: vstrw.32 q2, [sp, #64] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q2, [sp, #64] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q2, [r0, #48] ; CHECK-NEXT: vldrw.u32 q2, [r0, #48]
; CHECK-NEXT: vmov.32 r0, q3[0] ; CHECK-NEXT: vmov r0, s12
; CHECK-NEXT: vmov r2, s8 ; CHECK-NEXT: vmov r2, s8
; CHECK-NEXT: vmovx.f16 s0, s8 ; CHECK-NEXT: vmovx.f16 s0, s8
; CHECK-NEXT: vmov.16 q7[1], r2 ; CHECK-NEXT: vmov.16 q7[1], r2
; CHECK-NEXT: vmov r2, s0 ; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: vmov.16 q7[4], r2 ; CHECK-NEXT: vmov.16 q7[4], r2
; CHECK-NEXT: vmov r2, s21 ; CHECK-NEXT: vmov r2, s21
; CHECK-NEXT: vmov.16 q7[6], r2 ; CHECK-NEXT: vmov.16 q7[6], r2
; CHECK-NEXT: vmov r2, s9 ; CHECK-NEXT: vmov r2, s9
; CHECK-NEXT: vmovx.f16 s0, s20 ; CHECK-NEXT: vmovx.f16 s0, s20
; CHECK-NEXT: vmov.16 q7[7], r2 ; CHECK-NEXT: vmov.16 q7[7], r2
; CHECK-NEXT: vmov r2, s0 ; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: vdup.32 q0, r0 ; CHECK-NEXT: vdup.32 q0, r0
; CHECK-NEXT: vmov r0, s1 ; CHECK-NEXT: vmov r0, s1
; CHECK-NEXT: vmovx.f16 s0, s2 ; CHECK-NEXT: vmovx.f16 s0, s2
; CHECK-NEXT: vmov.16 q1[2], r0 ; CHECK-NEXT: vmov.16 q1[2], r0
; CHECK-NEXT: vmov.f32 s29, s20 ; CHECK-NEXT: vmov.f32 s29, s20
; CHECK-NEXT: vmov.16 q1[3], r2 ; CHECK-NEXT: vmov.16 q1[3], r2
; CHECK-NEXT: vmov r0, s30 ; CHECK-NEXT: vmov r0, s30
; CHECK-NEXT: vmov.16 q1[4], r0 ; CHECK-NEXT: vmov.16 q1[4], r0
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q1[5], r0 ; CHECK-NEXT: vmov.16 q1[5], r0
; CHECK-NEXT: vmovx.f16 s0, s14
; CHECK-NEXT: vstrw.32 q1, [sp, #16] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q1, [sp, #16] @ 16-byte Spill
; CHECK-NEXT: vmov q1, q2 ; CHECK-NEXT: vmov q1, q2
; CHECK-NEXT: vmovx.f16 s0, s6
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmovx.f16 s0, s14 ; CHECK-NEXT: vmovx.f16 s0, s6
; CHECK-NEXT: vmov r2, s0 ; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: vmov.16 q2[0], r0
; CHECK-NEXT: vmov.16 q2[1], r2
; CHECK-NEXT: vmov r0, s7
; CHECK-NEXT: vmovx.f16 s0, s7 ; CHECK-NEXT: vmovx.f16 s0, s7
; CHECK-NEXT: vmov.16 q2[0], r2
; CHECK-NEXT: vmov r2, s23
; CHECK-NEXT: vmov.16 q2[1], r0
; CHECK-NEXT: vmov r0, s7
; CHECK-NEXT: vmov.16 q2[3], r0 ; CHECK-NEXT: vmov.16 q2[3], r0
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmovx.f16 s0, s15 ; CHECK-NEXT: vmovx.f16 s0, s15
; CHECK-NEXT: vmov.16 q2[6], r0 ; CHECK-NEXT: vmov.16 q2[6], r0
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q2[7], r0 ; CHECK-NEXT: vmov.16 q2[7], r0
; CHECK-NEXT: vmov.32 r2, q5[3]
; CHECK-NEXT: vmov.f32 s10, s15 ; CHECK-NEXT: vmov.f32 s10, s15
; CHECK-NEXT: vmovx.f16 s0, s9 ; CHECK-NEXT: vmovx.f16 s0, s9
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vdup.32 q0, r2 ; CHECK-NEXT: vdup.32 q0, r2
; CHECK-NEXT: vmov r2, s1 ; CHECK-NEXT: vmov r2, s1
; CHECK-NEXT: vmovx.f16 s0, s2 ; CHECK-NEXT: vmovx.f16 s0, s2
; CHECK-NEXT: vmov.16 q6[2], r2 ; CHECK-NEXT: vmov.16 q6[2], r2
; CHECK-NEXT: vmov.16 q6[3], r0 ; CHECK-NEXT: vmov.16 q6[3], r0
▲ Show 20 Lines • Show All 171 Lines • Show Last 20 Lines