[WIP] syndicate code generation between dynamic alloca and static alloca during stack clash probing

[serge-sans-paille]

Summary

It's a WIP, but as spotted by @jonpa, there was room for improvement there, so I'm doing my best.

[jonpa]

I think this was actually @uweigands suggestion, but for now we are going to first try to make sure that the prologue is as fast as possible and not combine the reg/imm case. But it will be interesting to know if you can get the prologue code equally fast this way...

I also wonder if the X86 backend is adding the live-in list entries on the new MBBs in inlineStackProbe(). I discovered that I had to call recomputeLiveIns() on the new blocks (SystemZ patch is updated, so you can see what I mean there...)

[serge-sans-paille]

In D79589#2025581, @jonpa wrote:

I think this was actually @uweigands suggestion, but for now we are going to first try to make sure that the prologue is as fast as possible and not combine the reg/imm case. But it will be interesting to know if you can get the prologue code equally fast this way...

Yeah, that's my goal, having both equally fast.

I also wonder if the X86 backend is adding the live-in list entries on the new MBBs in inlineStackProbe(). I discovered that I had to call recomputeLiveIns() on the new blocks (SystemZ patch is updated, so you can see what I mean there...)

Indeed, I manually added the LiveIn for the testMBB, I'm surprised you need to recompute them instead of just adding the extra registers by hand.

[jonpa]

In D79589#2029266, @serge-sans-paille wrote:

In D79589#2025581, @jonpa wrote:

I think this was actually @uweigands suggestion, but for now we are going to first try to make sure that the prologue is as fast as possible and not combine the reg/imm case. But it will be interesting to know if you can get the prologue code equally fast this way...

Yeah, that's my goal, having both equally fast.

I also wonder if the X86 backend is adding the live-in list entries on the new MBBs in inlineStackProbe(). I discovered that I had to call recomputeLiveIns() on the new blocks (SystemZ patch is updated, so you can see what I mean there...)

Indeed, I manually added the LiveIn for the testMBB, I'm surprised you need to recompute them instead of just adding the extra registers by hand.

All the callee-saved registers are added as live-in on the entry block, of which most are saved (and killed) immediately on SystemZ. The function argument registers however are also live-in and as well live past the stack-probing loop. I found it most convenient to make those argument registers in particular live-in after the probing by recomputing the liveness...

[serge-sans-paille]

All the callee-saved registers are added as live-in on the entry block, of which most are saved (and killed) immediately on SystemZ. The function argument registers however are also live-in and as well live past the stack-probing loop. I found it most convenient to make those argument registers in particular live-in after the probing by recomputing the liveness...

I've got no prior knowledge of SystemZ, so pardon the seemingly stupid question, but how does the live-in of the entryblock impacts the Live-in of the probing loop?

[jonpa]

In D79589#2029464, @serge-sans-paille wrote:

All the callee-saved registers are added as live-in on the entry block, of which most are saved (and killed) immediately on SystemZ. The function argument registers however are also live-in and as well live past the stack-probing loop. I found it most convenient to make those argument registers in particular live-in after the probing by recomputing the liveness...

I've got no prior knowledge of SystemZ, so pardon the seemingly stupid question, but how does the live-in of the entryblock impacts the Live-in of the probing loop?

There are no stupid questions here :-) Well, the entry block is split at the point of the stub, with new MBBs inserted in between those two new halves. So my understanding is that any phys reg that is live at the point of the stub should also be live after it (in the rest of the original MBB), and therefore it should be live-in to all the other new blocks created so that the regs are proberly modelled as live-through through those blocks...

[serge-sans-paille]

In D79589#2029519, @jonpa wrote:

In D79589#2029464, @serge-sans-paille wrote:

All the callee-saved registers are added as live-in on the entry block, of which most are saved (and killed) immediately on SystemZ. The function argument registers however are also live-in and as well live past the stack-probing loop. I found it most convenient to make those argument registers in particular live-in after the probing by recomputing the liveness...

I've got no prior knowledge of SystemZ, so pardon the seemingly stupid question, but how does the live-in of the entryblock impacts the Live-in of the probing loop?

There are no stupid questions here :-) Well, the entry block is split at the point of the stub, with new MBBs inserted in between those two new halves. So my understanding is that any phys reg that is live at the point of the stub should also be live after it (in the rest of the original MBB), and therefore it should be live-in to all the other new blocks created so that the regs are proberly modelled as live-through through those blocks...

I can't find a reference in the doc that states whether Live-In for a block include live-In of its successors (which you seem to imply) or only of the block itself (which was my original belief)

[serge-sans-paille]

Apart from the fruitful discussion with @jonpa, I'm going to drop that attempt. I can't find of a correct way to syndicate theses codes without breaking existing method visibility.

[jonpa]

In D79589#2031116, @serge-sans-paille wrote:

In D79589#2029519, @jonpa wrote:

In D79589#2029464, @serge-sans-paille wrote:

All the callee-saved registers are added as live-in on the entry block, of which most are saved (and killed) immediately on SystemZ. The function argument registers however are also live-in and as well live past the stack-probing loop. I found it most convenient to make those argument registers in particular live-in after the probing by recomputing the liveness...

I've got no prior knowledge of SystemZ, so pardon the seemingly stupid question, but how does the live-in of the entryblock impacts the Live-in of the probing loop?

There are no stupid questions here :-) Well, the entry block is split at the point of the stub, with new MBBs inserted in between those two new halves. So my understanding is that any phys reg that is live at the point of the stub should also be live after it (in the rest of the original MBB), and therefore it should be live-in to all the other new blocks created so that the regs are proberly modelled as live-through through those blocks...

I can't find a reference in the doc that states whether Live-In for a block include live-In of its successors (which you seem to imply) or only of the block itself (which was my original belief)

In theory, all uses must have a prior definition in the IR model, and it is a broken IR if there is not. If there is a use in an MBB of a value defined in another MBB that is not an immediate predecessor, but further up in the CFG, that should be marked as live-in to MBB and also live-in to any other MBB that is on the path to the use (to model "live-through"). The machine verifier already has checks for this, and it is under development: https://reviews.llvm.org/D78586.

llvm/lib/Target/X86/X86FrameLowering.h

void emitStackProbeInlineGenericBlock(MachineFunction &MF,
                                         uint64_t Offset) const;
 
   void emitStackProbeInlineGenericLoop(MachineFunction &MF,
                                        MachineBasicBlock &MBB,
                                        MachineBasicBlock::iterator MBBI,
                                        const DebugLoc &DL,
                                        uint64_t Offset) const;
 
+public:
   /// Emit a stub to later inline the target stack probe.
+  MachineInstr *
+  emitStackProbeInlineStubFromReg(MachineFunction &MF, MachineBasicBlock &MBB,
+                                  MachineBasicBlock::iterator MBBI,
+                                  const DebugLoc &DL, unsigned Reg) const;
+  MachineInstr *
+  emitStackProbeInlineStubFromImm(MachineFunction &MF, MachineBasicBlock &MBB,
+                                  MachineBasicBlock::iterator MBBI,
+                                  const DebugLoc &DL, uint64_t Imm) const;
   MachineInstr *emitStackProbeInlineStub(MachineFunction &MF,
                                          MachineBasicBlock &MBB,
                                          MachineBasicBlock::iterator MBBI,
                                          const DebugLoc &DL,
                                          bool InProlog) const;
 
+private:
   /// Aligns the stack pointer by ANDing it with -MaxAlign.
   void BuildStackAlignAND(MachineBasicBlock &MBB,
                           MachineBasicBlock::iterator MBBI, const DebugLoc &DL,
                           unsigned Reg, uint64_t MaxAlign) const;
 
   /// Make small positive stack adjustments using POPs.
   bool adjustStackWithPops(MachineBasicBlock &MBB,
                            MachineBasicBlock::iterator MBBI, const DebugLoc &DL,

llvm/lib/Target/X86/X86FrameLowering.cpp

void X86FrameLowering::emitSPUpdate(MachineBasicBlock &MBB,
   const bool EmitInlineStackProbe = TLI.hasInlineStackProbe(MF);
 
   // It's ok to not take into account large chunks when probing, as the
   // allocation is split in smaller chunks anyway.
   if (EmitInlineStackProbe && !InEpilogue) {
 
     // Delegate stack probing to the `inlineStackProbe` mechanism to avoid
     // complications.
-    MachineInstr *Stub = emitStackProbeInlineStub(MF, MBB, MBBI, DL, true);
+    emitStackProbeInlineStubFromImm(MF, MBB, MBBI, DL, Offset);
 
-    // Encode the static offset as a metadata attached to the stub.
-    LLVMContext &Context = MF.getFunction().getContext();
-    MachineInstrBuilder(MF, Stub).addMetadata(
-        MDTuple::get(Context, {ConstantAsMetadata::get(ConstantInt::get(
-                                  IntegerType::get(Context, 64), Offset))}));
     return;
   } else if (Offset > Chunk) {
     // Rather than emit a long series of instructions for large offsets,
     // load the offset into a register and do one sub/add
     unsigned Reg = 0;
     unsigned Rax = (unsigned)(Is64Bit ? X86::RAX : X86::EAX);
 
     if (isSub && !isEAXLiveIn(MBB))
if (STI.isTargetWindowsCoreCLR() && STI.is64Bit())
     emitStackProbeInlineWindowsCoreCLR64(MF, MBB, MBBI, DL, InProlog);
   else
     emitStackProbeInlineGeneric(MF, MBB, MBBI, DL, InProlog);
 }
 
 void X86FrameLowering::emitStackProbeInlineGeneric(
     MachineFunction &MF, MachineBasicBlock &MBB,
     MachineBasicBlock::iterator MBBI, const DebugLoc &DL, bool InProlog) const {
-  MachineInstr &CallToInline = *std::prev(MBBI);
-  assert(CallToInline.getOperand(1).isMetadata() &&
-         "no metadata attached to that probe");
-  uint64_t Offset =
-      cast<ConstantInt>(
-          cast<ConstantAsMetadata>(
-              cast<MDTuple>(CallToInline.getOperand(1).getMetadata())
-                  ->getOperand(0))
-              ->getValue())
-          ->getZExtValue();
+
+  MachineInstr &SizeHolder = *std::prev(std::prev(MBBI));
 
   const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
   const X86TargetLowering &TLI = *STI.getTargetLowering();
   assert(!(STI.is64Bit() && STI.isTargetWindowsCoreCLR()) &&
          "different expansion expected for CoreCLR 64 bit");
 
+  if (SizeHolder.getOperand(1).isReg()) {
+    emitStackProbeInlineGenericLoop(MF, MBB, MBBI, DL,
+                                    SizeHolder.getOperand(1));
+    SizeHolder.eraseFromParent();
+    return;
+  }
   const uint64_t StackProbeSize = TLI.getStackProbeSize(MF);
   uint64_t ProbeChunk = StackProbeSize * 8;
 
+  uint64_t Offset = SizeHolder.getOperand(1).getImm();
   // Synthesize a loop or unroll it, depending on the number of iterations.
   if (Offset > ProbeChunk) {
-    emitStackProbeInlineGenericLoop(MF, MBB, MBBI, DL, Offset);
+    emitStackProbeInlineGenericLoop(MF, MBB, MBBI, DL,
+                                    SizeHolder.getOperand(1));
   } else {
     emitStackProbeInlineGenericBlock(MF, MBB, MBBI, DL, Offset);
   }
+  SizeHolder.eraseFromParent();
+  return;
 }
 
 void X86FrameLowering::emitStackProbeInlineGenericBlock(
     MachineFunction &MF, MachineBasicBlock &MBB,
     MachineBasicBlock::iterator MBBI, const DebugLoc &DL,
     uint64_t Offset) const {
 
   const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
                          .addImm(ChunkSize)
                          .setMIFlag(MachineInstr::FrameSetup);
   MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
 }
 
 void X86FrameLowering::emitStackProbeInlineGenericLoop(
     MachineFunction &MF, MachineBasicBlock &MBB,
     MachineBasicBlock::iterator MBBI, const DebugLoc &DL,
-    uint64_t Offset) const {
+    MachineOperand const &OffsetOperand) const {
 
   const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
   const X86TargetLowering &TLI = *STI.getTargetLowering();
   const unsigned MovMIOpc = Is64Bit ? X86::MOV64mi32 : X86::MOV32mi;
   const uint64_t StackProbeSize = TLI.getStackProbeSize(MF);
 
   // Synthesize a loop
   NumFrameLoopProbe++;
   const BasicBlock *LLVM_BB = MBB.getBasicBlock();
 
   MachineBasicBlock *testMBB = MF.CreateMachineBasicBlock(LLVM_BB);
   MachineBasicBlock *tailMBB = MF.CreateMachineBasicBlock(LLVM_BB);
 
   MachineFunction::iterator MBBIter = ++MBB.getIterator();
   MF.insert(MBBIter, testMBB);
   MF.insert(MBBIter, tailMBB);
 
   unsigned FinalStackPtr = Uses64BitFramePtr ? X86::R11 : X86::R11D;
   BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64rr), FinalStackPtr)
       .addReg(StackPtr)
       .setMIFlag(MachineInstr::FrameSetup);
 
   // save loop bound
-  {
+  if (OffsetOperand.isImm()) {
+    auto Offset = OffsetOperand.getImm();
     const unsigned Opc = getSUBriOpcode(Uses64BitFramePtr, Offset);
     BuildMI(MBB, MBBI, DL, TII.get(Opc), FinalStackPtr)
         .addReg(FinalStackPtr)
         .addImm(Offset / StackProbeSize * StackProbeSize)
         .setMIFlag(MachineInstr::FrameSetup);
+  } else {
+    auto Offset = OffsetOperand.getReg();
+    const unsigned Opc = getSUBrrOpcode(Uses64BitFramePtr);
+    BuildMI(MBB, MBBI, DL, TII.get(Opc), FinalStackPtr)
+        .addReg(FinalStackPtr)
+        .addReg(Offset)
+        .setMIFlag(MachineInstr::FrameSetup);
   }
 
   // allocate a page
   {
     const unsigned Opc = getSUBriOpcode(Uses64BitFramePtr, StackProbeSize);
     BuildMI(testMBB, DL, TII.get(Opc), StackPtr)
         .addReg(StackPtr)
         .addImm(StackProbeSize)
void X86FrameLowering::emitStackProbeInlineGenericLoop(
   BuildMI(testMBB, DL, TII.get(IsLP64 ? X86::CMP64rr : X86::CMP32rr))
       .addReg(StackPtr)
       .addReg(FinalStackPtr)
       .setMIFlag(MachineInstr::FrameSetup);
 
   // jump
   BuildMI(testMBB, DL, TII.get(X86::JCC_1))
       .addMBB(testMBB)
-      .addImm(X86::COND_NE)
+      .addImm(X86::COND_L)
       .setMIFlag(MachineInstr::FrameSetup);
   testMBB->addSuccessor(testMBB);
   testMBB->addSuccessor(tailMBB);
   testMBB->addLiveIn(FinalStackPtr);
 
   // allocate a block and touch it
 
   tailMBB->splice(tailMBB->end(), &MBB, MBBI, MBB.end());
   tailMBB->transferSuccessorsAndUpdatePHIs(&MBB);
   MBB.addSuccessor(testMBB);
 
-  if (Offset % StackProbeSize) {
-    const unsigned Opc = getSUBriOpcode(Uses64BitFramePtr, Offset);
-    BuildMI(*tailMBB, tailMBB->begin(), DL, TII.get(Opc), StackPtr)
-        .addReg(StackPtr)
-        .addImm(Offset % StackProbeSize)
+  // handle tail
+  if (OffsetOperand.isReg() || OffsetOperand.getImm() % StackProbeSize) {
+    BuildMI(*tailMBB, tailMBB->begin(), DL, TII.get(X86::MOV64rr), StackPtr)
+        .addReg(FinalStackPtr)
         .setMIFlag(MachineInstr::FrameSetup);
   }
 }
 
 void X86FrameLowering::emitStackProbeInlineWindowsCoreCLR64(
     MachineFunction &MF, MachineBasicBlock &MBB,
     MachineBasicBlock::iterator MBBI, const DebugLoc &DL, bool InProlog) const {
   const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
MachineInstr *X86FrameLowering::emitStackProbeInlineStub(
     MachineBasicBlock::iterator MBBI, const DebugLoc &DL, bool InProlog) const {
 
   assert(InProlog && "ChkStkStub called outside prolog!");
 
   return BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
       .addExternalSymbol("__chkstk_stub");
 }
 
+MachineInstr *X86FrameLowering::emitStackProbeInlineStubFromImm(
+    MachineFunction &MF, MachineBasicBlock &MBB,
+    MachineBasicBlock::iterator MBBI, const DebugLoc &DL,
+    uint64_t Offset) const {
+  BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri32), X86::RAX).addImm(Offset);
+  return BuildMI(MBB, MBBI, DL, TII.get(X86::CALL64pcrel32))
+      .addExternalSymbol("__chkstk_stub");
+}
+
+MachineInstr *X86FrameLowering::emitStackProbeInlineStubFromReg(
+    MachineFunction &MF, MachineBasicBlock &MBB,
+    MachineBasicBlock::iterator MBBI, const DebugLoc &DL, unsigned Reg) const {
+  BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64rr), X86::RAX).addReg(Reg);
+  return BuildMI(MBB, MBBI, DL, TII.get(X86::CALL64pcrel32))
+      .addExternalSymbol("__chkstk_stub");
+}
+
 static unsigned calculateSetFPREG(uint64_t SPAdjust) {
   // Win64 ABI has a less restrictive limitation of 240; 128 works equally well
   // and might require smaller successive adjustments.
   const uint64_t Win64MaxSEHOffset = 128;
   uint64_t SEHFrameOffset = std::min(SPAdjust, Win64MaxSEHOffset);
   // Win64 ABI requires 16-byte alignment for the UWOP_SET_FPREG opcode.
   return SEHFrameOffset & -16;
 }

llvm/lib/Target/X86/X86ISelLowering.cpp

X86TargetLowering::EmitLoweredSelect(MachineInstr &MI,
   ThisMBB->erase(MIItBegin, MIItEnd);
 
   return SinkMBB;
 }
 
 MachineBasicBlock *
 X86TargetLowering::EmitLoweredProbedAlloca(MachineInstr &MI,
                                            MachineBasicBlock *BB) const {
-  MachineFunction *MF = BB->getParent();
-  const TargetInstrInfo *TII = Subtarget.getInstrInfo();
+  MachineFunction &MF = *BB->getParent();
   const X86FrameLowering &TFI = *Subtarget.getFrameLowering();
   DebugLoc DL = MI.getDebugLoc();
-  const BasicBlock *LLVM_BB = BB->getBasicBlock();
 
-  const unsigned ProbeSize = getStackProbeSize(*MF);
-
-  MachineRegisterInfo &MRI = MF->getRegInfo();
-  MachineBasicBlock *testMBB = MF->CreateMachineBasicBlock(LLVM_BB);
-  MachineBasicBlock *tailMBB = MF->CreateMachineBasicBlock(LLVM_BB);
-  MachineBasicBlock *blockMBB = MF->CreateMachineBasicBlock(LLVM_BB);
-
-  MachineFunction::iterator MBBIter = ++BB->getIterator();
-  MF->insert(MBBIter, testMBB);
-  MF->insert(MBBIter, blockMBB);
-  MF->insert(MBBIter, tailMBB);
-
-  unsigned sizeVReg = MI.getOperand(1).getReg();
-
-  const TargetRegisterClass *SizeRegClass = MRI.getRegClass(sizeVReg);
-
-  unsigned tmpSizeVReg = MRI.createVirtualRegister(SizeRegClass);
-  unsigned tmpSizeVReg2 = MRI.createVirtualRegister(SizeRegClass);
-
-  unsigned physSPReg = TFI.Uses64BitFramePtr ? X86::RSP : X86::ESP;
-
-  // test rsp size
-  BuildMI(testMBB, DL, TII->get(X86::PHI), tmpSizeVReg)
-      .addReg(sizeVReg)
-      .addMBB(BB)
-      .addReg(tmpSizeVReg2)
-      .addMBB(blockMBB);
-
-  BuildMI(testMBB, DL,
-          TII->get(TFI.Uses64BitFramePtr ? X86::CMP64ri32 : X86::CMP32ri))
-      .addReg(tmpSizeVReg)
-      .addImm(ProbeSize);
-
-  BuildMI(testMBB, DL, TII->get(X86::JCC_1))
-      .addMBB(tailMBB)
-      .addImm(X86::COND_L);
-  testMBB->addSuccessor(blockMBB);
-  testMBB->addSuccessor(tailMBB);
-
-  // allocate a block and touch it
-
-  BuildMI(blockMBB, DL,
-          TII->get(TFI.Uses64BitFramePtr ? X86::SUB64ri32 : X86::SUB32ri),
-          tmpSizeVReg2)
-      .addReg(tmpSizeVReg)
-      .addImm(ProbeSize);
-
-  BuildMI(blockMBB, DL,
-          TII->get(TFI.Uses64BitFramePtr ? X86::SUB64ri32 : X86::SUB32ri),
-          physSPReg)
-      .addReg(physSPReg)
-      .addImm(ProbeSize);
-
-  const unsigned MovMIOpc =
-      TFI.Uses64BitFramePtr ? X86::MOV64mi32 : X86::MOV32mi;
-  addRegOffset(BuildMI(blockMBB, DL, TII->get(MovMIOpc)), physSPReg, false, 0)
-      .addImm(0);
-
-  BuildMI(blockMBB, DL, TII->get(X86::JMP_1)).addMBB(testMBB);
-  blockMBB->addSuccessor(testMBB);
-
-  // allocate the tail and continue
-  BuildMI(tailMBB, DL,
-          TII->get(TFI.Uses64BitFramePtr ? X86::SUB64rr : X86::SUB32rr),
-          physSPReg)
-      .addReg(physSPReg)
-      .addReg(tmpSizeVReg);
-
-  // touch the tail too, as we don't have any information about the context
-  addRegOffset(BuildMI(tailMBB, DL, TII->get(MovMIOpc)), physSPReg, false, 0)
-      .addImm(0);
-
-  BuildMI(tailMBB, DL, TII->get(TargetOpcode::COPY), MI.getOperand(0).getReg())
-      .addReg(physSPReg);
-
-  tailMBB->splice(tailMBB->end(), BB,
-                  std::next(MachineBasicBlock::iterator(MI)), BB->end());
-  tailMBB->transferSuccessorsAndUpdatePHIs(BB);
-  BB->addSuccessor(testMBB);
+  MachineBasicBlock::iterator MBBI(MI);
 
+  MachineInstr *Stub = TFI.emitStackProbeInlineStubFromReg(
+      MF, *BB, MBBI, DL, MI.getOperand(1).getReg());
   // Delete the original pseudo instruction.
-  MI.eraseFromParent();
+  // MI.removeFromParent();
 
   // And we're done.
-  return tailMBB;
+  return BB;
 }
 
 MachineBasicBlock *
 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr &MI,
                                         MachineBasicBlock *BB) const {
   MachineFunction *MF = BB->getParent();
   const TargetInstrInfo *TII = Subtarget.getInstrInfo();
   DebugLoc DL = MI.getDebugLoc();

llvm/test/CodeGen/X86/stack-clash-dynamic-alloca.ll

 ; RUN: llc < %s | FileCheck %s
 
 
 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-unknown-linux-gnu"
 
 define i32 @foo(i32 %n) local_unnamed_addr #0 {
 
 ; CHECK-LABEL: foo:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:   pushq %rbp
-; CHECK-NEXT:   .cfi_def_cfa_offset 16
-; CHECK-NEXT:   .cfi_offset %rbp, -16
-; CHECK-NEXT:   movq  %rsp, %rbp
-; CHECK-NEXT:   .cfi_def_cfa_register %rbp
-; CHECK-NEXT:   movl  %edi, %eax
-; CHECK-NEXT:   leaq  15(,%rax,4), %rax
-; CHECK-NEXT:   andq  $-16, %rax
-; CHECK-NEXT:   cmpq  $4096, %rax # imm = 0x1000
-; CHECK-NEXT:   jl  .LBB0_3
-; CHECK-NEXT:  .LBB0_2: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT:   subq  $4096, %rax # imm = 0x1000
-; CHECK-NEXT:   subq  $4096, %rsp # imm = 0x1000
-; CHECK-NEXT:   movq  $0, (%rsp)
-; CHECK-NEXT:   cmpq  $4096, %rax # imm = 0x1000
-; CHECK-NEXT:   jge .LBB0_2
-; CHECK-NEXT:  .LBB0_3:
-; CHECK-NEXT:   subq  %rax, %rsp
-; CHECK-NEXT:   movq  %rsp, %rax
-; CHECK-NEXT: movq  $0, (%rsp)
-; CHECK-NEXT:   movl  $1, 4792(%rax)
-; CHECK-NEXT:   movl  (%rax), %eax
-; CHECK-NEXT:   movq  %rbp, %rsp
-; CHECK-NEXT:   popq  %rbp
-; CHECK-NEXT:  .cfi_def_cfa %rsp, 8
-; CHECK-NEXT:   retq
+; CHECK-NEXT: pushq %rbp
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: .cfi_offset %rbp, -16
+; CHECK-NEXT: movq  %rsp, %rbp
+; CHECK-NEXT: .cfi_def_cfa_register %rbp
+; CHECK-NEXT: movl  %edi, %eax
+; CHECK-NEXT: leaq  15(,%rax,4), %rax
+; CHECK-NEXT: movq  %rsp, %r11
+; CHECK-NEXT: subq  %rax, %r11
+; CHECK-NEXT:.LBB0_1:                                # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: subq  $4096, %rsp             # imm = 0x1000
+; CHECK-NEXT: movq  $0, (%rsp)
+; CHECK-NEXT: cmpq  %r11, %rsp
+; CHECK-NEXT: jle .LBB0_1
+; CHECK-NEXT:# %bb.2:
+; CHECK-NEXT: movq  %r11, %rsp
+; CHECK-NEXT: # variable sized alloca with probing
+; CHECK-NEXT: movq  %rcx, %rsp
+; CHECK-NEXT: movl  $1, 4792(%rcx)
+; CHECK-NEXT: movl  (%rcx), %eax
+; CHECK-NEXT: movq  %rbp, %rsp
+; CHECK-NEXT: popq  %rbp
+; CHECK-NEXT: .cfi_def_cfa %rsp, 8
+; CHECK-NEXT: retq
 
+
   %a = alloca i32, i32 %n, align 16
   %b = getelementptr inbounds i32, i32* %a, i64 1198
   store volatile i32 1, i32* %b
   %c = load volatile i32, i32* %a
   ret i32 %c
 }
 
 attributes #0 =  {"probe-stack"="inline-asm"}