[mlir][spirv] Handle debug information during (de)serialization.

[denis13]

Summary

This is an initial version, currently supports OpString and OpLine
for autogenerated operations during (de)serialization.

[antiagainst]

Awesome! Thanks a lot for adding this, Denis! Overall LGTM; just a few nits.

mlir/lib/Dialect/SPIRV/Serialization/Deserializer.cpp

408

Add comment to explain what these three elements mean or maybe create a struct for it?

2040

OpNoLine should kill this definition. Could you add a process* function for it? It should be trivial. :)

mlir/lib/Dialect/SPIRV/Serialization/Serializer.cpp

589

if (!emitDebugInfo) return;

mlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp

496

We have a problem with the generated code size at the moment. Can we turn this into a utilty function in Serializer.cpp and call it here instead of embedding the logc for each op? (I'm also gonna clean up existing duplicated logic in the autogen'ed code soon.)

[denis13]

mlir/lib/Dialect/SPIRV/Serialization/Deserializer.cpp

2040

Thanks for review, if I got it right, we have to clear debug line in 3 cases:

1. end of block.
2. OpNoLine.
3. Another OpLine.

[denis13]

Addresses comments.

[denis13]

Remove new line.

[denis13]

Rebase on master.

[antiagainst]

Nice! Thanks Denis! I just have a few more nits. Feel free to land directly after addressing them!

mlir/lib/Dialect/SPIRV/Serialization/Deserializer.cpp

81

Actually all zeros might be a triple in real SPIR-V blobs. fileID=0 can map to a %0 = OpString and line=0 and col=0 can mean something related to the whole file.

Instead of baking the invalid/empty state in this struct, what about make the debugLine in Deserializer as Optional<DebugLine> so we can use llvm::None to mean no debug info? Then I think we can remove all the functions in this struct.

249

Discontinues

2040

Yup, correct. Thanks for handling the block end too!

2438

Can this function be replaced by op->hasTrait<IsTerminator>()?

[denis13]

Addresses comments.

[denis13]

@antiagainst thanks for review, can you please take a look, to make sure I've updated the patch in right way. Thanks.

[antiagainst]

mlir/lib/Dialect/SPIRV/Serialization/Deserializer.cpp

77

These constructors can be deleted too?

[aprantl]

mlir/lib/Dialect/SPIRV/Serialization/Deserializer.cpp

71

struct

[denis13]

mlir/lib/Dialect/SPIRV/Serialization/Deserializer.cpp

71

Thanks, fixed!

77

Thanks, fixed!

mlir/include/mlir/Dialect/SPIRV/SPIRVBase.td

 def SPV_OC_OpNop                       : I32EnumAttrCase<"OpNop", 0>;
 def SPV_OC_OpUndef                     : I32EnumAttrCase<"OpUndef", 1>;
 def SPV_OC_OpSourceContinued           : I32EnumAttrCase<"OpSourceContinued", 2>;
 def SPV_OC_OpSource                    : I32EnumAttrCase<"OpSource", 3>;
 def SPV_OC_OpSourceExtension           : I32EnumAttrCase<"OpSourceExtension", 4>;
 def SPV_OC_OpName                      : I32EnumAttrCase<"OpName", 5>;
 def SPV_OC_OpMemberName                : I32EnumAttrCase<"OpMemberName", 6>;
 def SPV_OC_OpString                    : I32EnumAttrCase<"OpString", 7>;
+def SPV_OC_OpLine                      : I32EnumAttrCase<"OpLine", 8>;
 def SPV_OC_OpExtension                 : I32EnumAttrCase<"OpExtension", 10>;
 def SPV_OC_OpExtInstImport             : I32EnumAttrCase<"OpExtInstImport", 11>;
 def SPV_OC_OpExtInst                   : I32EnumAttrCase<"OpExtInst", 12>;
 def SPV_OC_OpMemoryModel               : I32EnumAttrCase<"OpMemoryModel", 14>;
 def SPV_OC_OpEntryPoint                : I32EnumAttrCase<"OpEntryPoint", 15>;
 def SPV_OC_OpExecutionMode             : I32EnumAttrCase<"OpExecutionMode", 16>;
 def SPV_OC_OpCapability                : I32EnumAttrCase<"OpCapability", 17>;
 def SPV_OC_OpTypeVoid                  : I32EnumAttrCase<"OpTypeVoid", 19>;

 def SPV_OC_OpLoopMerge                 : I32EnumAttrCase<"OpLoopMerge", 246>;
 def SPV_OC_OpSelectionMerge            : I32EnumAttrCase<"OpSelectionMerge", 247>;
 def SPV_OC_OpLabel                     : I32EnumAttrCase<"OpLabel", 248>;
 def SPV_OC_OpBranch                    : I32EnumAttrCase<"OpBranch", 249>;
 def SPV_OC_OpBranchConditional         : I32EnumAttrCase<"OpBranchConditional", 250>;
 def SPV_OC_OpReturn                    : I32EnumAttrCase<"OpReturn", 253>;
 def SPV_OC_OpReturnValue               : I32EnumAttrCase<"OpReturnValue", 254>;
 def SPV_OC_OpUnreachable               : I32EnumAttrCase<"OpUnreachable", 255>;
+def SPV_OC_OpNoLine                    : I32EnumAttrCase<"OpNoLine", 317>;
 def SPV_OC_OpModuleProcessed           : I32EnumAttrCase<"OpModuleProcessed", 330>;
 def SPV_OC_OpGroupNonUniformElect      : I32EnumAttrCase<"OpGroupNonUniformElect", 333>;
 def SPV_OC_OpGroupNonUniformBallot     : I32EnumAttrCase<"OpGroupNonUniformBallot", 339>;
 def SPV_OC_OpGroupNonUniformIAdd       : I32EnumAttrCase<"OpGroupNonUniformIAdd", 349>;
 def SPV_OC_OpGroupNonUniformFAdd       : I32EnumAttrCase<"OpGroupNonUniformFAdd", 350>;
 def SPV_OC_OpGroupNonUniformIMul       : I32EnumAttrCase<"OpGroupNonUniformIMul", 351>;
 def SPV_OC_OpGroupNonUniformFMul       : I32EnumAttrCase<"OpGroupNonUniformFMul", 352>;
 def SPV_OC_OpGroupNonUniformSMin       : I32EnumAttrCase<"OpGroupNonUniformSMin", 353>;
 def SPV_OC_OpGroupNonUniformUMin       : I32EnumAttrCase<"OpGroupNonUniformUMin", 354>;
 def SPV_OC_OpGroupNonUniformFMin       : I32EnumAttrCase<"OpGroupNonUniformFMin", 355>;
 def SPV_OC_OpGroupNonUniformSMax       : I32EnumAttrCase<"OpGroupNonUniformSMax", 356>;
 def SPV_OC_OpGroupNonUniformUMax       : I32EnumAttrCase<"OpGroupNonUniformUMax", 357>;
 def SPV_OC_OpGroupNonUniformFMax       : I32EnumAttrCase<"OpGroupNonUniformFMax", 358>;
 def SPV_OC_OpSubgroupBallotKHR         : I32EnumAttrCase<"OpSubgroupBallotKHR", 4421>;
 
 def SPV_OpcodeAttr :
     SPV_I32EnumAttr<"Opcode", "valid SPIR-V instructions", [
       SPV_OC_OpNop, SPV_OC_OpUndef, SPV_OC_OpSourceContinued, SPV_OC_OpSource,
       SPV_OC_OpSourceExtension, SPV_OC_OpName, SPV_OC_OpMemberName, SPV_OC_OpString,
-      SPV_OC_OpExtension, SPV_OC_OpExtInstImport, SPV_OC_OpExtInst,
+      SPV_OC_OpLine, SPV_OC_OpExtension, SPV_OC_OpExtInstImport, SPV_OC_OpExtInst,
       SPV_OC_OpMemoryModel, SPV_OC_OpEntryPoint, SPV_OC_OpExecutionMode,
       SPV_OC_OpCapability, SPV_OC_OpTypeVoid, SPV_OC_OpTypeBool, SPV_OC_OpTypeInt,
       SPV_OC_OpTypeFloat, SPV_OC_OpTypeVector, SPV_OC_OpTypeArray,
       SPV_OC_OpTypeRuntimeArray, SPV_OC_OpTypeStruct, SPV_OC_OpTypePointer,
       SPV_OC_OpTypeFunction, SPV_OC_OpConstantTrue, SPV_OC_OpConstantFalse,
       SPV_OC_OpConstant, SPV_OC_OpConstantComposite, SPV_OC_OpConstantNull,
       SPV_OC_OpSpecConstantTrue, SPV_OC_OpSpecConstantFalse, SPV_OC_OpSpecConstant,
       SPV_OC_OpSpecConstantComposite, SPV_OC_OpFunction, SPV_OC_OpFunctionParameter,
SPV_I32EnumAttr<"Opcode", "valid SPIR-V instructions", [
       SPV_OC_OpBitFieldSExtract, SPV_OC_OpBitFieldUExtract, SPV_OC_OpBitReverse,
       SPV_OC_OpBitCount, SPV_OC_OpControlBarrier, SPV_OC_OpMemoryBarrier,
       SPV_OC_OpAtomicCompareExchangeWeak, SPV_OC_OpAtomicIIncrement,
       SPV_OC_OpAtomicIDecrement, SPV_OC_OpAtomicIAdd, SPV_OC_OpAtomicISub,
       SPV_OC_OpAtomicSMin, SPV_OC_OpAtomicUMin, SPV_OC_OpAtomicSMax,
       SPV_OC_OpAtomicUMax, SPV_OC_OpAtomicAnd, SPV_OC_OpAtomicOr, SPV_OC_OpAtomicXor,
       SPV_OC_OpPhi, SPV_OC_OpLoopMerge, SPV_OC_OpSelectionMerge, SPV_OC_OpLabel,
       SPV_OC_OpBranch, SPV_OC_OpBranchConditional, SPV_OC_OpReturn,
-      SPV_OC_OpReturnValue, SPV_OC_OpUnreachable, SPV_OC_OpModuleProcessed,
-      SPV_OC_OpGroupNonUniformElect, SPV_OC_OpGroupNonUniformBallot,
-      SPV_OC_OpGroupNonUniformIAdd, SPV_OC_OpGroupNonUniformFAdd,
-      SPV_OC_OpGroupNonUniformIMul, SPV_OC_OpGroupNonUniformFMul,
-      SPV_OC_OpGroupNonUniformSMin, SPV_OC_OpGroupNonUniformUMin,
-      SPV_OC_OpGroupNonUniformFMin, SPV_OC_OpGroupNonUniformSMax,
-      SPV_OC_OpGroupNonUniformUMax, SPV_OC_OpGroupNonUniformFMax,
-      SPV_OC_OpSubgroupBallotKHR
+      SPV_OC_OpReturnValue, SPV_OC_OpUnreachable, SPV_OC_OpNoLine,
+      SPV_OC_OpModuleProcessed, SPV_OC_OpGroupNonUniformElect,
+      SPV_OC_OpGroupNonUniformBallot, SPV_OC_OpGroupNonUniformIAdd,
+      SPV_OC_OpGroupNonUniformFAdd, SPV_OC_OpGroupNonUniformIMul,
+      SPV_OC_OpGroupNonUniformFMul, SPV_OC_OpGroupNonUniformSMin,
+      SPV_OC_OpGroupNonUniformUMin, SPV_OC_OpGroupNonUniformFMin,
+      SPV_OC_OpGroupNonUniformSMax, SPV_OC_OpGroupNonUniformUMax,
+      SPV_OC_OpGroupNonUniformFMax, SPV_OC_OpSubgroupBallotKHR
     ]>;
 
 // End opcode section. Generated from SPIR-V spec; DO NOT MODIFY!
 
 //===----------------------------------------------------------------------===//
 // SPIR-V op definitions
 //===----------------------------------------------------------------------===//
 

mlir/include/mlir/Dialect/SPIRV/Serialization.h

 class MLIRContext;
 
 namespace spirv {
 class ModuleOp;
 
 /// Serializes the given SPIR-V `module` and writes to `binary`. On failure,
 /// reports errors to the error handler registered with the MLIR context for
 /// `module`.
-LogicalResult serialize(ModuleOp module, SmallVectorImpl<uint32_t> &binary);
+LogicalResult serialize(ModuleOp module, SmallVectorImpl<uint32_t> &binary,
+                        bool emitDebugInfo = false);
 
 /// Deserializes the given SPIR-V `binary` module and creates a MLIR ModuleOp
 /// in the given `context`. Returns the ModuleOp on success; otherwise, reports
 /// errors to the error handler registered with `context` and returns
 /// llvm::None.
 Optional<ModuleOp> deserialize(ArrayRef<uint32_t> binary, MLIRContext *context);
 
 } // end namespace spirv
 } // end namespace mlir
 
 #endif // MLIR_DIALECT_SPIRV_SERIALIZATION_H_

mlir/lib/Dialect/SPIRV/Serialization/Deserializer.cpp

struct BlockMergeInfo {
   Block *mergeBlock;
   Block *continueBlock; // nullptr for spv.selection
 
   BlockMergeInfo() : mergeBlock(nullptr), continueBlock(nullptr) {}
   BlockMergeInfo(Block *m, Block *c = nullptr)
       : mergeBlock(m), continueBlock(c) {}
 };
 
+/// A struct for containing OpLine instruction information.
+struct DebugLine {
+  uint32_t fileID;
+  uint32_t line;
+  uint32_t col;
+
+  DebugLine(uint32_t fileIDNum, uint32_t lineNum, uint32_t colNum)
+      : fileID(fileIDNum), line(lineNum), col(colNum) {}
+};
+
 /// Map from a selection/loop's header block to its merge (and continue) target.
 using BlockMergeInfoMap = DenseMap<Block *, BlockMergeInfo>;
 
 /// A SPIR-V module serializer.
 ///
 /// A SPIR-V binary module is a single linear stream of instructions; each
 /// instruction is composed of 32-bit words. The first word of an instruction
 /// records the total number of words of that instruction using the 16
 /// higher-order bits. So this deserializer uses that to get instruction
private:
   /// Processes a SPIR-V OpConstantComposite instruction with the given
   /// `operands`.
   LogicalResult processConstantComposite(ArrayRef<uint32_t> operands);
 
   /// Processes a SPIR-V OpConstantNull instruction with the given `operands`.
   LogicalResult processConstantNull(ArrayRef<uint32_t> operands);
 
   //===--------------------------------------------------------------------===//
+  // Debug
+  //===--------------------------------------------------------------------===//
+
+  /// Discontinues any source-level location information that might be active
+  /// from a previous OpLine instruction.
+  LogicalResult clearDebugLine();
+
+  /// Creates a FileLineColLoc with the OpLine location information.
+  Location createFileLineColLoc(OpBuilder opBuilder);
+
+  /// Processes a SPIR-V OpLine instruction with the given `operands`.
+  LogicalResult processDebugLine(ArrayRef<uint32_t> operands);
+
+  /// Processes a SPIR-V OpString instruction with the given `operands`.
+  LogicalResult processDebugString(ArrayRef<uint32_t> operands);
+
+  //===--------------------------------------------------------------------===//
   // Control flow
   //===--------------------------------------------------------------------===//
 
   /// Returns the block for the given label <id>.
   Block *getBlock(uint32_t id) const { return blockMap.lookup(id); }
 
   // In SPIR-V, structured control flow is explicitly declared using merge
   // instructions (OpSelectionMerge and OpLoopMerge). In the SPIR-V dialect,
template <typename OpTy> LogicalResult processOp(ArrayRef<uint32_t> words) {
     return emitError(unknownLoc, "unsupported deserialization for ")
            << OpTy::getOperationName() << " op";
   }
 
 private:
   /// The SPIR-V binary module.
   ArrayRef<uint32_t> binary;
 
+  /// Contains the data of the OpLine instruction which precedes the current
+  /// processing instruction.
+  llvm::Optional<DebugLine> debugLine;
+
   /// The current word offset into the binary module.
   unsigned curOffset = 0;
 
   /// MLIRContext to create SPIR-V ModuleOp into.
   MLIRContext *context;
 
   // TODO(antiagainst): create Location subclass for binary blob
   Location unknownLoc;
private:
   DenseMap<uint32_t, Value> valueMap;
 
   // Mapping from result <id> to undef value of a type.
   DenseMap<uint32_t, Type> undefMap;
 
   // Result <id> to name mapping.
   DenseMap<uint32_t, StringRef> nameMap;
 
+  // Result <id> to debug info mapping.
+  DenseMap<uint32_t, StringRef> debugInfoMap;
+
   // Result <id> to decorations mapping.
   DenseMap<uint32_t, MutableDictionaryAttr> decorations;
 
   // Result <id> to type decorations.
   DenseMap<uint32_t, uint32_t> typeDecorations;
 
   // Result <id> to member decorations.
   // decorated-struct-type-<id> ->
LogicalResult Deserializer::processBranch(ArrayRef<uint32_t> operands) {
 
   if (operands.size() != 1) {
     return emitError(unknownLoc, "OpBranch must take exactly one target label");
   }
 
   auto *target = getOrCreateBlock(operands[0]);
   opBuilder.create<spirv::BranchOp>(unknownLoc, target);
 
+  clearDebugLine();
   return success();
 }
 
 LogicalResult
 Deserializer::processBranchConditional(ArrayRef<uint32_t> operands) {
   if (!curBlock) {
     return emitError(unknownLoc,
                      "OpBranchConditional must appear inside a block");
if (operands.size() == 5) {
     weights = std::make_pair(operands[3], operands[4]);
   }
 
   opBuilder.create<spirv::BranchConditionalOp>(
       unknownLoc, condition, trueBlock,
       /*trueArguments=*/ArrayRef<Value>(), falseBlock,
       /*falseArguments=*/ArrayRef<Value>(), weights);
 
+  clearDebugLine();
   return success();
 }
 
 LogicalResult Deserializer::processLabel(ArrayRef<uint32_t> operands) {
   if (!curFunction) {
     return emitError(unknownLoc, "OpLabel must appear inside a function");
   }
 
if (failed(ControlFlowStructurizer::structurize(unknownLoc, blockMergeInfo,
       return failure();
   }
 
   LLVM_DEBUG(llvm::dbgs() << "[cf] completed structurizing control flow\n");
   return success();
 }
 
 //===----------------------------------------------------------------------===//
+// Debug
+//===----------------------------------------------------------------------===//
+
+Location Deserializer::createFileLineColLoc(OpBuilder opBuilder) {
+  if (!debugLine)
+    return unknownLoc;
+
+  auto fileName = debugInfoMap.lookup(debugLine->fileID).str();
+  if (fileName.empty())
+    fileName = "<unknown>";
+  return opBuilder.getFileLineColLoc(opBuilder.getIdentifier(fileName),
+                                     debugLine->line, debugLine->col);
+}
+
+LogicalResult Deserializer::processDebugLine(ArrayRef<uint32_t> operands) {
+  // According to SPIR-V spec:
+  // "This location information applies to the instructions physically
+  // following this instruction, up to the first occurrence of any of the
+  // following: the next end of block, the next OpLine instruction, or the next
+  // OpNoLine instruction."
+  if (operands.size() != 3)
+    return emitError(unknownLoc, "OpLine must have 3 operands");
+  debugLine = DebugLine(operands[0], operands[1], operands[2]);
+  return success();
+}
+
+LogicalResult Deserializer::clearDebugLine() {
+  debugLine = llvm::None;
+  return success();
+}
+
+LogicalResult Deserializer::processDebugString(ArrayRef<uint32_t> operands) {
+  if (operands.size() < 2)
+    return emitError(unknownLoc, "OpString needs at least 2 operands");
+
+  if (!debugInfoMap.lookup(operands[0]).empty())
+    return emitError(unknownLoc,
+                     "duplicate debug string found for result <id> ")
+           << operands[0];
+
+  unsigned wordIndex = 1;
+  StringRef debugString = decodeStringLiteral(operands, wordIndex);
+  if (wordIndex != operands.size())
+    return emitError(unknownLoc,
+                     "unexpected trailing words in OpString instruction");
+
+  debugInfoMap[operands[0]] = debugString;
+  return success();
+}
+
+//===----------------------------------------------------------------------===//
 // Instruction
 //===----------------------------------------------------------------------===//
 
 Value Deserializer::getValue(uint32_t id) {
   if (auto constInfo = getConstant(id)) {
     // Materialize a `spv.constant` op at every use site.
     return opBuilder.create<spirv::ConstantOp>(unknownLoc, constInfo->second,
                                                constInfo->first);
if (deferInstructions) {
       return success();
     }
     break;
   case spirv::Opcode::OpVariable:
     if (isa<spirv::ModuleOp>(opBuilder.getBlock()->getParentOp())) {
       return processGlobalVariable(operands);
     }
     break;
+  case spirv::Opcode::OpLine:
+    return processDebugLine(operands);
+  case spirv::Opcode::OpNoLine:
+    return clearDebugLine();
   case spirv::Opcode::OpName:
     return processName(operands);
-  case spirv::Opcode::OpModuleProcessed:
   case spirv::Opcode::OpString:
+    return processDebugString(operands);
+  case spirv::Opcode::OpModuleProcessed:
   case spirv::Opcode::OpSource:
   case spirv::Opcode::OpSourceContinued:
   case spirv::Opcode::OpSourceExtension:
     // TODO: This is debug information embedded in the binary which should be
     // translated into the spv.module.
     return success();
   case spirv::Opcode::OpTypeVoid:
   case spirv::Opcode::OpTypeBool:
for (auto operand : operands) {
     argAttrs.push_back(argAttr);
   }
 
   opBuilder.create<spirv::MemoryBarrierOp>(unknownLoc, argAttrs[0],
                                            argAttrs[1]);
   return success();
 }
 
 // Pull in auto-generated Deserializer::dispatchToAutogenDeserialization() and
 // various Deserializer::processOp<...>() specializations.
 #define GET_DESERIALIZATION_FNS
 #include "mlir/Dialect/SPIRV/SPIRVSerialization.inc"
 } // namespace
 
 Optional<spirv::ModuleOp> spirv::deserialize(ArrayRef<uint32_t> binary,
                                              MLIRContext *context) {
   Deserializer deserializer(binary, context);
 
   if (failed(deserializer.deserialize()))
     return llvm::None;
 
   return deserializer.collect();
 }

mlir/lib/Dialect/SPIRV/Serialization/Serializer.cpp

 
 /// Encodes an SPIR-V instruction with the given `opcode` and `operands` into
 /// the given `binary` vector.
 static LogicalResult encodeInstructionInto(SmallVectorImpl<uint32_t> &binary,
                                            spirv::Opcode op,
                                            ArrayRef<uint32_t> operands) {
   uint32_t wordCount = 1 + operands.size();
   binary.push_back(spirv::getPrefixedOpcode(wordCount, op));
-    binary.append(operands.begin(), operands.end());
   return success();
 }
 
 /// A pre-order depth-first visitor function for processing basic blocks.
 ///
 /// Visits the basic blocks starting from the given `headerBlock` in pre-order
 /// depth-first manner and calls `blockHandler` on each block. Skips handling
 /// blocks in the `skipBlocks` list. If `skipHeader` is true, `blockHandler`

 /// For the first word, the 16 high-order bits are the word count of the
 /// instruction, the 16 low-order bits are the opcode enumerant. The
 /// instructions then belong to different sections, which must be laid out in
 /// the particular order as specified in "2.4 Logical Layout of a Module" of
 /// the SPIR-V spec.
 class Serializer {
 public:
   /// Creates a serializer for the given SPIR-V `module`.
-  explicit Serializer(spirv::ModuleOp module);
+  explicit Serializer(spirv::ModuleOp module, bool emitDebugInfo = false);
 
   /// Serializes the remembered SPIR-V module.
   LogicalResult serialize();
 
   /// Collects the final SPIR-V `binary`.
   void collect(SmallVectorImpl<uint32_t> &binary);
 
 #ifndef NDEBUG
private:
   }
 
   /// Gets the <id> for the function with the given name. Assigns the next
   /// available <id> if the function haven't been deserialized.
   uint32_t getOrCreateFunctionID(StringRef fnName);
 
   void processCapability();
 
+  void processDebugInfo();
+
   void processExtension();
 
   void processMemoryModel();
 
   LogicalResult processConstantOp(spirv::ConstantOp op);
 
   LogicalResult processSpecConstantOp(spirv::SpecConstantOp op);
 
private:
   // Utilities
   //===--------------------------------------------------------------------===//
 
   /// Emits an OpDecorate instruction to decorate the given `target` with the
   /// given `decoration`.
   LogicalResult emitDecoration(uint32_t target, spirv::Decoration decoration,
                                ArrayRef<uint32_t> params = {});
 
+  /// Emits an OpLine instruction with the given `loc` location information into
+  /// the given `binary` vector.
+  LogicalResult emitDebugLine(SmallVectorImpl<uint32_t> &binary, Location loc);
+
 private:
   /// The SPIR-V module to be serialized.
   spirv::ModuleOp module;
 
   /// An MLIR builder for getting MLIR constructs.
   mlir::Builder mlirBuilder;
 
+  /// A flag which indicates if the debuginfo should be emitted.
+  bool emitDebugInfo = false;
+
+  /// The <id> of the OpString instruction, which specifies a file name, for
+  /// use by other debug instructions.
+  uint32_t fileID = 0;
+
   /// The next available result <id>.
   uint32_t nextID = 1;
 
   // The following are for different SPIR-V instruction sections. They follow
   // the logical layout of a SPIR-V module.
 
   SmallVector<uint32_t, 4> capabilities;
   SmallVector<uint32_t, 0> extensions;
   SmallVector<uint32_t, 0> extendedSets;
   SmallVector<uint32_t, 3> memoryModel;
   SmallVector<uint32_t, 0> entryPoints;
   SmallVector<uint32_t, 4> executionModes;
-  // TODO(antiagainst): debug instructions
+  SmallVector<uint32_t, 0> debug;
   SmallVector<uint32_t, 0> names;
   SmallVector<uint32_t, 0> decorations;
   SmallVector<uint32_t, 0> typesGlobalValues;
   SmallVector<uint32_t, 0> functions;
 
   /// `functionHeader` contains all the instructions that must be in the first
   /// block in the function, and `functionBody` contains the rest. After
   /// processing FuncOp, the encoded instructions of a function are appended to
private:
   /// At the same time, we record their offsets in the emitted binary (which is
   /// placed inside `functions`) here. And then after emitting all blocks, we
   /// replace the dummy <id> 0 with the real result <id> by overwriting
   /// `functions[offset]`.
   DenseMap<Value, SmallVector<size_t, 1>> deferredPhiValues;
 };
 } // namespace
 
-Serializer::Serializer(spirv::ModuleOp module)
-    : module(module), mlirBuilder(module.getContext()) {}
+Serializer::Serializer(spirv::ModuleOp module, bool emitDebugInfo)
+    : module(module), mlirBuilder(module.getContext()),
+      emitDebugInfo(emitDebugInfo) {}
 
 LogicalResult Serializer::serialize() {
   LLVM_DEBUG(llvm::dbgs() << "+++ starting serialization +++\n");
 
   if (failed(module.verify()))
     return failure();
 
   // TODO(antiagainst): handle the other sections
   processCapability();
   processExtension();
   processMemoryModel();
+  processDebugInfo();
 
   // Iterate over the module body to serialize it. Assumptions are that there is
   // only one basic block in the moduleOp
   for (auto &op : module.getBlock()) {
     if (failed(processOperation(&op))) {
       return failure();
     }
   }
void Serializer::collect(SmallVectorImpl<uint32_t> &binary) {
 
   spirv::appendModuleHeader(binary, module.vce_triple()->getVersion(), nextID);
   binary.append(capabilities.begin(), capabilities.end());
   binary.append(extensions.begin(), extensions.end());
   binary.append(extendedSets.begin(), extendedSets.end());
   binary.append(memoryModel.begin(), memoryModel.end());
   binary.append(entryPoints.begin(), entryPoints.end());
   binary.append(executionModes.begin(), executionModes.end());
+  binary.append(debug.begin(), debug.end());
   binary.append(names.begin(), names.end());
   binary.append(decorations.begin(), decorations.end());
   binary.append(typesGlobalValues.begin(), typesGlobalValues.end());
   binary.append(functions.begin(), functions.end());
 }
 
 #ifndef NDEBUG
 void Serializer::printValueIDMap(raw_ostream &os) {

 }
 
 void Serializer::processCapability() {
   for (auto cap : module.vce_triple()->getCapabilities())
     encodeInstructionInto(capabilities, spirv::Opcode::OpCapability,
                           {static_cast<uint32_t>(cap)});
 }
 
+void Serializer::processDebugInfo() {
+  if (!emitDebugInfo)
+    return;
+  auto fileLoc = module.getLoc().dyn_cast<FileLineColLoc>();
+  auto fileName = fileLoc ? fileLoc.getFilename() : "<unknown>";
+  fileID = getNextID();
+  SmallVector<uint32_t, 16> operands;
+  operands.push_back(fileID);
+  spirv::encodeStringLiteralInto(operands, fileName);
+  encodeInstructionInto(debug, spirv::Opcode::OpString, operands);
+  // TODO: Encode more debug instructions.
+}
+
 void Serializer::processExtension() {
   llvm::SmallVector<uint32_t, 16> extName;
   for (spirv::Extension ext : module.vce_triple()->getExtensions()) {
     extName.clear();
     spirv::encodeStringLiteralInto(extName, spirv::stringifyExtension(ext));
     encodeInstructionInto(extensions, spirv::Opcode::OpExtension, extName);
   }
 }
LogicalResult Serializer::emitDecoration(uint32_t target,
   decorations.push_back(
       spirv::getPrefixedOpcode(wordCount, spirv::Opcode::OpDecorate));
   decorations.push_back(target);
   decorations.push_back(static_cast<uint32_t>(decoration));
   decorations.append(params.begin(), params.end());
   return success();
 }
 
+LogicalResult Serializer::emitDebugLine(SmallVectorImpl<uint32_t> &binary,
+                                        Location loc) {
+  if (!emitDebugInfo)
+    return success();
+
+  auto fileLoc = loc.dyn_cast<FileLineColLoc>();
+  if (fileLoc)
+    encodeInstructionInto(binary, spirv::Opcode::OpLine,
+                          {fileID, fileLoc.getLine(), fileLoc.getColumn()});
+  return success();
+}
+
 LogicalResult spirv::serialize(spirv::ModuleOp module,
-                               SmallVectorImpl<uint32_t> &binary) {
+                               SmallVectorImpl<uint32_t> &binary,
+                               bool emitDebugInfo) {
   if (!module.vce_triple().hasValue())
     return module.emitError(
         "module must have 'vce_triple' attribute to be serializeable");
 
-  Serializer serializer(module);
+  Serializer serializer(module, emitDebugInfo);
 
   if (failed(serializer.serialize()))
     return failure();
 
   LLVM_DEBUG(serializer.printValueIDMap(llvm::dbgs()));
 
   serializer.collect(binary);
   return success();
 }

mlir/lib/Dialect/SPIRV/Serialization/TranslateRegistration.cpp

static LogicalResult serializeModule(ModuleOp module, raw_ostream &output) {
   module.walk([&](spirv::ModuleOp op) { spirvModules.push_back(op); });
 
   if (spirvModules.empty())
     return module.emitError("found no 'spv.module' op");
 
   if (spirvModules.size() != 1)
     return module.emitError("found more than one 'spv.module' op");
 
-  if (failed(spirv::serialize(spirvModules[0], binary)))
+  if (failed(
+          spirv::serialize(spirvModules[0], binary, /*emitDebuginfo=*/false)))
     return failure();
 
   output.write(reinterpret_cast<char *>(binary.data()),
                binary.size() * sizeof(uint32_t));
 
   return mlir::success();
 }
 
 namespace mlir {
 void registerToSPIRVTranslation() {
   TranslateFromMLIRRegistration toBinary(
       "serialize-spirv", [](ModuleOp module, raw_ostream &output) {
         return serializeModule(module, output);
       });
 }
 } // namespace mlir
 
 //===----------------------------------------------------------------------===//
 // Round-trip registration
 //===----------------------------------------------------------------------===//
 
 static LogicalResult roundTripModule(llvm::SourceMgr &sourceMgr,
-                                     raw_ostream &output,
+                                     bool emitDebugInfo, raw_ostream &output,
                                      MLIRContext *context) {
   // Parse an MLIR module from the source manager.
   auto srcModule = OwningModuleRef(parseSourceFile(sourceMgr, context));
   if (!srcModule)
     return failure();
 
   SmallVector<uint32_t, 0> binary;
 
   auto spirvModules = srcModule->getOps<spirv::ModuleOp>();
 
   if (spirvModules.begin() == spirvModules.end())
     return srcModule->emitError("found no 'spv.module' op");
 
   if (std::next(spirvModules.begin()) != spirvModules.end())
     return srcModule->emitError("found more than one 'spv.module' op");
 
-  if (failed(spirv::serialize(*spirvModules.begin(), binary)))
+  if (failed(spirv::serialize(*spirvModules.begin(), binary, emitDebugInfo)))
     return failure();
 
   // Then deserialize to get back a SPIR-V module.
   auto spirvModule = spirv::deserialize(binary, context);
   if (!spirvModule)
     return failure();
 
   // Wrap around in a new MLIR module.
   OwningModuleRef dstModule(ModuleOp::create(FileLineColLoc::get(
       /*filename=*/"", /*line=*/0, /*column=*/0, context)));
   dstModule->getBody()->push_front(spirvModule->getOperation());
   dstModule->print(output);
 
   return mlir::success();
 }
 
 namespace mlir {
 void registerTestRoundtripSPIRV() {
   TranslateRegistration roundtrip(
       "test-spirv-roundtrip", [](llvm::SourceMgr &sourceMgr,
                                  raw_ostream &output, MLIRContext *context) {
-        return roundTripModule(sourceMgr, output, context);
+        return roundTripModule(sourceMgr, /*emitDebugInfo=*/false, output,
+                               context);
+      });
+}
+
+void registerTestRoundtripDebugSPIRV() {
+  TranslateRegistration roundtrip(
+      "test-spirv-roundtrip-debug",
+      [](llvm::SourceMgr &sourceMgr, raw_ostream &output,
+         MLIRContext *context) {
+        return roundTripModule(sourceMgr, /*emitDebugInfo=*/true, output,
+                               context);
       });
 }
 } // namespace mlir

mlir/test/Dialect/SPIRV/Serialization/debug.mlir

+// RUN: mlir-translate -test-spirv-roundtrip-debug -mlir-print-debuginfo %s | FileCheck %s
+
+spv.module Logical GLSL450 requires #spv.vce<v1.0, [Shader], []> {
+  spv.func @arithmetic(%arg0 : vector<4xf32>, %arg1 : vector<4xf32>) "None" {
+    // CHECK: loc({{".*debug.mlir"}}:6:10)
+    %0 = spv.FAdd %arg0, %arg1 : vector<4xf32>
+    // CHECK: loc({{".*debug.mlir"}}:8:10)
+    %1 = spv.FNegate %arg0 : vector<4xf32>
+    spv.Return
+  }
+
+  spv.func @atomic(%ptr: !spv.ptr<i32, Workgroup>, %value: i32, %comparator: i32) "None" {
+    // CHECK: loc({{".*debug.mlir"}}:14:10)
+    %1 = spv.AtomicAnd "Device" "None" %ptr, %value : !spv.ptr<i32, Workgroup>
+    spv.Return
+  }
+
+  spv.func @bitwiser(%arg0 : i32, %arg1 : i32) "None" {
+    // CHECK: loc({{".*debug.mlir"}}:20:10)
+    %0 = spv.BitwiseAnd %arg0, %arg1 : i32
+    spv.Return
+  }
+
+  spv.func @convert(%arg0 : f32) "None" {
+    // CHECK: loc({{".*debug.mlir"}}:26:10)
+    %0 = spv.ConvertFToU %arg0 : f32 to i32
+    spv.Return
+  }
+
+  spv.func @composite(%arg0 : !spv.struct<f32, !spv.struct<!spv.array<4xf32>, f32>>, %arg1: !spv.array<4xf32>, %arg2 : f32, %arg3 : f32) "None" {
+    // CHECK: loc({{".*debug.mlir"}}:32:10)
+    %0 = spv.CompositeInsert %arg1, %arg0[1 : i32, 0 : i32] : !spv.array<4xf32> into !spv.struct<f32, !spv.struct<!spv.array<4xf32>, f32>>
+    // CHECK: loc({{".*debug.mlir"}}:34:10)
+    %1 = spv.CompositeConstruct %arg2, %arg3 : vector<2xf32>
+    spv.Return
+  }
+
+  spv.func @group_non_uniform(%val: f32) "None" {
+    // CHECK: loc({{".*debug.mlir"}}:40:10)
+    %0 = spv.GroupNonUniformFAdd "Workgroup" "Reduce" %val : f32
+    spv.Return
+  }
+
+  spv.func @logical(%arg0: i32, %arg1: i32) "None" {
+    // CHECK: loc({{".*debug.mlir"}}:46:10)
+    %0 = spv.IEqual %arg0, %arg1 : i32
+    spv.Return
+  }
+
+  spv.func @memory_accesses(%arg0 : !spv.ptr<!spv.array<4x!spv.array<4xf32>>, StorageBuffer>, %arg1 : i32, %arg2 : i32) "None" {
+    // CHECK: loc({{".*debug.mlir"}}:52:10)
+    %2 = spv.AccessChain %arg0[%arg1, %arg2] : !spv.ptr<!spv.array<4x!spv.array<4xf32>>, StorageBuffer>
+    // CHECK: loc({{".*debug.mlir"}}:54:10)
+    %3 = spv.Load "StorageBuffer" %2 : f32
+    // CHECK: loc({{.*debug.mlir"}}:56:5)
+    spv.Store "StorageBuffer" %2, %3 : f32
+    // CHECK: loc({{".*debug.mlir"}}:58:5)
+    spv.Return
+  }
+}

mlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp

os << formatv("template <> constexpr inline ::mlir::spirv::Opcode "
                 "getOpcode<{0}>() {{\n",
                 op.getQualCppClassName());
   os << formatv("  return ::mlir::spirv::Opcode::{0};\n",
                 record->getValueAsString("spirvOpName"));
   os << "}\n";
 }
 
 /// Forward declaration of function to return the SPIR-V opcode corresponding to
 /// an operation. This function will be generated for all SPV_Op instances that
 /// have hasOpcode = 1.
 static void declareOpcodeFn(raw_ostream &os) {
   os << "template <typename OpClass> inline constexpr ::mlir::spirv::Opcode "
         "getOpcode();\n";
 }
 
 /// Generates code to serialize attributes of a SPV_Op `op` into `os`. The
 /// generates code extracts the attribute with name `attrName` from
static void emitSerializationFunction(const Record *attrClass,
   emitOperandSerialization(op, record->getLoc(), "  ", opVar, operands,
                            elidedAttrs, os);
 
   if (record->isSubClassOf("SPV_ExtInstOp")) {
     os << formatv("  encodeExtensionInstruction({0}, \"{1}\", {2}, {3});\n",
                   opVar, record->getValueAsString("extendedInstSetName"),
                   record->getValueAsInt("extendedInstOpcode"), operands);
   } else {
+    // Emit debug info.
+    os << formatv("  emitDebugLine(functionBody, {0}.getLoc());\n", opVar);
     os << formatv("  encodeInstructionInto("
                   "functionBody, spirv::getOpcode<{0}>(), {1});\n",
                   op.getQualCppClassName(), operands);
   }
 
   // Process decorations.
   emitDecorationSerialization(op, "  ", opVar, elidedAttrs, resultID, os);
 
emitResultDeserialization(op, record->getLoc(), "  ", words, wordIndex,
                             resultTypes, valueID, os);
 
   os << formatv("  SmallVector<Value, 4> {0};\n", operands);
   os << formatv("  SmallVector<NamedAttribute, 4> {0};\n", attributes);
   // Operand deserialization
   emitOperandDeserialization(op, record->getLoc(), "  ", words, wordIndex,
                              operands, attributes, os);
 
-  os << formatv(
-      "  auto {1} = opBuilder.create<{0}>(unknownLoc, {2}, {3}, {4}); "
+  os << formatv("  Location loc = createFileLineColLoc(opBuilder);\n");
+  os << formatv("  auto {1} = opBuilder.create<{0}>(loc, {2}, {3}, {4}); "
                 "(void){1};\n",
-      op.getQualCppClassName(), opVar, resultTypes, operands, attributes);
+                op.getQualCppClassName(), opVar, resultTypes, operands,
+                attributes);
   if (op.getNumResults() == 1) {
     os << formatv("  valueMap[{0}] = {1}.getResult();\n\n", valueID, opVar);
   }
 
+  // According to SPIR-V spec:
+  // This location information applies to the instructions physically following
+  // this instruction, up to the first occurrence of any of the following: the
+  // next end of block.
+  os << formatv("  if ({0}.hasTrait<OpTrait::IsTerminator>())\n", opVar);
+  os << formatv("    clearDebugLine();\n");
+
   // Decorations
   emitDecorationDeserialization(op, "  ", valueID, attributes, os);
   os << "  return success();\n";
   os << "}\n\n";
 }
 
 /// Generates the prologue for the function that dispatches the deserialization
 /// based on the `opcode`.

mlir/tools/mlir-translate/mlir-translate.cpp

static llvm::cl::opt<bool> verifyDiagnostics(
     "verify-diagnostics",
     llvm::cl::desc("Check that emitted diagnostics match "
                    "expected-* lines on the corresponding line"),
     llvm::cl::init(false));
 
 namespace mlir {
 // Defined in the test directory, no public header.
 void registerTestRoundtripSPIRV();
+void registerTestRoundtripDebugSPIRV();
 } // namespace mlir
 
-static void registerTestTranslations() { registerTestRoundtripSPIRV(); }
+static void registerTestTranslations() {
+  registerTestRoundtripSPIRV();
+  registerTestRoundtripDebugSPIRV();
+}
 
 int main(int argc, char **argv) {
   registerAllDialects();
   registerAllTranslations();
   registerTestTranslations();
   llvm::InitLLVM y(argc, argv);
 
   // Add flags for all the registered translations.