AArch64-MachO: use linker-private symbols for jump-tables

[t.p.northover]

Summary

This kind of kills two birds with one stone:

When they are in __TEXT,__const the separate symbols surviving to link stage allow the linker to split and separately dead-code eliminate any orphaned tables (if the functions are not called for example).

When they are at the end of a huge function, we still produce relocations for some reason (could probably be fixed) but MachO only allows 24-bit signed addends so these can be incorrect. Switching to linker-private means the relocations will be against that linker symbol rather than the start of the function and have no addend. Everything will work.

llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp

void AArch64AsmPrinter::emitJumpTableInfo() {
   const Function &F = MF->getFunction();
   const TargetLoweringObjectFile &TLOF = getObjFileLowering();
   MCSectionSubPair FnSection = OutStreamer->getCurrentSection();
 
   // 32-bit jump-table entries are LJTI - LBB expressions. Some object files
   // formats can't relocate these properly in all cases.
   bool JT32InFnSection = STI->isTargetCOFF() || STI->isTargetMachO();
 
+  // Using a linker-private symbol for the table allows the linker to dead-strip
+  // unused ones, and removes the 2^24 byte relocation limit if the function is
+  // huge.
+  bool UseLinkerPrivateJT = STI->isTargetMachO();
+
   auto AFI = MF->getInfo<AArch64FunctionInfo>();
   for (unsigned JTI = 0, e = JT.size(); JTI != e; ++JTI) {
     const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
 
     // If this jump table was deleted, ignore it.
     if (JTBBs.empty()) continue;
 
     unsigned Size = AFI->getJumpTableEntrySize(JTI);
     if (Size == 4 && JT32InFnSection)
       OutStreamer->SwitchSection(FnSection.first, FnSection.second);
     else
       OutStreamer->SwitchSection(TLOF.getSectionForJumpTable(F, TM));
 
     emitAlignment(Align(Size));
-    OutStreamer->emitLabel(GetJTISymbol(JTI));
+    OutStreamer->emitLabel(GetJTISymbol(JTI, UseLinkerPrivateJT));
 
     for (auto *JTBB : JTBBs)
       emitJumpTableEntry(MJTI, JTBB, JTI);
   }
 }
 
 void AArch64AsmPrinter::emitJumpTableEntry(const MachineJumpTableInfo *MJTI,
                                            const MachineBasicBlock *MBB,
                                            unsigned JTI) {
   const MCExpr *Value = MCSymbolRefExpr::create(MBB->getSymbol(), OutContext);
   auto AFI = MF->getInfo<AArch64FunctionInfo>();
   unsigned Size = AFI->getJumpTableEntrySize(JTI);
 
   if (Size == 4) {
     // .word LBB - LJTI
-    const TargetLowering *TLI = MF->getSubtarget().getTargetLowering();
-    const MCExpr *Base = TLI->getPICJumpTableRelocBaseExpr(MF, JTI, OutContext);
+    bool UseLinkerPrivateJT =
+        getSubtargetInfo().getTargetTriple().isOSBinFormatMachO();
+    const MCExpr *Base = MCSymbolRefExpr::create(
+        MF->getJTISymbol(JTI, OutContext, UseLinkerPrivateJT), OutContext);
     Value = MCBinaryExpr::createSub(Value, Base, OutContext);
   } else {
     // .byte (LBB - LBB) >> 2 (or .hword)
     const MCSymbol *BaseSym = AFI->getJumpTableEntryPCRelSymbol(JTI);
     const MCExpr *Base = MCSymbolRefExpr::create(BaseSym, OutContext);
     Value = MCBinaryExpr::createSub(Value, Base, OutContext);
     Value = MCBinaryExpr::createLShr(
         Value, MCConstantExpr::create(2, OutContext), OutContext);

llvm/lib/Target/AArch64/AArch64MCInstLower.cpp

case MachineOperand::MO_GlobalAddress:
     MCOp = LowerSymbolOperand(MO, GetGlobalAddressSymbol(MO));
     break;
   case MachineOperand::MO_ExternalSymbol:
     MCOp = LowerSymbolOperand(MO, GetExternalSymbolSymbol(MO));
     break;
   case MachineOperand::MO_MCSymbol:
     MCOp = LowerSymbolOperand(MO, MO.getMCSymbol());
     break;
-  case MachineOperand::MO_JumpTableIndex:
-    MCOp = LowerSymbolOperand(MO, Printer.GetJTISymbol(MO.getIndex()));
+  case MachineOperand::MO_JumpTableIndex: {
+    bool UseLinkerPrivateJT =
+        Printer.getSubtargetInfo().getTargetTriple().isOSBinFormatMachO();
+    MCOp = LowerSymbolOperand(
+        MO, Printer.GetJTISymbol(MO.getIndex(), UseLinkerPrivateJT));
     break;
+  }
   case MachineOperand::MO_ConstantPoolIndex:
     MCOp = LowerSymbolOperand(MO, Printer.GetCPISymbol(MO.getIndex()));
     break;
   case MachineOperand::MO_BlockAddress:
     MCOp = LowerSymbolOperand(
         MO, Printer.GetBlockAddressSymbol(MO.getBlockAddress()));
     break;
   }

llvm/test/CodeGen/AArch64/GlobalISel/arm64e-jump-table-hardening.ll

 ; RUN: llc -verify-machineinstrs -o - %s -mtriple=arm64-apple-ios -global-isel -global-isel-abort=1 -aarch64-enable-atomic-cfg-tidy=0 | FileCheck %s
 
 ; x16 and x17 are hard-coded into the pseudo-instruction because they have
 ; better security guarantees.
 
 ; CHECK-LABEL: test_jumptable:
 ; CHECK: ubfx  x16, x0, #0, #32
 ; CHECK: cmp   x16, #5
 ; CHECK: csel  x16, x16, xzr, ls
-; CHECK: adrp  x17, LJTI0_0@PAGE
-; CHECK: add   x17, x17, LJTI0_0@PAGEOFF
+; CHECK: adrp  x17, lJTI0_0@PAGE
+; CHECK: add   x17, x17, lJTI0_0@PAGEOFF
 ; CHECK: ldrsw x16, [x17, x16, lsl #2]
 ; CHECK: add   x16, x17, x16
 ; CHECK: br    x16
 
 define i32 @test_jumptable(i32 %in) "jump-table-hardening" {
 
   switch i32 %in, label %def [
     i32 0, label %lbl1

 lbl4:
   ret i32 8
 
 lbl5:
   ret i32 10
 
 }
 
-; CHECK: LJTI0_0:
-; CHECK-NEXT: .long LBB{{[0-9_]+}}-LJTI0_0
-; CHECK-NEXT: .long LBB{{[0-9_]+}}-LJTI0_0
-; CHECK-NEXT: .long LBB{{[0-9_]+}}-LJTI0_0
-; CHECK-NEXT: .long LBB{{[0-9_]+}}-LJTI0_0
-; CHECK-NEXT: .long LBB{{[0-9_]+}}-LJTI0_0
-; CHECK-NEXT: .long LBB{{[0-9_]+}}-LJTI0_0
+; CHECK: lJTI0_0:
+; CHECK-NEXT: .long LBB{{[0-9_]+}}-lJTI0_0
+; CHECK-NEXT: .long LBB{{[0-9_]+}}-lJTI0_0
+; CHECK-NEXT: .long LBB{{[0-9_]+}}-lJTI0_0
+; CHECK-NEXT: .long LBB{{[0-9_]+}}-lJTI0_0
+; CHECK-NEXT: .long LBB{{[0-9_]+}}-lJTI0_0
+; CHECK-NEXT: .long LBB{{[0-9_]+}}-lJTI0_0

llvm/test/CodeGen/AArch64/arm64-jumptable.ll

exit.sink.split:
   %.sink = phi i32 [ 5, %bb4 ], [ %b, %bb1 ], [ 3, %bb3 ], [ %a, %entry ]
   store i32 %.sink, i32* %to
   br label %exit
 exit:
   ret void
 }
 
 ; CHECK-LABEL: sum:
-; CHECK: adrp    {{x[0-9]+}}, LJTI0_0@PAGE
-; CHECK:  add    {{x[0-9]+}}, {{x[0-9]+}}, LJTI0_0@PAGEOFF
+; CHECK: adrp    {{x[0-9]+}}, lJTI0_0@PAGE
+; CHECK:  add    {{x[0-9]+}}, {{x[0-9]+}}, lJTI0_0@PAGEOFF
 
 ; CHECK-LINUX-LABEL: sum:
 ; CHECK-LINUX: adrp    {{x[0-9]+}}, .LJTI0_0
 ; CHECK-LINUX:  add    {{x[0-9]+}}, {{x[0-9]+}}, :lo12:.LJTI0_0

llvm/test/CodeGen/AArch64/arm64e-jump-table-hardening.ll

 ; RUN: llc -verify-machineinstrs -o - %s -mtriple=arm64-apple-ios -aarch64-enable-atomic-cfg-tidy=0 | FileCheck %s
 ; RUN: llc -verify-machineinstrs -o - %s -mtriple=arm64-apple-ios -code-model=large -aarch64-enable-atomic-cfg-tidy=0 | FileCheck %s
 
 ; CHECK-LABEL: test_jumptable:
 ; CHECK: mov   w[[INDEX:[0-9]+]], w0
 ; CHECK: cmp   x[[INDEX]], #5
 ; CHECK: csel  [[INDEX2:x[0-9]+]], x[[INDEX]], xzr, ls
-; CHECK: adrp  [[JTPAGE:x[0-9]+]], LJTI0_0@PAGE
-; CHECK: add   x[[JT:[0-9]+]], [[JTPAGE]], LJTI0_0@PAGEOFF
+; CHECK: adrp  [[JTPAGE:x[0-9]+]], lJTI0_0@PAGE
+; CHECK: add   x[[JT:[0-9]+]], [[JTPAGE]], lJTI0_0@PAGEOFF
 ; CHECK: ldrsw [[OFFSET:x[0-9]+]], [x[[JT]], [[INDEX2]], lsl #2]
 ; CHECK: add   [[DEST:x[0-9]+]], x[[JT]], [[OFFSET]]
 ; CHECK: br    [[DEST]]
 
 define i32 @test_jumptable(i32 %in) "jump-table-hardening" {
 
   switch i32 %in, label %def [
     i32 0, label %lbl1

 lbl4:
   ret i32 8
 
 lbl5:
   ret i32 10
 
 }
 
-; CHECK: LJTI0_0:
-; CHECK-NEXT: .long LBB{{[0-9_]+}}-LJTI0_0
-; CHECK-NEXT: .long LBB{{[0-9_]+}}-LJTI0_0
-; CHECK-NEXT: .long LBB{{[0-9_]+}}-LJTI0_0
-; CHECK-NEXT: .long LBB{{[0-9_]+}}-LJTI0_0
-; CHECK-NEXT: .long LBB{{[0-9_]+}}-LJTI0_0
-; CHECK-NEXT: .long LBB{{[0-9_]+}}-LJTI0_0
+; CHECK: lJTI0_0:
+; CHECK-NEXT: .long LBB{{[0-9_]+}}-lJTI0_0
+; CHECK-NEXT: .long LBB{{[0-9_]+}}-lJTI0_0
+; CHECK-NEXT: .long LBB{{[0-9_]+}}-lJTI0_0
+; CHECK-NEXT: .long LBB{{[0-9_]+}}-lJTI0_0
+; CHECK-NEXT: .long LBB{{[0-9_]+}}-lJTI0_0
+; CHECK-NEXT: .long LBB{{[0-9_]+}}-lJTI0_0

llvm/test/CodeGen/AArch64/jump-table-32.ll

 ; RUN: llc -verify-machineinstrs -o - %s -mtriple=arm64_32-apple-ios7.0 -aarch64-enable-atomic-cfg-tidy=0 | FileCheck %s
 
 define i32 @test_jumptable(i32 %in) {
 ; CHECK: test_jumptable
 
   switch i32 %in, label %def [
     i32 0, label %lbl1
     i32 1, label %lbl2
     i32 2, label %lbl3
     i32 4, label %lbl4
   ]
-; CHECK: adrp    [[JTPAGE:x[0-9]+]], LJTI0_0@PAGE
+; CHECK: adrp    [[JTPAGE:x[0-9]+]], lJTI0_0@PAGE
 ; CHECK: mov     w[[INDEX:[0-9]+]], w0
-; CHECK: add     x[[JT:[0-9]+]], [[JTPAGE]], LJTI0_0@PAGEOFF
+; CHECK: add     x[[JT:[0-9]+]], [[JTPAGE]], lJTI0_0@PAGEOFF
 ; CHECK: adr     [[BASE_BLOCK:x[0-9]+]], LBB0_2
 ; CHECK: ldrb    w[[OFFSET:[0-9]+]], [x[[JT]], x[[INDEX]]]
 ; CHECK: add     [[DEST:x[0-9]+]], [[BASE_BLOCK]], x[[OFFSET]], lsl #2
 ; CHECK: br      [[DEST]]
 
 def:
   ret i32 0
 
 lbl1:
   ret i32 1
 
 lbl2:
   ret i32 2
 
 lbl3:
   ret i32 4
 
 lbl4:
   ret i32 8
 
 }
 
-; CHECK: LJTI0_0:
+; CHECK: lJTI0_0:
 ; CHECK-NEXT: .byte
 ; CHECK-NEXT: .byte
 ; CHECK-NEXT: .byte
 ; CHECK-NEXT: .byte
 ; CHECK-NEXT: .byte

llvm/test/CodeGen/AArch64/jump-table.ll

 ; CHECK-PIC-LABEL: test_jumptable:
 ; CHECK-PIC:     adrp [[JTPAGE:x[0-9]+]], .LJTI0_0
 ; CHECK-PIC:     add x[[JT:[0-9]+]], [[JTPAGE]], {{#?}}:lo12:.LJTI0_0
 ; CHECK-PIC:     adr [[PCBASE:x[0-9]+]], [[JTBASE:.LBB[0-9]+_[0-9]+]]
 ; CHECK-PIC:     ldrb w[[OFFSET:[0-9]+]], [x[[JT]], {{x[0-9]+}}]
 ; CHECK-PIC:     add [[DEST:x[0-9]+]], [[PCBASE]], x[[OFFSET]], lsl #2
 ; CHECK-PIC:     br [[DEST]]
 
-; CHECK-IOS:     adrp [[JTPAGE:x[0-9]+]], LJTI0_0@PAGE
-; CHECK-IOS:     add x[[JT:[0-9]+]], [[JTPAGE]], LJTI0_0@PAGEOFF
+; CHECK-IOS:     adrp [[JTPAGE:x[0-9]+]], lJTI0_0@PAGE
+; CHECK-IOS:     add x[[JT:[0-9]+]], [[JTPAGE]], lJTI0_0@PAGEOFF
 ; CHECK-IOS:     adr [[PCBASE:x[0-9]+]], [[JTBASE:LBB[0-9]+_[0-9]+]]
 ; CHECK-IOS:     ldrb w[[OFFSET:[0-9]+]], [x[[JT]], {{x[0-9]+}}]
 ; CHECK-IOS:     add [[DEST:x[0-9]+]], [[PCBASE]], x[[OFFSET]], lsl #2
 ; CHECK-IOS: br [[DEST]]
 
 ; CHECK-TINY-LABEL: test_jumptable:
 ; CHECK-TINY:     adr x[[JT:[0-9]+]], .LJTI0_0
 ; CHECK-TINY:     adr [[PCBASE:x[0-9]+]], [[JTBASE:.LBB[0-9]+_[0-9]+]]

 ; CHECK-PIC-NEXT: .byte (.LBB{{.*}}-[[JTBASE]])>>2
 ; CHECK-PIC-NEXT: .byte (.LBB{{.*}}-[[JTBASE]])>>2
 ; CHECK-PIC-NEXT: .byte (.LBB{{.*}}-[[JTBASE]])>>2
 ; CHECK-PIC-NEXT: .byte (.LBB{{.*}}-[[JTBASE]])>>2
 ; CHECK-PIC-NOT: .end_data_region
 
 ; CHECK-IOS: .section __TEXT,__const
 ; CHECK-IOS-NOT: .data_region
-; CHECK-IOS: LJTI0_0:
+; CHECK-IOS: lJTI0_0:
 ; CHECK-IOS-NEXT:     .byte ([[JTBASE]]-[[JTBASE]])>>2
 ; CHECK-IOS-NEXT:     .byte (LBB{{.*}}-[[JTBASE]])>>2
 ; CHECK-IOS-NEXT:     .byte (LBB{{.*}}-[[JTBASE]])>>2
 ; CHECK-IOS-NEXT:     .byte (LBB{{.*}}-[[JTBASE]])>>2
 ; CHECK-IOS-NEXT:     .byte (LBB{{.*}}-[[JTBASE]])>>2
 ; CHECK-IOS-NOT: .end_data_region
 
 define i32 @test_jumptable32(i32 %in) {
 
   switch i32 %in, label %def [
     i32 0, label %lbl1
     i32 1, label %lbl2
     i32 2, label %lbl3
     i32 4, label %lbl4
   ]
 ; CHECK-IOS-LABEL: test_jumptable32:
-; CHECK-IOS:     adrp [[JTPAGE:x[0-9]+]], [[LJTI:LJTI[0-9]+_[0-9]+]]@PAGE
+; CHECK-IOS:     adrp [[JTPAGE:x[0-9]+]], [[LJTI:lJTI[0-9]+_[0-9]+]]@PAGE
 ; CHECK-IOS:     add x[[JT:[0-9]+]], [[JTPAGE]], [[LJTI]]@PAGEOFF
 ; CHECK-IOS:     ldrsw [[OFFSET:x[0-9]+]], [x[[JT]], {{x[0-9]+}}, lsl #2]
 ; CHECK-IOS:     add [[DEST:x[0-9]+]], x[[JT]], [[OFFSET]]
 ; CHECK-IOS:     br [[DEST]]
 
 ; CHECK: .rodata
 ; CHECK: .LJTI2_0:
 ; CHECK-NEXT: .word .LBB{{.*}}-.LJTI2_0