[ARM] VMOVrh of VMOVhr

[dmgreen]

Summary

A VMOVhr of a VMOVrh can be simply folded to the original HPR value.

[efriedma]

Isn't VMOVrh (VMOVhr (X)) equivalent to X & 65535?

[dmgreen]

Oh right. Yeah. My bad. I guess that's why we add tests for things.

I've removed that untested half of the patch, leaving only VMOVhr(VMOVrh(..))

[efriedma]

LGTM

llvm/lib/Target/ARM/ARMISelLowering.cpp

if (Op0.getOpcode() == ARMISD::VMOVRRD &&
       Op0.getNode() == Op1.getNode() &&
       Op0.getResNo() == 0 && Op1.getResNo() == 1)
     return DAG.getNode(ISD::BITCAST, SDLoc(N),
                        N->getValueType(0), Op0.getOperand(0));
   return SDValue();
 }
 
 static SDValue PerformVMOVhrCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
+  SDValue Op0 = N->getOperand(0);
+
+  // VMOVhr (VMOVrh (X)) -> X
+  if (Op0->getOpcode() == ARMISD::VMOVrh)
+    return Op0->getOperand(0);
+
   // FullFP16: half values are passed in S-registers, and we don't
   // need any of the bitcast and moves:
   //
   //     t2: f32,ch = CopyFromReg t0, Register:f32 %0
   //   t5: i32 = bitcast t2
   // t18: f16 = ARMISD::VMOVhr t5
-  SDValue Op0 = N->getOperand(0);
   if (Op0->getOpcode() == ISD::BITCAST) {
     SDValue Copy = Op0->getOperand(0);
     if (Copy.getValueType() == MVT::f32 &&
         Copy->getOpcode() == ISD::CopyFromReg) {
       SDValue Ops[] = {Copy->getOperand(0), Copy->getOperand(1)};
       SDValue NewCopy =
           DCI.DAG.getNode(ISD::CopyFromReg, SDLoc(N), MVT::f16, Ops);
       return NewCopy;
static SDValue PerformVMOVhrCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
   return SDValue();
 }
 
 static SDValue PerformVMOVrhCombine(SDNode *N,
                                     TargetLowering::DAGCombinerInfo &DCI) {
   SDValue N0 = N->getOperand(0);
   EVT VT = N->getValueType(0);
 
+  // VMOVrh (VMOVhr (X)) -> X
+  if (N0->getOpcode() == ARMISD::VMOVhr)
+    return N0->getOperand(0);
+
   // fold (VMOVrh (load x)) -> (zextload (i16*)x)
   if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse()) {
     LoadSDNode *LN0 = cast<LoadSDNode>(N0);
 
     SDValue Load =
         DCI.DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N), VT, LN0->getChain(),
                            LN0->getBasePtr(), MVT::i16, LN0->getMemOperand());
     DCI.DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Load.getValue(0));

llvm/test/CodeGen/Thumb2/mve-vdup.ll

 }
 
 define arm_aapcs_vfpcc half @vdup_f16_extract(half* %src1, half* %src2) {
 ; CHECK-LABEL: vdup_f16_extract:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    vldr.16 s0, [r2]
 ; CHECK-NEXT:    vldr.16 s2, [r1]
 ; CHECK-NEXT:    vadd.f16 s0, s2, s0
-; CHECK-NEXT:    vmov.f16 r1, s0
-; CHECK-NEXT:    vmov.f16 s0, r1
 ; CHECK-NEXT:    vstr.16 s0, [r0]
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = load half, half *%src1, align 2
   %1 = load half, half *%src2, align 2
   %2 = fadd half %0, %1
   %bc = bitcast half %2 to i16
   %3 = insertelement <8 x i16> undef, i16 %bc, i32 0
   %out = shufflevector <8 x i16> %3, <8 x i16> undef, <8 x i32> zeroinitializer
   %outbc = bitcast <8 x i16> %out to <8 x half>
   %ext = extractelement <8 x half> %outbc, i32 2
   ret half %ext
 }