This is an archive of the discontinued LLVM Phabricator instance.

Differential D78673

[SveEmitter] Use llvm.aarch64.sve.ld1/st1 for contiguous load/store builtins
ClosedPublic

Authored by sdesmalen on Apr 22 2020, 2:24 PM.

Details

Reviewers
SjoerdMeijer
efriedma
kmclaughlin
rengolin
Commits
rG7003a1da37b2: [SveEmitter] Use llvm.aarch64.sve.ld1/st1 for contiguous load/store builtins
Summary

This patch changes the codegen of the builtins for contiguous loads
to map onto the SVE specific IR intrinsics llvm.aarch64.sve.ld1/st1.

Diff Detail

Event Timeline

sdesmalen created this revision.Apr 22 2020, 2:24 PM
Herald added a reviewer: rengolin. · View Herald TranscriptApr 22 2020, 2:24 PM
Herald added a project: Restricted Project. · View Herald Transcript
Herald added subscribers: danielkiss, kristof.beyls, tschuett. · View Herald Transcript
sdesmalen added a child revision: D78674: [SveEmitter] Add builtins for contiguous prefetches.Apr 22 2020, 2:44 PM
efriedma accepted this revision.Apr 22 2020, 3:05 PM

LGTM

This revision is now accepted and ready to land.Apr 22 2020, 3:05 PM
Harbormaster failed remote builds in B54311: Diff 259389!Apr 22 2020, 3:16 PM
Closed by commit rG7003a1da37b2: [SveEmitter] Use llvm.aarch64.sve.ld1/st1 for contiguous load/store builtins (authored by sdesmalen). · Explain WhyApr 23 2020, 7:33 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
clang/
include/
clang/
Basic/
56 lines
lib/
CodeGen/
17 lines
test/
CodeGen/
aarch64-sve-intrinsics/
117 lines
54 lines
36 lines
18 lines
54 lines
36 lines
18 lines
120 lines
42 lines
28 lines
14 lines

Diff 259567

clang/include/clang/Basic/arm_sve.td

Show First 20 Lines • Show All 224 Lines • ▼ Show 20 Linesclass MInst<string n, string p, string t, list<FlagType> f,
MemEltType met = MemEltTyDefault, string i = ""> MemEltType met = MemEltTyDefault, string i = "">
: Inst<n, p, t, MergeNone, i, f, [], met> { : Inst<n, p, t, MergeNone, i, f, [], met> {
} }
//////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////
// Loads // Loads
// Load one vector (scalar base) // Load one vector (scalar base)
def SVLD1 : MInst<"svld1[_{2}]", "dPc", "csilUcUsUiUlhfd", [IsLoad]>; def SVLD1 : MInst<"svld1[_{2}]", "dPc", "csilUcUsUiUlhfd", [IsLoad], MemEltTyDefault, "aarch64_sve_ld1">;
def SVLD1SB : MInst<"svld1sb_{d}", "dPS", "silUsUiUl", [IsLoad], MemEltTyInt8>; def SVLD1SB : MInst<"svld1sb_{d}", "dPS", "silUsUiUl", [IsLoad], MemEltTyInt8, "aarch64_sve_ld1">;
def SVLD1UB : MInst<"svld1ub_{d}", "dPW", "silUsUiUl", [IsLoad, IsZExtReturn], MemEltTyInt8>; def SVLD1UB : MInst<"svld1ub_{d}", "dPW", "silUsUiUl", [IsLoad, IsZExtReturn], MemEltTyInt8, "aarch64_sve_ld1">;
def SVLD1SH : MInst<"svld1sh_{d}", "dPT", "ilUiUl", [IsLoad], MemEltTyInt16>; def SVLD1SH : MInst<"svld1sh_{d}", "dPT", "ilUiUl", [IsLoad], MemEltTyInt16, "aarch64_sve_ld1">;
def SVLD1UH : MInst<"svld1uh_{d}", "dPX", "ilUiUl", [IsLoad, IsZExtReturn], MemEltTyInt16>; def SVLD1UH : MInst<"svld1uh_{d}", "dPX", "ilUiUl", [IsLoad, IsZExtReturn], MemEltTyInt16, "aarch64_sve_ld1">;
def SVLD1SW : MInst<"svld1sw_{d}", "dPU", "lUl", [IsLoad], MemEltTyInt32>; def SVLD1SW : MInst<"svld1sw_{d}", "dPU", "lUl", [IsLoad], MemEltTyInt32, "aarch64_sve_ld1">;
def SVLD1UW : MInst<"svld1uw_{d}", "dPY", "lUl", [IsLoad, IsZExtReturn], MemEltTyInt32>; def SVLD1UW : MInst<"svld1uw_{d}", "dPY", "lUl", [IsLoad, IsZExtReturn], MemEltTyInt32, "aarch64_sve_ld1">;
// Load one vector (scalar base, VL displacement) // Load one vector (scalar base, VL displacement)
def SVLD1_VNUM : MInst<"svld1_vnum[_{2}]", "dPcl", "csilUcUsUiUlhfd", [IsLoad]>; def SVLD1_VNUM : MInst<"svld1_vnum[_{2}]", "dPcl", "csilUcUsUiUlhfd", [IsLoad], MemEltTyDefault, "aarch64_sve_ld1">;
def SVLD1SB_VNUM : MInst<"svld1sb_vnum_{d}", "dPSl", "silUsUiUl", [IsLoad], MemEltTyInt8>; def SVLD1SB_VNUM : MInst<"svld1sb_vnum_{d}", "dPSl", "silUsUiUl", [IsLoad], MemEltTyInt8, "aarch64_sve_ld1">;
def SVLD1UB_VNUM : MInst<"svld1ub_vnum_{d}", "dPWl", "silUsUiUl", [IsLoad, IsZExtReturn], MemEltTyInt8>; def SVLD1UB_VNUM : MInst<"svld1ub_vnum_{d}", "dPWl", "silUsUiUl", [IsLoad, IsZExtReturn], MemEltTyInt8, "aarch64_sve_ld1">;
def SVLD1SH_VNUM : MInst<"svld1sh_vnum_{d}", "dPTl", "ilUiUl", [IsLoad], MemEltTyInt16>; def SVLD1SH_VNUM : MInst<"svld1sh_vnum_{d}", "dPTl", "ilUiUl", [IsLoad], MemEltTyInt16, "aarch64_sve_ld1">;
def SVLD1UH_VNUM : MInst<"svld1uh_vnum_{d}", "dPXl", "ilUiUl", [IsLoad, IsZExtReturn], MemEltTyInt16>; def SVLD1UH_VNUM : MInst<"svld1uh_vnum_{d}", "dPXl", "ilUiUl", [IsLoad, IsZExtReturn], MemEltTyInt16, "aarch64_sve_ld1">;
def SVLD1SW_VNUM : MInst<"svld1sw_vnum_{d}", "dPUl", "lUl", [IsLoad], MemEltTyInt32>; def SVLD1SW_VNUM : MInst<"svld1sw_vnum_{d}", "dPUl", "lUl", [IsLoad], MemEltTyInt32, "aarch64_sve_ld1">;
def SVLD1UW_VNUM : MInst<"svld1uw_vnum_{d}", "dPYl", "lUl", [IsLoad, IsZExtReturn], MemEltTyInt32>; def SVLD1UW_VNUM : MInst<"svld1uw_vnum_{d}", "dPYl", "lUl", [IsLoad, IsZExtReturn], MemEltTyInt32, "aarch64_sve_ld1">;
// Load one vector (vector base) // Load one vector (vector base)
def SVLD1_GATHER_BASES_U : MInst<"svld1_gather[_{2}base]_{d}", "dPu", "ilUiUlfd", [IsGatherLoad], MemEltTyDefault, "aarch64_sve_ld1_gather_scalar_offset">; def SVLD1_GATHER_BASES_U : MInst<"svld1_gather[_{2}base]_{d}", "dPu", "ilUiUlfd", [IsGatherLoad], MemEltTyDefault, "aarch64_sve_ld1_gather_scalar_offset">;
def SVLD1SB_GATHER_BASES_U : MInst<"svld1sb_gather[_{2}base]_{d}", "dPu", "ilUiUl", [IsGatherLoad], MemEltTyInt8, "aarch64_sve_ld1_gather_scalar_offset">; def SVLD1SB_GATHER_BASES_U : MInst<"svld1sb_gather[_{2}base]_{d}", "dPu", "ilUiUl", [IsGatherLoad], MemEltTyInt8, "aarch64_sve_ld1_gather_scalar_offset">;
def SVLD1UB_GATHER_BASES_U : MInst<"svld1ub_gather[_{2}base]_{d}", "dPu", "ilUiUl", [IsGatherLoad, IsZExtReturn], MemEltTyInt8, "aarch64_sve_ld1_gather_scalar_offset">; def SVLD1UB_GATHER_BASES_U : MInst<"svld1ub_gather[_{2}base]_{d}", "dPu", "ilUiUl", [IsGatherLoad, IsZExtReturn], MemEltTyInt8, "aarch64_sve_ld1_gather_scalar_offset">;
def SVLD1SH_GATHER_BASES_U : MInst<"svld1sh_gather[_{2}base]_{d}", "dPu", "ilUiUl", [IsGatherLoad], MemEltTyInt16, "aarch64_sve_ld1_gather_scalar_offset">; def SVLD1SH_GATHER_BASES_U : MInst<"svld1sh_gather[_{2}base]_{d}", "dPu", "ilUiUl", [IsGatherLoad], MemEltTyInt16, "aarch64_sve_ld1_gather_scalar_offset">;
def SVLD1UH_GATHER_BASES_U : MInst<"svld1uh_gather[_{2}base]_{d}", "dPu", "ilUiUl", [IsGatherLoad, IsZExtReturn], MemEltTyInt16, "aarch64_sve_ld1_gather_scalar_offset">; def SVLD1UH_GATHER_BASES_U : MInst<"svld1uh_gather[_{2}base]_{d}", "dPu", "ilUiUl", [IsGatherLoad, IsZExtReturn], MemEltTyInt16, "aarch64_sve_ld1_gather_scalar_offset">;
def SVLD1SW_GATHER_BASES_U : MInst<"svld1sw_gather[_{2}base]_{d}", "dPu", "lUl", [IsGatherLoad], MemEltTyInt32, "aarch64_sve_ld1_gather_scalar_offset">; def SVLD1SW_GATHER_BASES_U : MInst<"svld1sw_gather[_{2}base]_{d}", "dPu", "lUl", [IsGatherLoad], MemEltTyInt32, "aarch64_sve_ld1_gather_scalar_offset">;
▲ Show 20 Lines • Show All 187 Lines • ▼ Show 20 Lines
// Load one vector, unextended load, non-temporal (scalar base, VL displacement) // Load one vector, unextended load, non-temporal (scalar base, VL displacement)
def SVLDNT1_VNUM : MInst<"svldnt1_vnum[_{2}]", "dPcl", "csilUcUsUiUlhfd", [IsLoad], MemEltTyDefault, "aarch64_sve_ldnt1">; def SVLDNT1_VNUM : MInst<"svldnt1_vnum[_{2}]", "dPcl", "csilUcUsUiUlhfd", [IsLoad], MemEltTyDefault, "aarch64_sve_ldnt1">;
//////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////
// Stores // Stores
// Store one vector (scalar base) // Store one vector (scalar base)
def SVST1 : MInst<"svst1[_{d}]", "vPpd", "csilUcUsUiUlhfd", [IsStore]>; def SVST1 : MInst<"svst1[_{d}]", "vPpd", "csilUcUsUiUlhfd", [IsStore], MemEltTyDefault, "aarch64_sve_st1">;
def SVST1B_S : MInst<"svst1b[_{d}]", "vPAd", "sil", [IsStore], MemEltTyInt8>; def SVST1B_S : MInst<"svst1b[_{d}]", "vPAd", "sil", [IsStore], MemEltTyInt8, "aarch64_sve_st1">;
def SVST1B_U : MInst<"svst1b[_{d}]", "vPEd", "UsUiUl", [IsStore], MemEltTyInt8>; def SVST1B_U : MInst<"svst1b[_{d}]", "vPEd", "UsUiUl", [IsStore], MemEltTyInt8, "aarch64_sve_st1">;
def SVST1H_S : MInst<"svst1h[_{d}]", "vPBd", "il", [IsStore], MemEltTyInt16>; def SVST1H_S : MInst<"svst1h[_{d}]", "vPBd", "il", [IsStore], MemEltTyInt16, "aarch64_sve_st1">;
def SVST1H_U : MInst<"svst1h[_{d}]", "vPFd", "UiUl", [IsStore], MemEltTyInt16>; def SVST1H_U : MInst<"svst1h[_{d}]", "vPFd", "UiUl", [IsStore], MemEltTyInt16, "aarch64_sve_st1">;
def SVST1W_S : MInst<"svst1w[_{d}]", "vPCd", "l", [IsStore], MemEltTyInt32>; def SVST1W_S : MInst<"svst1w[_{d}]", "vPCd", "l", [IsStore], MemEltTyInt32, "aarch64_sve_st1">;
def SVST1W_U : MInst<"svst1w[_{d}]", "vPGd", "Ul", [IsStore], MemEltTyInt32>; def SVST1W_U : MInst<"svst1w[_{d}]", "vPGd", "Ul", [IsStore], MemEltTyInt32, "aarch64_sve_st1">;
// Store one vector (scalar base, VL displacement) // Store one vector (scalar base, VL displacement)
def SVST1_VNUM : MInst<"svst1_vnum[_{d}]", "vPpld", "csilUcUsUiUlhfd", [IsStore]>; def SVST1_VNUM : MInst<"svst1_vnum[_{d}]", "vPpld", "csilUcUsUiUlhfd", [IsStore], MemEltTyDefault, "aarch64_sve_st1">;
def SVST1B_VNUM_S : MInst<"svst1b_vnum[_{d}]", "vPAld", "sil", [IsStore], MemEltTyInt8>; def SVST1B_VNUM_S : MInst<"svst1b_vnum[_{d}]", "vPAld", "sil", [IsStore], MemEltTyInt8, "aarch64_sve_st1">;
def SVST1B_VNUM_U : MInst<"svst1b_vnum[_{d}]", "vPEld", "UsUiUl", [IsStore], MemEltTyInt8>; def SVST1B_VNUM_U : MInst<"svst1b_vnum[_{d}]", "vPEld", "UsUiUl", [IsStore], MemEltTyInt8, "aarch64_sve_st1">;
def SVST1H_VNUM_S : MInst<"svst1h_vnum[_{d}]", "vPBld", "il", [IsStore], MemEltTyInt16>; def SVST1H_VNUM_S : MInst<"svst1h_vnum[_{d}]", "vPBld", "il", [IsStore], MemEltTyInt16, "aarch64_sve_st1">;
def SVST1H_VNUM_U : MInst<"svst1h_vnum[_{d}]", "vPFld", "UiUl", [IsStore], MemEltTyInt16>; def SVST1H_VNUM_U : MInst<"svst1h_vnum[_{d}]", "vPFld", "UiUl", [IsStore], MemEltTyInt16, "aarch64_sve_st1">;
def SVST1W_VNUM_S : MInst<"svst1w_vnum[_{d}]", "vPCld", "l", [IsStore], MemEltTyInt32>; def SVST1W_VNUM_S : MInst<"svst1w_vnum[_{d}]", "vPCld", "l", [IsStore], MemEltTyInt32, "aarch64_sve_st1">;
def SVST1W_VNUM_U : MInst<"svst1w_vnum[_{d}]", "vPGld", "Ul", [IsStore], MemEltTyInt32>; def SVST1W_VNUM_U : MInst<"svst1w_vnum[_{d}]", "vPGld", "Ul", [IsStore], MemEltTyInt32, "aarch64_sve_st1">;
// Store one vector, with no truncation, non-temporal (scalar base) // Store one vector, with no truncation, non-temporal (scalar base)
def SVSTNT1 : MInst<"svstnt1[_{d}]", "vPpd", "csilUcUsUiUlhfd", [IsStore], MemEltTyDefault, "aarch64_sve_stnt1">; def SVSTNT1 : MInst<"svstnt1[_{d}]", "vPpd", "csilUcUsUiUlhfd", [IsStore], MemEltTyDefault, "aarch64_sve_stnt1">;
// Store one vector, with no truncation, non-temporal (scalar base, VL displacement) // Store one vector, with no truncation, non-temporal (scalar base, VL displacement)
def SVSTNT1_VNUM : MInst<"svstnt1_vnum[_{d}]", "vPpld", "csilUcUsUiUlhfd", [IsStore], MemEltTyDefault, "aarch64_sve_stnt1">; def SVSTNT1_VNUM : MInst<"svstnt1_vnum[_{d}]", "vPpld", "csilUcUsUiUlhfd", [IsStore], MemEltTyDefault, "aarch64_sve_stnt1">;
//////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////
▲ Show 20 Lines • Show All 354 Lines • Show Last 20 Lines

clang/lib/CodeGen/CGBuiltin.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 7,720 Lines • ▼ Show 20 LinesValue *CodeGenFunction::EmitSVEMaskedLoad(const CallExpr *E,
auto VectorTy = cast<llvm::VectorType>(ReturnTy); auto VectorTy = cast<llvm::VectorType>(ReturnTy);
auto MemoryTy = llvm::VectorType::get(MemEltTy, VectorTy->getElementCount()); auto MemoryTy = llvm::VectorType::get(MemEltTy, VectorTy->getElementCount());
Value *Predicate = EmitSVEPredicateCast(Ops[0], MemoryTy); Value *Predicate = EmitSVEPredicateCast(Ops[0], MemoryTy);
Value *BasePtr = Builder.CreateBitCast(Ops[1], MemoryTy->getPointerTo()); Value *BasePtr = Builder.CreateBitCast(Ops[1], MemoryTy->getPointerTo());
Value *Offset = Ops.size() > 2 ? Ops[2] : Builder.getInt32(0); Value *Offset = Ops.size() > 2 ? Ops[2] : Builder.getInt32(0);
BasePtr = Builder.CreateGEP(MemoryTy, BasePtr, Offset); BasePtr = Builder.CreateGEP(MemoryTy, BasePtr, Offset);
Value *Splat0 = Constant::getNullValue(MemoryTy);
Value *Load = nullptr;
if (!BuiltinID)
// Regular masked loads take a different path from the SVE-specific ones.
Load = Builder.CreateMaskedLoad(BasePtr, llvm::Align(1), Predicate, Splat0);
else {
BasePtr = Builder.CreateBitCast(BasePtr, MemEltTy->getPointerTo()); BasePtr = Builder.CreateBitCast(BasePtr, MemEltTy->getPointerTo());
Function *F = CGM.getIntrinsic(BuiltinID, MemoryTy); Function *F = CGM.getIntrinsic(BuiltinID, MemoryTy);
Load = Builder.CreateCall(F, {Predicate, BasePtr}); Value *Load = Builder.CreateCall(F, {Predicate, BasePtr});
}
return IsZExtReturn ? Builder.CreateZExt(Load, VectorTy) return IsZExtReturn ? Builder.CreateZExt(Load, VectorTy)
: Builder.CreateSExt(Load, VectorTy); : Builder.CreateSExt(Load, VectorTy);
} }
Value *CodeGenFunction::EmitSVEMaskedStore(const CallExpr *E, Value *CodeGenFunction::EmitSVEMaskedStore(const CallExpr *E,
SmallVectorImpl<Value *> &Ops, SmallVectorImpl<Value *> &Ops,
unsigned BuiltinID) { unsigned BuiltinID) {
Show All 9 LinesValue *CodeGenFunction::EmitSVEMaskedStore(const CallExpr *E,
Value *Predicate = EmitSVEPredicateCast(Ops[0], MemoryTy); Value *Predicate = EmitSVEPredicateCast(Ops[0], MemoryTy);
Value *BasePtr = Builder.CreateBitCast(Ops[1], MemoryTy->getPointerTo()); Value *BasePtr = Builder.CreateBitCast(Ops[1], MemoryTy->getPointerTo());
Value *Offset = Ops.size() == 4 ? Ops[2] : Builder.getInt32(0); Value *Offset = Ops.size() == 4 ? Ops[2] : Builder.getInt32(0);
BasePtr = Builder.CreateGEP(MemoryTy, BasePtr, Offset); BasePtr = Builder.CreateGEP(MemoryTy, BasePtr, Offset);
// Last value is always the data // Last value is always the data
llvm::Value *Val = Builder.CreateTrunc(Ops.back(), MemoryTy); llvm::Value *Val = Builder.CreateTrunc(Ops.back(), MemoryTy);
if (!BuiltinID)
return Builder.CreateMaskedStore(Val, BasePtr, llvm::Align(1), Predicate);
BasePtr = Builder.CreateBitCast(BasePtr, MemEltTy->getPointerTo()); BasePtr = Builder.CreateBitCast(BasePtr, MemEltTy->getPointerTo());
Function *F = CGM.getIntrinsic(BuiltinID, MemoryTy); Function *F = CGM.getIntrinsic(BuiltinID, MemoryTy);
return Builder.CreateCall(F, {Val, Predicate, BasePtr}); return Builder.CreateCall(F, {Val, Predicate, BasePtr});
} }
constexpr unsigned SVEBitsPerBlock = 128; constexpr unsigned SVEBitsPerBlock = 128;
static llvm::VectorType* getSVEVectorForElementType(llvm::Type *EltTy) { static llvm::VectorType* getSVEVectorForElementType(llvm::Type *EltTy) {
▲ Show 20 Lines • Show All 8,200 Lines • Show Last 20 Lines

clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1.c

// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s // RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s
// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s // RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s
#include <arm_sve.h> #include <arm_sve.h>
#ifdef SVE_OVERLOADED_FORMS #ifdef SVE_OVERLOADED_FORMS
// A simple used,unused... macro, long enough to represent any SVE builtin. // A simple used,unused... macro, long enough to represent any SVE builtin.
#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3 #define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
#else #else
#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4 #define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
#endif #endif
svint8_t test_svld1_s8(svbool_t pg, const int8_t *base) svint8_t test_svld1_s8(svbool_t pg, const int8_t *base)
{ {
// CHECK-LABEL: test_svld1_s8 // CHECK-LABEL: test_svld1_s8
// CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to <vscale x 16 x i8>* // CHECK: %[[LOAD:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1.nxv16i8(<vscale x 16 x i1> %pg, i8* %base)
// CHECK-DAG: %[[LOAD:.*]] = call <vscale x 16 x i8> @llvm.masked.load.nxv16i8.p0nxv16i8(<vscale x 16 x i8>* %[[BASE]], i32 1, <vscale x 16 x i1> %pg, <vscale x 16 x i8> zeroinitializer)
// CHECK: ret <vscale x 16 x i8> %[[LOAD]] // CHECK: ret <vscale x 16 x i8> %[[LOAD]]
return SVE_ACLE_FUNC(svld1,_s8,,)(pg, base); return SVE_ACLE_FUNC(svld1,_s8,,)(pg, base);
} }
svint16_t test_svld1_s16(svbool_t pg, const int16_t *base) svint16_t test_svld1_s16(svbool_t pg, const int16_t *base)
{ {
// CHECK-LABEL: test_svld1_s16 // CHECK-LABEL: test_svld1_s16
// CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg) // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to <vscale x 8 x i16>* // CHECK: %[[LOAD:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.ld1.nxv8i16(<vscale x 8 x i1> %[[PG]], i16* %base)
// CHECK: %[[LOAD:.*]] = call <vscale x 8 x i16> @llvm.masked.load.nxv8i16.p0nxv8i16(<vscale x 8 x i16>* %[[BASE]], i32 1, <vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> zeroinitializer)
// CHECK: ret <vscale x 8 x i16> %[[LOAD]] // CHECK: ret <vscale x 8 x i16> %[[LOAD]]
return SVE_ACLE_FUNC(svld1,_s16,,)(pg, base); return SVE_ACLE_FUNC(svld1,_s16,,)(pg, base);
} }
svint32_t test_svld1_s32(svbool_t pg, const int32_t *base) svint32_t test_svld1_s32(svbool_t pg, const int32_t *base)
{ {
// CHECK-LABEL: test_svld1_s32 // CHECK-LABEL: test_svld1_s32
// CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg) // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i32* %base to <vscale x 4 x i32>* // CHECK: %[[LOAD:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1.nxv4i32(<vscale x 4 x i1> %[[PG]], i32* %base)
// CHECK: %[[LOAD:.*]] = call <vscale x 4 x i32> @llvm.masked.load.nxv4i32.p0nxv4i32(<vscale x 4 x i32>* %[[BASE]], i32 1, <vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> zeroinitializer)
// CHECK: ret <vscale x 4 x i32> %[[LOAD]] // CHECK: ret <vscale x 4 x i32> %[[LOAD]]
return SVE_ACLE_FUNC(svld1,_s32,,)(pg, base); return SVE_ACLE_FUNC(svld1,_s32,,)(pg, base);
} }
svint64_t test_svld1_s64(svbool_t pg, const int64_t *base) svint64_t test_svld1_s64(svbool_t pg, const int64_t *base)
{ {
// CHECK-LABEL: test_svld1_s64 // CHECK-LABEL: test_svld1_s64
// CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg) // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i64* %base to <vscale x 2 x i64>* // CHECK: %[[LOAD:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1.nxv2i64(<vscale x 2 x i1> %[[PG]], i64* %base)
// CHECK: %[[LOAD:.*]] = call <vscale x 2 x i64> @llvm.masked.load.nxv2i64.p0nxv2i64(<vscale x 2 x i64>* %[[BASE]], i32 1, <vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> zeroinitializer)
// CHECK: ret <vscale x 2 x i64> %[[LOAD]] // CHECK: ret <vscale x 2 x i64> %[[LOAD]]
return SVE_ACLE_FUNC(svld1,_s64,,)(pg, base); return SVE_ACLE_FUNC(svld1,_s64,,)(pg, base);
} }
svuint8_t test_svld1_u8(svbool_t pg, const uint8_t *base) svuint8_t test_svld1_u8(svbool_t pg, const uint8_t *base)
{ {
// CHECK-LABEL: test_svld1_u8 // CHECK-LABEL: test_svld1_u8
// CHECK: %[[BASE:.*]] = bitcast i8* %base to <vscale x 16 x i8>* // CHECK: %[[LOAD:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1.nxv16i8(<vscale x 16 x i1> %pg, i8* %base)
// CHECK: %[[LOAD:.*]] = call <vscale x 16 x i8> @llvm.masked.load.nxv16i8.p0nxv16i8(<vscale x 16 x i8>* %[[BASE]], i32 1, <vscale x 16 x i1> %pg, <vscale x 16 x i8> zeroinitializer)
// CHECK: ret <vscale x 16 x i8> %[[LOAD]] // CHECK: ret <vscale x 16 x i8> %[[LOAD]]
return SVE_ACLE_FUNC(svld1,_u8,,)(pg, base); return SVE_ACLE_FUNC(svld1,_u8,,)(pg, base);
} }
svuint16_t test_svld1_u16(svbool_t pg, const uint16_t *base) svuint16_t test_svld1_u16(svbool_t pg, const uint16_t *base)
{ {
// CHECK-LABEL: test_svld1_u16 // CHECK-LABEL: test_svld1_u16
// CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg) // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to <vscale x 8 x i16>* // CHECK: %[[LOAD:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.ld1.nxv8i16(<vscale x 8 x i1> %[[PG]], i16* %base)
// CHECK: %[[LOAD:.*]] = call <vscale x 8 x i16> @llvm.masked.load.nxv8i16.p0nxv8i16(<vscale x 8 x i16>* %[[BASE]], i32 1, <vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> zeroinitializer)
// CHECK: ret <vscale x 8 x i16> %[[LOAD]] // CHECK: ret <vscale x 8 x i16> %[[LOAD]]
return SVE_ACLE_FUNC(svld1,_u16,,)(pg, base); return SVE_ACLE_FUNC(svld1,_u16,,)(pg, base);
} }
svuint32_t test_svld1_u32(svbool_t pg, const uint32_t *base) svuint32_t test_svld1_u32(svbool_t pg, const uint32_t *base)
{ {
// CHECK-LABEL: test_svld1_u32 // CHECK-LABEL: test_svld1_u32
// CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg) // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i32* %base to <vscale x 4 x i32>* // CHECK: %[[LOAD:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1.nxv4i32(<vscale x 4 x i1> %[[PG]], i32* %base)
// CHECK: %[[LOAD:.*]] = call <vscale x 4 x i32> @llvm.masked.load.nxv4i32.p0nxv4i32(<vscale x 4 x i32>* %[[BASE]], i32 1, <vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> zeroinitializer)
// CHECK: ret <vscale x 4 x i32> %[[LOAD]] // CHECK: ret <vscale x 4 x i32> %[[LOAD]]
return SVE_ACLE_FUNC(svld1,_u32,,)(pg, base); return SVE_ACLE_FUNC(svld1,_u32,,)(pg, base);
} }
svuint64_t test_svld1_u64(svbool_t pg, const uint64_t *base) svuint64_t test_svld1_u64(svbool_t pg, const uint64_t *base)
{ {
// CHECK-LABEL: test_svld1_u64 // CHECK-LABEL: test_svld1_u64
// CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg) // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i64* %base to <vscale x 2 x i64>* // CHECK: %[[LOAD:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1.nxv2i64(<vscale x 2 x i1> %[[PG]], i64* %base)
// CHECK: %[[LOAD:.*]] = call <vscale x 2 x i64> @llvm.masked.load.nxv2i64.p0nxv2i64(<vscale x 2 x i64>* %[[BASE]], i32 1, <vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> zeroinitializer)
// CHECK: ret <vscale x 2 x i64> %[[LOAD]] // CHECK: ret <vscale x 2 x i64> %[[LOAD]]
return SVE_ACLE_FUNC(svld1,_u64,,)(pg, base); return SVE_ACLE_FUNC(svld1,_u64,,)(pg, base);
} }
svfloat16_t test_svld1_f16(svbool_t pg, const float16_t *base) svfloat16_t test_svld1_f16(svbool_t pg, const float16_t *base)
{ {
// CHECK-LABEL: test_svld1_f16 // CHECK-LABEL: test_svld1_f16
// CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg) // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast half* %base to <vscale x 8 x half>* // CHECK: %[[LOAD:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.ld1.nxv8f16(<vscale x 8 x i1> %[[PG]], half* %base)
// CHECK: %[[LOAD:.*]] = call <vscale x 8 x half> @llvm.masked.load.nxv8f16.p0nxv8f16(<vscale x 8 x half>* %[[BASE]], i32 1, <vscale x 8 x i1> %[[PG]], <vscale x 8 x half> zeroinitializer)
// CHECK: ret <vscale x 8 x half> %[[LOAD]] // CHECK: ret <vscale x 8 x half> %[[LOAD]]
return SVE_ACLE_FUNC(svld1,_f16,,)(pg, base); return SVE_ACLE_FUNC(svld1,_f16,,)(pg, base);
} }
svfloat32_t test_svld1_f32(svbool_t pg, const float32_t *base) svfloat32_t test_svld1_f32(svbool_t pg, const float32_t *base)
{ {
// CHECK-LABEL: test_svld1_f32 // CHECK-LABEL: test_svld1_f32
// CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg) // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast float* %base to <vscale x 4 x float>* // CHECK: %[[LOAD:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.ld1.nxv4f32(<vscale x 4 x i1> %[[PG]], float* %base)
// CHECK: %[[LOAD:.*]] = call <vscale x 4 x float> @llvm.masked.load.nxv4f32.p0nxv4f32(<vscale x 4 x float>* %[[BASE]], i32 1, <vscale x 4 x i1> %[[PG]], <vscale x 4 x float> zeroinitializer)
// CHECK: ret <vscale x 4 x float> %[[LOAD]] // CHECK: ret <vscale x 4 x float> %[[LOAD]]
return SVE_ACLE_FUNC(svld1,_f32,,)(pg, base); return SVE_ACLE_FUNC(svld1,_f32,,)(pg, base);
} }
svfloat64_t test_svld1_f64(svbool_t pg, const float64_t *base) svfloat64_t test_svld1_f64(svbool_t pg, const float64_t *base)
{ {
// CHECK-LABEL: test_svld1_f64 // CHECK-LABEL: test_svld1_f64
// CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg) // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast double* %base to <vscale x 2 x double>* // CHECK: %[[LOAD:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.ld1.nxv2f64(<vscale x 2 x i1> %[[PG]], double* %base)
// CHECK: %[[LOAD:.*]] = call <vscale x 2 x double> @llvm.masked.load.nxv2f64.p0nxv2f64(<vscale x 2 x double>* %[[BASE]], i32 1, <vscale x 2 x i1> %[[PG]], <vscale x 2 x double> zeroinitializer)
// CHECK: ret <vscale x 2 x double> %[[LOAD]] // CHECK: ret <vscale x 2 x double> %[[LOAD]]
return SVE_ACLE_FUNC(svld1,_f64,,)(pg, base); return SVE_ACLE_FUNC(svld1,_f64,,)(pg, base);
} }
svint8_t test_svld1_vnum_s8(svbool_t pg, const int8_t *base, int64_t vnum) svint8_t test_svld1_vnum_s8(svbool_t pg, const int8_t *base, int64_t vnum)
{ {
// CHECK-LABEL: test_svld1_vnum_s8 // CHECK-LABEL: test_svld1_vnum_s8
// CHECK: %[[BASE:.*]] = bitcast i8* %base to <vscale x 16 x i8>* // CHECK: %[[BITCAST:.*]] = bitcast i8* %base to <vscale x 16 x i8>*
// CHECK: %[[GEP:.*]] = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %[[BASE]], i64 %vnum // CHECK: %[[GEP:.*]] = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %[[BITCAST]], i64 %vnum, i64 0
// CHECK: %[[LOAD:.*]] = call <vscale x 16 x i8> @llvm.masked.load.nxv16i8.p0nxv16i8(<vscale x 16 x i8>* %[[GEP]], i32 1, <vscale x 16 x i1> %pg, <vscale x 16 x i8> zeroinitializer) // CHECK: %[[LOAD:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1.nxv16i8(<vscale x 16 x i1> %pg, i8* %[[GEP]])
// CHECK: ret <vscale x 16 x i8> %[[LOAD]] // CHECK: ret <vscale x 16 x i8> %[[LOAD]]
return SVE_ACLE_FUNC(svld1_vnum,_s8,,)(pg, base, vnum); return SVE_ACLE_FUNC(svld1_vnum,_s8,,)(pg, base, vnum);
} }
svint16_t test_svld1_vnum_s16(svbool_t pg, const int16_t *base, int64_t vnum) svint16_t test_svld1_vnum_s16(svbool_t pg, const int16_t *base, int64_t vnum)
{ {
// CHECK-LABEL: test_svld1_vnum_s16 // CHECK-LABEL: test_svld1_vnum_s16
// CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to <vscale x 8 x i16>* // CHECK-DAG: %[[BITCAST:.*]] = bitcast i16* %base to <vscale x 8 x i16>*
// CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 8 x i16>, <vscale x 8 x i16>* %[[BASE]], i64 %vnum // CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 8 x i16>, <vscale x 8 x i16>* %[[BITCAST]], i64 %vnum, i64 0
// CHECK: %[[LOAD:.*]] = call <vscale x 8 x i16> @llvm.masked.load.nxv8i16.p0nxv8i16(<vscale x 8 x i16>* %[[GEP]], i32 1, <vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> zeroinitializer) // CHECK: %[[LOAD:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.ld1.nxv8i16(<vscale x 8 x i1> %[[PG]], i16* %[[GEP]])
// CHECK: ret <vscale x 8 x i16> %[[LOAD]] // CHECK: ret <vscale x 8 x i16> %[[LOAD]]
return SVE_ACLE_FUNC(svld1_vnum,_s16,,)(pg, base, vnum); return SVE_ACLE_FUNC(svld1_vnum,_s16,,)(pg, base, vnum);
} }
svint32_t test_svld1_vnum_s32(svbool_t pg, const int32_t *base, int64_t vnum) svint32_t test_svld1_vnum_s32(svbool_t pg, const int32_t *base, int64_t vnum)
{ {
// CHECK-LABEL: test_svld1_vnum_s32 // CHECK-LABEL: test_svld1_vnum_s32
// CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i32* %base to <vscale x 4 x i32>* // CHECK-DAG: %[[BITCAST:.*]] = bitcast i32* %base to <vscale x 4 x i32>*
// CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* %[[BASE]], i64 %vnum // CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* %[[BITCAST]], i64 %vnum, i64 0
// CHECK: %[[LOAD:.*]] = call <vscale x 4 x i32> @llvm.masked.load.nxv4i32.p0nxv4i32(<vscale x 4 x i32>* %[[GEP]], i32 1, <vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> zeroinitializer) // CHECK: %[[LOAD:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1.nxv4i32(<vscale x 4 x i1> %[[PG]], i32* %[[GEP]])
// CHECK: ret <vscale x 4 x i32> %[[LOAD]] // CHECK: ret <vscale x 4 x i32> %[[LOAD]]
return SVE_ACLE_FUNC(svld1_vnum,_s32,,)(pg, base, vnum); return SVE_ACLE_FUNC(svld1_vnum,_s32,,)(pg, base, vnum);
} }
svint64_t test_svld1_vnum_s64(svbool_t pg, const int64_t *base, int64_t vnum) svint64_t test_svld1_vnum_s64(svbool_t pg, const int64_t *base, int64_t vnum)
{ {
// CHECK-LABEL: test_svld1_vnum_s64 // CHECK-LABEL: test_svld1_vnum_s64
// CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i64* %base to <vscale x 2 x i64>* // CHECK-DAG: %[[BITCAST:.*]] = bitcast i64* %base to <vscale x 2 x i64>*
// CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 2 x i64>, <vscale x 2 x i64>* %[[BASE]], i64 %vnum // CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 2 x i64>, <vscale x 2 x i64>* %[[BITCAST]], i64 %vnum, i64 0
// CHECK: %[[LOAD:.*]] = call <vscale x 2 x i64> @llvm.masked.load.nxv2i64.p0nxv2i64(<vscale x 2 x i64>* %[[GEP]], i32 1, <vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> zeroinitializer) // CHECK: %[[LOAD:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1.nxv2i64(<vscale x 2 x i1> %[[PG]], i64* %[[GEP]])
// CHECK: ret <vscale x 2 x i64> %[[LOAD]] // CHECK: ret <vscale x 2 x i64> %[[LOAD]]
return SVE_ACLE_FUNC(svld1_vnum,_s64,,)(pg, base, vnum); return SVE_ACLE_FUNC(svld1_vnum,_s64,,)(pg, base, vnum);
} }
svuint8_t test_svld1_vnum_u8(svbool_t pg, const uint8_t *base, int64_t vnum) svuint8_t test_svld1_vnum_u8(svbool_t pg, const uint8_t *base, int64_t vnum)
{ {
// CHECK-LABEL: test_svld1_vnum_u8 // CHECK-LABEL: test_svld1_vnum_u8
// CHECK: %[[BASE:.*]] = bitcast i8* %base to <vscale x 16 x i8>* // CHECK: %[[BITCAST:.*]] = bitcast i8* %base to <vscale x 16 x i8>*
// CHECK: %[[GEP:.*]] = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %[[BASE]], i64 %vnum // CHECK: %[[GEP:.*]] = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %[[BITCAST]], i64 %vnum, i64 0
// CHECK: %[[LOAD:.*]] = call <vscale x 16 x i8> @llvm.masked.load.nxv16i8.p0nxv16i8(<vscale x 16 x i8>* %[[GEP]], i32 1, <vscale x 16 x i1> %pg, <vscale x 16 x i8> zeroinitializer) // CHECK: %[[LOAD:.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1.nxv16i8(<vscale x 16 x i1> %pg, i8* %[[GEP]])
// CHECK: ret <vscale x 16 x i8> %[[LOAD]] // CHECK: ret <vscale x 16 x i8> %[[LOAD]]
return SVE_ACLE_FUNC(svld1_vnum,_u8,,)(pg, base, vnum); return SVE_ACLE_FUNC(svld1_vnum,_u8,,)(pg, base, vnum);
} }
svuint16_t test_svld1_vnum_u16(svbool_t pg, const uint16_t *base, int64_t vnum) svuint16_t test_svld1_vnum_u16(svbool_t pg, const uint16_t *base, int64_t vnum)
{ {
// CHECK-LABEL: test_svld1_vnum_u16 // CHECK-LABEL: test_svld1_vnum_u16
// CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to <vscale x 8 x i16>* // CHECK-DAG: %[[BITCAST:.*]] = bitcast i16* %base to <vscale x 8 x i16>*
// CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 8 x i16>, <vscale x 8 x i16>* %[[BASE]], i64 %vnum // CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 8 x i16>, <vscale x 8 x i16>* %[[BITCAST]], i64 %vnum, i64 0
// CHECK: %[[LOAD:.*]] = call <vscale x 8 x i16> @llvm.masked.load.nxv8i16.p0nxv8i16(<vscale x 8 x i16>* %[[GEP]], i32 1, <vscale x 8 x i1> %[[PG]], <vscale x 8 x i16> zeroinitializer) // CHECK: %[[LOAD:.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.ld1.nxv8i16(<vscale x 8 x i1> %[[PG]], i16* %[[GEP]])
// CHECK: ret <vscale x 8 x i16> %[[LOAD]] // CHECK: ret <vscale x 8 x i16> %[[LOAD]]
return SVE_ACLE_FUNC(svld1_vnum,_u16,,)(pg, base, vnum); return SVE_ACLE_FUNC(svld1_vnum,_u16,,)(pg, base, vnum);
} }
svuint32_t test_svld1_vnum_u32(svbool_t pg, const uint32_t *base, int64_t vnum) svuint32_t test_svld1_vnum_u32(svbool_t pg, const uint32_t *base, int64_t vnum)
{ {
// CHECK-LABEL: test_svld1_vnum_u32 // CHECK-LABEL: test_svld1_vnum_u32
// CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i32* %base to <vscale x 4 x i32>* // CHECK-DAG: %[[BITCAST:.*]] = bitcast i32* %base to <vscale x 4 x i32>*
// CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* %[[BASE]], i64 %vnum // CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* %[[BITCAST]], i64 %vnum, i64 0
// CHECK: %[[LOAD:.*]] = call <vscale x 4 x i32> @llvm.masked.load.nxv4i32.p0nxv4i32(<vscale x 4 x i32>* %[[GEP]], i32 1, <vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> zeroinitializer) // CHECK: %[[LOAD:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1.nxv4i32(<vscale x 4 x i1> %[[PG]], i32* %[[GEP]])
// CHECK: ret <vscale x 4 x i32> %[[LOAD]] // CHECK: ret <vscale x 4 x i32> %[[LOAD]]
return SVE_ACLE_FUNC(svld1_vnum,_u32,,)(pg, base, vnum); return SVE_ACLE_FUNC(svld1_vnum,_u32,,)(pg, base, vnum);
} }
svuint64_t test_svld1_vnum_u64(svbool_t pg, const uint64_t *base, int64_t vnum) svuint64_t test_svld1_vnum_u64(svbool_t pg, const uint64_t *base, int64_t vnum)
{ {
// CHECK-LABEL: test_svld1_vnum_u64 // CHECK-LABEL: test_svld1_vnum_u64
// CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i64* %base to <vscale x 2 x i64>* // CHECK-DAG: %[[BITCAST:.*]] = bitcast i64* %base to <vscale x 2 x i64>*
// CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 2 x i64>, <vscale x 2 x i64>* %[[BASE]], i64 %vnum // CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 2 x i64>, <vscale x 2 x i64>* %[[BITCAST]], i64 %vnum, i64 0
// CHECK: %[[LOAD:.*]] = call <vscale x 2 x i64> @llvm.masked.load.nxv2i64.p0nxv2i64(<vscale x 2 x i64>* %[[GEP]], i32 1, <vscale x 2 x i1> %[[PG]], <vscale x 2 x i64> zeroinitializer) // CHECK: %[[LOAD:.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1.nxv2i64(<vscale x 2 x i1> %[[PG]], i64* %[[GEP]])
// CHECK: ret <vscale x 2 x i64> %[[LOAD]] // CHECK: ret <vscale x 2 x i64> %[[LOAD]]
return SVE_ACLE_FUNC(svld1_vnum,_u64,,)(pg, base, vnum); return SVE_ACLE_FUNC(svld1_vnum,_u64,,)(pg, base, vnum);
} }
svfloat16_t test_svld1_vnum_f16(svbool_t pg, const float16_t *base, int64_t vnum) svfloat16_t test_svld1_vnum_f16(svbool_t pg, const float16_t *base, int64_t vnum)
{ {
// CHECK-LABEL: test_svld1_vnum_f16 // CHECK-LABEL: test_svld1_vnum_f16
// CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast half* %base to <vscale x 8 x half>* // CHECK-DAG: %[[BITCAST:.*]] = bitcast half* %base to <vscale x 8 x half>*
// CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 8 x half>, <vscale x 8 x half>* %[[BASE]], i64 %vnum // CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 8 x half>, <vscale x 8 x half>* %[[BITCAST]], i64 %vnum, i64 0
// CHECK: %[[LOAD:.*]] = call <vscale x 8 x half> @llvm.masked.load.nxv8f16.p0nxv8f16(<vscale x 8 x half>* %[[GEP]], i32 1, <vscale x 8 x i1> %[[PG]], <vscale x 8 x half> zeroinitializer) // CHECK: %[[LOAD:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.ld1.nxv8f16(<vscale x 8 x i1> %[[PG]], half* %[[GEP]])
// CHECK: ret <vscale x 8 x half> %[[LOAD]] // CHECK: ret <vscale x 8 x half> %[[LOAD]]
return SVE_ACLE_FUNC(svld1_vnum,_f16,,)(pg, base, vnum); return SVE_ACLE_FUNC(svld1_vnum,_f16,,)(pg, base, vnum);
} }
svfloat32_t test_svld1_vnum_f32(svbool_t pg, const float32_t *base, int64_t vnum) svfloat32_t test_svld1_vnum_f32(svbool_t pg, const float32_t *base, int64_t vnum)
{ {
// CHECK-LABEL: test_svld1_vnum_f32 // CHECK-LABEL: test_svld1_vnum_f32
// CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast float* %base to <vscale x 4 x float>* // CHECK-DAG: %[[BITCAST:.*]] = bitcast float* %base to <vscale x 4 x float>*
// CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 4 x float>, <vscale x 4 x float>* %[[BASE]], i64 %vnum // CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 4 x float>, <vscale x 4 x float>* %[[BITCAST]], i64 %vnum, i64 0
// CHECK: %[[LOAD:.*]] = call <vscale x 4 x float> @llvm.masked.load.nxv4f32.p0nxv4f32(<vscale x 4 x float>* %[[GEP]], i32 1, <vscale x 4 x i1> %[[PG]], <vscale x 4 x float> zeroinitializer) // CHECK: %[[LOAD:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.ld1.nxv4f32(<vscale x 4 x i1> %[[PG]], float* %[[GEP]])
// CHECK: ret <vscale x 4 x float> %[[LOAD]] // CHECK: ret <vscale x 4 x float> %[[LOAD]]
return SVE_ACLE_FUNC(svld1_vnum,_f32,,)(pg, base, vnum); return SVE_ACLE_FUNC(svld1_vnum,_f32,,)(pg, base, vnum);
} }
svfloat64_t test_svld1_vnum_f64(svbool_t pg, const float64_t *base, int64_t vnum) svfloat64_t test_svld1_vnum_f64(svbool_t pg, const float64_t *base, int64_t vnum)
{ {
// CHECK-LABEL: test_svld1_vnum_f64 // CHECK-LABEL: test_svld1_vnum_f64
// CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast double* %base to <vscale x 2 x double>* // CHECK-DAG: %[[BITCAST:.*]] = bitcast double* %base to <vscale x 2 x double>*
// CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 2 x double>, <vscale x 2 x double>* %[[BASE]], i64 %vnum // CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 2 x double>, <vscale x 2 x double>* %[[BITCAST]], i64 %vnum, i64 0
// CHECK: %[[LOAD:.*]] = call <vscale x 2 x double> @llvm.masked.load.nxv2f64.p0nxv2f64(<vscale x 2 x double>* %[[GEP]], i32 1, <vscale x 2 x i1> %[[PG]], <vscale x 2 x double> zeroinitializer) // CHECK: %[[LOAD:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.ld1.nxv2f64(<vscale x 2 x i1> %[[PG]], double* %[[GEP]])
// CHECK: ret <vscale x 2 x double> %[[LOAD]] // CHECK: ret <vscale x 2 x double> %[[LOAD]]
return SVE_ACLE_FUNC(svld1_vnum,_f64,,)(pg, base, vnum); return SVE_ACLE_FUNC(svld1_vnum,_f64,,)(pg, base, vnum);
} }
svint32_t test_svld1_gather_u32base_s32(svbool_t pg, svuint32_t bases) { svint32_t test_svld1_gather_u32base_s32(svbool_t pg, svuint32_t bases) {
// CHECK-LABEL: test_svld1_gather_u32base_s32 // CHECK-LABEL: test_svld1_gather_u32base_s32
// CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg) // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
// CHECK: %[[LOAD:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i32.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %bases, i64 0) // CHECK: %[[LOAD:.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1.gather.scalar.offset.nxv4i32.nxv4i32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x i32> %bases, i64 0)
▲ Show 20 Lines • Show All 337 Lines • Show Last 20 Lines

clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1sb.c

// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s // RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s
// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s // RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s
#include <arm_sve.h> #include <arm_sve.h>
#ifdef SVE_OVERLOADED_FORMS #ifdef SVE_OVERLOADED_FORMS
// A simple used,unused... macro, long enough to represent any SVE builtin. // A simple used,unused... macro, long enough to represent any SVE builtin.
#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3 #define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
#else #else
#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4 #define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
#endif #endif
svint16_t test_svld1sb_s16(svbool_t pg, const int8_t *base) svint16_t test_svld1sb_s16(svbool_t pg, const int8_t *base)
{ {
// CHECK-LABEL: test_svld1sb_s16 // CHECK-LABEL: test_svld1sb_s16
// CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg) // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to <vscale x 8 x i8>* // CHECK: %[[LOAD:.*]] = call <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8(<vscale x 8 x i1> %[[PG]], i8* %base)
// CHECK: %[[LOAD:.*]] = call <vscale x 8 x i8> @llvm.masked.load.nxv8i8.p0nxv8i8(<vscale x 8 x i8>* %[[BASE]], i32 1, <vscale x 8 x i1> %[[PG]], <vscale x 8 x i8> zeroinitializer)
// CHECK: %[[SEXT:.*]] = sext <vscale x 8 x i8> %[[LOAD]] to <vscale x 8 x i16> // CHECK: %[[SEXT:.*]] = sext <vscale x 8 x i8> %[[LOAD]] to <vscale x 8 x i16>
// CHECK: ret <vscale x 8 x i16> %[[SEXT]] // CHECK: ret <vscale x 8 x i16> %[[SEXT]]
return svld1sb_s16(pg, base); return svld1sb_s16(pg, base);
} }
svint32_t test_svld1sb_s32(svbool_t pg, const int8_t *base) svint32_t test_svld1sb_s32(svbool_t pg, const int8_t *base)
{ {
// CHECK-LABEL: test_svld1sb_s32 // CHECK-LABEL: test_svld1sb_s32
// CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg) // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to <vscale x 4 x i8>* // CHECK: %[[LOAD:.*]] = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8(<vscale x 4 x i1> %[[PG]], i8* %base)
// CHECK: %[[LOAD:.*]] = call <vscale x 4 x i8> @llvm.masked.load.nxv4i8.p0nxv4i8(<vscale x 4 x i8>* %[[BASE]], i32 1, <vscale x 4 x i1> %[[PG]], <vscale x 4 x i8> zeroinitializer)
// CHECK: %[[SEXT:.*]] = sext <vscale x 4 x i8> %[[LOAD]] to <vscale x 4 x i32> // CHECK: %[[SEXT:.*]] = sext <vscale x 4 x i8> %[[LOAD]] to <vscale x 4 x i32>
// CHECK: ret <vscale x 4 x i32> %[[SEXT]] // CHECK: ret <vscale x 4 x i32> %[[SEXT]]
return svld1sb_s32(pg, base); return svld1sb_s32(pg, base);
} }
svint64_t test_svld1sb_s64(svbool_t pg, const int8_t *base) svint64_t test_svld1sb_s64(svbool_t pg, const int8_t *base)
{ {
// CHECK-LABEL: test_svld1sb_s64 // CHECK-LABEL: test_svld1sb_s64
// CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg) // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to <vscale x 2 x i8>* // CHECK: %[[LOAD:.*]] = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.nxv2i8(<vscale x 2 x i1> %[[PG]], i8* %base)
// CHECK: %[[LOAD:.*]] = call <vscale x 2 x i8> @llvm.masked.load.nxv2i8.p0nxv2i8(<vscale x 2 x i8>* %[[BASE]], i32 1, <vscale x 2 x i1> %[[PG]], <vscale x 2 x i8> zeroinitializer)
// CHECK: %[[SEXT:.*]] = sext <vscale x 2 x i8> %[[LOAD]] to <vscale x 2 x i64> // CHECK: %[[SEXT:.*]] = sext <vscale x 2 x i8> %[[LOAD]] to <vscale x 2 x i64>
// CHECK: ret <vscale x 2 x i64> %[[SEXT]] // CHECK: ret <vscale x 2 x i64> %[[SEXT]]
return svld1sb_s64(pg, base); return svld1sb_s64(pg, base);
} }
svuint16_t test_svld1sb_u16(svbool_t pg, const int8_t *base) svuint16_t test_svld1sb_u16(svbool_t pg, const int8_t *base)
{ {
// CHECK-LABEL: test_svld1sb_u16 // CHECK-LABEL: test_svld1sb_u16
// CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg) // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to <vscale x 8 x i8>* // CHECK: %[[LOAD:.*]] = call <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8(<vscale x 8 x i1> %[[PG]], i8* %base)
// CHECK: %[[LOAD:.*]] = call <vscale x 8 x i8> @llvm.masked.load.nxv8i8.p0nxv8i8(<vscale x 8 x i8>* %[[BASE]], i32 1, <vscale x 8 x i1> %[[PG]], <vscale x 8 x i8> zeroinitializer)
// CHECK: %[[SEXT:.*]] = sext <vscale x 8 x i8> %[[LOAD]] to <vscale x 8 x i16> // CHECK: %[[SEXT:.*]] = sext <vscale x 8 x i8> %[[LOAD]] to <vscale x 8 x i16>
// CHECK: ret <vscale x 8 x i16> %[[SEXT]] // CHECK: ret <vscale x 8 x i16> %[[SEXT]]
return svld1sb_u16(pg, base); return svld1sb_u16(pg, base);
} }
svuint32_t test_svld1sb_u32(svbool_t pg, const int8_t *base) svuint32_t test_svld1sb_u32(svbool_t pg, const int8_t *base)
{ {
// CHECK-LABEL: test_svld1sb_u32 // CHECK-LABEL: test_svld1sb_u32
// CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg) // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to <vscale x 4 x i8>* // CHECK: %[[LOAD:.*]] = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8(<vscale x 4 x i1> %[[PG]], i8* %base)
// CHECK: %[[LOAD:.*]] = call <vscale x 4 x i8> @llvm.masked.load.nxv4i8.p0nxv4i8(<vscale x 4 x i8>* %[[BASE]], i32 1, <vscale x 4 x i1> %[[PG]], <vscale x 4 x i8> zeroinitializer)
// CHECK: %[[SEXT:.*]] = sext <vscale x 4 x i8> %[[LOAD]] to <vscale x 4 x i32> // CHECK: %[[SEXT:.*]] = sext <vscale x 4 x i8> %[[LOAD]] to <vscale x 4 x i32>
// CHECK: ret <vscale x 4 x i32> %[[SEXT]] // CHECK: ret <vscale x 4 x i32> %[[SEXT]]
return svld1sb_u32(pg, base); return svld1sb_u32(pg, base);
} }
svuint64_t test_svld1sb_u64(svbool_t pg, const int8_t *base) svuint64_t test_svld1sb_u64(svbool_t pg, const int8_t *base)
{ {
// CHECK-LABEL: test_svld1sb_u64 // CHECK-LABEL: test_svld1sb_u64
// CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg) // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to <vscale x 2 x i8>* // CHECK: %[[LOAD:.*]] = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.nxv2i8(<vscale x 2 x i1> %[[PG]], i8* %base)
// CHECK: %[[LOAD:.*]] = call <vscale x 2 x i8> @llvm.masked.load.nxv2i8.p0nxv2i8(<vscale x 2 x i8>* %[[BASE]], i32 1, <vscale x 2 x i1> %[[PG]], <vscale x 2 x i8> zeroinitializer)
// CHECK: %[[SEXT:.*]] = sext <vscale x 2 x i8> %[[LOAD]] to <vscale x 2 x i64> // CHECK: %[[SEXT:.*]] = sext <vscale x 2 x i8> %[[LOAD]] to <vscale x 2 x i64>
// CHECK: ret <vscale x 2 x i64> %[[SEXT]] // CHECK: ret <vscale x 2 x i64> %[[SEXT]]
return svld1sb_u64(pg, base); return svld1sb_u64(pg, base);
} }
svint16_t test_svld1sb_vnum_s16(svbool_t pg, const int8_t *base, int64_t vnum) svint16_t test_svld1sb_vnum_s16(svbool_t pg, const int8_t *base, int64_t vnum)
{ {
// CHECK-LABEL: test_svld1sb_vnum_s16 // CHECK-LABEL: test_svld1sb_vnum_s16
// CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to <vscale x 8 x i8>* // CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to <vscale x 8 x i8>*
// CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 8 x i8>, <vscale x 8 x i8>* %[[BASE]], i64 %vnum // CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 8 x i8>, <vscale x 8 x i8>* %[[BASE]], i64 %vnum, i64 0
// CHECK: %[[LOAD:.*]] = call <vscale x 8 x i8> @llvm.masked.load.nxv8i8.p0nxv8i8(<vscale x 8 x i8>* %[[GEP]], i32 1, <vscale x 8 x i1> %[[PG]], <vscale x 8 x i8> zeroinitializer) // CHECK: %[[LOAD:.*]] = call <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8(<vscale x 8 x i1> %[[PG]], i8* %[[GEP]])
// CHECK: %[[SEXT:.*]] = sext <vscale x 8 x i8> %[[LOAD]] to <vscale x 8 x i16> // CHECK: %[[SEXT:.*]] = sext <vscale x 8 x i8> %[[LOAD]] to <vscale x 8 x i16>
// CHECK: ret <vscale x 8 x i16> %[[SEXT]] // CHECK: ret <vscale x 8 x i16> %[[SEXT]]
return svld1sb_vnum_s16(pg, base, vnum); return svld1sb_vnum_s16(pg, base, vnum);
} }
svint32_t test_svld1sb_vnum_s32(svbool_t pg, const int8_t *base, int64_t vnum) svint32_t test_svld1sb_vnum_s32(svbool_t pg, const int8_t *base, int64_t vnum)
{ {
// CHECK-LABEL: test_svld1sb_vnum_s32 // CHECK-LABEL: test_svld1sb_vnum_s32
// CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to <vscale x 4 x i8>* // CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to <vscale x 4 x i8>*
// CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 4 x i8>, <vscale x 4 x i8>* %[[BASE]], i64 %vnum // CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 4 x i8>, <vscale x 4 x i8>* %[[BASE]], i64 %vnum, i64 0
// CHECK: %[[LOAD:.*]] = call <vscale x 4 x i8> @llvm.masked.load.nxv4i8.p0nxv4i8(<vscale x 4 x i8>* %[[GEP]], i32 1, <vscale x 4 x i1> %[[PG]], <vscale x 4 x i8> zeroinitializer) // CHECK: %[[LOAD:.*]] = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8(<vscale x 4 x i1> %[[PG]], i8* %[[GEP]])
// CHECK: %[[SEXT:.*]] = sext <vscale x 4 x i8> %[[LOAD]] to <vscale x 4 x i32> // CHECK: %[[SEXT:.*]] = sext <vscale x 4 x i8> %[[LOAD]] to <vscale x 4 x i32>
// CHECK: ret <vscale x 4 x i32> %[[SEXT]] // CHECK: ret <vscale x 4 x i32> %[[SEXT]]
return svld1sb_vnum_s32(pg, base, vnum); return svld1sb_vnum_s32(pg, base, vnum);
} }
svint64_t test_svld1sb_vnum_s64(svbool_t pg, const int8_t *base, int64_t vnum) svint64_t test_svld1sb_vnum_s64(svbool_t pg, const int8_t *base, int64_t vnum)
{ {
// CHECK-LABEL: test_svld1sb_vnum_s64 // CHECK-LABEL: test_svld1sb_vnum_s64
// CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to <vscale x 2 x i8>* // CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to <vscale x 2 x i8>*
// CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 2 x i8>, <vscale x 2 x i8>* %[[BASE]], i64 %vnum // CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 2 x i8>, <vscale x 2 x i8>* %[[BASE]], i64 %vnum, i64 0
// CHECK: %[[LOAD:.*]] = call <vscale x 2 x i8> @llvm.masked.load.nxv2i8.p0nxv2i8(<vscale x 2 x i8>* %[[GEP]], i32 1, <vscale x 2 x i1> %[[PG]], <vscale x 2 x i8> zeroinitializer) // CHECK: %[[LOAD:.*]] = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.nxv2i8(<vscale x 2 x i1> %[[PG]], i8* %[[GEP]])
// CHECK: %[[SEXT:.*]] = sext <vscale x 2 x i8> %[[LOAD]] to <vscale x 2 x i64> // CHECK: %[[SEXT:.*]] = sext <vscale x 2 x i8> %[[LOAD]] to <vscale x 2 x i64>
// CHECK: ret <vscale x 2 x i64> %[[SEXT]] // CHECK: ret <vscale x 2 x i64> %[[SEXT]]
return svld1sb_vnum_s64(pg, base, vnum); return svld1sb_vnum_s64(pg, base, vnum);
} }
svuint16_t test_svld1sb_vnum_u16(svbool_t pg, const int8_t *base, int64_t vnum) svuint16_t test_svld1sb_vnum_u16(svbool_t pg, const int8_t *base, int64_t vnum)
{ {
// CHECK-LABEL: test_svld1sb_vnum_u16 // CHECK-LABEL: test_svld1sb_vnum_u16
// CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to <vscale x 8 x i8>* // CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to <vscale x 8 x i8>*
// CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 8 x i8>, <vscale x 8 x i8>* %[[BASE]], i64 %vnum // CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 8 x i8>, <vscale x 8 x i8>* %[[BASE]], i64 %vnum, i64 0
// CHECK: %[[LOAD:.*]] = call <vscale x 8 x i8> @llvm.masked.load.nxv8i8.p0nxv8i8(<vscale x 8 x i8>* %[[GEP]], i32 1, <vscale x 8 x i1> %[[PG]], <vscale x 8 x i8> zeroinitializer) // CHECK: %[[LOAD:.*]] = call <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8(<vscale x 8 x i1> %[[PG]], i8* %[[GEP]])
// CHECK: %[[SEXT:.*]] = sext <vscale x 8 x i8> %[[LOAD]] to <vscale x 8 x i16> // CHECK: %[[SEXT:.*]] = sext <vscale x 8 x i8> %[[LOAD]] to <vscale x 8 x i16>
// CHECK: ret <vscale x 8 x i16> %[[SEXT]] // CHECK: ret <vscale x 8 x i16> %[[SEXT]]
return svld1sb_vnum_u16(pg, base, vnum); return svld1sb_vnum_u16(pg, base, vnum);
} }
svuint32_t test_svld1sb_vnum_u32(svbool_t pg, const int8_t *base, int64_t vnum) svuint32_t test_svld1sb_vnum_u32(svbool_t pg, const int8_t *base, int64_t vnum)
{ {
// CHECK-LABEL: test_svld1sb_vnum_u32 // CHECK-LABEL: test_svld1sb_vnum_u32
// CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to <vscale x 4 x i8>* // CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to <vscale x 4 x i8>*
// CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 4 x i8>, <vscale x 4 x i8>* %[[BASE]], i64 %vnum // CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 4 x i8>, <vscale x 4 x i8>* %[[BASE]], i64 %vnum, i64 0
// CHECK: %[[LOAD:.*]] = call <vscale x 4 x i8> @llvm.masked.load.nxv4i8.p0nxv4i8(<vscale x 4 x i8>* %[[GEP]], i32 1, <vscale x 4 x i1> %[[PG]], <vscale x 4 x i8> zeroinitializer) // CHECK: %[[LOAD:.*]] = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8(<vscale x 4 x i1> %[[PG]], i8* %[[GEP]])
// CHECK: %[[SEXT:.*]] = sext <vscale x 4 x i8> %[[LOAD]] to <vscale x 4 x i32> // CHECK: %[[SEXT:.*]] = sext <vscale x 4 x i8> %[[LOAD]] to <vscale x 4 x i32>
// CHECK: ret <vscale x 4 x i32> %[[SEXT]] // CHECK: ret <vscale x 4 x i32> %[[SEXT]]
return svld1sb_vnum_u32(pg, base, vnum); return svld1sb_vnum_u32(pg, base, vnum);
} }
svuint64_t test_svld1sb_vnum_u64(svbool_t pg, const int8_t *base, int64_t vnum) svuint64_t test_svld1sb_vnum_u64(svbool_t pg, const int8_t *base, int64_t vnum)
{ {
// CHECK-LABEL: test_svld1sb_vnum_u64 // CHECK-LABEL: test_svld1sb_vnum_u64
// CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to <vscale x 2 x i8>* // CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to <vscale x 2 x i8>*
// CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 2 x i8>, <vscale x 2 x i8>* %[[BASE]], i64 %vnum // CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 2 x i8>, <vscale x 2 x i8>* %[[BASE]], i64 %vnum, i64 0
// CHECK: %[[LOAD:.*]] = call <vscale x 2 x i8> @llvm.masked.load.nxv2i8.p0nxv2i8(<vscale x 2 x i8>* %[[GEP]], i32 1, <vscale x 2 x i1> %[[PG]], <vscale x 2 x i8> zeroinitializer) // CHECK: %[[LOAD:.*]] = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.nxv2i8(<vscale x 2 x i1> %[[PG]], i8* %[[GEP]])
// CHECK: %[[SEXT:.*]] = sext <vscale x 2 x i8> %[[LOAD]] to <vscale x 2 x i64> // CHECK: %[[SEXT:.*]] = sext <vscale x 2 x i8> %[[LOAD]] to <vscale x 2 x i64>
// CHECK: ret <vscale x 2 x i64> %[[SEXT]] // CHECK: ret <vscale x 2 x i64> %[[SEXT]]
return svld1sb_vnum_u64(pg, base, vnum); return svld1sb_vnum_u64(pg, base, vnum);
} }
svint32_t test_svld1sb_gather_u32base_s32(svbool_t pg, svuint32_t bases) { svint32_t test_svld1sb_gather_u32base_s32(svbool_t pg, svuint32_t bases) {
// CHECK-LABEL: test_svld1sb_gather_u32base_s32 // CHECK-LABEL: test_svld1sb_gather_u32base_s32
// CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg) // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
▲ Show 20 Lines • Show All 140 Lines • Show Last 20 Lines

clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1sh.c

// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s // RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s
// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s // RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s
#include <arm_sve.h> #include <arm_sve.h>
#ifdef SVE_OVERLOADED_FORMS #ifdef SVE_OVERLOADED_FORMS
// A simple used,unused... macro, long enough to represent any SVE builtin. // A simple used,unused... macro, long enough to represent any SVE builtin.
#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3 #define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
#else #else
#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4 #define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
#endif #endif
svint32_t test_svld1sh_s32(svbool_t pg, const int16_t *base) svint32_t test_svld1sh_s32(svbool_t pg, const int16_t *base)
{ {
// CHECK-LABEL: test_svld1sh_s32 // CHECK-LABEL: test_svld1sh_s32
// CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg) // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to <vscale x 4 x i16>* // CHECK: %[[LOAD:.*]] = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16(<vscale x 4 x i1> %[[PG]], i16* %base)
// CHECK: %[[LOAD:.*]] = call <vscale x 4 x i16> @llvm.masked.load.nxv4i16.p0nxv4i16(<vscale x 4 x i16>* %[[BASE]], i32 1, <vscale x 4 x i1> %[[PG]], <vscale x 4 x i16> zeroinitializer)
// CHECK: %[[SEXT:.*]] = sext <vscale x 4 x i16> %[[LOAD]] to <vscale x 4 x i32> // CHECK: %[[SEXT:.*]] = sext <vscale x 4 x i16> %[[LOAD]] to <vscale x 4 x i32>
// CHECK: ret <vscale x 4 x i32> %[[SEXT]] // CHECK: ret <vscale x 4 x i32> %[[SEXT]]
return svld1sh_s32(pg, base); return svld1sh_s32(pg, base);
} }
svint64_t test_svld1sh_s64(svbool_t pg, const int16_t *base) svint64_t test_svld1sh_s64(svbool_t pg, const int16_t *base)
{ {
// CHECK-LABEL: test_svld1sh_s64 // CHECK-LABEL: test_svld1sh_s64
// CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg) // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to <vscale x 2 x i16>* // CHECK: %[[LOAD:.*]] = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16(<vscale x 2 x i1> %[[PG]], i16* %base)
// CHECK: %[[LOAD:.*]] = call <vscale x 2 x i16> @llvm.masked.load.nxv2i16.p0nxv2i16(<vscale x 2 x i16>* %[[BASE]], i32 1, <vscale x 2 x i1> %[[PG]], <vscale x 2 x i16> zeroinitializer)
// CHECK: %[[SEXT:.*]] = sext <vscale x 2 x i16> %[[LOAD]] to <vscale x 2 x i64> // CHECK: %[[SEXT:.*]] = sext <vscale x 2 x i16> %[[LOAD]] to <vscale x 2 x i64>
// CHECK: ret <vscale x 2 x i64> %[[SEXT]] // CHECK: ret <vscale x 2 x i64> %[[SEXT]]
return svld1sh_s64(pg, base); return svld1sh_s64(pg, base);
} }
svuint32_t test_svld1sh_u32(svbool_t pg, const int16_t *base) svuint32_t test_svld1sh_u32(svbool_t pg, const int16_t *base)
{ {
// CHECK-LABEL: test_svld1sh_u32 // CHECK-LABEL: test_svld1sh_u32
// CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg) // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to <vscale x 4 x i16>* // CHECK: %[[LOAD:.*]] = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16(<vscale x 4 x i1> %[[PG]], i16* %base)
// CHECK: %[[LOAD:.*]] = call <vscale x 4 x i16> @llvm.masked.load.nxv4i16.p0nxv4i16(<vscale x 4 x i16>* %[[BASE]], i32 1, <vscale x 4 x i1> %[[PG]], <vscale x 4 x i16> zeroinitializer)
// CHECK: %[[SEXT:.*]] = sext <vscale x 4 x i16> %[[LOAD]] to <vscale x 4 x i32> // CHECK: %[[SEXT:.*]] = sext <vscale x 4 x i16> %[[LOAD]] to <vscale x 4 x i32>
// CHECK: ret <vscale x 4 x i32> %[[SEXT]] // CHECK: ret <vscale x 4 x i32> %[[SEXT]]
return svld1sh_u32(pg, base); return svld1sh_u32(pg, base);
} }
svuint64_t test_svld1sh_u64(svbool_t pg, const int16_t *base) svuint64_t test_svld1sh_u64(svbool_t pg, const int16_t *base)
{ {
// CHECK-LABEL: test_svld1sh_u64 // CHECK-LABEL: test_svld1sh_u64
// CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg) // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to <vscale x 2 x i16>* // CHECK: %[[LOAD:.*]] = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16(<vscale x 2 x i1> %[[PG]], i16* %base)
// CHECK: %[[LOAD:.*]] = call <vscale x 2 x i16> @llvm.masked.load.nxv2i16.p0nxv2i16(<vscale x 2 x i16>* %[[BASE]], i32 1, <vscale x 2 x i1> %[[PG]], <vscale x 2 x i16> zeroinitializer)
// CHECK: %[[SEXT:.*]] = sext <vscale x 2 x i16> %[[LOAD]] to <vscale x 2 x i64> // CHECK: %[[SEXT:.*]] = sext <vscale x 2 x i16> %[[LOAD]] to <vscale x 2 x i64>
// CHECK: ret <vscale x 2 x i64> %[[SEXT]] // CHECK: ret <vscale x 2 x i64> %[[SEXT]]
return svld1sh_u64(pg, base); return svld1sh_u64(pg, base);
} }
svint32_t test_svld1sh_vnum_s32(svbool_t pg, const int16_t *base, int64_t vnum) svint32_t test_svld1sh_vnum_s32(svbool_t pg, const int16_t *base, int64_t vnum)
{ {
// CHECK-LABEL: test_svld1sh_vnum_s32 // CHECK-LABEL: test_svld1sh_vnum_s32
// CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to <vscale x 4 x i16>* // CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to <vscale x 4 x i16>*
// CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 4 x i16>, <vscale x 4 x i16>* %[[BASE]], i64 %vnum // CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 4 x i16>, <vscale x 4 x i16>* %[[BASE]], i64 %vnum, i64 0
// CHECK: %[[LOAD:.*]] = call <vscale x 4 x i16> @llvm.masked.load.nxv4i16.p0nxv4i16(<vscale x 4 x i16>* %[[GEP]], i32 1, <vscale x 4 x i1> %[[PG]], <vscale x 4 x i16> zeroinitializer) // CHECK: %[[LOAD:.*]] = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16(<vscale x 4 x i1> %[[PG]], i16* %[[GEP]])
// CHECK: %[[SEXT:.*]] = sext <vscale x 4 x i16> %[[LOAD]] to <vscale x 4 x i32> // CHECK: %[[SEXT:.*]] = sext <vscale x 4 x i16> %[[LOAD]] to <vscale x 4 x i32>
// CHECK: ret <vscale x 4 x i32> %[[SEXT]] // CHECK: ret <vscale x 4 x i32> %[[SEXT]]
return svld1sh_vnum_s32(pg, base, vnum); return svld1sh_vnum_s32(pg, base, vnum);
} }
svint64_t test_svld1sh_vnum_s64(svbool_t pg, const int16_t *base, int64_t vnum) svint64_t test_svld1sh_vnum_s64(svbool_t pg, const int16_t *base, int64_t vnum)
{ {
// CHECK-LABEL: test_svld1sh_vnum_s64 // CHECK-LABEL: test_svld1sh_vnum_s64
// CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to <vscale x 2 x i16>* // CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to <vscale x 2 x i16>*
// CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 2 x i16>, <vscale x 2 x i16>* %[[BASE]], i64 %vnum // CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 2 x i16>, <vscale x 2 x i16>* %[[BASE]], i64 %vnum, i64 0
// CHECK: %[[LOAD:.*]] = call <vscale x 2 x i16> @llvm.masked.load.nxv2i16.p0nxv2i16(<vscale x 2 x i16>* %[[GEP]], i32 1, <vscale x 2 x i1> %[[PG]], <vscale x 2 x i16> zeroinitializer) // CHECK: %[[LOAD:.*]] = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16(<vscale x 2 x i1> %[[PG]], i16* %[[GEP]])
// CHECK: %[[SEXT:.*]] = sext <vscale x 2 x i16> %[[LOAD]] to <vscale x 2 x i64> // CHECK: %[[SEXT:.*]] = sext <vscale x 2 x i16> %[[LOAD]] to <vscale x 2 x i64>
// CHECK: ret <vscale x 2 x i64> %[[SEXT]] // CHECK: ret <vscale x 2 x i64> %[[SEXT]]
return svld1sh_vnum_s64(pg, base, vnum); return svld1sh_vnum_s64(pg, base, vnum);
} }
svuint32_t test_svld1sh_vnum_u32(svbool_t pg, const int16_t *base, int64_t vnum) svuint32_t test_svld1sh_vnum_u32(svbool_t pg, const int16_t *base, int64_t vnum)
{ {
// CHECK-LABEL: test_svld1sh_vnum_u32 // CHECK-LABEL: test_svld1sh_vnum_u32
// CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to <vscale x 4 x i16>* // CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to <vscale x 4 x i16>*
// CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 4 x i16>, <vscale x 4 x i16>* %[[BASE]], i64 %vnum // CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 4 x i16>, <vscale x 4 x i16>* %[[BASE]], i64 %vnum, i64 0
// CHECK: %[[LOAD:.*]] = call <vscale x 4 x i16> @llvm.masked.load.nxv4i16.p0nxv4i16(<vscale x 4 x i16>* %[[GEP]], i32 1, <vscale x 4 x i1> %[[PG]], <vscale x 4 x i16> zeroinitializer) // CHECK: %[[LOAD:.*]] = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16(<vscale x 4 x i1> %[[PG]], i16* %[[GEP]])
// CHECK: %[[SEXT:.*]] = sext <vscale x 4 x i16> %[[LOAD]] to <vscale x 4 x i32> // CHECK: %[[SEXT:.*]] = sext <vscale x 4 x i16> %[[LOAD]] to <vscale x 4 x i32>
// CHECK: ret <vscale x 4 x i32> %[[SEXT]] // CHECK: ret <vscale x 4 x i32> %[[SEXT]]
return svld1sh_vnum_u32(pg, base, vnum); return svld1sh_vnum_u32(pg, base, vnum);
} }
svuint64_t test_svld1sh_vnum_u64(svbool_t pg, const int16_t *base, int64_t vnum) svuint64_t test_svld1sh_vnum_u64(svbool_t pg, const int16_t *base, int64_t vnum)
{ {
// CHECK-LABEL: test_svld1sh_vnum_u64 // CHECK-LABEL: test_svld1sh_vnum_u64
// CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to <vscale x 2 x i16>* // CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to <vscale x 2 x i16>*
// CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 2 x i16>, <vscale x 2 x i16>* %[[BASE]], i64 %vnum // CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 2 x i16>, <vscale x 2 x i16>* %[[BASE]], i64 %vnum, i64 0
// CHECK: %[[LOAD:.*]] = call <vscale x 2 x i16> @llvm.masked.load.nxv2i16.p0nxv2i16(<vscale x 2 x i16>* %[[GEP]], i32 1, <vscale x 2 x i1> %[[PG]], <vscale x 2 x i16> zeroinitializer) // CHECK: %[[LOAD:.*]] = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16(<vscale x 2 x i1> %[[PG]], i16* %[[GEP]])
// CHECK: %[[SEXT:.*]] = sext <vscale x 2 x i16> %[[LOAD]] to <vscale x 2 x i64> // CHECK: %[[SEXT:.*]] = sext <vscale x 2 x i16> %[[LOAD]] to <vscale x 2 x i64>
// CHECK: ret <vscale x 2 x i64> %[[SEXT]] // CHECK: ret <vscale x 2 x i64> %[[SEXT]]
return svld1sh_vnum_u64(pg, base, vnum); return svld1sh_vnum_u64(pg, base, vnum);
} }
svint32_t test_svld1sh_gather_u32base_s32(svbool_t pg, svuint32_t bases) { svint32_t test_svld1sh_gather_u32base_s32(svbool_t pg, svuint32_t bases) {
// CHECK-LABEL: test_svld1sh_gather_u32base_s32 // CHECK-LABEL: test_svld1sh_gather_u32base_s32
// CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg) // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
▲ Show 20 Lines • Show All 252 Lines • Show Last 20 Lines

clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1sw.c

// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s // RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s
// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s // RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s
#include <arm_sve.h> #include <arm_sve.h>
#ifdef SVE_OVERLOADED_FORMS #ifdef SVE_OVERLOADED_FORMS
// A simple used,unused... macro, long enough to represent any SVE builtin. // A simple used,unused... macro, long enough to represent any SVE builtin.
#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3 #define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
#else #else
#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4 #define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
#endif #endif
svint64_t test_svld1sw_s64(svbool_t pg, const int32_t *base) svint64_t test_svld1sw_s64(svbool_t pg, const int32_t *base)
{ {
// CHECK-LABEL: test_svld1sw_s64 // CHECK-LABEL: test_svld1sw_s64
// CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg) // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i32* %base to <vscale x 2 x i32>* // CHECK: %[[LOAD:.*]] = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32(<vscale x 2 x i1> %[[PG]], i32* %base)
// CHECK: %[[LOAD:.*]] = call <vscale x 2 x i32> @llvm.masked.load.nxv2i32.p0nxv2i32(<vscale x 2 x i32>* %[[BASE]], i32 1, <vscale x 2 x i1> %[[PG]], <vscale x 2 x i32> zeroinitializer)
// CHECK: %[[SEXT:.*]] = sext <vscale x 2 x i32> %[[LOAD]] to <vscale x 2 x i64> // CHECK: %[[SEXT:.*]] = sext <vscale x 2 x i32> %[[LOAD]] to <vscale x 2 x i64>
// CHECK: ret <vscale x 2 x i64> %[[SEXT]] // CHECK: ret <vscale x 2 x i64> %[[SEXT]]
return svld1sw_s64(pg, base); return svld1sw_s64(pg, base);
} }
svuint64_t test_svld1sw_u64(svbool_t pg, const int32_t *base) svuint64_t test_svld1sw_u64(svbool_t pg, const int32_t *base)
{ {
// CHECK-LABEL: test_svld1sw_u64 // CHECK-LABEL: test_svld1sw_u64
// CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg) // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i32* %base to <vscale x 2 x i32>* // CHECK: %[[LOAD:.*]] = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32(<vscale x 2 x i1> %[[PG]], i32* %base)
// CHECK: %[[LOAD:.*]] = call <vscale x 2 x i32> @llvm.masked.load.nxv2i32.p0nxv2i32(<vscale x 2 x i32>* %[[BASE]], i32 1, <vscale x 2 x i1> %[[PG]], <vscale x 2 x i32> zeroinitializer)
// CHECK: %[[SEXT:.*]] = sext <vscale x 2 x i32> %[[LOAD]] to <vscale x 2 x i64> // CHECK: %[[SEXT:.*]] = sext <vscale x 2 x i32> %[[LOAD]] to <vscale x 2 x i64>
// CHECK: ret <vscale x 2 x i64> %[[SEXT]] // CHECK: ret <vscale x 2 x i64> %[[SEXT]]
return svld1sw_u64(pg, base); return svld1sw_u64(pg, base);
} }
svint64_t test_svld1sw_vnum_s64(svbool_t pg, const int32_t *base, int64_t vnum) svint64_t test_svld1sw_vnum_s64(svbool_t pg, const int32_t *base, int64_t vnum)
{ {
// CHECK-LABEL: test_svld1sw_vnum_s64 // CHECK-LABEL: test_svld1sw_vnum_s64
// CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i32* %base to <vscale x 2 x i32>* // CHECK-DAG: %[[BASE:.*]] = bitcast i32* %base to <vscale x 2 x i32>*
// CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 2 x i32>, <vscale x 2 x i32>* %[[BASE]], i64 %vnum // CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 2 x i32>, <vscale x 2 x i32>* %[[BASE]], i64 %vnum, i64 0
// CHECK: %[[LOAD:.*]] = call <vscale x 2 x i32> @llvm.masked.load.nxv2i32.p0nxv2i32(<vscale x 2 x i32>* %[[GEP]], i32 1, <vscale x 2 x i1> %[[PG]], <vscale x 2 x i32> zeroinitializer) // CHECK: %[[LOAD:.*]] = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32(<vscale x 2 x i1> %[[PG]], i32* %[[GEP]])
// CHECK: %[[SEXT:.*]] = sext <vscale x 2 x i32> %[[LOAD]] to <vscale x 2 x i64> // CHECK: %[[SEXT:.*]] = sext <vscale x 2 x i32> %[[LOAD]] to <vscale x 2 x i64>
// CHECK: ret <vscale x 2 x i64> %[[SEXT]] // CHECK: ret <vscale x 2 x i64> %[[SEXT]]
return svld1sw_vnum_s64(pg, base, vnum); return svld1sw_vnum_s64(pg, base, vnum);
} }
svuint64_t test_svld1sw_vnum_u64(svbool_t pg, const int32_t *base, int64_t vnum) svuint64_t test_svld1sw_vnum_u64(svbool_t pg, const int32_t *base, int64_t vnum)
{ {
// CHECK-LABEL: test_svld1sw_vnum_u64 // CHECK-LABEL: test_svld1sw_vnum_u64
// CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i32* %base to <vscale x 2 x i32>* // CHECK-DAG: %[[BASE:.*]] = bitcast i32* %base to <vscale x 2 x i32>*
// CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 2 x i32>, <vscale x 2 x i32>* %[[BASE]], i64 %vnum // CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 2 x i32>, <vscale x 2 x i32>* %[[BASE]], i64 %vnum, i64 0
// CHECK: %[[LOAD:.*]] = call <vscale x 2 x i32> @llvm.masked.load.nxv2i32.p0nxv2i32(<vscale x 2 x i32>* %[[GEP]], i32 1, <vscale x 2 x i1> %[[PG]], <vscale x 2 x i32> zeroinitializer) // CHECK: %[[LOAD:.*]] = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32(<vscale x 2 x i1> %[[PG]], i32* %[[GEP]])
// CHECK: %[[SEXT:.*]] = sext <vscale x 2 x i32> %[[LOAD]] to <vscale x 2 x i64> // CHECK: %[[SEXT:.*]] = sext <vscale x 2 x i32> %[[LOAD]] to <vscale x 2 x i64>
// CHECK: ret <vscale x 2 x i64> %[[SEXT]] // CHECK: ret <vscale x 2 x i64> %[[SEXT]]
return svld1sw_vnum_u64(pg, base, vnum); return svld1sw_vnum_u64(pg, base, vnum);
} }
svint64_t test_svld1sw_gather_u64base_s64(svbool_t pg, svuint64_t bases) { svint64_t test_svld1sw_gather_u64base_s64(svbool_t pg, svuint64_t bases) {
// CHECK-LABEL: test_svld1sw_gather_u64base_s64 // CHECK-LABEL: test_svld1sw_gather_u64base_s64
// CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg) // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
▲ Show 20 Lines • Show All 124 Lines • Show Last 20 Lines

clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1ub.c

// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s // RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s
// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s // RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s
#include <arm_sve.h> #include <arm_sve.h>
#ifdef SVE_OVERLOADED_FORMS #ifdef SVE_OVERLOADED_FORMS
// A simple used,unused... macro, long enough to represent any SVE builtin. // A simple used,unused... macro, long enough to represent any SVE builtin.
#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3 #define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
#else #else
#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4 #define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
#endif #endif
svint16_t test_svld1ub_s16(svbool_t pg, const uint8_t *base) svint16_t test_svld1ub_s16(svbool_t pg, const uint8_t *base)
{ {
// CHECK-LABEL: test_svld1ub_s16 // CHECK-LABEL: test_svld1ub_s16
// CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg) // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to <vscale x 8 x i8>* // CHECK: %[[LOAD:.*]] = call <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8(<vscale x 8 x i1> %[[PG]], i8* %base)
// CHECK: %[[LOAD:.*]] = call <vscale x 8 x i8> @llvm.masked.load.nxv8i8.p0nxv8i8(<vscale x 8 x i8>* %[[BASE]], i32 1, <vscale x 8 x i1> %[[PG]], <vscale x 8 x i8> zeroinitializer)
// CHECK: %[[ZEXT:.*]] = zext <vscale x 8 x i8> %[[LOAD]] to <vscale x 8 x i16> // CHECK: %[[ZEXT:.*]] = zext <vscale x 8 x i8> %[[LOAD]] to <vscale x 8 x i16>
// CHECK: ret <vscale x 8 x i16> %[[ZEXT]] // CHECK: ret <vscale x 8 x i16> %[[ZEXT]]
return svld1ub_s16(pg, base); return svld1ub_s16(pg, base);
} }
svint32_t test_svld1ub_s32(svbool_t pg, const uint8_t *base) svint32_t test_svld1ub_s32(svbool_t pg, const uint8_t *base)
{ {
// CHECK-LABEL: test_svld1ub_s32 // CHECK-LABEL: test_svld1ub_s32
// CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg) // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to <vscale x 4 x i8>* // CHECK: %[[LOAD:.*]] = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8(<vscale x 4 x i1> %[[PG]], i8* %base)
// CHECK: %[[LOAD:.*]] = call <vscale x 4 x i8> @llvm.masked.load.nxv4i8.p0nxv4i8(<vscale x 4 x i8>* %[[BASE]], i32 1, <vscale x 4 x i1> %[[PG]], <vscale x 4 x i8> zeroinitializer)
// CHECK: %[[ZEXT:.*]] = zext <vscale x 4 x i8> %[[LOAD]] to <vscale x 4 x i32> // CHECK: %[[ZEXT:.*]] = zext <vscale x 4 x i8> %[[LOAD]] to <vscale x 4 x i32>
// CHECK: ret <vscale x 4 x i32> %[[ZEXT]] // CHECK: ret <vscale x 4 x i32> %[[ZEXT]]
return svld1ub_s32(pg, base); return svld1ub_s32(pg, base);
} }
svint64_t test_svld1ub_s64(svbool_t pg, const uint8_t *base) svint64_t test_svld1ub_s64(svbool_t pg, const uint8_t *base)
{ {
// CHECK-LABEL: test_svld1ub_s64 // CHECK-LABEL: test_svld1ub_s64
// CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg) // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to <vscale x 2 x i8>* // CHECK: %[[LOAD:.*]] = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.nxv2i8(<vscale x 2 x i1> %[[PG]], i8* %base)
// CHECK: %[[LOAD:.*]] = call <vscale x 2 x i8> @llvm.masked.load.nxv2i8.p0nxv2i8(<vscale x 2 x i8>* %[[BASE]], i32 1, <vscale x 2 x i1> %[[PG]], <vscale x 2 x i8> zeroinitializer)
// CHECK: %[[ZEXT:.*]] = zext <vscale x 2 x i8> %[[LOAD]] to <vscale x 2 x i64> // CHECK: %[[ZEXT:.*]] = zext <vscale x 2 x i8> %[[LOAD]] to <vscale x 2 x i64>
// CHECK: ret <vscale x 2 x i64> %[[ZEXT]] // CHECK: ret <vscale x 2 x i64> %[[ZEXT]]
return svld1ub_s64(pg, base); return svld1ub_s64(pg, base);
} }
svuint16_t test_svld1ub_u16(svbool_t pg, const uint8_t *base) svuint16_t test_svld1ub_u16(svbool_t pg, const uint8_t *base)
{ {
// CHECK-LABEL: test_svld1ub_u16 // CHECK-LABEL: test_svld1ub_u16
// CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg) // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to <vscale x 8 x i8>* // CHECK: %[[LOAD:.*]] = call <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8(<vscale x 8 x i1> %[[PG]], i8* %base)
// CHECK: %[[LOAD:.*]] = call <vscale x 8 x i8> @llvm.masked.load.nxv8i8.p0nxv8i8(<vscale x 8 x i8>* %[[BASE]], i32 1, <vscale x 8 x i1> %[[PG]], <vscale x 8 x i8> zeroinitializer)
// CHECK: %[[ZEXT:.*]] = zext <vscale x 8 x i8> %[[LOAD]] to <vscale x 8 x i16> // CHECK: %[[ZEXT:.*]] = zext <vscale x 8 x i8> %[[LOAD]] to <vscale x 8 x i16>
// CHECK: ret <vscale x 8 x i16> %[[ZEXT]] // CHECK: ret <vscale x 8 x i16> %[[ZEXT]]
return svld1ub_u16(pg, base); return svld1ub_u16(pg, base);
} }
svuint32_t test_svld1ub_u32(svbool_t pg, const uint8_t *base) svuint32_t test_svld1ub_u32(svbool_t pg, const uint8_t *base)
{ {
// CHECK-LABEL: test_svld1ub_u32 // CHECK-LABEL: test_svld1ub_u32
// CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg) // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to <vscale x 4 x i8>* // CHECK: %[[LOAD:.*]] = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8(<vscale x 4 x i1> %[[PG]], i8* %base)
// CHECK: %[[LOAD:.*]] = call <vscale x 4 x i8> @llvm.masked.load.nxv4i8.p0nxv4i8(<vscale x 4 x i8>* %[[BASE]], i32 1, <vscale x 4 x i1> %[[PG]], <vscale x 4 x i8> zeroinitializer)
// CHECK: %[[ZEXT:.*]] = zext <vscale x 4 x i8> %[[LOAD]] to <vscale x 4 x i32> // CHECK: %[[ZEXT:.*]] = zext <vscale x 4 x i8> %[[LOAD]] to <vscale x 4 x i32>
// CHECK: ret <vscale x 4 x i32> %[[ZEXT]] // CHECK: ret <vscale x 4 x i32> %[[ZEXT]]
return svld1ub_u32(pg, base); return svld1ub_u32(pg, base);
} }
svuint64_t test_svld1ub_u64(svbool_t pg, const uint8_t *base) svuint64_t test_svld1ub_u64(svbool_t pg, const uint8_t *base)
{ {
// CHECK-LABEL: test_svld1ub_u64 // CHECK-LABEL: test_svld1ub_u64
// CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg) // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to <vscale x 2 x i8>* // CHECK: %[[LOAD:.*]] = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.nxv2i8(<vscale x 2 x i1> %[[PG]], i8* %base)
// CHECK: %[[LOAD:.*]] = call <vscale x 2 x i8> @llvm.masked.load.nxv2i8.p0nxv2i8(<vscale x 2 x i8>* %[[BASE]], i32 1, <vscale x 2 x i1> %[[PG]], <vscale x 2 x i8> zeroinitializer)
// CHECK: %[[ZEXT:.*]] = zext <vscale x 2 x i8> %[[LOAD]] to <vscale x 2 x i64> // CHECK: %[[ZEXT:.*]] = zext <vscale x 2 x i8> %[[LOAD]] to <vscale x 2 x i64>
// CHECK: ret <vscale x 2 x i64> %[[ZEXT]] // CHECK: ret <vscale x 2 x i64> %[[ZEXT]]
return svld1ub_u64(pg, base); return svld1ub_u64(pg, base);
} }
svint16_t test_svld1ub_vnum_s16(svbool_t pg, const uint8_t *base, int64_t vnum) svint16_t test_svld1ub_vnum_s16(svbool_t pg, const uint8_t *base, int64_t vnum)
{ {
// CHECK-LABEL: test_svld1ub_vnum_s16 // CHECK-LABEL: test_svld1ub_vnum_s16
// CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to <vscale x 8 x i8>* // CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to <vscale x 8 x i8>*
// CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 8 x i8>, <vscale x 8 x i8>* %[[BASE]], i64 %vnum // CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 8 x i8>, <vscale x 8 x i8>* %[[BASE]], i64 %vnum, i64 0
// CHECK: %[[LOAD:.*]] = call <vscale x 8 x i8> @llvm.masked.load.nxv8i8.p0nxv8i8(<vscale x 8 x i8>* %[[GEP]], i32 1, <vscale x 8 x i1> %[[PG]], <vscale x 8 x i8> zeroinitializer) // CHECK: %[[LOAD:.*]] = call <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8(<vscale x 8 x i1> %[[PG]], i8* %[[GEP]])
// CHECK: %[[ZEXT:.*]] = zext <vscale x 8 x i8> %[[LOAD]] to <vscale x 8 x i16> // CHECK: %[[ZEXT:.*]] = zext <vscale x 8 x i8> %[[LOAD]] to <vscale x 8 x i16>
// CHECK: ret <vscale x 8 x i16> %[[ZEXT]] // CHECK: ret <vscale x 8 x i16> %[[ZEXT]]
return svld1ub_vnum_s16(pg, base, vnum); return svld1ub_vnum_s16(pg, base, vnum);
} }
svint32_t test_svld1ub_vnum_s32(svbool_t pg, const uint8_t *base, int64_t vnum) svint32_t test_svld1ub_vnum_s32(svbool_t pg, const uint8_t *base, int64_t vnum)
{ {
// CHECK-LABEL: test_svld1ub_vnum_s32 // CHECK-LABEL: test_svld1ub_vnum_s32
// CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to <vscale x 4 x i8>* // CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to <vscale x 4 x i8>*
// CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 4 x i8>, <vscale x 4 x i8>* %[[BASE]], i64 %vnum // CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 4 x i8>, <vscale x 4 x i8>* %[[BASE]], i64 %vnum, i64 0
// CHECK: %[[LOAD:.*]] = call <vscale x 4 x i8> @llvm.masked.load.nxv4i8.p0nxv4i8(<vscale x 4 x i8>* %[[GEP]], i32 1, <vscale x 4 x i1> %[[PG]], <vscale x 4 x i8> zeroinitializer) // CHECK: %[[LOAD:.*]] = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8(<vscale x 4 x i1> %[[PG]], i8* %[[GEP]])
// CHECK: %[[ZEXT:.*]] = zext <vscale x 4 x i8> %[[LOAD]] to <vscale x 4 x i32> // CHECK: %[[ZEXT:.*]] = zext <vscale x 4 x i8> %[[LOAD]] to <vscale x 4 x i32>
// CHECK: ret <vscale x 4 x i32> %[[ZEXT]] // CHECK: ret <vscale x 4 x i32> %[[ZEXT]]
return svld1ub_vnum_s32(pg, base, vnum); return svld1ub_vnum_s32(pg, base, vnum);
} }
svint64_t test_svld1ub_vnum_s64(svbool_t pg, const uint8_t *base, int64_t vnum) svint64_t test_svld1ub_vnum_s64(svbool_t pg, const uint8_t *base, int64_t vnum)
{ {
// CHECK-LABEL: test_svld1ub_vnum_s64 // CHECK-LABEL: test_svld1ub_vnum_s64
// CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to <vscale x 2 x i8>* // CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to <vscale x 2 x i8>*
// CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 2 x i8>, <vscale x 2 x i8>* %[[BASE]], i64 %vnum // CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 2 x i8>, <vscale x 2 x i8>* %[[BASE]], i64 %vnum, i64 0
// CHECK: %[[LOAD:.*]] = call <vscale x 2 x i8> @llvm.masked.load.nxv2i8.p0nxv2i8(<vscale x 2 x i8>* %[[GEP]], i32 1, <vscale x 2 x i1> %[[PG]], <vscale x 2 x i8> zeroinitializer) // CHECK: %[[LOAD:.*]] = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.nxv2i8(<vscale x 2 x i1> %[[PG]], i8* %[[GEP]])
// CHECK: %[[ZEXT:.*]] = zext <vscale x 2 x i8> %[[LOAD]] to <vscale x 2 x i64> // CHECK: %[[ZEXT:.*]] = zext <vscale x 2 x i8> %[[LOAD]] to <vscale x 2 x i64>
// CHECK: ret <vscale x 2 x i64> %[[ZEXT]] // CHECK: ret <vscale x 2 x i64> %[[ZEXT]]
return svld1ub_vnum_s64(pg, base, vnum); return svld1ub_vnum_s64(pg, base, vnum);
} }
svuint16_t test_svld1ub_vnum_u16(svbool_t pg, const uint8_t *base, int64_t vnum) svuint16_t test_svld1ub_vnum_u16(svbool_t pg, const uint8_t *base, int64_t vnum)
{ {
// CHECK-LABEL: test_svld1ub_vnum_u16 // CHECK-LABEL: test_svld1ub_vnum_u16
// CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to <vscale x 8 x i8>* // CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to <vscale x 8 x i8>*
// CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 8 x i8>, <vscale x 8 x i8>* %[[BASE]], i64 %vnum // CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 8 x i8>, <vscale x 8 x i8>* %[[BASE]], i64 %vnum, i64 0
// CHECK: %[[LOAD:.*]] = call <vscale x 8 x i8> @llvm.masked.load.nxv8i8.p0nxv8i8(<vscale x 8 x i8>* %[[GEP]], i32 1, <vscale x 8 x i1> %[[PG]], <vscale x 8 x i8> zeroinitializer) // CHECK: %[[LOAD:.*]] = call <vscale x 8 x i8> @llvm.aarch64.sve.ld1.nxv8i8(<vscale x 8 x i1> %[[PG]], i8* %[[GEP]])
// CHECK: %[[ZEXT:.*]] = zext <vscale x 8 x i8> %[[LOAD]] to <vscale x 8 x i16> // CHECK: %[[ZEXT:.*]] = zext <vscale x 8 x i8> %[[LOAD]] to <vscale x 8 x i16>
// CHECK: ret <vscale x 8 x i16> %[[ZEXT]] // CHECK: ret <vscale x 8 x i16> %[[ZEXT]]
return svld1ub_vnum_u16(pg, base, vnum); return svld1ub_vnum_u16(pg, base, vnum);
} }
svuint32_t test_svld1ub_vnum_u32(svbool_t pg, const uint8_t *base, int64_t vnum) svuint32_t test_svld1ub_vnum_u32(svbool_t pg, const uint8_t *base, int64_t vnum)
{ {
// CHECK-LABEL: test_svld1ub_vnum_u32 // CHECK-LABEL: test_svld1ub_vnum_u32
// CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to <vscale x 4 x i8>* // CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to <vscale x 4 x i8>*
// CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 4 x i8>, <vscale x 4 x i8>* %[[BASE]], i64 %vnum // CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 4 x i8>, <vscale x 4 x i8>* %[[BASE]], i64 %vnum, i64 0
// CHECK: %[[LOAD:.*]] = call <vscale x 4 x i8> @llvm.masked.load.nxv4i8.p0nxv4i8(<vscale x 4 x i8>* %[[GEP]], i32 1, <vscale x 4 x i1> %[[PG]], <vscale x 4 x i8> zeroinitializer) // CHECK: %[[LOAD:.*]] = call <vscale x 4 x i8> @llvm.aarch64.sve.ld1.nxv4i8(<vscale x 4 x i1> %[[PG]], i8* %[[GEP]])
// CHECK: %[[ZEXT:.*]] = zext <vscale x 4 x i8> %[[LOAD]] to <vscale x 4 x i32> // CHECK: %[[ZEXT:.*]] = zext <vscale x 4 x i8> %[[LOAD]] to <vscale x 4 x i32>
// CHECK: ret <vscale x 4 x i32> %[[ZEXT]] // CHECK: ret <vscale x 4 x i32> %[[ZEXT]]
return svld1ub_vnum_u32(pg, base, vnum); return svld1ub_vnum_u32(pg, base, vnum);
} }
svuint64_t test_svld1ub_vnum_u64(svbool_t pg, const uint8_t *base, int64_t vnum) svuint64_t test_svld1ub_vnum_u64(svbool_t pg, const uint8_t *base, int64_t vnum)
{ {
// CHECK-LABEL: test_svld1ub_vnum_u64 // CHECK-LABEL: test_svld1ub_vnum_u64
// CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to <vscale x 2 x i8>* // CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to <vscale x 2 x i8>*
// CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 2 x i8>, <vscale x 2 x i8>* %[[BASE]], i64 %vnum // CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 2 x i8>, <vscale x 2 x i8>* %[[BASE]], i64 %vnum, i64 0
// CHECK: %[[LOAD:.*]] = call <vscale x 2 x i8> @llvm.masked.load.nxv2i8.p0nxv2i8(<vscale x 2 x i8>* %[[GEP]], i32 1, <vscale x 2 x i1> %[[PG]], <vscale x 2 x i8> zeroinitializer) // CHECK: %[[LOAD:.*]] = call <vscale x 2 x i8> @llvm.aarch64.sve.ld1.nxv2i8(<vscale x 2 x i1> %[[PG]], i8* %[[GEP]])
// CHECK: %[[ZEXT:.*]] = zext <vscale x 2 x i8> %[[LOAD]] to <vscale x 2 x i64> // CHECK: %[[ZEXT:.*]] = zext <vscale x 2 x i8> %[[LOAD]] to <vscale x 2 x i64>
// CHECK: ret <vscale x 2 x i64> %[[ZEXT]] // CHECK: ret <vscale x 2 x i64> %[[ZEXT]]
return svld1ub_vnum_u64(pg, base, vnum); return svld1ub_vnum_u64(pg, base, vnum);
} }
svint32_t test_svld1ub_gather_u32base_s32(svbool_t pg, svuint32_t bases) { svint32_t test_svld1ub_gather_u32base_s32(svbool_t pg, svuint32_t bases) {
// CHECK-LABEL: test_svld1ub_gather_u32base_s32 // CHECK-LABEL: test_svld1ub_gather_u32base_s32
// CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg) // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
▲ Show 20 Lines • Show All 140 Lines • Show Last 20 Lines

clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1uh.c

// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s // RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s
// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s // RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s
#include <arm_sve.h> #include <arm_sve.h>
#ifdef SVE_OVERLOADED_FORMS #ifdef SVE_OVERLOADED_FORMS
// A simple used,unused... macro, long enough to represent any SVE builtin. // A simple used,unused... macro, long enough to represent any SVE builtin.
#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3 #define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
#else #else
#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4 #define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
#endif #endif
svint32_t test_svld1uh_s32(svbool_t pg, const uint16_t *base) svint32_t test_svld1uh_s32(svbool_t pg, const uint16_t *base)
{ {
// CHECK-LABEL: test_svld1uh_s32 // CHECK-LABEL: test_svld1uh_s32
// CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg) // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to <vscale x 4 x i16>* // CHECK: %[[LOAD:.*]] = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16(<vscale x 4 x i1> %[[PG]], i16* %base)
// CHECK: %[[LOAD:.*]] = call <vscale x 4 x i16> @llvm.masked.load.nxv4i16.p0nxv4i16(<vscale x 4 x i16>* %[[BASE]], i32 1, <vscale x 4 x i1> %[[PG]], <vscale x 4 x i16> zeroinitializer)
// CHECK: %[[ZEXT:.*]] = zext <vscale x 4 x i16> %[[LOAD]] to <vscale x 4 x i32> // CHECK: %[[ZEXT:.*]] = zext <vscale x 4 x i16> %[[LOAD]] to <vscale x 4 x i32>
// CHECK: ret <vscale x 4 x i32> %[[ZEXT]] // CHECK: ret <vscale x 4 x i32> %[[ZEXT]]
return svld1uh_s32(pg, base); return svld1uh_s32(pg, base);
} }
svint64_t test_svld1uh_s64(svbool_t pg, const uint16_t *base) svint64_t test_svld1uh_s64(svbool_t pg, const uint16_t *base)
{ {
// CHECK-LABEL: test_svld1uh_s64 // CHECK-LABEL: test_svld1uh_s64
// CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg) // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to <vscale x 2 x i16>* // CHECK: %[[LOAD:.*]] = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16(<vscale x 2 x i1> %[[PG]], i16* %base)
// CHECK: %[[LOAD:.*]] = call <vscale x 2 x i16> @llvm.masked.load.nxv2i16.p0nxv2i16(<vscale x 2 x i16>* %[[BASE]], i32 1, <vscale x 2 x i1> %[[PG]], <vscale x 2 x i16> zeroinitializer)
// CHECK: %[[ZEXT:.*]] = zext <vscale x 2 x i16> %[[LOAD]] to <vscale x 2 x i64> // CHECK: %[[ZEXT:.*]] = zext <vscale x 2 x i16> %[[LOAD]] to <vscale x 2 x i64>
// CHECK: ret <vscale x 2 x i64> %[[ZEXT]] // CHECK: ret <vscale x 2 x i64> %[[ZEXT]]
return svld1uh_s64(pg, base); return svld1uh_s64(pg, base);
} }
svuint32_t test_svld1uh_u32(svbool_t pg, const uint16_t *base) svuint32_t test_svld1uh_u32(svbool_t pg, const uint16_t *base)
{ {
// CHECK-LABEL: test_svld1uh_u32 // CHECK-LABEL: test_svld1uh_u32
// CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg) // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to <vscale x 4 x i16>* // CHECK: %[[LOAD:.*]] = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16(<vscale x 4 x i1> %[[PG]], i16* %base)
// CHECK: %[[LOAD:.*]] = call <vscale x 4 x i16> @llvm.masked.load.nxv4i16.p0nxv4i16(<vscale x 4 x i16>* %[[BASE]], i32 1, <vscale x 4 x i1> %[[PG]], <vscale x 4 x i16> zeroinitializer)
// CHECK: %[[ZEXT:.*]] = zext <vscale x 4 x i16> %[[LOAD]] to <vscale x 4 x i32> // CHECK: %[[ZEXT:.*]] = zext <vscale x 4 x i16> %[[LOAD]] to <vscale x 4 x i32>
// CHECK: ret <vscale x 4 x i32> %[[ZEXT]] // CHECK: ret <vscale x 4 x i32> %[[ZEXT]]
return svld1uh_u32(pg, base); return svld1uh_u32(pg, base);
} }
svuint64_t test_svld1uh_u64(svbool_t pg, const uint16_t *base) svuint64_t test_svld1uh_u64(svbool_t pg, const uint16_t *base)
{ {
// CHECK-LABEL: test_svld1uh_u64 // CHECK-LABEL: test_svld1uh_u64
// CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg) // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to <vscale x 2 x i16>* // CHECK: %[[LOAD:.*]] = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16(<vscale x 2 x i1> %[[PG]], i16* %base)
// CHECK: %[[LOAD:.*]] = call <vscale x 2 x i16> @llvm.masked.load.nxv2i16.p0nxv2i16(<vscale x 2 x i16>* %[[BASE]], i32 1, <vscale x 2 x i1> %[[PG]], <vscale x 2 x i16> zeroinitializer)
// CHECK: %[[ZEXT:.*]] = zext <vscale x 2 x i16> %[[LOAD]] to <vscale x 2 x i64> // CHECK: %[[ZEXT:.*]] = zext <vscale x 2 x i16> %[[LOAD]] to <vscale x 2 x i64>
// CHECK: ret <vscale x 2 x i64> %[[ZEXT]] // CHECK: ret <vscale x 2 x i64> %[[ZEXT]]
return svld1uh_u64(pg, base); return svld1uh_u64(pg, base);
} }
svint32_t test_svld1uh_vnum_s32(svbool_t pg, const uint16_t *base, int64_t vnum) svint32_t test_svld1uh_vnum_s32(svbool_t pg, const uint16_t *base, int64_t vnum)
{ {
// CHECK-LABEL: test_svld1uh_vnum_s32 // CHECK-LABEL: test_svld1uh_vnum_s32
// CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to <vscale x 4 x i16>* // CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to <vscale x 4 x i16>*
// CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 4 x i16>, <vscale x 4 x i16>* %[[BASE]], i64 %vnum // CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 4 x i16>, <vscale x 4 x i16>* %[[BASE]], i64 %vnum, i64 0
// CHECK: %[[LOAD:.*]] = call <vscale x 4 x i16> @llvm.masked.load.nxv4i16.p0nxv4i16(<vscale x 4 x i16>* %[[GEP]], i32 1, <vscale x 4 x i1> %[[PG]], <vscale x 4 x i16> zeroinitializer) // CHECK: %[[LOAD:.*]] = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16(<vscale x 4 x i1> %[[PG]], i16* %[[GEP]])
// CHECK: %[[ZEXT:.*]] = zext <vscale x 4 x i16> %[[LOAD]] to <vscale x 4 x i32> // CHECK: %[[ZEXT:.*]] = zext <vscale x 4 x i16> %[[LOAD]] to <vscale x 4 x i32>
// CHECK: ret <vscale x 4 x i32> %[[ZEXT]] // CHECK: ret <vscale x 4 x i32> %[[ZEXT]]
return svld1uh_vnum_s32(pg, base, vnum); return svld1uh_vnum_s32(pg, base, vnum);
} }
svint64_t test_svld1uh_vnum_s64(svbool_t pg, const uint16_t *base, int64_t vnum) svint64_t test_svld1uh_vnum_s64(svbool_t pg, const uint16_t *base, int64_t vnum)
{ {
// CHECK-LABEL: test_svld1uh_vnum_s64 // CHECK-LABEL: test_svld1uh_vnum_s64
// CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to <vscale x 2 x i16>* // CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to <vscale x 2 x i16>*
// CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 2 x i16>, <vscale x 2 x i16>* %[[BASE]], i64 %vnum // CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 2 x i16>, <vscale x 2 x i16>* %[[BASE]], i64 %vnum, i64 0
// CHECK: %[[LOAD:.*]] = call <vscale x 2 x i16> @llvm.masked.load.nxv2i16.p0nxv2i16(<vscale x 2 x i16>* %[[GEP]], i32 1, <vscale x 2 x i1> %[[PG]], <vscale x 2 x i16> zeroinitializer) // CHECK: %[[LOAD:.*]] = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16(<vscale x 2 x i1> %[[PG]], i16* %[[GEP]])
// CHECK: %[[ZEXT:.*]] = zext <vscale x 2 x i16> %[[LOAD]] to <vscale x 2 x i64> // CHECK: %[[ZEXT:.*]] = zext <vscale x 2 x i16> %[[LOAD]] to <vscale x 2 x i64>
// CHECK: ret <vscale x 2 x i64> %[[ZEXT]] // CHECK: ret <vscale x 2 x i64> %[[ZEXT]]
return svld1uh_vnum_s64(pg, base, vnum); return svld1uh_vnum_s64(pg, base, vnum);
} }
svuint32_t test_svld1uh_vnum_u32(svbool_t pg, const uint16_t *base, int64_t vnum) svuint32_t test_svld1uh_vnum_u32(svbool_t pg, const uint16_t *base, int64_t vnum)
{ {
// CHECK-LABEL: test_svld1uh_vnum_u32 // CHECK-LABEL: test_svld1uh_vnum_u32
// CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to <vscale x 4 x i16>* // CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to <vscale x 4 x i16>*
// CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 4 x i16>, <vscale x 4 x i16>* %[[BASE]], i64 %vnum // CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 4 x i16>, <vscale x 4 x i16>* %[[BASE]], i64 %vnum, i64 0
// CHECK: %[[LOAD:.*]] = call <vscale x 4 x i16> @llvm.masked.load.nxv4i16.p0nxv4i16(<vscale x 4 x i16>* %[[GEP]], i32 1, <vscale x 4 x i1> %[[PG]], <vscale x 4 x i16> zeroinitializer) // CHECK: %[[LOAD:.*]] = call <vscale x 4 x i16> @llvm.aarch64.sve.ld1.nxv4i16(<vscale x 4 x i1> %[[PG]], i16* %[[GEP]])
// CHECK: %[[ZEXT:.*]] = zext <vscale x 4 x i16> %[[LOAD]] to <vscale x 4 x i32> // CHECK: %[[ZEXT:.*]] = zext <vscale x 4 x i16> %[[LOAD]] to <vscale x 4 x i32>
// CHECK: ret <vscale x 4 x i32> %[[ZEXT]] // CHECK: ret <vscale x 4 x i32> %[[ZEXT]]
return svld1uh_vnum_u32(pg, base, vnum); return svld1uh_vnum_u32(pg, base, vnum);
} }
svuint64_t test_svld1uh_vnum_u64(svbool_t pg, const uint16_t *base, int64_t vnum) svuint64_t test_svld1uh_vnum_u64(svbool_t pg, const uint16_t *base, int64_t vnum)
{ {
// CHECK-LABEL: test_svld1uh_vnum_u64 // CHECK-LABEL: test_svld1uh_vnum_u64
// CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to <vscale x 2 x i16>* // CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to <vscale x 2 x i16>*
// CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 2 x i16>, <vscale x 2 x i16>* %[[BASE]], i64 %vnum // CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 2 x i16>, <vscale x 2 x i16>* %[[BASE]], i64 %vnum, i64 0
// CHECK: %[[LOAD:.*]] = call <vscale x 2 x i16> @llvm.masked.load.nxv2i16.p0nxv2i16(<vscale x 2 x i16>* %[[GEP]], i32 1, <vscale x 2 x i1> %[[PG]], <vscale x 2 x i16> zeroinitializer) // CHECK: %[[LOAD:.*]] = call <vscale x 2 x i16> @llvm.aarch64.sve.ld1.nxv2i16(<vscale x 2 x i1> %[[PG]], i16* %[[GEP]])
// CHECK: %[[ZEXT:.*]] = zext <vscale x 2 x i16> %[[LOAD]] to <vscale x 2 x i64> // CHECK: %[[ZEXT:.*]] = zext <vscale x 2 x i16> %[[LOAD]] to <vscale x 2 x i64>
// CHECK: ret <vscale x 2 x i64> %[[ZEXT]] // CHECK: ret <vscale x 2 x i64> %[[ZEXT]]
return svld1uh_vnum_u64(pg, base, vnum); return svld1uh_vnum_u64(pg, base, vnum);
} }
svint32_t test_svld1uh_gather_u32base_s32(svbool_t pg, svuint32_t bases) { svint32_t test_svld1uh_gather_u32base_s32(svbool_t pg, svuint32_t bases) {
// CHECK-LABEL: test_svld1uh_gather_u32base_s32 // CHECK-LABEL: test_svld1uh_gather_u32base_s32
// CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg) // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
▲ Show 20 Lines • Show All 252 Lines • Show Last 20 Lines

clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1uw.c

// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s // RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s
// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s // RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s
#include <arm_sve.h> #include <arm_sve.h>
#ifdef SVE_OVERLOADED_FORMS #ifdef SVE_OVERLOADED_FORMS
// A simple used,unused... macro, long enough to represent any SVE builtin. // A simple used,unused... macro, long enough to represent any SVE builtin.
#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3 #define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
#else #else
#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4 #define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
#endif #endif
svint64_t test_svld1uw_s64(svbool_t pg, const uint32_t *base) svint64_t test_svld1uw_s64(svbool_t pg, const uint32_t *base)
{ {
// CHECK-LABEL: test_svld1uw_s64 // CHECK-LABEL: test_svld1uw_s64
// CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg) // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i32* %base to <vscale x 2 x i32>* // CHECK: %[[LOAD:.*]] = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32(<vscale x 2 x i1> %[[PG]], i32* %base)
// CHECK: %[[LOAD:.*]] = call <vscale x 2 x i32> @llvm.masked.load.nxv2i32.p0nxv2i32(<vscale x 2 x i32>* %[[BASE]], i32 1, <vscale x 2 x i1> %[[PG]], <vscale x 2 x i32> zeroinitializer)
// CHECK: %[[ZEXT:.*]] = zext <vscale x 2 x i32> %[[LOAD]] to <vscale x 2 x i64> // CHECK: %[[ZEXT:.*]] = zext <vscale x 2 x i32> %[[LOAD]] to <vscale x 2 x i64>
// CHECK: ret <vscale x 2 x i64> %[[ZEXT]] // CHECK: ret <vscale x 2 x i64> %[[ZEXT]]
return svld1uw_s64(pg, base); return svld1uw_s64(pg, base);
} }
svuint64_t test_svld1uw_u64(svbool_t pg, const uint32_t *base) svuint64_t test_svld1uw_u64(svbool_t pg, const uint32_t *base)
{ {
// CHECK-LABEL: test_svld1uw_u64 // CHECK-LABEL: test_svld1uw_u64
// CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg) // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i32* %base to <vscale x 2 x i32>* // CHECK: %[[LOAD:.*]] = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32(<vscale x 2 x i1> %[[PG]], i32* %base)
// CHECK: %[[LOAD:.*]] = call <vscale x 2 x i32> @llvm.masked.load.nxv2i32.p0nxv2i32(<vscale x 2 x i32>* %[[BASE]], i32 1, <vscale x 2 x i1> %[[PG]], <vscale x 2 x i32> zeroinitializer)
// CHECK: %[[ZEXT:.*]] = zext <vscale x 2 x i32> %[[LOAD]] to <vscale x 2 x i64> // CHECK: %[[ZEXT:.*]] = zext <vscale x 2 x i32> %[[LOAD]] to <vscale x 2 x i64>
// CHECK: ret <vscale x 2 x i64> %[[ZEXT]] // CHECK: ret <vscale x 2 x i64> %[[ZEXT]]
return svld1uw_u64(pg, base); return svld1uw_u64(pg, base);
} }
svint64_t test_svld1uw_vnum_s64(svbool_t pg, const uint32_t *base, int64_t vnum) svint64_t test_svld1uw_vnum_s64(svbool_t pg, const uint32_t *base, int64_t vnum)
{ {
// CHECK-LABEL: test_svld1uw_vnum_s64 // CHECK-LABEL: test_svld1uw_vnum_s64
// CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i32* %base to <vscale x 2 x i32>* // CHECK-DAG: %[[BASE:.*]] = bitcast i32* %base to <vscale x 2 x i32>*
// CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 2 x i32>, <vscale x 2 x i32>* %[[BASE]], i64 %vnum // CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 2 x i32>, <vscale x 2 x i32>* %[[BASE]], i64 %vnum, i64 0
// CHECK: %[[LOAD:.*]] = call <vscale x 2 x i32> @llvm.masked.load.nxv2i32.p0nxv2i32(<vscale x 2 x i32>* %[[GEP]], i32 1, <vscale x 2 x i1> %[[PG]], <vscale x 2 x i32> zeroinitializer) // CHECK: %[[LOAD:.*]] = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32(<vscale x 2 x i1> %[[PG]], i32* %[[GEP]])
// CHECK: %[[ZEXT:.*]] = zext <vscale x 2 x i32> %[[LOAD]] to <vscale x 2 x i64> // CHECK: %[[ZEXT:.*]] = zext <vscale x 2 x i32> %[[LOAD]] to <vscale x 2 x i64>
// CHECK: ret <vscale x 2 x i64> %[[ZEXT]] // CHECK: ret <vscale x 2 x i64> %[[ZEXT]]
return svld1uw_vnum_s64(pg, base, vnum); return svld1uw_vnum_s64(pg, base, vnum);
} }
svuint64_t test_svld1uw_vnum_u64(svbool_t pg, const uint32_t *base, int64_t vnum) svuint64_t test_svld1uw_vnum_u64(svbool_t pg, const uint32_t *base, int64_t vnum)
{ {
// CHECK-LABEL: test_svld1uw_vnum_u64 // CHECK-LABEL: test_svld1uw_vnum_u64
// CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i32* %base to <vscale x 2 x i32>* // CHECK-DAG: %[[BASE:.*]] = bitcast i32* %base to <vscale x 2 x i32>*
// CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 2 x i32>, <vscale x 2 x i32>* %[[BASE]], i64 %vnum // CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 2 x i32>, <vscale x 2 x i32>* %[[BASE]], i64 %vnum, i64 0
// CHECK: %[[LOAD:.*]] = call <vscale x 2 x i32> @llvm.masked.load.nxv2i32.p0nxv2i32(<vscale x 2 x i32>* %[[GEP]], i32 1, <vscale x 2 x i1> %[[PG]], <vscale x 2 x i32> zeroinitializer) // CHECK: %[[LOAD:.*]] = call <vscale x 2 x i32> @llvm.aarch64.sve.ld1.nxv2i32(<vscale x 2 x i1> %[[PG]], i32* %[[GEP]])
// CHECK: %[[ZEXT:.*]] = zext <vscale x 2 x i32> %[[LOAD]] to <vscale x 2 x i64> // CHECK: %[[ZEXT:.*]] = zext <vscale x 2 x i32> %[[LOAD]] to <vscale x 2 x i64>
// CHECK: ret <vscale x 2 x i64> %[[ZEXT]] // CHECK: ret <vscale x 2 x i64> %[[ZEXT]]
return svld1uw_vnum_u64(pg, base, vnum); return svld1uw_vnum_u64(pg, base, vnum);
} }
svint64_t test_svld1uw_gather_u64base_s64(svbool_t pg, svuint64_t bases) { svint64_t test_svld1uw_gather_u64base_s64(svbool_t pg, svuint64_t bases) {
// CHECK-LABEL: test_svld1uw_gather_u64base_s64 // CHECK-LABEL: test_svld1uw_gather_u64base_s64
// CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg) // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
▲ Show 20 Lines • Show All 124 Lines • Show Last 20 Lines

clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1.c

// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s // RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s
// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s // RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s
#include <arm_sve.h> #include <arm_sve.h>
#ifdef SVE_OVERLOADED_FORMS #ifdef SVE_OVERLOADED_FORMS
// A simple used,unused... macro, long enough to represent any SVE builtin. // A simple used,unused... macro, long enough to represent any SVE builtin.
#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3 #define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
#else #else
#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4 #define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
#endif #endif
void test_svst1_s8(svbool_t pg, int8_t *base, svint8_t data) void test_svst1_s8(svbool_t pg, int8_t *base, svint8_t data)
{ {
// CHECK-LABEL: test_svst1_s8 // CHECK-LABEL: test_svst1_s8
// CHECK: %[[BASE:.*]] = bitcast i8* %base to <vscale x 16 x i8>* // CHECK: call void @llvm.aarch64.sve.st1.nxv16i8(<vscale x 16 x i8> %data, <vscale x 16 x i1> %pg, i8* %base)
// CHECK: call void @llvm.masked.store.nxv16i8.p0nxv16i8(<vscale x 16 x i8> %data, <vscale x 16 x i8>* %[[BASE]], i32 1, <vscale x 16 x i1> %pg) // CHECK: ret void
return SVE_ACLE_FUNC(svst1,_s8,,)(pg, base, data); return SVE_ACLE_FUNC(svst1,_s8,,)(pg, base, data);
} }
void test_svst1_s16(svbool_t pg, int16_t *base, svint16_t data) void test_svst1_s16(svbool_t pg, int16_t *base, svint16_t data)
{ {
// CHECK-LABEL: test_svst1_s16 // CHECK-LABEL: test_svst1_s16
// CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg) // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to <vscale x 8 x i16>* // CHECK: call void @llvm.aarch64.sve.st1.nxv8i16(<vscale x 8 x i16> %data, <vscale x 8 x i1> %[[PG]], i16* %base)
// CHECK: call void @llvm.masked.store.nxv8i16.p0nxv8i16(<vscale x 8 x i16> %data, <vscale x 8 x i16>* %[[BASE]], i32 1, <vscale x 8 x i1> %[[PG]]) // CHECK: ret void
return SVE_ACLE_FUNC(svst1,_s16,,)(pg, base, data); return SVE_ACLE_FUNC(svst1,_s16,,)(pg, base, data);
} }
void test_svst1_s32(svbool_t pg, int32_t *base, svint32_t data) void test_svst1_s32(svbool_t pg, int32_t *base, svint32_t data)
{ {
// CHECK-LABEL: test_svst1_s32 // CHECK-LABEL: test_svst1_s32
// CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg) // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i32* %base to <vscale x 4 x i32>* // CHECK: call void @llvm.aarch64.sve.st1.nxv4i32(<vscale x 4 x i32> %data, <vscale x 4 x i1> %[[PG]], i32* %base)
// CHECK: call void @llvm.masked.store.nxv4i32.p0nxv4i32(<vscale x 4 x i32> %data, <vscale x 4 x i32>* %[[BASE]], i32 1, <vscale x 4 x i1> %[[PG]]) // CHECK: ret void
return SVE_ACLE_FUNC(svst1,_s32,,)(pg, base, data); return SVE_ACLE_FUNC(svst1,_s32,,)(pg, base, data);
} }
void test_svst1_s64(svbool_t pg, int64_t *base, svint64_t data) void test_svst1_s64(svbool_t pg, int64_t *base, svint64_t data)
{ {
// CHECK-LABEL: test_svst1_s64 // CHECK-LABEL: test_svst1_s64
// CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg) // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i64* %base to <vscale x 2 x i64>* // CHECK: call void @llvm.aarch64.sve.st1.nxv2i64(<vscale x 2 x i64> %data, <vscale x 2 x i1> %[[PG]], i64* %base)
// CHECK: call void @llvm.masked.store.nxv2i64.p0nxv2i64(<vscale x 2 x i64> %data, <vscale x 2 x i64>* %[[BASE]], i32 1, <vscale x 2 x i1> %[[PG]]) // CHECK: ret void
return SVE_ACLE_FUNC(svst1,_s64,,)(pg, base, data); return SVE_ACLE_FUNC(svst1,_s64,,)(pg, base, data);
} }
void test_svst1_u8(svbool_t pg, uint8_t *base, svuint8_t data) void test_svst1_u8(svbool_t pg, uint8_t *base, svuint8_t data)
{ {
// CHECK-LABEL: test_svst1_u8 // CHECK-LABEL: test_svst1_u8
// CHECK: %[[BASE:.*]] = bitcast i8* %base to <vscale x 16 x i8>* // CHECK: call void @llvm.aarch64.sve.st1.nxv16i8(<vscale x 16 x i8> %data, <vscale x 16 x i1> %pg, i8* %base)
// CHECK: call void @llvm.masked.store.nxv16i8.p0nxv16i8(<vscale x 16 x i8> %data, <vscale x 16 x i8>* %[[BASE]], i32 1, <vscale x 16 x i1> %pg) // CHECK: ret void
return SVE_ACLE_FUNC(svst1,_u8,,)(pg, base, data); return SVE_ACLE_FUNC(svst1,_u8,,)(pg, base, data);
} }
void test_svst1_u16(svbool_t pg, uint16_t *base, svuint16_t data) void test_svst1_u16(svbool_t pg, uint16_t *base, svuint16_t data)
{ {
// CHECK-LABEL: test_svst1_u16 // CHECK-LABEL: test_svst1_u16
// CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg) // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to <vscale x 8 x i16>* // CHECK: call void @llvm.aarch64.sve.st1.nxv8i16(<vscale x 8 x i16> %data, <vscale x 8 x i1> %[[PG]], i16* %base)
// CHECK: call void @llvm.masked.store.nxv8i16.p0nxv8i16(<vscale x 8 x i16> %data, <vscale x 8 x i16>* %[[BASE]], i32 1, <vscale x 8 x i1> %[[PG]]) // CHECK: ret void
return SVE_ACLE_FUNC(svst1,_u16,,)(pg, base, data); return SVE_ACLE_FUNC(svst1,_u16,,)(pg, base, data);
} }
void test_svst1_u32(svbool_t pg, uint32_t *base, svuint32_t data) void test_svst1_u32(svbool_t pg, uint32_t *base, svuint32_t data)
{ {
// CHECK-LABEL: test_svst1_u32 // CHECK-LABEL: test_svst1_u32
// CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg) // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i32* %base to <vscale x 4 x i32>* // CHECK: call void @llvm.aarch64.sve.st1.nxv4i32(<vscale x 4 x i32> %data, <vscale x 4 x i1> %[[PG]], i32* %base)
// CHECK: call void @llvm.masked.store.nxv4i32.p0nxv4i32(<vscale x 4 x i32> %data, <vscale x 4 x i32>* %[[BASE]], i32 1, <vscale x 4 x i1> %[[PG]]) // CHECK: ret void
return SVE_ACLE_FUNC(svst1,_u32,,)(pg, base, data); return SVE_ACLE_FUNC(svst1,_u32,,)(pg, base, data);
} }
void test_svst1_u64(svbool_t pg, uint64_t *base, svuint64_t data) void test_svst1_u64(svbool_t pg, uint64_t *base, svuint64_t data)
{ {
// CHECK-LABEL: test_svst1_u64 // CHECK-LABEL: test_svst1_u64
// CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg) // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i64* %base to <vscale x 2 x i64>* // CHECK: call void @llvm.aarch64.sve.st1.nxv2i64(<vscale x 2 x i64> %data, <vscale x 2 x i1> %[[PG]], i64* %base)
// CHECK: call void @llvm.masked.store.nxv2i64.p0nxv2i64(<vscale x 2 x i64> %data, <vscale x 2 x i64>* %[[BASE]], i32 1, <vscale x 2 x i1> %[[PG]]) // CHECK: ret void
return SVE_ACLE_FUNC(svst1,_u64,,)(pg, base, data); return SVE_ACLE_FUNC(svst1,_u64,,)(pg, base, data);
} }
void test_svst1_f16(svbool_t pg, float16_t *base, svfloat16_t data) void test_svst1_f16(svbool_t pg, float16_t *base, svfloat16_t data)
{ {
// CHECK-LABEL: test_svst1_f16 // CHECK-LABEL: test_svst1_f16
// CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg) // CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast half* %base to <vscale x 8 x half>* // CHECK: call void @llvm.aarch64.sve.st1.nxv8f16(<vscale x 8 x half> %data, <vscale x 8 x i1> %[[PG]], half* %base)
// CHECK: call void @llvm.masked.store.nxv8f16.p0nxv8f16(<vscale x 8 x half> %data, <vscale x 8 x half>* %[[BASE]], i32 1, <vscale x 8 x i1> %[[PG]]) // CHECK: ret void
return SVE_ACLE_FUNC(svst1,_f16,,)(pg, base, data); return SVE_ACLE_FUNC(svst1,_f16,,)(pg, base, data);
} }
void test_svst1_f32(svbool_t pg, float32_t *base, svfloat32_t data) void test_svst1_f32(svbool_t pg, float32_t *base, svfloat32_t data)
{ {
// CHECK-LABEL: test_svst1_f32 // CHECK-LABEL: test_svst1_f32
// CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg) // CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast float* %base to <vscale x 4 x float>* // CHECK: call void @llvm.aarch64.sve.st1.nxv4f32(<vscale x 4 x float> %data, <vscale x 4 x i1> %[[PG]], float* %base)
// CHECK: call void @llvm.masked.store.nxv4f32.p0nxv4f32(<vscale x 4 x float> %data, <vscale x 4 x float>* %[[BASE]], i32 1, <vscale x 4 x i1> %[[PG]]) // CHECK: ret void
return SVE_ACLE_FUNC(svst1,_f32,,)(pg, base, data); return SVE_ACLE_FUNC(svst1,_f32,,)(pg, base, data);
} }
void test_svst1_f64(svbool_t pg, float64_t *base, svfloat64_t data) void test_svst1_f64(svbool_t pg, float64_t *base, svfloat64_t data)
{ {
// CHECK-LABEL: test_svst1_f64 // CHECK-LABEL: test_svst1_f64
// CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg) // CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast double* %base to <vscale x 2 x double>* // CHECK: call void @llvm.aarch64.sve.st1.nxv2f64(<vscale x 2 x double> %data, <vscale x 2 x i1> %[[PG]], double* %base)
// CHECK: call void @llvm.masked.store.nxv2f64.p0nxv2f64(<vscale x 2 x double> %data, <vscale x 2 x double>* %[[BASE]], i32 1, <vscale x 2 x i1> %[[PG]]) // CHECK: ret void
return SVE_ACLE_FUNC(svst1,_f64,,)(pg, base, data); return SVE_ACLE_FUNC(svst1,_f64,,)(pg, base, data);
} }
void test_svst1_vnum_s8(svbool_t pg, int8_t *base, int64_t vnum, svint8_t data) void test_svst1_vnum_s8(svbool_t pg, int8_t *base, int64_t vnum, svint8_t data)
{ {
// CHECK-LABEL: test_svst1_vnum_s8 // CHECK-LABEL: test_svst1_vnum_s8
// CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to <vscale x 16 x i8>* // CHECK: %[[BASE:.*]] = bitcast i8* %base to <vscale x 16 x i8>*
// CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %[[BASE]], i64 %vnum // CHECK: %[[GEP:.*]] = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %[[BASE]], i64 %vnum, i64 0
// CHECK: call void @llvm.masked.store.nxv16i8.p0nxv16i8(<vscale x 16 x i8> %data, <vscale x 16 x i8>* %[[GEP]], i32 1, <vscale x 16 x i1> %pg) // CHECK: call void @llvm.aarch64.sve.st1.nxv16i8(<vscale x 16 x i8> %data, <vscale x 16 x i1> %pg, i8* %[[GEP]])
// CHECK: ret void
return SVE_ACLE_FUNC(svst1_vnum,_s8,,)(pg, base, vnum, data); return SVE_ACLE_FUNC(svst1_vnum,_s8,,)(pg, base, vnum, data);
} }
void test_svst1_vnum_s16(svbool_t pg, int16_t *base, int64_t vnum, svint16_t data) void test_svst1_vnum_s16(svbool_t pg, int16_t *base, int64_t vnum, svint16_t data)
{ {
// CHECK-LABEL: test_svst1_vnum_s16 // CHECK-LABEL: test_svst1_vnum_s16
// CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to <vscale x 8 x i16>* // CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to <vscale x 8 x i16>*
// CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 8 x i16>, <vscale x 8 x i16>* %[[BASE]], i64 %vnum // CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 8 x i16>, <vscale x 8 x i16>* %[[BASE]], i64 %vnum, i64 0
// CHECK: call void @llvm.masked.store.nxv8i16.p0nxv8i16(<vscale x 8 x i16> %data, <vscale x 8 x i16>* %[[GEP]], i32 1, <vscale x 8 x i1> %[[PG]]) // CHECK: call void @llvm.aarch64.sve.st1.nxv8i16(<vscale x 8 x i16> %data, <vscale x 8 x i1> %[[PG]], i16* %[[GEP]])
// CHECK: ret void
return SVE_ACLE_FUNC(svst1_vnum,_s16,,)(pg, base, vnum, data); return SVE_ACLE_FUNC(svst1_vnum,_s16,,)(pg, base, vnum, data);
} }
void test_svst1_vnum_s32(svbool_t pg, int32_t *base, int64_t vnum, svint32_t data) void test_svst1_vnum_s32(svbool_t pg, int32_t *base, int64_t vnum, svint32_t data)
{ {
// CHECK-LABEL: test_svst1_vnum_s32 // CHECK-LABEL: test_svst1_vnum_s32
// CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i32* %base to <vscale x 4 x i32>* // CHECK-DAG: %[[BASE:.*]] = bitcast i32* %base to <vscale x 4 x i32>*
// CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* %[[BASE]], i64 %vnum // CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* %[[BASE]], i64 %vnum, i64 0
// CHECK: call void @llvm.masked.store.nxv4i32.p0nxv4i32(<vscale x 4 x i32> %data, <vscale x 4 x i32>* %[[GEP]], i32 1, <vscale x 4 x i1> %[[PG]]) // CHECK: call void @llvm.aarch64.sve.st1.nxv4i32(<vscale x 4 x i32> %data, <vscale x 4 x i1> %[[PG]], i32* %[[GEP]])
// CHECK: ret void
return SVE_ACLE_FUNC(svst1_vnum,_s32,,)(pg, base, vnum, data); return SVE_ACLE_FUNC(svst1_vnum,_s32,,)(pg, base, vnum, data);
} }
void test_svst1_vnum_s64(svbool_t pg, int64_t *base, int64_t vnum, svint64_t data) void test_svst1_vnum_s64(svbool_t pg, int64_t *base, int64_t vnum, svint64_t data)
{ {
// CHECK-LABEL: test_svst1_vnum_s64 // CHECK-LABEL: test_svst1_vnum_s64
// CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i64* %base to <vscale x 2 x i64>* // CHECK-DAG: %[[BASE:.*]] = bitcast i64* %base to <vscale x 2 x i64>*
// CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 2 x i64>, <vscale x 2 x i64>* %[[BASE]], i64 %vnum // CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 2 x i64>, <vscale x 2 x i64>* %[[BASE]], i64 %vnum, i64 0
// CHECK: call void @llvm.masked.store.nxv2i64.p0nxv2i64(<vscale x 2 x i64> %data, <vscale x 2 x i64>* %[[GEP]], i32 1, <vscale x 2 x i1> %[[PG]]) // CHECK: call void @llvm.aarch64.sve.st1.nxv2i64(<vscale x 2 x i64> %data, <vscale x 2 x i1> %[[PG]], i64* %[[GEP]])
// CHECK: ret void
return SVE_ACLE_FUNC(svst1_vnum,_s64,,)(pg, base, vnum, data); return SVE_ACLE_FUNC(svst1_vnum,_s64,,)(pg, base, vnum, data);
} }
void test_svst1_vnum_u8(svbool_t pg, uint8_t *base, int64_t vnum, svuint8_t data) void test_svst1_vnum_u8(svbool_t pg, uint8_t *base, int64_t vnum, svuint8_t data)
{ {
// CHECK-LABEL: test_svst1_vnum_u8 // CHECK-LABEL: test_svst1_vnum_u8
// CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to <vscale x 16 x i8>* // CHECK: %[[BASE:.*]] = bitcast i8* %base to <vscale x 16 x i8>*
// CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %[[BASE]], i64 %vnum // CHECK: %[[GEP:.*]] = getelementptr <vscale x 16 x i8>, <vscale x 16 x i8>* %[[BASE]], i64 %vnum, i64 0
// CHECK: call void @llvm.masked.store.nxv16i8.p0nxv16i8(<vscale x 16 x i8> %data, <vscale x 16 x i8>* %[[GEP]], i32 1, <vscale x 16 x i1> %pg) // CHECK: call void @llvm.aarch64.sve.st1.nxv16i8(<vscale x 16 x i8> %data, <vscale x 16 x i1> %pg, i8* %[[GEP]])
// CHECK: ret void
return SVE_ACLE_FUNC(svst1_vnum,_u8,,)(pg, base, vnum, data); return SVE_ACLE_FUNC(svst1_vnum,_u8,,)(pg, base, vnum, data);
} }
void test_svst1_vnum_u16(svbool_t pg, uint16_t *base, int64_t vnum, svuint16_t data) void test_svst1_vnum_u16(svbool_t pg, uint16_t *base, int64_t vnum, svuint16_t data)
{ {
// CHECK-LABEL: test_svst1_vnum_u16 // CHECK-LABEL: test_svst1_vnum_u16
// CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to <vscale x 8 x i16>* // CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to <vscale x 8 x i16>*
// CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 8 x i16>, <vscale x 8 x i16>* %[[BASE]], i64 %vnum // CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 8 x i16>, <vscale x 8 x i16>* %[[BASE]], i64 %vnum, i64 0
// CHECK: call void @llvm.masked.store.nxv8i16.p0nxv8i16(<vscale x 8 x i16> %data, <vscale x 8 x i16>* %[[GEP]], i32 1, <vscale x 8 x i1> %[[PG]]) // CHECK: call void @llvm.aarch64.sve.st1.nxv8i16(<vscale x 8 x i16> %data, <vscale x 8 x i1> %[[PG]], i16* %[[GEP]])
// CHECK: ret void
return SVE_ACLE_FUNC(svst1_vnum,_u16,,)(pg, base, vnum, data); return SVE_ACLE_FUNC(svst1_vnum,_u16,,)(pg, base, vnum, data);
} }
void test_svst1_vnum_u32(svbool_t pg, uint32_t *base, int64_t vnum, svuint32_t data) void test_svst1_vnum_u32(svbool_t pg, uint32_t *base, int64_t vnum, svuint32_t data)
{ {
// CHECK-LABEL: test_svst1_vnum_u32 // CHECK-LABEL: test_svst1_vnum_u32
// CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i32* %base to <vscale x 4 x i32>* // CHECK-DAG: %[[BASE:.*]] = bitcast i32* %base to <vscale x 4 x i32>*
// CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* %[[BASE]], i64 %vnum // CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* %[[BASE]], i64 %vnum, i64 0
// CHECK: call void @llvm.masked.store.nxv4i32.p0nxv4i32(<vscale x 4 x i32> %data, <vscale x 4 x i32>* %[[GEP]], i32 1, <vscale x 4 x i1> %[[PG]]) // CHECK: call void @llvm.aarch64.sve.st1.nxv4i32(<vscale x 4 x i32> %data, <vscale x 4 x i1> %[[PG]], i32* %[[GEP]])
// CHECK: ret void
return SVE_ACLE_FUNC(svst1_vnum,_u32,,)(pg, base, vnum, data); return SVE_ACLE_FUNC(svst1_vnum,_u32,,)(pg, base, vnum, data);
} }
void test_svst1_vnum_u64(svbool_t pg, uint64_t *base, int64_t vnum, svuint64_t data) void test_svst1_vnum_u64(svbool_t pg, uint64_t *base, int64_t vnum, svuint64_t data)
{ {
// CHECK-LABEL: test_svst1_vnum_u64 // CHECK-LABEL: test_svst1_vnum_u64
// CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i64* %base to <vscale x 2 x i64>* // CHECK-DAG: %[[BASE:.*]] = bitcast i64* %base to <vscale x 2 x i64>*
// CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 2 x i64>, <vscale x 2 x i64>* %[[BASE]], i64 %vnum // CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 2 x i64>, <vscale x 2 x i64>* %[[BASE]], i64 %vnum, i64 0
// CHECK: call void @llvm.masked.store.nxv2i64.p0nxv2i64(<vscale x 2 x i64> %data, <vscale x 2 x i64>* %[[GEP]], i32 1, <vscale x 2 x i1> %[[PG]]) // CHECK: call void @llvm.aarch64.sve.st1.nxv2i64(<vscale x 2 x i64> %data, <vscale x 2 x i1> %[[PG]], i64* %[[GEP]])
// CHECK: ret void
return SVE_ACLE_FUNC(svst1_vnum,_u64,,)(pg, base, vnum, data); return SVE_ACLE_FUNC(svst1_vnum,_u64,,)(pg, base, vnum, data);
} }
void test_svst1_vnum_f16(svbool_t pg, float16_t *base, int64_t vnum, svfloat16_t data) void test_svst1_vnum_f16(svbool_t pg, float16_t *base, int64_t vnum, svfloat16_t data)
{ {
// CHECK-LABEL: test_svst1_vnum_f16 // CHECK-LABEL: test_svst1_vnum_f16
// CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast half* %base to <vscale x 8 x half>* // CHECK-DAG: %[[BASE:.*]] = bitcast half* %base to <vscale x 8 x half>*
// CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 8 x half>, <vscale x 8 x half>* %[[BASE]], i64 %vnum // CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 8 x half>, <vscale x 8 x half>* %[[BASE]], i64 %vnum, i64 0
// CHECK: call void @llvm.masked.store.nxv8f16.p0nxv8f16(<vscale x 8 x half> %data, <vscale x 8 x half>* %[[GEP]], i32 1, <vscale x 8 x i1> %[[PG]]) // CHECK: call void @llvm.aarch64.sve.st1.nxv8f16(<vscale x 8 x half> %data, <vscale x 8 x i1> %[[PG]], half* %[[GEP]])
// CHECK: ret void
return SVE_ACLE_FUNC(svst1_vnum,_f16,,)(pg, base, vnum, data); return SVE_ACLE_FUNC(svst1_vnum,_f16,,)(pg, base, vnum, data);
} }
void test_svst1_vnum_f32(svbool_t pg, float32_t *base, int64_t vnum, svfloat32_t data) void test_svst1_vnum_f32(svbool_t pg, float32_t *base, int64_t vnum, svfloat32_t data)
{ {
// CHECK-LABEL: test_svst1_vnum_f32 // CHECK-LABEL: test_svst1_vnum_f32
// CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast float* %base to <vscale x 4 x float>* // CHECK-DAG: %[[BASE:.*]] = bitcast float* %base to <vscale x 4 x float>*
// CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 4 x float>, <vscale x 4 x float>* %[[BASE]], i64 %vnum // CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 4 x float>, <vscale x 4 x float>* %[[BASE]], i64 %vnum, i64 0
// CHECK: call void @llvm.masked.store.nxv4f32.p0nxv4f32(<vscale x 4 x float> %data, <vscale x 4 x float>* %[[GEP]], i32 1, <vscale x 4 x i1> %[[PG]]) // CHECK: call void @llvm.aarch64.sve.st1.nxv4f32(<vscale x 4 x float> %data, <vscale x 4 x i1> %[[PG]], float* %[[GEP]])
// CHECK: ret void
return SVE_ACLE_FUNC(svst1_vnum,_f32,,)(pg, base, vnum, data); return SVE_ACLE_FUNC(svst1_vnum,_f32,,)(pg, base, vnum, data);
} }
void test_svst1_vnum_f64(svbool_t pg, float64_t *base, int64_t vnum, svfloat64_t data) void test_svst1_vnum_f64(svbool_t pg, float64_t *base, int64_t vnum, svfloat64_t data)
{ {
// CHECK-LABEL: test_svst1_vnum_f64 // CHECK-LABEL: test_svst1_vnum_f64
// CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast double* %base to <vscale x 2 x double>* // CHECK-DAG: %[[BASE:.*]] = bitcast double* %base to <vscale x 2 x double>*
// CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 2 x double>, <vscale x 2 x double>* %[[BASE]], i64 %vnum // CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 2 x double>, <vscale x 2 x double>* %[[BASE]], i64 %vnum, i64 0
// CHECK: call void @llvm.masked.store.nxv2f64.p0nxv2f64(<vscale x 2 x double> %data, <vscale x 2 x double>* %[[GEP]], i32 1, <vscale x 2 x i1> %[[PG]]) // CHECK: call void @llvm.aarch64.sve.st1.nxv2f64(<vscale x 2 x double> %data, <vscale x 2 x i1> %[[PG]], double* %[[GEP]])
return SVE_ACLE_FUNC(svst1_vnum,_f64,,)(pg, base, vnum, data); return SVE_ACLE_FUNC(svst1_vnum,_f64,,)(pg, base, vnum, data);
} }

clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1b.c

// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -o - -emit-llvm %s | FileCheck %s // RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -o - -emit-llvm %s | FileCheck %s
// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -o - -emit-llvm %s | FileCheck %s // RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -o - -emit-llvm %s | FileCheck %s
#include <arm_sve.h> #include <arm_sve.h>
#ifdef SVE_OVERLOADED_FORMS #ifdef SVE_OVERLOADED_FORMS
// A simple used,unused... macro, long enough to represent any SVE builtin. // A simple used,unused... macro, long enough to represent any SVE builtin.
#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3 #define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
#else #else
#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4 #define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
#endif #endif
void test_svst1b_s16(svbool_t pg, int8_t *base, svint16_t data) void test_svst1b_s16(svbool_t pg, int8_t *base, svint16_t data)
{ {
// CHECK-LABEL: test_svst1b_s16 // CHECK-LABEL: test_svst1b_s16
// CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to <vscale x 8 x i8>*
// CHECK-DAG: %[[DATA:.*]] = trunc <vscale x 8 x i16> %data to <vscale x 8 x i8> // CHECK-DAG: %[[DATA:.*]] = trunc <vscale x 8 x i16> %data to <vscale x 8 x i8>
// CHECK: call void @llvm.masked.store.nxv8i8.p0nxv8i8(<vscale x 8 x i8> %[[DATA]], <vscale x 8 x i8>* %[[BASE]], i32 1, <vscale x 8 x i1> %[[PG]]) // CHECK: call void @llvm.aarch64.sve.st1.nxv8i8(<vscale x 8 x i8> %[[DATA]], <vscale x 8 x i1> %[[PG]], i8* %base)
// CHECK: ret void // CHECK: ret void
return SVE_ACLE_FUNC(svst1b,_s16,,)(pg, base, data); return SVE_ACLE_FUNC(svst1b,_s16,,)(pg, base, data);
} }
void test_svst1b_s32(svbool_t pg, int8_t *base, svint32_t data) void test_svst1b_s32(svbool_t pg, int8_t *base, svint32_t data)
{ {
// CHECK-LABEL: test_svst1b_s32 // CHECK-LABEL: test_svst1b_s32
// CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to <vscale x 4 x i8>*
// CHECK-DAG: %[[DATA:.*]] = trunc <vscale x 4 x i32> %data to <vscale x 4 x i8> // CHECK-DAG: %[[DATA:.*]] = trunc <vscale x 4 x i32> %data to <vscale x 4 x i8>
// CHECK: call void @llvm.masked.store.nxv4i8.p0nxv4i8(<vscale x 4 x i8> %[[DATA]], <vscale x 4 x i8>* %[[BASE]], i32 1, <vscale x 4 x i1> %[[PG]]) // CHECK: call void @llvm.aarch64.sve.st1.nxv4i8(<vscale x 4 x i8> %[[DATA]], <vscale x 4 x i1> %[[PG]], i8* %base)
// CHECK: ret void // CHECK: ret void
return SVE_ACLE_FUNC(svst1b,_s32,,)(pg, base, data); return SVE_ACLE_FUNC(svst1b,_s32,,)(pg, base, data);
} }
void test_svst1b_s64(svbool_t pg, int8_t *base, svint64_t data) void test_svst1b_s64(svbool_t pg, int8_t *base, svint64_t data)
{ {
// CHECK-LABEL: test_svst1b_s64 // CHECK-LABEL: test_svst1b_s64
// CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to <vscale x 2 x i8>*
// CHECK-DAG: %[[DATA:.*]] = trunc <vscale x 2 x i64> %data to <vscale x 2 x i8> // CHECK-DAG: %[[DATA:.*]] = trunc <vscale x 2 x i64> %data to <vscale x 2 x i8>
// CHECK: call void @llvm.masked.store.nxv2i8.p0nxv2i8(<vscale x 2 x i8> %[[DATA]], <vscale x 2 x i8>* %[[BASE]], i32 1, <vscale x 2 x i1> %[[PG]]) // CHECK: call void @llvm.aarch64.sve.st1.nxv2i8(<vscale x 2 x i8> %[[DATA]], <vscale x 2 x i1> %[[PG]], i8* %base)
// CHECK: ret void // CHECK: ret void
return SVE_ACLE_FUNC(svst1b,_s64,,)(pg, base, data); return SVE_ACLE_FUNC(svst1b,_s64,,)(pg, base, data);
} }
void test_svst1b_u16(svbool_t pg, uint8_t *base, svuint16_t data) void test_svst1b_u16(svbool_t pg, uint8_t *base, svuint16_t data)
{ {
// CHECK-LABEL: test_svst1b_u16 // CHECK-LABEL: test_svst1b_u16
// CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to <vscale x 8 x i8>*
// CHECK-DAG: %[[DATA:.*]] = trunc <vscale x 8 x i16> %data to <vscale x 8 x i8> // CHECK-DAG: %[[DATA:.*]] = trunc <vscale x 8 x i16> %data to <vscale x 8 x i8>
// CHECK: call void @llvm.masked.store.nxv8i8.p0nxv8i8(<vscale x 8 x i8> %[[DATA]], <vscale x 8 x i8>* %[[BASE]], i32 1, <vscale x 8 x i1> %[[PG]]) // CHECK: call void @llvm.aarch64.sve.st1.nxv8i8(<vscale x 8 x i8> %[[DATA]], <vscale x 8 x i1> %[[PG]], i8* %base)
// CHECK: ret void // CHECK: ret void
return SVE_ACLE_FUNC(svst1b,_u16,,)(pg, base, data); return SVE_ACLE_FUNC(svst1b,_u16,,)(pg, base, data);
} }
void test_svst1b_u32(svbool_t pg, uint8_t *base, svuint32_t data) void test_svst1b_u32(svbool_t pg, uint8_t *base, svuint32_t data)
{ {
// CHECK-LABEL: test_svst1b_u32 // CHECK-LABEL: test_svst1b_u32
// CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to <vscale x 4 x i8>*
// CHECK-DAG: %[[DATA:.*]] = trunc <vscale x 4 x i32> %data to <vscale x 4 x i8> // CHECK-DAG: %[[DATA:.*]] = trunc <vscale x 4 x i32> %data to <vscale x 4 x i8>
// CHECK: call void @llvm.masked.store.nxv4i8.p0nxv4i8(<vscale x 4 x i8> %[[DATA]], <vscale x 4 x i8>* %[[BASE]], i32 1, <vscale x 4 x i1> %[[PG]]) // CHECK: call void @llvm.aarch64.sve.st1.nxv4i8(<vscale x 4 x i8> %[[DATA]], <vscale x 4 x i1> %[[PG]], i8* %base)
// CHECK: ret void // CHECK: ret void
return SVE_ACLE_FUNC(svst1b,_u32,,)(pg, base, data); return SVE_ACLE_FUNC(svst1b,_u32,,)(pg, base, data);
} }
void test_svst1b_u64(svbool_t pg, uint8_t *base, svuint64_t data) void test_svst1b_u64(svbool_t pg, uint8_t *base, svuint64_t data)
{ {
// CHECK-LABEL: test_svst1b_u64 // CHECK-LABEL: test_svst1b_u64
// CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to <vscale x 2 x i8>*
// CHECK-DAG: %[[DATA:.*]] = trunc <vscale x 2 x i64> %data to <vscale x 2 x i8> // CHECK-DAG: %[[DATA:.*]] = trunc <vscale x 2 x i64> %data to <vscale x 2 x i8>
// CHECK: call void @llvm.masked.store.nxv2i8.p0nxv2i8(<vscale x 2 x i8> %[[DATA]], <vscale x 2 x i8>* %[[BASE]], i32 1, <vscale x 2 x i1> %[[PG]]) // CHECK: call void @llvm.aarch64.sve.st1.nxv2i8(<vscale x 2 x i8> %[[DATA]], <vscale x 2 x i1> %[[PG]], i8* %base)
// CHECK: ret void // CHECK: ret void
return SVE_ACLE_FUNC(svst1b,_u64,,)(pg, base, data); return SVE_ACLE_FUNC(svst1b,_u64,,)(pg, base, data);
} }
void test_svst1b_vnum_s16(svbool_t pg, int8_t *base, int64_t vnum, svint16_t data) void test_svst1b_vnum_s16(svbool_t pg, int8_t *base, int64_t vnum, svint16_t data)
{ {
// CHECK-LABEL: test_svst1b_vnum_s16 // CHECK-LABEL: test_svst1b_vnum_s16
// CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to <vscale x 8 x i8>* // CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to <vscale x 8 x i8>*
// CHECK-DAG: %[[DATA:.*]] = trunc <vscale x 8 x i16> %data to <vscale x 8 x i8> // CHECK-DAG: %[[DATA:.*]] = trunc <vscale x 8 x i16> %data to <vscale x 8 x i8>
// CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 8 x i8>, <vscale x 8 x i8>* %[[BASE]], i64 %vnum // CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 8 x i8>, <vscale x 8 x i8>* %[[BASE]], i64 %vnum, i64 0
// CHECK: call void @llvm.masked.store.nxv8i8.p0nxv8i8(<vscale x 8 x i8> %[[DATA]], <vscale x 8 x i8>* %[[GEP]], i32 1, <vscale x 8 x i1> %[[PG]]) // CHECK: call void @llvm.aarch64.sve.st1.nxv8i8(<vscale x 8 x i8> %[[DATA]], <vscale x 8 x i1> %[[PG]], i8* %[[GEP]])
// CHECK: ret void // CHECK: ret void
return SVE_ACLE_FUNC(svst1b_vnum,_s16,,)(pg, base, vnum, data); return SVE_ACLE_FUNC(svst1b_vnum,_s16,,)(pg, base, vnum, data);
} }
void test_svst1b_vnum_s32(svbool_t pg, int8_t *base, int64_t vnum, svint32_t data) void test_svst1b_vnum_s32(svbool_t pg, int8_t *base, int64_t vnum, svint32_t data)
{ {
// CHECK-LABEL: test_svst1b_vnum_s32 // CHECK-LABEL: test_svst1b_vnum_s32
// CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to <vscale x 4 x i8>* // CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to <vscale x 4 x i8>*
// CHECK-DAG: %[[DATA:.*]] = trunc <vscale x 4 x i32> %data to <vscale x 4 x i8> // CHECK-DAG: %[[DATA:.*]] = trunc <vscale x 4 x i32> %data to <vscale x 4 x i8>
// CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 4 x i8>, <vscale x 4 x i8>* %[[BASE]], i64 %vnum // CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 4 x i8>, <vscale x 4 x i8>* %[[BASE]], i64 %vnum, i64 0
// CHECK: call void @llvm.masked.store.nxv4i8.p0nxv4i8(<vscale x 4 x i8> %[[DATA]], <vscale x 4 x i8>* %[[GEP]], i32 1, <vscale x 4 x i1> %[[PG]]) // CHECK: call void @llvm.aarch64.sve.st1.nxv4i8(<vscale x 4 x i8> %[[DATA]], <vscale x 4 x i1> %[[PG]], i8* %[[GEP]])
// CHECK: ret void // CHECK: ret void
return SVE_ACLE_FUNC(svst1b_vnum,_s32,,)(pg, base, vnum, data); return SVE_ACLE_FUNC(svst1b_vnum,_s32,,)(pg, base, vnum, data);
} }
void test_svst1b_vnum_s64(svbool_t pg, int8_t *base, int64_t vnum, svint64_t data) void test_svst1b_vnum_s64(svbool_t pg, int8_t *base, int64_t vnum, svint64_t data)
{ {
// CHECK-LABEL: test_svst1b_vnum_s64 // CHECK-LABEL: test_svst1b_vnum_s64
// CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to <vscale x 2 x i8>* // CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to <vscale x 2 x i8>*
// CHECK-DAG: %[[DATA:.*]] = trunc <vscale x 2 x i64> %data to <vscale x 2 x i8> // CHECK-DAG: %[[DATA:.*]] = trunc <vscale x 2 x i64> %data to <vscale x 2 x i8>
// CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 2 x i8>, <vscale x 2 x i8>* %[[BASE]], i64 %vnum // CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 2 x i8>, <vscale x 2 x i8>* %[[BASE]], i64 %vnum, i64 0
// CHECK: call void @llvm.masked.store.nxv2i8.p0nxv2i8(<vscale x 2 x i8> %[[DATA]], <vscale x 2 x i8>* %[[GEP]], i32 1, <vscale x 2 x i1> %[[PG]]) // CHECK: call void @llvm.aarch64.sve.st1.nxv2i8(<vscale x 2 x i8> %[[DATA]], <vscale x 2 x i1> %[[PG]], i8* %[[GEP]])
// CHECK: ret void // CHECK: ret void
return SVE_ACLE_FUNC(svst1b_vnum,_s64,,)(pg, base, vnum, data); return SVE_ACLE_FUNC(svst1b_vnum,_s64,,)(pg, base, vnum, data);
} }
void test_svst1b_vnum_u16(svbool_t pg, uint8_t *base, int64_t vnum, svuint16_t data) void test_svst1b_vnum_u16(svbool_t pg, uint8_t *base, int64_t vnum, svuint16_t data)
{ {
// CHECK-LABEL: test_svst1b_vnum_u16 // CHECK-LABEL: test_svst1b_vnum_u16
// CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to <vscale x 8 x i8>* // CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to <vscale x 8 x i8>*
// CHECK-DAG: %[[DATA:.*]] = trunc <vscale x 8 x i16> %data to <vscale x 8 x i8> // CHECK-DAG: %[[DATA:.*]] = trunc <vscale x 8 x i16> %data to <vscale x 8 x i8>
// CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 8 x i8>, <vscale x 8 x i8>* %[[BASE]], i64 %vnum // CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 8 x i8>, <vscale x 8 x i8>* %[[BASE]], i64 %vnum, i64 0
// CHECK: call void @llvm.masked.store.nxv8i8.p0nxv8i8(<vscale x 8 x i8> %[[DATA]], <vscale x 8 x i8>* %[[GEP]], i32 1, <vscale x 8 x i1> %[[PG]]) // CHECK: call void @llvm.aarch64.sve.st1.nxv8i8(<vscale x 8 x i8> %[[DATA]], <vscale x 8 x i1> %[[PG]], i8* %[[GEP]])
// CHECK: ret void // CHECK: ret void
return SVE_ACLE_FUNC(svst1b_vnum,_u16,,)(pg, base, vnum, data); return SVE_ACLE_FUNC(svst1b_vnum,_u16,,)(pg, base, vnum, data);
} }
void test_svst1b_vnum_u32(svbool_t pg, uint8_t *base, int64_t vnum, svuint32_t data) void test_svst1b_vnum_u32(svbool_t pg, uint8_t *base, int64_t vnum, svuint32_t data)
{ {
// CHECK-LABEL: test_svst1b_vnum_u32 // CHECK-LABEL: test_svst1b_vnum_u32
// CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to <vscale x 4 x i8>* // CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to <vscale x 4 x i8>*
// CHECK-DAG: %[[DATA:.*]] = trunc <vscale x 4 x i32> %data to <vscale x 4 x i8> // CHECK-DAG: %[[DATA:.*]] = trunc <vscale x 4 x i32> %data to <vscale x 4 x i8>
// CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 4 x i8>, <vscale x 4 x i8>* %[[BASE]], i64 %vnum // CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 4 x i8>, <vscale x 4 x i8>* %[[BASE]], i64 %vnum, i64 0
// CHECK: call void @llvm.masked.store.nxv4i8.p0nxv4i8(<vscale x 4 x i8> %[[DATA]], <vscale x 4 x i8>* %[[GEP]], i32 1, <vscale x 4 x i1> %[[PG]]) // CHECK: call void @llvm.aarch64.sve.st1.nxv4i8(<vscale x 4 x i8> %[[DATA]], <vscale x 4 x i1> %[[PG]], i8* %[[GEP]])
// CHECK: ret void // CHECK: ret void
return SVE_ACLE_FUNC(svst1b_vnum,_u32,,)(pg, base, vnum, data); return SVE_ACLE_FUNC(svst1b_vnum,_u32,,)(pg, base, vnum, data);
} }
void test_svst1b_vnum_u64(svbool_t pg, uint8_t *base, int64_t vnum, svuint64_t data) void test_svst1b_vnum_u64(svbool_t pg, uint8_t *base, int64_t vnum, svuint64_t data)
{ {
// CHECK-LABEL: test_svst1b_vnum_u64 // CHECK-LABEL: test_svst1b_vnum_u64
// CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to <vscale x 2 x i8>* // CHECK-DAG: %[[BASE:.*]] = bitcast i8* %base to <vscale x 2 x i8>*
// CHECK-DAG: %[[DATA:.*]] = trunc <vscale x 2 x i64> %data to <vscale x 2 x i8> // CHECK-DAG: %[[DATA:.*]] = trunc <vscale x 2 x i64> %data to <vscale x 2 x i8>
// CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 2 x i8>, <vscale x 2 x i8>* %[[BASE]], i64 %vnum // CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 2 x i8>, <vscale x 2 x i8>* %[[BASE]], i64 %vnum, i64 0
// CHECK: call void @llvm.masked.store.nxv2i8.p0nxv2i8(<vscale x 2 x i8> %[[DATA]], <vscale x 2 x i8>* %[[GEP]], i32 1, <vscale x 2 x i1> %[[PG]]) // CHECK: call void @llvm.aarch64.sve.st1.nxv2i8(<vscale x 2 x i8> %[[DATA]], <vscale x 2 x i1> %[[PG]], i8* %[[GEP]])
// CHECK: ret void // CHECK: ret void
return SVE_ACLE_FUNC(svst1b_vnum,_u64,,)(pg, base, vnum, data); return SVE_ACLE_FUNC(svst1b_vnum,_u64,,)(pg, base, vnum, data);
} }

clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1h.c

// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -o - -emit-llvm %s | FileCheck %s // RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -o - -emit-llvm %s | FileCheck %s
// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -o - -emit-llvm %s | FileCheck %s // RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -o - -emit-llvm %s | FileCheck %s
#include <arm_sve.h> #include <arm_sve.h>
#ifdef SVE_OVERLOADED_FORMS #ifdef SVE_OVERLOADED_FORMS
// A simple used,unused... macro, long enough to represent any SVE builtin. // A simple used,unused... macro, long enough to represent any SVE builtin.
#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3 #define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
#else #else
#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4 #define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
#endif #endif
void test_svst1h_s32(svbool_t pg, int16_t *base, svint32_t data) void test_svst1h_s32(svbool_t pg, int16_t *base, svint32_t data)
{ {
// CHECK-LABEL: test_svst1h_s32 // CHECK-LABEL: test_svst1h_s32
// CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to <vscale x 4 x i16>*
// CHECK-DAG: %[[DATA:.*]] = trunc <vscale x 4 x i32> %data to <vscale x 4 x i16> // CHECK-DAG: %[[DATA:.*]] = trunc <vscale x 4 x i32> %data to <vscale x 4 x i16>
// CHECK: call void @llvm.masked.store.nxv4i16.p0nxv4i16(<vscale x 4 x i16> %[[DATA]], <vscale x 4 x i16>* %[[BASE]], i32 1, <vscale x 4 x i1> %[[PG]]) // CHECK: call void @llvm.aarch64.sve.st1.nxv4i16(<vscale x 4 x i16> %[[DATA]], <vscale x 4 x i1> %[[PG]], i16* %base)
// CHECK: ret void // CHECK: ret void
return SVE_ACLE_FUNC(svst1h,_s32,,)(pg, base, data); return SVE_ACLE_FUNC(svst1h,_s32,,)(pg, base, data);
} }
void test_svst1h_s64(svbool_t pg, int16_t *base, svint64_t data) void test_svst1h_s64(svbool_t pg, int16_t *base, svint64_t data)
{ {
// CHECK-LABEL: test_svst1h_s64 // CHECK-LABEL: test_svst1h_s64
// CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to <vscale x 2 x i16>*
// CHECK-DAG: %[[DATA:.*]] = trunc <vscale x 2 x i64> %data to <vscale x 2 x i16> // CHECK-DAG: %[[DATA:.*]] = trunc <vscale x 2 x i64> %data to <vscale x 2 x i16>
// CHECK: call void @llvm.masked.store.nxv2i16.p0nxv2i16(<vscale x 2 x i16> %[[DATA]], <vscale x 2 x i16>* %[[BASE]], i32 1, <vscale x 2 x i1> %[[PG]]) // CHECK: call void @llvm.aarch64.sve.st1.nxv2i16(<vscale x 2 x i16> %[[DATA]], <vscale x 2 x i1> %[[PG]], i16* %base)
// CHECK: ret void // CHECK: ret void
return SVE_ACLE_FUNC(svst1h,_s64,,)(pg, base, data); return SVE_ACLE_FUNC(svst1h,_s64,,)(pg, base, data);
} }
void test_svst1h_u32(svbool_t pg, uint16_t *base, svuint32_t data) void test_svst1h_u32(svbool_t pg, uint16_t *base, svuint32_t data)
{ {
// CHECK-LABEL: test_svst1h_u32 // CHECK-LABEL: test_svst1h_u32
// CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to <vscale x 4 x i16>*
// CHECK-DAG: %[[DATA:.*]] = trunc <vscale x 4 x i32> %data to <vscale x 4 x i16> // CHECK-DAG: %[[DATA:.*]] = trunc <vscale x 4 x i32> %data to <vscale x 4 x i16>
// CHECK: call void @llvm.masked.store.nxv4i16.p0nxv4i16(<vscale x 4 x i16> %[[DATA]], <vscale x 4 x i16>* %[[BASE]], i32 1, <vscale x 4 x i1> %[[PG]]) // CHECK: call void @llvm.aarch64.sve.st1.nxv4i16(<vscale x 4 x i16> %[[DATA]], <vscale x 4 x i1> %[[PG]], i16* %base)
// CHECK: ret void // CHECK: ret void
return SVE_ACLE_FUNC(svst1h,_u32,,)(pg, base, data); return SVE_ACLE_FUNC(svst1h,_u32,,)(pg, base, data);
} }
void test_svst1h_u64(svbool_t pg, uint16_t *base, svuint64_t data) void test_svst1h_u64(svbool_t pg, uint16_t *base, svuint64_t data)
{ {
// CHECK-LABEL: test_svst1h_u64 // CHECK-LABEL: test_svst1h_u64
// CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to <vscale x 2 x i16>*
// CHECK-DAG: %[[DATA:.*]] = trunc <vscale x 2 x i64> %data to <vscale x 2 x i16> // CHECK-DAG: %[[DATA:.*]] = trunc <vscale x 2 x i64> %data to <vscale x 2 x i16>
// CHECK: call void @llvm.masked.store.nxv2i16.p0nxv2i16(<vscale x 2 x i16> %[[DATA]], <vscale x 2 x i16>* %[[BASE]], i32 1, <vscale x 2 x i1> %[[PG]]) // CHECK: call void @llvm.aarch64.sve.st1.nxv2i16(<vscale x 2 x i16> %[[DATA]], <vscale x 2 x i1> %[[PG]], i16* %base)
// CHECK: ret void // CHECK: ret void
return SVE_ACLE_FUNC(svst1h,_u64,,)(pg, base, data); return SVE_ACLE_FUNC(svst1h,_u64,,)(pg, base, data);
} }
void test_svst1h_vnum_s32(svbool_t pg, int16_t *base, int64_t vnum, svint32_t data) void test_svst1h_vnum_s32(svbool_t pg, int16_t *base, int64_t vnum, svint32_t data)
{ {
// CHECK-LABEL: test_svst1h_vnum_s32 // CHECK-LABEL: test_svst1h_vnum_s32
// CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to <vscale x 4 x i16>* // CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to <vscale x 4 x i16>*
// CHECK-DAG: %[[DATA:.*]] = trunc <vscale x 4 x i32> %data to <vscale x 4 x i16> // CHECK-DAG: %[[DATA:.*]] = trunc <vscale x 4 x i32> %data to <vscale x 4 x i16>
// CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 4 x i16>, <vscale x 4 x i16>* %[[BASE]], i64 %vnum // CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 4 x i16>, <vscale x 4 x i16>* %[[BASE]], i64 %vnum, i64 0
// CHECK: call void @llvm.masked.store.nxv4i16.p0nxv4i16(<vscale x 4 x i16> %[[DATA]], <vscale x 4 x i16>* %[[GEP]], i32 1, <vscale x 4 x i1> %[[PG]]) // CHECK: call void @llvm.aarch64.sve.st1.nxv4i16(<vscale x 4 x i16> %[[DATA]], <vscale x 4 x i1> %[[PG]], i16* %[[GEP]])
// CHECK: ret void // CHECK: ret void
return SVE_ACLE_FUNC(svst1h_vnum,_s32,,)(pg, base, vnum, data); return SVE_ACLE_FUNC(svst1h_vnum,_s32,,)(pg, base, vnum, data);
} }
void test_svst1h_vnum_s64(svbool_t pg, int16_t *base, int64_t vnum, svint64_t data) void test_svst1h_vnum_s64(svbool_t pg, int16_t *base, int64_t vnum, svint64_t data)
{ {
// CHECK-LABEL: test_svst1h_vnum_s64 // CHECK-LABEL: test_svst1h_vnum_s64
// CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to <vscale x 2 x i16>* // CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to <vscale x 2 x i16>*
// CHECK-DAG: %[[DATA:.*]] = trunc <vscale x 2 x i64> %data to <vscale x 2 x i16> // CHECK-DAG: %[[DATA:.*]] = trunc <vscale x 2 x i64> %data to <vscale x 2 x i16>
// CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 2 x i16>, <vscale x 2 x i16>* %[[BASE]], i64 %vnum // CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 2 x i16>, <vscale x 2 x i16>* %[[BASE]], i64 %vnum, i64 0
// CHECK: call void @llvm.masked.store.nxv2i16.p0nxv2i16(<vscale x 2 x i16> %[[DATA]], <vscale x 2 x i16>* %[[GEP]], i32 1, <vscale x 2 x i1> %[[PG]]) // CHECK: call void @llvm.aarch64.sve.st1.nxv2i16(<vscale x 2 x i16> %[[DATA]], <vscale x 2 x i1> %[[PG]], i16* %[[GEP]])
// CHECK: ret void // CHECK: ret void
return SVE_ACLE_FUNC(svst1h_vnum,_s64,,)(pg, base, vnum, data); return SVE_ACLE_FUNC(svst1h_vnum,_s64,,)(pg, base, vnum, data);
} }
void test_svst1h_vnum_u32(svbool_t pg, uint16_t *base, int64_t vnum, svuint32_t data) void test_svst1h_vnum_u32(svbool_t pg, uint16_t *base, int64_t vnum, svuint32_t data)
{ {
// CHECK-LABEL: test_svst1h_vnum_u32 // CHECK-LABEL: test_svst1h_vnum_u32
// CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to <vscale x 4 x i16>* // CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to <vscale x 4 x i16>*
// CHECK-DAG: %[[DATA:.*]] = trunc <vscale x 4 x i32> %data to <vscale x 4 x i16> // CHECK-DAG: %[[DATA:.*]] = trunc <vscale x 4 x i32> %data to <vscale x 4 x i16>
// CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 4 x i16>, <vscale x 4 x i16>* %[[BASE]], i64 %vnum // CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 4 x i16>, <vscale x 4 x i16>* %[[BASE]], i64 %vnum, i64 0
// CHECK: call void @llvm.masked.store.nxv4i16.p0nxv4i16(<vscale x 4 x i16> %[[DATA]], <vscale x 4 x i16>* %[[GEP]], i32 1, <vscale x 4 x i1> %[[PG]]) // CHECK: call void @llvm.aarch64.sve.st1.nxv4i16(<vscale x 4 x i16> %[[DATA]], <vscale x 4 x i1> %[[PG]], i16* %[[GEP]])
// CHECK: ret void // CHECK: ret void
return SVE_ACLE_FUNC(svst1h_vnum,_u32,,)(pg, base, vnum, data); return SVE_ACLE_FUNC(svst1h_vnum,_u32,,)(pg, base, vnum, data);
} }
void test_svst1h_vnum_u64(svbool_t pg, uint16_t *base, int64_t vnum, svuint64_t data) void test_svst1h_vnum_u64(svbool_t pg, uint16_t *base, int64_t vnum, svuint64_t data)
{ {
// CHECK-LABEL: test_svst1h_vnum_u64 // CHECK-LABEL: test_svst1h_vnum_u64
// CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to <vscale x 2 x i16>* // CHECK-DAG: %[[BASE:.*]] = bitcast i16* %base to <vscale x 2 x i16>*
// CHECK-DAG: %[[DATA:.*]] = trunc <vscale x 2 x i64> %data to <vscale x 2 x i16> // CHECK-DAG: %[[DATA:.*]] = trunc <vscale x 2 x i64> %data to <vscale x 2 x i16>
// CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 2 x i16>, <vscale x 2 x i16>* %[[BASE]], i64 %vnum // CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 2 x i16>, <vscale x 2 x i16>* %[[BASE]], i64 %vnum, i64 0
// CHECK: call void @llvm.masked.store.nxv2i16.p0nxv2i16(<vscale x 2 x i16> %[[DATA]], <vscale x 2 x i16>* %[[GEP]], i32 1, <vscale x 2 x i1> %[[PG]]) // CHECK: call void @llvm.aarch64.sve.st1.nxv2i16(<vscale x 2 x i16> %[[DATA]], <vscale x 2 x i1> %[[PG]], i16* %[[GEP]])
// CHECK: ret void // CHECK: ret void
return SVE_ACLE_FUNC(svst1h_vnum,_u64,,)(pg, base, vnum, data); return SVE_ACLE_FUNC(svst1h_vnum,_u64,,)(pg, base, vnum, data);
} }

clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1w.c

// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -o - -emit-llvm %s | FileCheck %s // RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -o - -emit-llvm %s | FileCheck %s
// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -o - -emit-llvm %s | FileCheck %s // RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -o - -emit-llvm %s | FileCheck %s
#include <arm_sve.h> #include <arm_sve.h>
#ifdef SVE_OVERLOADED_FORMS #ifdef SVE_OVERLOADED_FORMS
// A simple used,unused... macro, long enough to represent any SVE builtin. // A simple used,unused... macro, long enough to represent any SVE builtin.
#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3 #define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
#else #else
#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4 #define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
#endif #endif
void test_svst1w_s64(svbool_t pg, int32_t *base, svint64_t data) void test_svst1w_s64(svbool_t pg, int32_t *base, svint64_t data)
{ {
// CHECK-LABEL: test_svst1w_s64 // CHECK-LABEL: test_svst1w_s64
// CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i32* %base to <vscale x 2 x i32>*
// CHECK-DAG: %[[DATA:.*]] = trunc <vscale x 2 x i64> %data to <vscale x 2 x i32> // CHECK-DAG: %[[DATA:.*]] = trunc <vscale x 2 x i64> %data to <vscale x 2 x i32>
// CHECK: call void @llvm.masked.store.nxv2i32.p0nxv2i32(<vscale x 2 x i32> %[[DATA]], <vscale x 2 x i32>* %[[BASE]], i32 1, <vscale x 2 x i1> %[[PG]]) // CHECK: call void @llvm.aarch64.sve.st1.nxv2i32(<vscale x 2 x i32> %[[DATA]], <vscale x 2 x i1> %[[PG]], i32* %base)
// CHECK: ret void // CHECK: ret void
return SVE_ACLE_FUNC(svst1w,_s64,,)(pg, base, data); return SVE_ACLE_FUNC(svst1w,_s64,,)(pg, base, data);
} }
void test_svst1w_u64(svbool_t pg, uint32_t *base, svuint64_t data) void test_svst1w_u64(svbool_t pg, uint32_t *base, svuint64_t data)
{ {
// CHECK-LABEL: test_svst1w_u64 // CHECK-LABEL: test_svst1w_u64
// CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i32* %base to <vscale x 2 x i32>*
// CHECK-DAG: %[[DATA:.*]] = trunc <vscale x 2 x i64> %data to <vscale x 2 x i32> // CHECK-DAG: %[[DATA:.*]] = trunc <vscale x 2 x i64> %data to <vscale x 2 x i32>
// CHECK: call void @llvm.masked.store.nxv2i32.p0nxv2i32(<vscale x 2 x i32> %[[DATA]], <vscale x 2 x i32>* %[[BASE]], i32 1, <vscale x 2 x i1> %[[PG]]) // CHECK: call void @llvm.aarch64.sve.st1.nxv2i32(<vscale x 2 x i32> %[[DATA]], <vscale x 2 x i1> %[[PG]], i32* %base)
// CHECK: ret void // CHECK: ret void
return SVE_ACLE_FUNC(svst1w,_u64,,)(pg, base, data); return SVE_ACLE_FUNC(svst1w,_u64,,)(pg, base, data);
} }
void test_svst1w_vnum_s64(svbool_t pg, int32_t *base, int64_t vnum, svint64_t data) void test_svst1w_vnum_s64(svbool_t pg, int32_t *base, int64_t vnum, svint64_t data)
{ {
// CHECK-LABEL: test_svst1w_vnum_s64 // CHECK-LABEL: test_svst1w_vnum_s64
// CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i32* %base to <vscale x 2 x i32>* // CHECK-DAG: %[[BASE:.*]] = bitcast i32* %base to <vscale x 2 x i32>*
// CHECK-DAG: %[[DATA:.*]] = trunc <vscale x 2 x i64> %data to <vscale x 2 x i32> // CHECK-DAG: %[[DATA:.*]] = trunc <vscale x 2 x i64> %data to <vscale x 2 x i32>
// CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 2 x i32>, <vscale x 2 x i32>* %[[BASE]], i64 %vnum // CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 2 x i32>, <vscale x 2 x i32>* %[[BASE]], i64 %vnum, i64 0
// CHECK: call void @llvm.masked.store.nxv2i32.p0nxv2i32(<vscale x 2 x i32> %[[DATA]], <vscale x 2 x i32>* %[[GEP]], i32 1, <vscale x 2 x i1> %[[PG]]) // CHECK: call void @llvm.aarch64.sve.st1.nxv2i32(<vscale x 2 x i32> %[[DATA]], <vscale x 2 x i1> %[[PG]], i32* %[[GEP]])
// CHECK: ret void // CHECK: ret void
return SVE_ACLE_FUNC(svst1w_vnum,_s64,,)(pg, base, vnum, data); return SVE_ACLE_FUNC(svst1w_vnum,_s64,,)(pg, base, vnum, data);
} }
void test_svst1w_vnum_u64(svbool_t pg, uint32_t *base, int64_t vnum, svuint64_t data) void test_svst1w_vnum_u64(svbool_t pg, uint32_t *base, int64_t vnum, svuint64_t data)
{ {
// CHECK-LABEL: test_svst1w_vnum_u64 // CHECK-LABEL: test_svst1w_vnum_u64
// CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg) // CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
// CHECK-DAG: %[[BASE:.*]] = bitcast i32* %base to <vscale x 2 x i32>* // CHECK-DAG: %[[BASE:.*]] = bitcast i32* %base to <vscale x 2 x i32>*
// CHECK-DAG: %[[DATA:.*]] = trunc <vscale x 2 x i64> %data to <vscale x 2 x i32> // CHECK-DAG: %[[DATA:.*]] = trunc <vscale x 2 x i64> %data to <vscale x 2 x i32>
// CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 2 x i32>, <vscale x 2 x i32>* %[[BASE]], i64 %vnum // CHECK-DAG: %[[GEP:.*]] = getelementptr <vscale x 2 x i32>, <vscale x 2 x i32>* %[[BASE]], i64 %vnum, i64 0
// CHECK: call void @llvm.masked.store.nxv2i32.p0nxv2i32(<vscale x 2 x i32> %[[DATA]], <vscale x 2 x i32>* %[[GEP]], i32 1, <vscale x 2 x i1> %[[PG]]) // CHECK: call void @llvm.aarch64.sve.st1.nxv2i32(<vscale x 2 x i32> %[[DATA]], <vscale x 2 x i1> %[[PG]], i32* %[[GEP]])
// CHECK: ret void // CHECK: ret void
return SVE_ACLE_FUNC(svst1w_vnum,_u64,,)(pg, base, vnum, data); return SVE_ACLE_FUNC(svst1w_vnum,_u64,,)(pg, base, vnum, data);
} }