[RISCV] Add instruction definition for dret

[pzheng]

Summary

The instruction dret is used to return from debug mode and is defined in the
RISC-V debug mode spec.

https://github.com/riscv/riscv-opcodes/blob/master/opcodes-system

[asb]

Thanks for the patch, as we discussed last week I think supporting dret with the same ease as the privileged instructions is the right path. Given dret is defined in the debug spec rather than the privileged spec, could you please:

• Move the test to a new test file debug-valid.s
• Move the DRET instruction definition to a new section of RISCVInstrInfo.td with an internal header like

//===----------------------------------------------------------------------===//
// Debug instructions
//===----------------------------------------------------------------------===//

[pzheng]

Addressing comments

[pzheng]

Reverted changes in priv-valid.s

[apazos]

LGTM thanks for addressing Alex's comments.

llvm/lib/Target/RISCV/RISCVInstrInfo.td

 let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
 def SFENCE_VMA : RVInstR<0b0001001, 0b000, OPC_SYSTEM, (outs),
                          (ins GPR:$rs1, GPR:$rs2),
                          "sfence.vma", "$rs1, $rs2">, Sched<[]> {
   let rd = 0;
 }
 
 //===----------------------------------------------------------------------===//
+// Debug instructions
+//===----------------------------------------------------------------------===//
+
+let isBarrier = 1, isReturn = 1, isTerminator = 1 in {
+def DRET : Priv<"dret", 0b0111101>, Sched<[]> {
+  let rd = 0;
+  let rs1 = 0;
+  let rs2 = 0b10010;
+}
+} // isBarrier = 1, isReturn = 1, isTerminator = 1
+
+//===----------------------------------------------------------------------===//
 // Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
 //===----------------------------------------------------------------------===//
 
 def : InstAlias<"nop",           (ADDI      X0,      X0,       0)>;
 
 // Note that the size is 32 because up to 8 32-bit instructions are needed to
 // generate an arbitrary 64-bit immediate. However, the size does not really
 // matter since PseudoLI is currently only used in the AsmParser where it gets

llvm/test/MC/RISCV/debug-valid.s

 # RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK,CHECK-INST %s
 # RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK,CHECK-INST %s
 # RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
 # RUN:     | llvm-objdump -M no-aliases -d - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST %s
 # RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
 # RUN:     | llvm-objdump -M no-aliases -d - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST %s
 
-# CHECK-INST: uret
-# CHECK: encoding: [0x73,0x00,0x20,0x00]
-uret
-
-# CHECK-INST: sret
-# CHECK: encoding: [0x73,0x00,0x20,0x10]
-sret
-
-# CHECK-INST: mret
-# CHECK: encoding: [0x73,0x00,0x20,0x30]
-mret
-
-# CHECK-INST: wfi
-# CHECK: encoding: [0x73,0x00,0x50,0x10]
-wfi
-
-# CHECK-INST: sfence.vma zero, zero
-# CHECK: encoding: [0x73,0x00,0x00,0x12]
-sfence.vma zero, zero
-
-# CHECK-INST: sfence.vma a0, a1
-# CHECK: encoding: [0x73,0x00,0xb5,0x12]
-sfence.vma a0, a1
+# CHECK-INST: dret
+# CHECK: encoding: [0x73,0x00,0x20,0x7b]
+dret

llvm/test/MC/RISCV/priv-valid.s

 # CHECK-INST: sret
 # CHECK: encoding: [0x73,0x00,0x20,0x10]
 sret
 
 # CHECK-INST: mret
 # CHECK: encoding: [0x73,0x00,0x20,0x30]
 mret
 
+# CHECK-INST: dret
+# CHECK: encoding: [0x73,0x00,0x20,0x7b]
+dret
+
 # CHECK-INST: wfi
 # CHECK: encoding: [0x73,0x00,0x50,0x10]
 wfi
 
 # CHECK-INST: sfence.vma zero, zero
 # CHECK: encoding: [0x73,0x00,0x00,0x12]
 sfence.vma zero, zero
 
 # CHECK-INST: sfence.vma a0, a1
 # CHECK: encoding: [0x73,0x00,0xb5,0x12]
 sfence.vma a0, a1