[AMDGPU] Use RegClass helper functions in getRegForInlineAsmConstraint.

[foad]

Summary

This avoids more long lists of register classes that have to be updated
every time we add a new one. NFC.

[foad]

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

10597–10600

I don't like having exceptions like this, where we override the class that getSGPRClassForBitWidth would return. There are similar things in e.g. SIRegisterInfo::getEquivalentSGPRClass.

Perhaps getSGPRClassForBitWidth et al should be split into two different helpers, "get allocatable class" and "get *something else* class". But I really don't understand the purpose and the naming of the SReg/VReg/AReg vs SGPR/VGPR/AGPR classes, so I'm not sure how to do that.

[arsenm]

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

10597–10600

For the VGPR and AGPR cases, I think it's a naming mistake based on how these are defined in tablegen. We ended up with the register list as VGPR_* and then the class as VReg_*s for > 32.

For SGPRs, there is a distinction. SReg_* is more inclusive. SGPR_* only include number SGPRs. The various SReg_*s include different combinations of special registers like m0 and vcc or ttmp

[rampitec]

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

10626–10630

This comment is obsolete. We do support v32* since then. You probably do not need special case for 1024 here.

[foad]

Rebase.

[foad]

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

10597–10600

Thanks. Perhaps we should have both getSGPRClassForBitWidth and getSRegClassForBitWidth?

What about the TTMP classes? Should there be one for every SGPR class? Currently we have TTMP_32/64/128/256/512, missing 96/160/1024.

10626–10630

Thanks. I committed that separately and rebased this patch.

[rampitec]

LGTM

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

 //===----------------------------------------------------------------------===//
 
 std::pair<unsigned, const TargetRegisterClass *>
 SITargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
                                                StringRef Constraint,
                                                MVT VT) const {
   const TargetRegisterClass *RC = nullptr;
   if (Constraint.size() == 1) {
+    const unsigned BitWidth = VT.getSizeInBits();
     switch (Constraint[0]) {
     default:
       return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
     case 's':
     case 'r':
-      switch (VT.getSizeInBits()) {
-      default:
-        return std::make_pair(0U, nullptr);
-      case 32:
+      switch (BitWidth) {
       case 16:
         RC = &AMDGPU::SReg_32RegClass;
         break;
       case 64:
         RC = &AMDGPU::SGPR_64RegClass;
         break;
-      case 96:
-        RC = &AMDGPU::SGPR_96RegClass;
-        break;
-      case 128:
-        RC = &AMDGPU::SGPR_128RegClass;
-        break;
-      case 160:
-        RC = &AMDGPU::SGPR_160RegClass;
-        break;
-      case 192:
-        RC = &AMDGPU::SGPR_192RegClass;
-        break;
-      case 256:
-        RC = &AMDGPU::SGPR_256RegClass;
-        break;
-      case 512:
-        RC = &AMDGPU::SGPR_512RegClass;
+      default:
+        RC = SIRegisterInfo::getSGPRClassForBitWidth(BitWidth);
+        if (!RC)
+          return std::make_pair(0U, nullptr);
         break;
       }
       break;
     case 'v':
-      switch (VT.getSizeInBits()) {
-      default:
-        return std::make_pair(0U, nullptr);
-      case 32:
+      switch (BitWidth) {
       case 16:
         RC = &AMDGPU::VGPR_32RegClass;
         break;
-      case 64:
-        RC = &AMDGPU::VReg_64RegClass;
-        break;
-      case 96:
-        RC = &AMDGPU::VReg_96RegClass;
-        break;
-      case 128:
-        RC = &AMDGPU::VReg_128RegClass;
-        break;
-      case 160:
-        RC = &AMDGPU::VReg_160RegClass;
-        break;
-      case 192:
-        RC = &AMDGPU::VReg_192RegClass;
-        break;
-      case 256:
-        RC = &AMDGPU::VReg_256RegClass;
-        break;
-      case 512:
-        RC = &AMDGPU::VReg_512RegClass;
+      default:
+        RC = SIRegisterInfo::getVGPRClassForBitWidth(BitWidth);
+        if (!RC)
+          return std::make_pair(0U, nullptr);
         break;
       }
       break;
     case 'a':
       if (!Subtarget->hasMAIInsts())
         break;
-      switch (VT.getSizeInBits()) {
-      default:
-        return std::make_pair(0U, nullptr);
-      case 32:
+      switch (BitWidth) {
       case 16:
         RC = &AMDGPU::AGPR_32RegClass;
         break;
-      case 64:
-        RC = &AMDGPU::AReg_64RegClass;
-        break;
-      case 96:
-        RC = &AMDGPU::AReg_96RegClass;
-        break;
-      case 128:
-        RC = &AMDGPU::AReg_128RegClass;
-        break;
-      case 160:
-        RC = &AMDGPU::AReg_160RegClass;
-        break;
-      case 192:
-        RC = &AMDGPU::AReg_192RegClass;
-        break;
-      case 256:
-        RC = &AMDGPU::AReg_256RegClass;
-        break;
-      case 512:
-        RC = &AMDGPU::AReg_512RegClass;
-        break;
-      case 1024:
-        RC = &AMDGPU::AReg_1024RegClass;
+      default:
+        RC = SIRegisterInfo::getAGPRClassForBitWidth(BitWidth);
+        if (!RC)
+          return std::make_pair(0U, nullptr);
         break;
       }
       break;
     }
     // We actually support i128, i16 and f16 as inline parameters
     // even if they are not reported as legal
     if (RC && (isTypeLegal(VT) || VT.SimpleTy == MVT::i128 ||
                VT.SimpleTy == MVT::i16 || VT.SimpleTy == MVT::f16))
       return std::make_pair(0U, RC);