[RISCV][PowerPC] Fix google/benchmark benchmark::cycleclock::Now

[luismarques]

Summary

This is a cherrypick of the upstream fix commit a77d5f7 onto
llvm/utils/benchmark and libcxx/utils/google-benchmark.
This fixes LLVM's 32-bit RISC-V compilation, and the issues
mentioned in https://github.com/google/benchmark/pull/955
An additional cherrypick of ecc1685 fixes some minor formatting
issues introduced by the preceding commit.

[lebedev.ri]

Thank you for this.
Please also update *benchmark/README.LLVM to note the cherry-pick.
Also, there's one more copy in test-suite, you may want to patch that one too, though that one is not in the monorepor.

[ldionne]

Nice, thanks! LGTM once @lebedev.ri 's comment is addressed.

[luismarques]

• Also apply a cherrypick that minimizes LLVM lint formatting issues;
• List the cherrypicks in benchmark*/README.LLVM;
• Update summary accordingly.

[luismarques]

Merged the */README.LLVM change entries, as having separate entries for a single LLVM commit could be confusing.

[lebedev.ri]

LG, thank you!
Please consider following-up with similar test-suite change.

libcxx/utils/google-benchmark/src/cycleclock.h

#elif defined(__i386__)
   __asm__ volatile("rdtsc" : "=A"(ret));
   return ret;
 #elif defined(__x86_64__) || defined(__amd64__)
   uint64_t low, high;
   __asm__ volatile("rdtsc" : "=a"(low), "=d"(high));
   return (high << 32) | low;
 #elif defined(__powerpc__) || defined(__ppc__)
   // This returns a time-base, which is not always precisely a cycle-count.
-  int64_t tbl, tbu0, tbu1;
-  asm("mftbu %0" : "=r"(tbu0));
-  asm("mftb  %0" : "=r"(tbl));
-  asm("mftbu %0" : "=r"(tbu1));
-  tbl &= -static_cast<int64_t>(tbu0 == tbu1);
-  // high 32 bits in tbu1; low 32 bits in tbl  (tbu0 is garbage)
-  return (tbu1 << 32) | tbl;
+#if defined(__powerpc64__) || defined(__ppc64__)
+  int64_t tb;
+  asm volatile("mfspr %0, 268" : "=r" (tb));
+  return tb;
+#else
+  uint32_t tbl, tbu0, tbu1;
+  asm volatile(
+    "mftbu %0\n"
+    "mftbl %1\n"
+    "mftbu %2"
+    : "=r"(tbu0), "=r"(tbl), "=r"(tbu1));
+  tbl &= -static_cast<int32_t>(tbu0 == tbu1);
+  // high 32 bits in tbu1; low 32 bits in tbl  (tbu0 is no longer needed)
+  return (static_cast<uint64_t>(tbu1) << 32) | tbl;
+#endif
 #elif defined(__sparc__)
   int64_t tick;
   asm(".byte 0x83, 0x41, 0x00, 0x00");
   asm("mov   %%g1, %0" : "=r"(tick));
   return tick;
 #elif defined(__ia64__)
   int64_t itc;
   asm("mov %0 = ar.itc" : "=r"(itc));

 #elif defined(__s390__)  // Covers both s390 and s390x.
   // Return the CPU clock.
   uint64_t tsc;
   asm("stck %0" : "=Q"(tsc) : : "cc");
   return tsc;
 #elif defined(__riscv) // RISC-V
   // Use RDCYCLE (and RDCYCLEH on riscv32)
 #if __riscv_xlen == 32
-  uint64_t cycles_low, cycles_hi0, cycles_hi1;
-  asm("rdcycleh %0" : "=r"(cycles_hi0));
-  asm("rdcycle %0" : "=r"(cycles_lo));
-  asm("rdcycleh %0" : "=r"(cycles_hi1));
-  // This matches the PowerPC overflow detection, above
-  cycles_lo &= -static_cast<int64_t>(cycles_hi0 == cycles_hi1);
-  return (cycles_hi1 << 32) | cycles_lo;
+  uint32_t cycles_lo, cycles_hi0, cycles_hi1;
+  // This asm also includes the PowerPC overflow handling strategy, as above.
+  // Implemented in assembly because Clang insisted on branching.
+  asm volatile(
+    "rdcycleh %0\n"
+    "rdcycle %1\n"
+    "rdcycleh %2\n"
+    "sub %0, %0, %2\n"
+    "seqz %0, %0\n"
+    "sub %0, zero, %0\n"
+    "and %1, %1, %0\n"
+    : "=r"(cycles_hi0), "=r"(cycles_lo), "=r"(cycles_hi1));
+  return (static_cast<uint64_t>(cycles_hi1) << 32) | cycles_lo;
 #else
   uint64_t cycles;
-  asm("rdcycle %0" : "=r"(cycles));
+  asm volatile("rdcycle %0" : "=r"(cycles));
   return cycles;
 #endif
 #else
 // The soft failover to a generic implementation is automatic only for ARM.
 // For other platforms the developer is expected to make an attempt to create
 // a fast implementation and use generic version if nothing better is available.
 #error You need to define CycleTimer for your OS and CPU
 #endif
 }
 }  // end namespace cycleclock
 }  // end namespace benchmark
 
 #endif  // BENCHMARK_CYCLECLOCK_H_

llvm/utils/benchmark/src/cycleclock.h

#elif defined(__i386__)
   __asm__ volatile("rdtsc" : "=A"(ret));
   return ret;
 #elif defined(__x86_64__) || defined(__amd64__)
   uint64_t low, high;
   __asm__ volatile("rdtsc" : "=a"(low), "=d"(high));
   return (high << 32) | low;
 #elif defined(__powerpc__) || defined(__ppc__)
   // This returns a time-base, which is not always precisely a cycle-count.
-  int64_t tbl, tbu0, tbu1;
-  asm("mftbu %0" : "=r"(tbu0));
-  asm("mftb  %0" : "=r"(tbl));
-  asm("mftbu %0" : "=r"(tbu1));
-  tbl &= -static_cast<int64_t>(tbu0 == tbu1);
-  // high 32 bits in tbu1; low 32 bits in tbl  (tbu0 is garbage)
-  return (tbu1 << 32) | tbl;
+#if defined(__powerpc64__) || defined(__ppc64__)
+  int64_t tb;
+  asm volatile("mfspr %0, 268" : "=r" (tb));
+  return tb;
+#else
+  uint32_t tbl, tbu0, tbu1;
+  asm volatile(
+    "mftbu %0\n"
+    "mftbl %1\n"
+    "mftbu %2"
+    : "=r"(tbu0), "=r"(tbl), "=r"(tbu1));
+  tbl &= -static_cast<int32_t>(tbu0 == tbu1);
+  // high 32 bits in tbu1; low 32 bits in tbl  (tbu0 is no longer needed)
+  return (static_cast<uint64_t>(tbu1) << 32) | tbl;
+#endif
 #elif defined(__sparc__)
   int64_t tick;
   asm(".byte 0x83, 0x41, 0x00, 0x00");
   asm("mov   %%g1, %0" : "=r"(tick));
   return tick;
 #elif defined(__ia64__)
   int64_t itc;
   asm("mov %0 = ar.itc" : "=r"(itc));

 #elif defined(__s390__) // Covers both s390 and s390x.
   // Return the CPU clock.
   uint64_t tsc;
   asm("stck %0" : "=Q" (tsc) : : "cc");
   return tsc;
 #elif defined(__riscv) // RISC-V
   // Use RDCYCLE (and RDCYCLEH on riscv32)
 #if __riscv_xlen == 32
-  uint64_t cycles_low, cycles_hi0, cycles_hi1;
-  asm("rdcycleh %0" : "=r"(cycles_hi0));
-  asm("rdcycle %0" : "=r"(cycles_lo));
-  asm("rdcycleh %0" : "=r"(cycles_hi1));
-  // This matches the PowerPC overflow detection, above
-  cycles_lo &= -static_cast<int64_t>(cycles_hi0 == cycles_hi1);
-  return (cycles_hi1 << 32) | cycles_lo;
+  uint32_t cycles_lo, cycles_hi0, cycles_hi1;
+  // This asm also includes the PowerPC overflow handling strategy, as above.
+  // Implemented in assembly because Clang insisted on branching.
+  asm volatile(
+    "rdcycleh %0\n"
+    "rdcycle %1\n"
+    "rdcycleh %2\n"
+    "sub %0, %0, %2\n"
+    "seqz %0, %0\n"
+    "sub %0, zero, %0\n"
+    "and %1, %1, %0\n"
+    : "=r"(cycles_hi0), "=r"(cycles_lo), "=r"(cycles_hi1));
+  return (static_cast<uint64_t>(cycles_hi1) << 32) | cycles_lo;
 #else
   uint64_t cycles;
-  asm("rdcycle %0" : "=r"(cycles));
+  asm volatile("rdcycle %0" : "=r"(cycles));
   return cycles;
 #endif
 #else
 // The soft failover to a generic implementation is automatic only for ARM.
 // For other platforms the developer is expected to make an attempt to create
 // a fast implementation and use generic version if nothing better is available.
 #error You need to define CycleTimer for your OS and CPU
 #endif
 }
 }  // end namespace cycleclock
 }  // end namespace benchmark
 
 #endif  // BENCHMARK_CYCLECLOCK_H_