[PowerPC] Add some InstAlias definitions

[ZhangKang]

Summary

This patch add the InstAlias definitions for below instructions.

ADDI ADDIS ADDI8 ADDIS8
RLWINM8
ISEL ISEL8
OR OR_rec ORI ORI8 XORI8
CNTLZW8 CNTLZW8_rec
TEND TSR
RFEBB
NOR NOR_rec
MTCRF
SUBF SUBF_rec SUBFC SUBFC_rec
RLDICL_32_64
TW

[ZhangKang]

ping

[steven.zhang]

LGTM. I trust in you that you have done a fully test for this patch and check it carefully with PowerISA.

[ZhangKang]

Rebase.

lld/test/ELF/ppc32-call-stub-pic.s

 ## Operand of addi: 0x100a8-.glink = 24
 # CHECK-NEXT:         addis 11, 11, 0
 # CHECK-NEXT:         mflr 0
 # CHECK-NEXT:         bcl 20, 31, 0x[[#%x,NEXT:]]
 # CHECK-NEXT: [[#%x,NEXT]]: addi 11, 11, 24
 
 # CHECK-NEXT: mflr 12
 # CHECK-NEXT: mtlr 0
-# CHECK-NEXT: subf 11, 12, 11
+# CHECK-NEXT: sub 11, 11, 12
 
 ## Operand of lwz in -pie mode: &.got[1] - 0x100a8 = 0x20088+4 - 0x100a8 = 65536*1-28
 # CHECK-NEXT:  addis 12, 12, 1
 # PIE-NEXT:    lwz 0, 192(12)
 # SHARED-NEXT: lwz 0, 184(12)
 
 # PIE-NEXT:    lwz 12, 196(12)
 # SHARED-NEXT: lwz 12, 188(12)

llvm/lib/Target/PowerPC/PPCInstr64Bit.td

 def ISEL8   : AForm_4<31, 15,
                      (outs g8rc:$rT), (ins g8rc_nox0:$rA, g8rc:$rB, crbitrc:$cond),
                      "isel $rT, $rA, $rB, $cond", IIC_IntISEL,
                      []>;
 }  // Interpretation64Bit
 }  // hasSideEffects = 0
 }  // End FXU Operations.
 
+def : InstAlias<"li $rD, $imm", (ADDI8 g8rc:$rD, ZERO8, s16imm64:$imm)>;
+def : InstAlias<"lis $rD, $imm", (ADDIS8 g8rc:$rD, ZERO8, s17imm64:$imm)>;
+
 def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
 def : InstAlias<"mr. $rA, $rB", (OR8_rec g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
 
 def : InstAlias<"not $rA, $rB", (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
 def : InstAlias<"not. $rA, $rB", (NOR8_rec g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
 
 def : InstAlias<"mtcr $rA", (MTCRF8 255, g8rc:$rA)>;
 
 def : InstAlias<"sub $rA, $rB, $rC", (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
 def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8_rec g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
 def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
 def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8_rec g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
 
 def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM8 g8rc:$rA, g8rc:$rS, u5imm:$n, 0, 31)>;
 def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINM8_rec g8rc:$rA, g8rc:$rS, u5imm:$n, 0, 31)>;
 def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM8 g8rc:$rA, g8rc:$rS, g8rc:$rB, 0, 31)>;
 def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNM8_rec g8rc:$rA, g8rc:$rS, g8rc:$rB, 0, 31)>;
+def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM8 g8rc:$rA, g8rc:$rS, 0, u5imm:$n, 31)>;
+def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINM8_rec g8rc:$rA, g8rc:$rS, 0, u5imm:$n, 31)>;
+
+def : InstAlias<"isellt $rT, $rA, $rB",
+                (ISEL8 g8rc:$rT, g8rc_nox0:$rA, g8rc:$rB, CR0LT)>;
+def : InstAlias<"iselgt $rT, $rA, $rB",
+                (ISEL8 g8rc:$rT, g8rc_nox0:$rA, g8rc:$rB, CR0GT)>;
+def : InstAlias<"iseleq $rT, $rA, $rB",
+                (ISEL8 g8rc:$rT, g8rc_nox0:$rA, g8rc:$rB, CR0EQ)>;
+
+def : InstAlias<"nop", (ORI8 X0, X0, 0)>;
+def : InstAlias<"xnop", (XORI8 X0, X0, 0)>;
+
+def : InstAlias<"cntlzw $rA, $rS", (CNTLZW8 g8rc:$rA, g8rc:$rS)>;
+def : InstAlias<"cntlzw. $rA, $rS", (CNTLZW8_rec g8rc:$rA, g8rc:$rS)>;
 
 //===----------------------------------------------------------------------===//
 // Load/Store instructions.
 //
 
 
 // Sign extending loads.
 let PPC970_Unit = 2 in {

llvm/lib/Target/PowerPC/PPCInstrHTM.td

def : Pat<(int_ppc_tsuspend),
           (TSR 0)>;
 
 def : Pat<(i64 (int_ppc_ttest)),
           (RLDICL (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
                                       (TABORTWCI 0, (LI 0), 0), sub_32)),
                    36, 28)>;
 
 } // [HasHTM]
+
+def : InstAlias<"tend.", (TEND 0)>, Requires<[HasHTM]>;
+def : InstAlias<"tendall.", (TEND 1)>, Requires<[HasHTM]>;
+def : InstAlias<"tsuspend.", (TSR 0)>, Requires<[HasHTM]>;
+def : InstAlias<"tresume.", (TSR 1)>, Requires<[HasHTM]>;

llvm/lib/Target/PowerPC/PPCInstrInfo.td

def MFBHRBE : XFXForm_3p<31, 302, (outs gprc:$rD),
                          [(set i32:$rD,
                                (PPCmfbhrbe imm:$imm, imm:$dmy))]>,
                          PPC970_DGroup_First;
 
 def RFEBB : XLForm_S<19, 146, (outs), (ins u1imm:$imm), "rfebb $imm",
                      IIC_BrB, [(PPCrfebb (i32 imm:$imm))]>,
                      PPC970_DGroup_Single;
 
+def : InstAlias<"rfebb", (RFEBB 1)>;
+
 // DCB* instructions.
 def DCBA   : DCB_Form<758, 0, (outs), (ins memrr:$dst), "dcba $dst",
                       IIC_LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
                       PPC970_DGroup_Single;
 def DCBI   : DCB_Form<470, 0, (outs), (ins memrr:$dst), "dcbi $dst",
                       IIC_LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
                       PPC970_DGroup_Single;
 def DCBST  : DCB_Form<54, 0, (outs), (ins memrr:$dst), "dcbst $dst",
def LI  : DForm_2_r0<14, (outs gprc:$rD), (ins s16imm:$imm),
                        "li $rD, $imm", IIC_IntSimple,
                        [(set i32:$rD, imm32SExt16:$imm)]>;
   def LIS : DForm_2_r0<15, (outs gprc:$rD), (ins s17imm:$imm),
                        "lis $rD, $imm", IIC_IntSimple,
                        [(set i32:$rD, imm16ShiftedSExt:$imm)]>;
 }
 }
 
+def : InstAlias<"li $rD, $imm", (ADDI gprc:$rD, ZERO, s16imm:$imm)>;
+def : InstAlias<"lis $rD, $imm", (ADDIS gprc:$rD, ZERO, s17imm:$imm)>;
+
 let PPC970_Unit = 1 in {  // FXU Operations.
 let Defs = [CR0] in {
 def ANDI_rec : DForm_4<28, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
                     "andi. $dst, $src1, $src2", IIC_IntGeneral,
                     [(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>,
                     isRecordForm;
 def ANDIS_rec : DForm_4<29, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
                     "andis. $dst, $src1, $src2", IIC_IntGeneral,

 defm SRW  : XForm_6r<31, 536, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
                      "srw", "$rA, $rS, $rB", IIC_IntGeneral,
                      [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>;
 defm SRAW : XForm_6rc<31, 792, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
                       "sraw", "$rA, $rS, $rB", IIC_IntShift,
                       [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>;
 }
 
+def : InstAlias<"mr $rA, $rB", (OR gprc:$rA, gprc:$rB, gprc:$rB)>;
+def : InstAlias<"mr. $rA, $rB", (OR_rec gprc:$rA, gprc:$rB, gprc:$rB)>;
+
+def : InstAlias<"not $rA, $rS", (NOR gprc:$rA, gprc:$rS, gprc:$rS)>;
+def : InstAlias<"not. $rA, $rS", (NOR_rec gprc:$rA, gprc:$rS, gprc:$rS)>;
+
+def : InstAlias<"nop", (ORI R0, R0, 0)>;
+
 let PPC970_Unit = 1 in {  // FXU Operations.
 let hasSideEffects = 0 in {
 defm SRAWI : XForm_10rc<31, 824, (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH),
                         "srawi", "$rA, $rS, $SH", IIC_IntShift,
                         [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>;
 defm CNTLZW : XForm_11r<31,  26, (outs gprc:$rA), (ins gprc:$rS),
                         "cntlzw", "$rA, $rS", IIC_IntGeneral,
                         [(set i32:$rA, (ctlz i32:$rS))]>;
def MFCR : XFXForm_3<31, 19, (outs gprc:$rT), (ins),
                      "mfcr $rT", IIC_SprMFCR>,
                      PPC970_MicroCode, PPC970_Unit_CRU;
 } // hasExtraSrcRegAllocReq = 1
 
 def MCRXRX : X_BF3<31, 576, (outs crrc:$BF), (ins),
                    "mcrxrx $BF", IIC_BrMCRX>, Requires<[IsISA3_0]>;
 } // hasSideEffects = 0
 
+def : InstAlias<"mtcr $rA", (MTCRF 255, gprc:$rA)>;
+
 let Predicates = [HasFPU] in {
 // Custom inserter instruction to perform FADD in round-to-zero mode.
 let Uses = [RM] in {
   def FADDrtz: PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "",
                       [(set f64:$FRT, (PPCfaddrtz f64:$FRA, f64:$FRB))]>;
 }
 
 // The above pseudo gets expanded to make use of the following instructions
defm SUBFME : XOForm_3rc<31, 232, 0, (outs gprc:$rT), (ins gprc:$rA),
                          "subfme", "$rT, $rA", IIC_IntGeneral,
                          [(set i32:$rT, (sube -1, i32:$rA))]>;
 defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$rT), (ins gprc:$rA),
                          "subfze", "$rT, $rA", IIC_IntGeneral,
                          [(set i32:$rT, (sube 0, i32:$rA))]>;
 }
 }
 
+def : InstAlias<"sub $rA, $rB, $rC", (SUBF gprc:$rA, gprc:$rC, gprc:$rB)>;
+def : InstAlias<"sub. $rA, $rB, $rC", (SUBF_rec gprc:$rA, gprc:$rC, gprc:$rB)>;
+def : InstAlias<"subc $rA, $rB, $rC", (SUBFC gprc:$rA, gprc:$rC, gprc:$rB)>;
+def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC_rec gprc:$rA, gprc:$rC, gprc:$rB)>;
+
 // A-Form instructions.  Most of the instructions executed in the FPU are of
 // this type.
 //
 let PPC970_Unit = 3, hasSideEffects = 0, Predicates = [HasFPU] in {  // FPU Operations.
 let Uses = [RM] in {
 let isCommutable = 1 in {
   defm FMADD : AForm_1r<63, 29, 
                       (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
def CLRRWI : PPCAsmPseudo<"clrrwi $rA, $rS, $n",
                           (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
 def CLRRWI_rec : PPCAsmPseudo<"clrrwi. $rA, $rS, $n",
                            (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
 def CLRLSLWI : PPCAsmPseudo<"clrlslwi $rA, $rS, $b, $n",
                             (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
 def CLRLSLWI_rec : PPCAsmPseudo<"clrlslwi. $rA, $rS, $b, $n",
                              (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
 
+def : InstAlias<"isellt $rT, $rA, $rB",
+                (ISEL gprc:$rT, gprc_nor0:$rA, gprc:$rB, CR0LT)>;
+def : InstAlias<"iselgt $rT, $rA, $rB",
+                (ISEL gprc:$rT, gprc_nor0:$rA, gprc:$rB, CR0GT)>;
+def : InstAlias<"iseleq $rT, $rA, $rB",
+                (ISEL gprc:$rT, gprc_nor0:$rA, gprc:$rB, CR0EQ)>;
+
 def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
 def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINM_rec gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
 def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
 def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNM_rec gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
 def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
 def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINM_rec gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
 
 def : InstAlias<"cntlzw $rA, $rS", (CNTLZW gprc:$rA, gprc:$rS)>;
def CLRRDI_rec : PPCAsmPseudo<"clrrdi. $rA, $rS, $n",
                            (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
 def CLRLSLDI : PPCAsmPseudo<"clrlsldi $rA, $rS, $b, $n",
                             (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
 def CLRLSLDI_rec : PPCAsmPseudo<"clrlsldi. $rA, $rS, $b, $n",
                              (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
 def SUBPCIS : PPCAsmPseudo<"subpcis $RT, $D", (ins g8rc:$RT, s16imm:$D)>;
 
 def : InstAlias<"rotldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
+def : InstAlias<"rotldi $rA, $rS, $n",
+                (RLDICL_32_64 g8rc:$rA, gprc:$rS, u6imm:$n, 0)>;
 def : InstAlias<"rotldi. $rA, $rS, $n", (RLDICL_rec g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
 def : InstAlias<"rotld $rA, $rS, $rB", (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
 def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCL_rec g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
 def : InstAlias<"clrldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
 def : InstAlias<"clrldi $rA, $rS, $n",
                 (RLDICL_32_64 g8rc:$rA, gprc:$rS, 0, u6imm:$n)>;
 def : InstAlias<"clrldi. $rA, $rS, $n", (RLDICL_rec g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
 def : InstAlias<"lnia $RT", (ADDPCIS g8rc:$RT, 0)>;

 def : InstAlias<"cmp $bf, 0, $rA, $rB", (CMPW crrc:$bf, gprc:$rA, gprc:$rB)>;
 def : InstAlias<"cmpli $bf, 0, $rA, $imm", (CMPLWI crrc:$bf, gprc:$rA, u16imm:$imm)>;
 def : InstAlias<"cmpl $bf, 0, $rA, $rB", (CMPLW crrc:$bf, gprc:$rA, gprc:$rB)>;
 def : InstAlias<"cmpi $bf, 1, $rA, $imm", (CMPDI crrc:$bf, g8rc:$rA, s16imm64:$imm)>;
 def : InstAlias<"cmp $bf, 1, $rA, $rB", (CMPD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
 def : InstAlias<"cmpli $bf, 1, $rA, $imm", (CMPLDI crrc:$bf, g8rc:$rA, u16imm64:$imm)>;
 def : InstAlias<"cmpl $bf, 1, $rA, $rB", (CMPLD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
 
+def : InstAlias<"trap", (TW 31, R0, R0)>;
+
 multiclass TrapExtendedMnemonic<string name, int to> {
   def : InstAlias<"td"#name#"i $rA, $imm", (TDI to, g8rc:$rA, s16imm:$imm)>;
   def : InstAlias<"td"#name#" $rA, $rB", (TD to, g8rc:$rA, g8rc:$rB)>;
   def : InstAlias<"tw"#name#"i $rA, $imm", (TWI to, gprc:$rA, s16imm:$imm)>;
   def : InstAlias<"tw"#name#" $rA, $rB", (TW to, gprc:$rA, gprc:$rB)>;
 }
 defm : TrapExtendedMnemonic<"lt", 16>;
 defm : TrapExtendedMnemonic<"le", 20>;

llvm/test/CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll

 ; RUN: llc -verify-machineinstrs < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs < %s -regalloc=fast -optimize-regalloc=0 | FileCheck %s
 ; The first argument of subfc must not be the same as any other register.
 
 ; CHECK: APP
-; CHECK: subfc [[REG:[0-9]+]],
+; CHECK: subc [[REG:[0-9]+]],
 ; CHECK-NOT: [[REG]]
 ; CHECK: NO_APP
 ; PR1357
 
 ;target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
 target triple = "powerpc-unknown-linux-gnu"
 
 ;long long test(int A, int B, int C) {

llvm/test/CodeGen/PowerPC/2010-02-12-saveCR.ll

 ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu -break-anti-dependencies=none | FileCheck %s
 ; ModuleID = 'hh.c'
 ;;;;; target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128-n32"
 target triple = "powerpc-unknown-linux-gnu.6"
 
 define void @foo() nounwind {
 entry:
 ; Note that part of what is being checked here is proper register reuse.
 ; CHECK: mfcr [[T1:[0-9]+]]
-; CHECK-DAG: subf 0, 0, 1
+; CHECK-DAG: sub 0, 1, 0
 ; CHECK-DAG: ori [[T2:[0-9]+]], [[T2]], 34492
 ; CHECK-DAG: stwx [[T1]], 1, [[T2]]
 ; CHECK-DAG: addi 3, 1, 28
 ; CHECK: bl bar
   %x = alloca [100000 x i8]                       ; <[100000 x i8]*> [#uses=1]
   %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
   %x1 = bitcast [100000 x i8]* %x to i8*          ; <i8*> [#uses=1]
   call void @bar(i8* %x1) nounwind

llvm/test/CodeGen/PowerPC/CompareEliminationSpillIssue.ll

entry:
   %sub = sub nsw i32 %add, %c
   %conv = sext i32 %sub to i64
   tail call void @call(i64 %conv)
   tail call void asm sideeffect "#Do Nothing", "~{r0},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15},~{r16},~{r17},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29},~{r30},~{r31}"()
   %cmp = icmp sle i32 %add, %c
   %conv1 = zext i1 %cmp to i32
   ret i32 %conv1
 ; CHECK-LABEL: test
-; CHECK: subf r3,
+; CHECK: sub r3,
 ; CHECK: extsw r3,
 ; CHECK: bl call
 ; CHECK: sub r3,
 ; CHECK: rldicl r3, r3, 1, 63
 ; CHECK: std r3, [[OFF:[0-9]+]](r1)
 ; CHECK: #APP
 ; CHECK: ld r3, [[OFF]](r1)
 ; CHECK: xori r3, r3, 1

llvm/test/CodeGen/PowerPC/atomics-regression.ll

; PPC64LE-NEXT:    blr
   ret i64 %ret
 }
 
 define i8 @test160(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test160:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB160_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB160_1
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i8* %ptr, i8 %val monotonic
   ret i8 %ret
 }
 
 define i8 @test161(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test161:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB161_1: #
 ; PPC64LE-NEXT:    lbarx 3, 0, 5
-; PPC64LE-NEXT:    subf 6, 4, 3
+; PPC64LE-NEXT:    sub 6, 3, 4
 ; PPC64LE-NEXT:    stbcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB161_1
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i8* %ptr, i8 %val acquire
   ret i8 %ret
 }
 
 define i8 @test162(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test162:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB162_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB162_1
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i8* %ptr, i8 %val release
   ret i8 %ret
 }
 
 define i8 @test163(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test163:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB163_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB163_1
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i8* %ptr, i8 %val acq_rel
   ret i8 %ret
 }
 
 define i8 @test164(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test164:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB164_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB164_1
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i8* %ptr, i8 %val seq_cst
   ret i8 %ret
 }
 
 define i16 @test165(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test165:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB165_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB165_1
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i16* %ptr, i16 %val monotonic
   ret i16 %ret
 }
 
 define i16 @test166(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test166:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB166_1: #
 ; PPC64LE-NEXT:    lharx 3, 0, 5
-; PPC64LE-NEXT:    subf 6, 4, 3
+; PPC64LE-NEXT:    sub 6, 3, 4
 ; PPC64LE-NEXT:    sthcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB166_1
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i16* %ptr, i16 %val acquire
   ret i16 %ret
 }
 
 define i16 @test167(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test167:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB167_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB167_1
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i16* %ptr, i16 %val release
   ret i16 %ret
 }
 
 define i16 @test168(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test168:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB168_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB168_1
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i16* %ptr, i16 %val acq_rel
   ret i16 %ret
 }
 
 define i16 @test169(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test169:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB169_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB169_1
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i16* %ptr, i16 %val seq_cst
   ret i16 %ret
 }
 
 define i32 @test170(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test170:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB170_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB170_1
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i32* %ptr, i32 %val monotonic
   ret i32 %ret
 }
 
 define i32 @test171(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test171:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB171_1: #
 ; PPC64LE-NEXT:    lwarx 3, 0, 5
-; PPC64LE-NEXT:    subf 6, 4, 3
+; PPC64LE-NEXT:    sub 6, 3, 4
 ; PPC64LE-NEXT:    stwcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB171_1
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i32* %ptr, i32 %val acquire
   ret i32 %ret
 }
 
 define i32 @test172(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test172:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB172_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB172_1
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i32* %ptr, i32 %val release
   ret i32 %ret
 }
 
 define i32 @test173(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test173:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB173_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB173_1
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i32* %ptr, i32 %val acq_rel
   ret i32 %ret
 }
 
 define i32 @test174(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test174:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB174_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB174_1
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i32* %ptr, i32 %val seq_cst
   ret i32 %ret
; PPC64LE-NEXT:    blr
   ret i64 %ret
 }
 
 define i8 @test380(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test380:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB380_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB380_1
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i8* %ptr, i8 %val syncscope("singlethread") monotonic
   ret i8 %ret
 }
 
 define i8 @test381(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test381:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB381_1: #
 ; PPC64LE-NEXT:    lbarx 3, 0, 5
-; PPC64LE-NEXT:    subf 6, 4, 3
+; PPC64LE-NEXT:    sub 6, 3, 4
 ; PPC64LE-NEXT:    stbcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB381_1
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i8* %ptr, i8 %val syncscope("singlethread") acquire
   ret i8 %ret
 }
 
 define i8 @test382(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test382:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB382_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB382_1
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i8* %ptr, i8 %val syncscope("singlethread") release
   ret i8 %ret
 }
 
 define i8 @test383(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test383:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB383_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB383_1
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i8* %ptr, i8 %val syncscope("singlethread") acq_rel
   ret i8 %ret
 }
 
 define i8 @test384(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test384:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB384_1: #
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB384_1
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i8* %ptr, i8 %val syncscope("singlethread") seq_cst
   ret i8 %ret
 }
 
 define i16 @test385(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test385:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB385_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB385_1
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i16* %ptr, i16 %val syncscope("singlethread") monotonic
   ret i16 %ret
 }
 
 define i16 @test386(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test386:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB386_1: #
 ; PPC64LE-NEXT:    lharx 3, 0, 5
-; PPC64LE-NEXT:    subf 6, 4, 3
+; PPC64LE-NEXT:    sub 6, 3, 4
 ; PPC64LE-NEXT:    sthcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB386_1
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i16* %ptr, i16 %val syncscope("singlethread") acquire
   ret i16 %ret
 }
 
 define i16 @test387(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test387:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB387_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB387_1
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i16* %ptr, i16 %val syncscope("singlethread") release
   ret i16 %ret
 }
 
 define i16 @test388(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test388:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB388_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB388_1
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i16* %ptr, i16 %val syncscope("singlethread") acq_rel
   ret i16 %ret
 }
 
 define i16 @test389(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test389:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB389_1: #
 ; PPC64LE-NEXT:    lharx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB389_1
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i16* %ptr, i16 %val syncscope("singlethread") seq_cst
   ret i16 %ret
 }
 
 define i32 @test390(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test390:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB390_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB390_1
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i32* %ptr, i32 %val syncscope("singlethread") monotonic
   ret i32 %ret
 }
 
 define i32 @test391(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test391:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB391_1: #
 ; PPC64LE-NEXT:    lwarx 3, 0, 5
-; PPC64LE-NEXT:    subf 6, 4, 3
+; PPC64LE-NEXT:    sub 6, 3, 4
 ; PPC64LE-NEXT:    stwcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB391_1
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i32* %ptr, i32 %val syncscope("singlethread") acquire
   ret i32 %ret
 }
 
 define i32 @test392(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test392:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB392_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB392_1
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i32* %ptr, i32 %val syncscope("singlethread") release
   ret i32 %ret
 }
 
 define i32 @test393(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test393:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB393_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB393_1
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i32* %ptr, i32 %val syncscope("singlethread") acq_rel
   ret i32 %ret
 }
 
 define i32 @test394(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test394:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB394_1: #
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB394_1
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i32* %ptr, i32 %val syncscope("singlethread") seq_cst
   ret i32 %ret

llvm/test/CodeGen/PowerPC/crbits.ll

 ; CHECK: crnor
 ; CHECK: crnor
 ; CHECK: crnand [[REG4:[0-9]+]],
 ; CHECK: isel 3, 0, [[REG1]], [[REG4]]
 ; CHECK-NO-ISEL-LABEL: @test1
 ; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
 ; CHECK-NO-ISEL-NEXT: blr
 ; CHECK-NO-ISEL-NEXT: [[TRUE]]
-; CHECK-NO-ISEL-NEXT: addi 3, 0, 0
+; CHECK-NO-ISEL-NEXT: li 3, 0
 ; CHECK-NO-ISEL-NEXT: blr
 ; CHECK: blr
 }
 
 ; Function Attrs: nounwind readnone
 define zeroext i1 @test2(float %v1, float %v2) #0 {
 entry:
   %cmp = fcmp oge float %v1, %v2

 ; Function Attrs: nounwind readnone
 define signext i32 @test7(i1 zeroext %v2, i32 signext %i1, i32 signext %i2) #0 {
 entry:
   %cond = select i1 %v2, i32 %i1, i32 %i2
   ret i32 %cond
 
 ; CHECK-LABEL: @test7
 ; CHECK: andi. {{[0-9]+}}, 3, 1
-; CHECK: isel 3, 4, 5, 1
+; CHECK: iselgt 3, 4, 5
 ; CHECK: blr
 }
 
 define signext i32 @exttest7(i32 signext %a) #0 {
 entry:
   %cmp = icmp eq i32 %a, 5
   %cond = select i1 %cmp, i32 7, i32 8
   ret i32 %cond

llvm/test/CodeGen/PowerPC/eqv-andc-orc-nor.ll

 ; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | \
 ; RUN:   grep eqv | count 3
 ; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=g5 | \
 ; RUN:   grep andc | count 3
 ; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | \
 ; RUN:   grep orc | count 2
 ; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=g5 | \
-; RUN:   grep nor | count 3
+; RUN:   grep nor | count 2
 ; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | \
 ; RUN:   grep nand | count 1
 
 define i32 @EQV1(i32 %X, i32 %Y) nounwind {
   %A = xor i32 %X, %Y   ; <i32> [#uses=1]
   %B = xor i32 %A, -1   ; <i32> [#uses=1]
   ret i32 %B
 }

llvm/test/CodeGen/PowerPC/fast-isel-binary.ll

 
 ; Test sub with non-legal types
 
 define void @sub_i8(i8 %a, i8 %b) nounwind {
 entry:
 ; ELF64: sub_i8
   %a.addr = alloca i8, align 4
   %0 = sub i8 %a, %b
-; ELF64: subf
+; ELF64: sub
   store i8 %0, i8* %a.addr, align 4
   ret void
 }
 
 define void @sub_i8_imm(i8 %a) nounwind {
 entry:
 ; ELF64: sub_i8_imm
   %a.addr = alloca i8, align 4
   %0 = sub i8 %a, 22;
 ; ELF64: addi
   store i8 %0, i8* %a.addr, align 4
   ret void
 }
 
 define void @sub_i16(i16 %a, i16 %b) nounwind {
 entry:
 ; ELF64: sub_i16
   %a.addr = alloca i16, align 4
   %0 = sub i16 %a, %b
-; ELF64: subf
+; ELF64: sub
   store i16 %0, i16* %a.addr, align 4
   ret void
 }
 
 define void @sub_i16_imm(i16 %a) nounwind {
 entry:
 ; ELF64: sub_i16_imm
   %a.addr = alloca i16, align 4
   %0 = sub i16 %a, 247;
 ; ELF64: addi
   store i16 %0, i16* %a.addr, align 4
   ret void
 }
 
 define void @sub_i16_badimm(i16 %a) nounwind {
 entry:
 ; ELF64: sub_i16_imm
   %a.addr = alloca i16, align 4
   %0 = sub i16 %a, -32768;
-; ELF64: subf
+; ELF64: sub
   store i16 %0, i16* %a.addr, align 4
   ret void
 }

llvm/test/CodeGen/PowerPC/fold-zero.ll

 }
 
 define i32 @test2(i1 %a, i32 %c) nounwind  {
   %x = select i1 %a, i32 0, i32 %c
   ret i32 %x
 
 ; CHECK-CRB-LABEL: @test2
 ; CHECK-CRB-NOT: li {{[0-9]+}}, 0
-; CHECK-CRB: isel 3, 0,
+; CHECK-CRB: iselgt 3, 0,
 ; CHECK-CRB: blr
 ; CHECK-NO-ISEL-LABEL: @test2
 ; CHECK-NO-ISEL: bc 12, 1, [[TRUE:.LBB[0-9]+]]
 ; CHECK-NO-ISEL: ori 3, 4, 0
 ; CHECK-NO-ISEL-NEXT: blr
 ; CHECK-NO-ISEL-NEXT: [[TRUE]]
-; CHECK-NO-ISEL-NEXT: addi 3, 0, 0
+; CHECK-NO-ISEL-NEXT: li 3, 0
 ; CHECK-NO-ISEL-NEXT: blr
 }
 

llvm/test/CodeGen/PowerPC/i1-ext-fold.ll

 ; CHECK-DAG: li [[REG1:[0-9]+]], 16
 ; CHECK: isel 3, 0, [[REG1]],
 ; CHECK: blr
 
 ; CHECK-NO-ISEL: bc 12, 1, [[TRUE:.LBB[0-9]+]]
 ; CHECK-NO-ISEL: ori 3, 5, 0
 ; CHECK-NO-ISEL-NEXT: blr
 ; CHECK-NO-ISEL-NEXT: [[TRUE]]
-; CHECK-NO-ISEL-NEXT: addi 3, 0, 0
+; CHECK-NO-ISEL-NEXT: li 3, 0
 ; CHECK-NO-ISEL-NEXT: blr
 }
 
 attributes #0 = { nounwind readnone }
 

llvm/test/CodeGen/PowerPC/ifcvt.ll

 
 cond.false:                                       ; preds = %sw.epilog
   %add37 = add nsw i32 %conv29, %a
   br label %cond.end
 
 ; CHECK-LABEL: @test
 ; CHECK-NO-ISEL-LABEL: @test
 ; CHECK: add [[REG:[0-9]+]], 
-; CHECK: subf [[REG2:[0-9]+]],
+; CHECK: sub [[REG2:[0-9]+]],
 ; CHECK: isel {{[0-9]+}}, [[REG]], [[REG2]],
 ; CHECK-NO-ISEL: bc 12, 1, [[TRUE:.LBB[0-9]+]]
 ; CHECK-NO-ISEL-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
 ; CHECK-NO-ISEL: [[TRUE]]
 ; CHECK-NO-ISEL-NEXT: addi 5, 6, 0
 ; CHECK-NO-ISEL: extsh 5, 5
 ; CHECK-NO-ISEL-NEXT: add 3, 3, 5
 ; CHECK-NO-ISEL-NEXT: blr

llvm/test/CodeGen/PowerPC/inc-of-add.ll

; PPC64LE-NEXT:    blr
   %t0 = add <4 x i32> %x, <i32 1, i32 1, i32 1, i32 1>
   %t1 = add <4 x i32> %y, %t0
   ret <4 x i32> %t1
 }
 
 define <2 x i64> @vector_i128_i64(<2 x i64> %x, <2 x i64> %y) nounwind {
 ; PPC32-LABEL: vector_i128_i64:
 ; PPC32:       # %bb.0:
-; PPC32-NEXT:    nor 4, 4, 4
-; PPC32-NEXT:    nor 3, 3, 3
+; PPC32-NEXT:    not 4, 4
+; PPC32-NEXT:    not 3, 3
 ; PPC32-NEXT:    subfc 4, 4, 8
-; PPC32-NEXT:    nor 6, 6, 6
+; PPC32-NEXT:    not 6, 6
 ; PPC32-NEXT:    subfe 3, 3, 7
-; PPC32-NEXT:    nor 5, 5, 5
+; PPC32-NEXT:    not 5, 5
 ; PPC32-NEXT:    subfc 6, 6, 10
 ; PPC32-NEXT:    subfe 5, 5, 9
 ; PPC32-NEXT:    blr
 ;
 ; PPC64BE-LABEL: vector_i128_i64:
 ; PPC64BE:       # %bb.0:
 ; PPC64BE-NEXT:    add 3, 5, 3
 ; PPC64BE-NEXT:    add 4, 6, 4

llvm/test/CodeGen/PowerPC/memcmp.ll

; CHECK-NEXT:    blr
   ret i32 %call
 }
 
 define signext i32 @memcmp2(i32* nocapture readonly %buffer1, i32* nocapture readonly %buffer2) {
 ; CHECK-LABEL: memcmp2:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lhbrx 3, 0, 3
 ; CHECK-NEXT:    lhbrx 4, 0, 4
-; CHECK-NEXT:    subf 3, 4, 3
+; CHECK-NEXT:    sub 3, 3, 4
 ; CHECK-NEXT:    extsw 3, 3
 ; CHECK-NEXT:    blr
   %t0 = bitcast i32* %buffer1 to i8*
   %t1 = bitcast i32* %buffer2 to i8*
   %call = tail call signext i32 @memcmp(i8* %t0, i8* %t1, i64 2)
   ret i32 %call
 }
 
 define signext i32 @memcmp1(i32* nocapture readonly %buffer1, i32* nocapture readonly %buffer2) {
 ; CHECK-LABEL: memcmp1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lbz 3, 0(3)
 ; CHECK-NEXT:    lbz 4, 0(4)
-; CHECK-NEXT:    subf 3, 4, 3
+; CHECK-NEXT:    sub 3, 3, 4
 ; CHECK-NEXT:    extsw 3, 3
 ; CHECK-NEXT:    blr
   %t0 = bitcast i32* %buffer1 to i8*
   %t1 = bitcast i32* %buffer2 to i8*
   %call = tail call signext i32 @memcmp(i8* %t0, i8* %t1, i64 1) #2
   ret i32 %call
 }
 
 declare signext i32 @memcmp(i8*, i8*, i64)

llvm/test/CodeGen/PowerPC/popcnt-zext.ll

 ; FAST-NEXT:    blr
 ;
 ; SLOW-LABEL: zpop_i8_i16:
 ; SLOW:       # %bb.0:
 ; SLOW-NEXT:    clrlwi 5, 3, 24
 ; SLOW-NEXT:    rlwinm 3, 3, 31, 0, 31
 ; SLOW-NEXT:    andi. 3, 3, 85
 ; SLOW-NEXT:    lis 4, 13107
-; SLOW-NEXT:    subf 3, 3, 5
+; SLOW-NEXT:    sub 3, 5, 3
 ; SLOW-NEXT:    ori 4, 4, 13107
 ; SLOW-NEXT:    rotlwi 5, 3, 30
 ; SLOW-NEXT:    and 3, 3, 4
 ; SLOW-NEXT:    andis. 4, 5, 13107
 ; SLOW-NEXT:    andi. 5, 5, 13107
 ; SLOW-NEXT:    or 4, 5, 4
 ; SLOW-NEXT:    add 3, 3, 4
 ; SLOW-NEXT:    lis 5, 3855

 ; FAST-NEXT:    blr
 ;
 ; SLOW-LABEL: popz_i8_i16:
 ; SLOW:       # %bb.0:
 ; SLOW-NEXT:    clrlwi 5, 3, 24
 ; SLOW-NEXT:    rlwinm 3, 3, 31, 0, 31
 ; SLOW-NEXT:    andi. 3, 3, 85
 ; SLOW-NEXT:    lis 4, 13107
-; SLOW-NEXT:    subf 3, 3, 5
+; SLOW-NEXT:    sub 3, 5, 3
 ; SLOW-NEXT:    ori 4, 4, 13107
 ; SLOW-NEXT:    rotlwi 5, 3, 30
 ; SLOW-NEXT:    and 3, 3, 4
 ; SLOW-NEXT:    andis. 4, 5, 13107
 ; SLOW-NEXT:    andi. 5, 5, 13107
 ; SLOW-NEXT:    or 4, 5, 4
 ; SLOW-NEXT:    add 3, 3, 4
 ; SLOW-NEXT:    lis 5, 3855

 ; FAST-NEXT:    blr
 ;
 ; SLOW-LABEL: zpop_i8_i32:
 ; SLOW:       # %bb.0:
 ; SLOW-NEXT:    clrlwi 5, 3, 24
 ; SLOW-NEXT:    rlwinm 3, 3, 31, 0, 31
 ; SLOW-NEXT:    andi. 3, 3, 85
 ; SLOW-NEXT:    lis 4, 13107
-; SLOW-NEXT:    subf 3, 3, 5
+; SLOW-NEXT:    sub 3, 5, 3
 ; SLOW-NEXT:    ori 4, 4, 13107
 ; SLOW-NEXT:    rotlwi 5, 3, 30
 ; SLOW-NEXT:    and 3, 3, 4
 ; SLOW-NEXT:    andis. 4, 5, 13107
 ; SLOW-NEXT:    andi. 5, 5, 13107
 ; SLOW-NEXT:    or 4, 5, 4
 ; SLOW-NEXT:    add 3, 3, 4
 ; SLOW-NEXT:    lis 5, 3855

 ; FAST-NEXT:    blr
 ;
 ; SLOW-LABEL: popz_i8_32:
 ; SLOW:       # %bb.0:
 ; SLOW-NEXT:    clrlwi 5, 3, 24
 ; SLOW-NEXT:    rlwinm 3, 3, 31, 0, 31
 ; SLOW-NEXT:    andi. 3, 3, 85
 ; SLOW-NEXT:    lis 4, 13107
-; SLOW-NEXT:    subf 3, 3, 5
+; SLOW-NEXT:    sub 3, 5, 3
 ; SLOW-NEXT:    ori 4, 4, 13107
 ; SLOW-NEXT:    rotlwi 5, 3, 30
 ; SLOW-NEXT:    and 3, 3, 4
 ; SLOW-NEXT:    andis. 4, 5, 13107
 ; SLOW-NEXT:    andi. 5, 5, 13107
 ; SLOW-NEXT:    or 4, 5, 4
 ; SLOW-NEXT:    add 3, 3, 4
 ; SLOW-NEXT:    lis 5, 3855

 ; FAST-NEXT:    blr
 ;
 ; SLOW-LABEL: zpop_i16_i32:
 ; SLOW:       # %bb.0:
 ; SLOW-NEXT:    clrlwi 5, 3, 16
 ; SLOW-NEXT:    rlwinm 3, 3, 31, 0, 31
 ; SLOW-NEXT:    andi. 3, 3, 21845
 ; SLOW-NEXT:    lis 4, 13107
-; SLOW-NEXT:    subf 3, 3, 5
+; SLOW-NEXT:    sub 3, 5, 3
 ; SLOW-NEXT:    ori 4, 4, 13107
 ; SLOW-NEXT:    rotlwi 5, 3, 30
 ; SLOW-NEXT:    and 3, 3, 4
 ; SLOW-NEXT:    andis. 4, 5, 13107
 ; SLOW-NEXT:    andi. 5, 5, 13107
 ; SLOW-NEXT:    or 4, 5, 4
 ; SLOW-NEXT:    add 3, 3, 4
 ; SLOW-NEXT:    lis 5, 3855

 ; FAST-NEXT:    blr
 ;
 ; SLOW-LABEL: popz_i16_32:
 ; SLOW:       # %bb.0:
 ; SLOW-NEXT:    clrlwi 5, 3, 16
 ; SLOW-NEXT:    rlwinm 3, 3, 31, 0, 31
 ; SLOW-NEXT:    andi. 3, 3, 21845
 ; SLOW-NEXT:    lis 4, 13107
-; SLOW-NEXT:    subf 3, 3, 5
+; SLOW-NEXT:    sub 3, 5, 3
 ; SLOW-NEXT:    ori 4, 4, 13107
 ; SLOW-NEXT:    rotlwi 5, 3, 30
 ; SLOW-NEXT:    and 3, 3, 4
 ; SLOW-NEXT:    andis. 4, 5, 13107
 ; SLOW-NEXT:    andi. 5, 5, 13107
 ; SLOW-NEXT:    or 4, 5, 4
 ; SLOW-NEXT:    add 3, 3, 4
 ; SLOW-NEXT:    lis 5, 3855

 ; FAST-NEXT:    blr
 ;
 ; SLOW-LABEL: popa_i16_i64:
 ; SLOW:       # %bb.0:
 ; SLOW-NEXT:    clrlwi 5, 3, 16
 ; SLOW-NEXT:    rlwinm 3, 3, 31, 0, 31
 ; SLOW-NEXT:    andi. 3, 3, 21845
 ; SLOW-NEXT:    lis 4, 13107
-; SLOW-NEXT:    subf 3, 3, 5
+; SLOW-NEXT:    sub 3, 5, 3
 ; SLOW-NEXT:    ori 4, 4, 13107
 ; SLOW-NEXT:    rotlwi 5, 3, 30
 ; SLOW-NEXT:    and 3, 3, 4
 ; SLOW-NEXT:    andis. 4, 5, 13107
 ; SLOW-NEXT:    andi. 5, 5, 13107
 ; SLOW-NEXT:    or 4, 5, 4
 ; SLOW-NEXT:    add 3, 3, 4
 ; SLOW-NEXT:    lis 5, 3855

llvm/test/CodeGen/PowerPC/ppc-crbits-onoff.ll

 ; CHECK-DAG: cmplwi {{[0-9]+}}, 3, 0
 ; CHECK-DAG: li [[REG2:[0-9]+]], 1
 ; CHECK-DAG: cntlzw [[REG3:[0-9]+]],
 ; CHECK: isel [[REG4:[0-9]+]], 0, [[REG2]]
 ; CHECK-NO-ISEL: bc 12, 2, [[TRUE:.LBB[0-9]+]]
 ; CHECK-NO-ISEL: ori 4, 5, 0
 ; CHECK-NO-ISEL-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
 ; CHECK-NO-ISEL: [[TRUE]]
-; CHECK-NO-ISEL-NEXT: addi 4, 0, 0
+; CHECK-NO-ISEL-NEXT: li 4, 0
 ; CHECK: and 3, [[REG4]], [[REG3]]
 ; CHECK: blr
 }
 
 define signext i32 @crbitson(i32 signext %v1, i32 signext %v2) #1 {
 entry:
   %tobool = icmp ne i32 %v1, 0
   %lnot = icmp eq i32 %v2, 0

llvm/test/CodeGen/PowerPC/ppc64-P9-vabsd.ll

entry:
   %ispos199 = icmp sgt i32 %sub120, -1
   %neg200 = sub nsw i32 0, %sub120
   %15 = select i1 %ispos199, i32 %sub120, i32 %neg200
   %conv122 = trunc i32 %15 to i8
   %vecins123 = insertelement <16 x i8> %vecins115, i8 %conv122, i32 15
   ret <16 x i8> %vecins123
 ; CHECK-LABEL: sub_absv_8_ext
 ; CHECK-NOT: vabsdub
-; CHECK: subf
+; CHECK: sub
 ; CHECK-NOT: vabsdub
 ; CHECK: xor
 ; CHECK-NOT: vabsdub
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: sub_absv_8_ext
-; CHECK-PWR8: subf
+; CHECK-PWR8: sub
 ; CHECK-PWR8: xor
 ; CHECK-PWR8: blr
 }
 
 define <4 x i32> @sub_absv_vec_32(<4 x i32> %a, <4 x i32> %b) local_unnamed_addr {
 entry:
   %sub = sub <4 x i32> %a, %b
   %sub.i = sub <4 x i32> zeroinitializer, %sub

llvm/test/CodeGen/PowerPC/pr44183.ll

 ; CHECK-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std r0, 16(r1)
 ; CHECK-NEXT:    stdu r1, -48(r1)
 ; CHECK-NEXT:    mr r30, r3
 ; CHECK-NEXT:    ld r4, 8(r30)
 ; CHECK-NEXT:    lwz r5, 36(r30)
 ; CHECK-NEXT:    rldicl r4, r4, 60, 4
 ; CHECK-NEXT:    rlwinm r3, r4, 31, 0, 0
-; CHECK-NEXT:    rlwinm r4, r5, 0, 31, 31
+; CHECK-NEXT:    clrlwi r4, r5, 31
 ; CHECK-NEXT:    or r4, r4, r3
 ; CHECK-NEXT:    bl _ZN1llsE1d
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    ld r3, 16(r30)
 ; CHECK-NEXT:    ld r4, 8(r30)
 ; CHECK-NEXT:    rldicl r4, r4, 60, 4
 ; CHECK-NEXT:    sldi r3, r3, 60
 ; CHECK-NEXT:    or r3, r4, r3

llvm/test/CodeGen/PowerPC/remove-redundant-load-imm.ll

 ; PPC64LE-LABEL: redundancy_on_ppc_only:
 ; PPC64LE:       # %bb.0: # %bb
 ; PPC64LE-NEXT:    mflr 0
 ; PPC64LE-NEXT:    andi. 3, 3, 1
 ; PPC64LE-NEXT:    std 0, 16(1)
 ; PPC64LE-NEXT:    stdu 1, -32(1)
 ; PPC64LE-NEXT:    li 3, 1
 ; PPC64LE-NEXT:    li 4, 0
-; PPC64LE-NEXT:    isel 3, 3, 4, 1
+; PPC64LE-NEXT:    iselgt 3, 3, 4
 ; PPC64LE-NEXT:    bl barney.88
 ; PPC64LE-NEXT:    nop
 ; PPC64LE-NEXT:    addi 1, 1, 32
 ; PPC64LE-NEXT:    ld 0, 16(1)
 ; PPC64LE-NEXT:    mtlr 0
 ; PPC64LE-NEXT:    blr
 bb:
   br label %bb10

llvm/test/CodeGen/PowerPC/sat-add.ll

; CHECK-NEXT:    blr
   %c = icmp ugt i64 %x, -43
   %r = select i1 %c, i64 -1, i64 %a
   ret i64 %r
 }
 
 define i8 @unsigned_sat_variable_i8_using_min(i8 %x, i8 %y) {
 ; CHECK-LABEL: unsigned_sat_variable_i8_using_min:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    nor 5, 4, 4
+; CHECK-NEXT:    not 5, 4
 ; CHECK-NEXT:    clrlwi 6, 3, 24
 ; CHECK-NEXT:    clrlwi 7, 5, 24
 ; CHECK-NEXT:    cmplw 6, 7
 ; CHECK-NEXT:    isel 3, 3, 5, 0
 ; CHECK-NEXT:    add 3, 3, 4
 ; CHECK-NEXT:    blr
   %noty = xor i8 %y, -1
   %c = icmp ult i8 %x, %noty
; CHECK-NEXT:    blr
   %c = icmp ugt i8 %x, %a
   %r = select i1 %c, i8 -1, i8 %a
   ret i8 %r
 }
 
 define i8 @unsigned_sat_variable_i8_using_cmp_notval(i8 %x, i8 %y) {
 ; CHECK-LABEL: unsigned_sat_variable_i8_using_cmp_notval:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    nor 6, 4, 4
+; CHECK-NEXT:    not 6, 4
 ; CHECK-NEXT:    clrlwi 7, 3, 24
 ; CHECK-NEXT:    li 5, -1
 ; CHECK-NEXT:    add 3, 3, 4
 ; CHECK-NEXT:    clrlwi 6, 6, 24
 ; CHECK-NEXT:    cmplw 7, 6
 ; CHECK-NEXT:    isel 3, 5, 3, 1
 ; CHECK-NEXT:    blr
   %noty = xor i8 %y, -1
   %a = add i8 %x, %y
   %c = icmp ugt i8 %x, %noty
   %r = select i1 %c, i8 -1, i8 %a
   ret i8 %r
 }
 
 define i16 @unsigned_sat_variable_i16_using_min(i16 %x, i16 %y) {
 ; CHECK-LABEL: unsigned_sat_variable_i16_using_min:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    nor 5, 4, 4
+; CHECK-NEXT:    not 5, 4
 ; CHECK-NEXT:    clrlwi 6, 3, 16
 ; CHECK-NEXT:    clrlwi 7, 5, 16
 ; CHECK-NEXT:    cmplw 6, 7
 ; CHECK-NEXT:    isel 3, 3, 5, 0
 ; CHECK-NEXT:    add 3, 3, 4
 ; CHECK-NEXT:    blr
   %noty = xor i16 %y, -1
   %c = icmp ult i16 %x, %noty
; CHECK-NEXT:    blr
   %c = icmp ugt i16 %x, %a
   %r = select i1 %c, i16 -1, i16 %a
   ret i16 %r
 }
 
 define i16 @unsigned_sat_variable_i16_using_cmp_notval(i16 %x, i16 %y) {
 ; CHECK-LABEL: unsigned_sat_variable_i16_using_cmp_notval:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    nor 6, 4, 4
+; CHECK-NEXT:    not 6, 4
 ; CHECK-NEXT:    clrlwi 7, 3, 16
 ; CHECK-NEXT:    li 5, -1
 ; CHECK-NEXT:    add 3, 3, 4
 ; CHECK-NEXT:    clrlwi 6, 6, 16
 ; CHECK-NEXT:    cmplw 7, 6
 ; CHECK-NEXT:    isel 3, 5, 3, 1
 ; CHECK-NEXT:    blr
   %noty = xor i16 %y, -1
   %a = add i16 %x, %y
   %c = icmp ugt i16 %x, %noty
   %r = select i1 %c, i16 -1, i16 %a
   ret i16 %r
 }
 
 define i32 @unsigned_sat_variable_i32_using_min(i32 %x, i32 %y) {
 ; CHECK-LABEL: unsigned_sat_variable_i32_using_min:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    nor 5, 4, 4
+; CHECK-NEXT:    not 5, 4
 ; CHECK-NEXT:    cmplw 3, 5
 ; CHECK-NEXT:    isel 3, 3, 5, 0
 ; CHECK-NEXT:    add 3, 3, 4
 ; CHECK-NEXT:    blr
   %noty = xor i32 %y, -1
   %c = icmp ult i32 %x, %noty
   %s = select i1 %c, i32 %x, i32 %noty
   %r = add i32 %s, %y
; CHECK-NEXT:    blr
   %c = icmp ugt i32 %x, %a
   %r = select i1 %c, i32 -1, i32 %a
   ret i32 %r
 }
 
 define i32 @unsigned_sat_variable_i32_using_cmp_notval(i32 %x, i32 %y) {
 ; CHECK-LABEL: unsigned_sat_variable_i32_using_cmp_notval:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    nor 6, 4, 4
+; CHECK-NEXT:    not 6, 4
 ; CHECK-NEXT:    li 5, -1
 ; CHECK-NEXT:    cmplw 3, 6
 ; CHECK-NEXT:    add 3, 3, 4
 ; CHECK-NEXT:    isel 3, 5, 3, 1
 ; CHECK-NEXT:    blr
   %noty = xor i32 %y, -1
   %a = add i32 %x, %y
   %c = icmp ugt i32 %x, %noty

llvm/test/CodeGen/PowerPC/select_const.ll

 ; select Cond, C1, C2 --> add (mul (zext Cond), C1-C2), C2 --> add (and (sext Cond), C1-C2), C2
 
 define i32 @select_C1_C2(i1 %cond) {
 ; ISEL-LABEL: select_C1_C2:
 ; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, 421
 ; ISEL-NEXT:    li 3, 42
-; ISEL-NEXT:    isel 3, 4, 3, 1
+; ISEL-NEXT:    iselgt 3, 4, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: select_C1_C2:
 ; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    li 4, 421
 ; NO_ISEL-NEXT:    li 3, 42
 ; NO_ISEL-NEXT:    bc 12, 1, .LBB18_1
 ; NO_ISEL-NEXT:    blr
 ; NO_ISEL-NEXT:  .LBB18_1:
 ; NO_ISEL-NEXT:    addi 3, 4, 0
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i32 421, i32 42
   ret i32 %sel
 }
 
 define i32 @select_C1_C2_zeroext(i1 zeroext %cond) {
 ; ISEL-LABEL: select_C1_C2_zeroext:
 ; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, 421
 ; ISEL-NEXT:    li 3, 42
-; ISEL-NEXT:    isel 3, 4, 3, 1
+; ISEL-NEXT:    iselgt 3, 4, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: select_C1_C2_zeroext:
 ; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    li 4, 421
 ; NO_ISEL-NEXT:    li 3, 42
 ; NO_ISEL-NEXT:    bc 12, 1, .LBB19_1
 ; NO_ISEL-NEXT:    blr
 ; NO_ISEL-NEXT:  .LBB19_1:
 ; NO_ISEL-NEXT:    addi 3, 4, 0
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i32 421, i32 42
   ret i32 %sel
 }
 
 define i32 @select_C1_C2_signext(i1 signext %cond) {
 ; ISEL-LABEL: select_C1_C2_signext:
 ; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, 421
 ; ISEL-NEXT:    li 3, 42
-; ISEL-NEXT:    isel 3, 4, 3, 1
+; ISEL-NEXT:    iselgt 3, 4, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: select_C1_C2_signext:
 ; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    li 4, 421
 ; NO_ISEL-NEXT:    li 3, 42
 ; NO_ISEL-NEXT:    bc 12, 1, .LBB20_1
 ; NO_ISEL-NEXT:    blr
 ; NO_ISEL-NEXT:  .LBB20_1:
 ; NO_ISEL-NEXT:    addi 3, 4, 0
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i32 421, i32 42
   ret i32 %sel
 }
 
 ; A binary operator with constant after the select should always get folded into the select.
 
 define i8 @sel_constants_add_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_add_constant:
 ; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, 1
 ; ISEL-NEXT:    li 3, 28
-; ISEL-NEXT:    isel 3, 4, 3, 1
+; ISEL-NEXT:    iselgt 3, 4, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_add_constant:
 ; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    li 4, 1
 ; NO_ISEL-NEXT:    li 3, 28
 ; NO_ISEL-NEXT:    bc 12, 1, .LBB21_1
 ; NO_ISEL-NEXT:    blr
 ; NO_ISEL-NEXT:  .LBB21_1:
 ; NO_ISEL-NEXT:    addi 3, 4, 0
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = add i8 %sel, 5
   ret i8 %bo
 }
 
 define i8 @sel_constants_sub_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_sub_constant:
 ; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, -9
 ; ISEL-NEXT:    li 3, 18
-; ISEL-NEXT:    isel 3, 4, 3, 1
+; ISEL-NEXT:    iselgt 3, 4, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_sub_constant:
 ; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    li 4, -9
 ; NO_ISEL-NEXT:    li 3, 18
 ; NO_ISEL-NEXT:    bc 12, 1, .LBB22_1
 ; NO_ISEL-NEXT:    blr
 ; NO_ISEL-NEXT:  .LBB22_1:
 ; NO_ISEL-NEXT:    addi 3, 4, 0
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = sub i8 %sel, 5
   ret i8 %bo
 }
 
 define i8 @sel_constants_sub_constant_sel_constants(i1 %cond) {
 ; ISEL-LABEL: sel_constants_sub_constant_sel_constants:
 ; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, 9
 ; ISEL-NEXT:    li 3, 2
-; ISEL-NEXT:    isel 3, 4, 3, 1
+; ISEL-NEXT:    iselgt 3, 4, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_sub_constant_sel_constants:
 ; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    li 4, 9
 ; NO_ISEL-NEXT:    li 3, 2
 ; NO_ISEL-NEXT:    bc 12, 1, .LBB23_1
 ; NO_ISEL-NEXT:    blr
 ; NO_ISEL-NEXT:  .LBB23_1:
 ; NO_ISEL-NEXT:    addi 3, 4, 0
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i8 -4, i8 3
   %bo = sub i8 5, %sel
   ret i8 %bo
 }
 
 define i8 @sel_constants_mul_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_mul_constant:
 ; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, -20
 ; ISEL-NEXT:    li 3, 115
-; ISEL-NEXT:    isel 3, 4, 3, 1
+; ISEL-NEXT:    iselgt 3, 4, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_mul_constant:
 ; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    li 4, -20
 ; NO_ISEL-NEXT:    li 3, 115
 ; NO_ISEL-NEXT:    bc 12, 1, .LBB24_1
 ; NO_ISEL-NEXT:    blr
 ; NO_ISEL-NEXT:  .LBB24_1:
 ; NO_ISEL-NEXT:    addi 3, 4, 0
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = mul i8 %sel, 5
   ret i8 %bo
 }
 
 define i8 @sel_constants_sdiv_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_sdiv_constant:
 ; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 3, 4
-; ISEL-NEXT:    isel 3, 0, 3, 1
+; ISEL-NEXT:    iselgt 3, 0, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_sdiv_constant:
 ; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    li 3, 4
 ; NO_ISEL-NEXT:    bc 12, 1, .LBB25_1
 ; NO_ISEL-NEXT:    blr
 ; NO_ISEL-NEXT:  .LBB25_1:
-; NO_ISEL-NEXT:    addi 3, 0, 0
+; NO_ISEL-NEXT:    li 3, 0
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = sdiv i8 %sel, 5
   ret i8 %bo
 }
 
 define i8 @sdiv_constant_sel_constants(i1 %cond) {
 ; ISEL-LABEL: sdiv_constant_sel_constants:
 ; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 3, 5
-; ISEL-NEXT:    isel 3, 0, 3, 1
+; ISEL-NEXT:    iselgt 3, 0, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sdiv_constant_sel_constants:
 ; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    li 3, 5
 ; NO_ISEL-NEXT:    bc 12, 1, .LBB26_1
 ; NO_ISEL-NEXT:    blr
 ; NO_ISEL-NEXT:  .LBB26_1:
-; NO_ISEL-NEXT:    addi 3, 0, 0
+; NO_ISEL-NEXT:    li 3, 0
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i8 121, i8 23
   %bo = sdiv i8 120, %sel
   ret i8 %bo
 }
 
 define i8 @sel_constants_udiv_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_udiv_constant:
 ; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, 50
 ; ISEL-NEXT:    li 3, 4
-; ISEL-NEXT:    isel 3, 4, 3, 1
+; ISEL-NEXT:    iselgt 3, 4, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_udiv_constant:
 ; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    li 4, 50
 ; NO_ISEL-NEXT:    li 3, 4
 ; NO_ISEL-NEXT:    bc 12, 1, .LBB27_1
 ; NO_ISEL-NEXT:    blr
 ; NO_ISEL-NEXT:  .LBB27_1:
 ; NO_ISEL-NEXT:    addi 3, 4, 0
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = udiv i8 %sel, 5
   ret i8 %bo
 }
 
 define i8 @udiv_constant_sel_constants(i1 %cond) {
 ; ISEL-LABEL: udiv_constant_sel_constants:
 ; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 3, 5
-; ISEL-NEXT:    isel 3, 0, 3, 1
+; ISEL-NEXT:    iselgt 3, 0, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: udiv_constant_sel_constants:
 ; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    li 3, 5
 ; NO_ISEL-NEXT:    bc 12, 1, .LBB28_1
 ; NO_ISEL-NEXT:    blr
 ; NO_ISEL-NEXT:  .LBB28_1:
-; NO_ISEL-NEXT:    addi 3, 0, 0
+; NO_ISEL-NEXT:    li 3, 0
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = udiv i8 120, %sel
   ret i8 %bo
 }
 
 define i8 @sel_constants_srem_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_srem_constant:
 ; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, -4
 ; ISEL-NEXT:    li 3, 3
-; ISEL-NEXT:    isel 3, 4, 3, 1
+; ISEL-NEXT:    iselgt 3, 4, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_srem_constant:
 ; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    li 4, -4
 ; NO_ISEL-NEXT:    li 3, 3
 ; NO_ISEL-NEXT:    bc 12, 1, .LBB29_1
 ; NO_ISEL-NEXT:    blr
 ; NO_ISEL-NEXT:  .LBB29_1:
 ; NO_ISEL-NEXT:    addi 3, 4, 0
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = srem i8 %sel, 5
   ret i8 %bo
 }
 
 define i8 @srem_constant_sel_constants(i1 %cond) {
 ; ISEL-LABEL: srem_constant_sel_constants:
 ; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, 120
 ; ISEL-NEXT:    li 3, 5
-; ISEL-NEXT:    isel 3, 4, 3, 1
+; ISEL-NEXT:    iselgt 3, 4, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: srem_constant_sel_constants:
 ; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    li 4, 120
 ; NO_ISEL-NEXT:    li 3, 5
 ; NO_ISEL-NEXT:    bc 12, 1, .LBB30_1

 }
 
 define i8 @urem_constant_sel_constants(i1 %cond) {
 ; ISEL-LABEL: urem_constant_sel_constants:
 ; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, 120
 ; ISEL-NEXT:    li 3, 5
-; ISEL-NEXT:    isel 3, 4, 3, 1
+; ISEL-NEXT:    iselgt 3, 4, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: urem_constant_sel_constants:
 ; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    li 4, 120
 ; NO_ISEL-NEXT:    li 3, 5
 ; NO_ISEL-NEXT:    bc 12, 1, .LBB32_1

 }
 
 define i8 @sel_constants_or_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_or_constant:
 ; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, -3
 ; ISEL-NEXT:    li 3, 23
-; ISEL-NEXT:    isel 3, 4, 3, 1
+; ISEL-NEXT:    iselgt 3, 4, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_or_constant:
 ; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    li 4, -3
 ; NO_ISEL-NEXT:    li 3, 23
 ; NO_ISEL-NEXT:    bc 12, 1, .LBB34_1
 ; NO_ISEL-NEXT:    blr
 ; NO_ISEL-NEXT:  .LBB34_1:
 ; NO_ISEL-NEXT:    addi 3, 4, 0
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = or i8 %sel, 5
   ret i8 %bo
 }
 
 define i8 @sel_constants_xor_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_xor_constant:
 ; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, -7
 ; ISEL-NEXT:    li 3, 18
-; ISEL-NEXT:    isel 3, 4, 3, 1
+; ISEL-NEXT:    iselgt 3, 4, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_xor_constant:
 ; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    li 4, -7
 ; NO_ISEL-NEXT:    li 3, 18
 ; NO_ISEL-NEXT:    bc 12, 1, .LBB35_1
 ; NO_ISEL-NEXT:    blr
 ; NO_ISEL-NEXT:  .LBB35_1:
 ; NO_ISEL-NEXT:    addi 3, 4, 0
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = xor i8 %sel, 5
   ret i8 %bo
 }
 
 define i8 @sel_constants_shl_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_shl_constant:
 ; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, -128
 ; ISEL-NEXT:    li 3, -32
-; ISEL-NEXT:    isel 3, 4, 3, 1
+; ISEL-NEXT:    iselgt 3, 4, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_shl_constant:
 ; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    li 4, -128
 ; NO_ISEL-NEXT:    li 3, -32
 ; NO_ISEL-NEXT:    bc 12, 1, .LBB36_1

 }
 
 define i8 @sel_constants_lshr_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_lshr_constant:
 ; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, 7
 ; ISEL-NEXT:    li 3, 0
-; ISEL-NEXT:    isel 3, 4, 3, 1
+; ISEL-NEXT:    iselgt 3, 4, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_lshr_constant:
 ; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    li 4, 7
 ; NO_ISEL-NEXT:    li 3, 0
 ; NO_ISEL-NEXT:    bc 12, 1, .LBB38_1

 define double @sel_constants_fadd_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_fadd_constant:
 ; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    addis 4, 2, .LCPI42_0@toc@ha
 ; ISEL-NEXT:    addis 3, 2, .LCPI42_1@toc@ha
 ; ISEL-NEXT:    addi 4, 4, .LCPI42_0@toc@l
 ; ISEL-NEXT:    addi 3, 3, .LCPI42_1@toc@l
-; ISEL-NEXT:    isel 3, 3, 4, 1
+; ISEL-NEXT:    iselgt 3, 3, 4
 ; ISEL-NEXT:    lfdx 1, 0, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_fadd_constant:
 ; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    addis 4, 2, .LCPI42_0@toc@ha
 ; NO_ISEL-NEXT:    addis 3, 2, .LCPI42_1@toc@ha

 define double @sel_constants_fsub_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_fsub_constant:
 ; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    addis 4, 2, .LCPI43_0@toc@ha
 ; ISEL-NEXT:    addis 3, 2, .LCPI43_1@toc@ha
 ; ISEL-NEXT:    addi 4, 4, .LCPI43_0@toc@l
 ; ISEL-NEXT:    addi 3, 3, .LCPI43_1@toc@l
-; ISEL-NEXT:    isel 3, 3, 4, 1
+; ISEL-NEXT:    iselgt 3, 3, 4
 ; ISEL-NEXT:    lfdx 1, 0, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_fsub_constant:
 ; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    addis 4, 2, .LCPI43_0@toc@ha
 ; NO_ISEL-NEXT:    addis 3, 2, .LCPI43_1@toc@ha

 define double @fsub_constant_sel_constants(i1 %cond) {
 ; ISEL-LABEL: fsub_constant_sel_constants:
 ; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    addis 4, 2, .LCPI44_0@toc@ha
 ; ISEL-NEXT:    addis 3, 2, .LCPI44_1@toc@ha
 ; ISEL-NEXT:    addi 4, 4, .LCPI44_0@toc@l
 ; ISEL-NEXT:    addi 3, 3, .LCPI44_1@toc@l
-; ISEL-NEXT:    isel 3, 3, 4, 1
+; ISEL-NEXT:    iselgt 3, 3, 4
 ; ISEL-NEXT:    lfdx 1, 0, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: fsub_constant_sel_constants:
 ; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    addis 4, 2, .LCPI44_0@toc@ha
 ; NO_ISEL-NEXT:    addis 3, 2, .LCPI44_1@toc@ha

 define double @sel_constants_fmul_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_fmul_constant:
 ; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    addis 4, 2, .LCPI45_0@toc@ha
 ; ISEL-NEXT:    addis 3, 2, .LCPI45_1@toc@ha
 ; ISEL-NEXT:    addi 4, 4, .LCPI45_0@toc@l
 ; ISEL-NEXT:    addi 3, 3, .LCPI45_1@toc@l
-; ISEL-NEXT:    isel 3, 3, 4, 1
+; ISEL-NEXT:    iselgt 3, 3, 4
 ; ISEL-NEXT:    lfdx 1, 0, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_fmul_constant:
 ; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    addis 4, 2, .LCPI45_0@toc@ha
 ; NO_ISEL-NEXT:    addis 3, 2, .LCPI45_1@toc@ha

 define double @sel_constants_fdiv_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_fdiv_constant:
 ; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    addis 4, 2, .LCPI46_0@toc@ha
 ; ISEL-NEXT:    addis 3, 2, .LCPI46_1@toc@ha
 ; ISEL-NEXT:    addi 4, 4, .LCPI46_0@toc@l
 ; ISEL-NEXT:    addi 3, 3, .LCPI46_1@toc@l
-; ISEL-NEXT:    isel 3, 3, 4, 1
+; ISEL-NEXT:    iselgt 3, 3, 4
 ; ISEL-NEXT:    lfdx 1, 0, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_fdiv_constant:
 ; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    addis 4, 2, .LCPI46_0@toc@ha
 ; NO_ISEL-NEXT:    addis 3, 2, .LCPI46_1@toc@ha

 define double @fdiv_constant_sel_constants(i1 %cond) {
 ; ISEL-LABEL: fdiv_constant_sel_constants:
 ; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    addis 4, 2, .LCPI47_0@toc@ha
 ; ISEL-NEXT:    addis 3, 2, .LCPI47_1@toc@ha
 ; ISEL-NEXT:    addi 4, 4, .LCPI47_0@toc@l
 ; ISEL-NEXT:    addi 3, 3, .LCPI47_1@toc@l
-; ISEL-NEXT:    isel 3, 3, 4, 1
+; ISEL-NEXT:    iselgt 3, 3, 4
 ; ISEL-NEXT:    lfdx 1, 0, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: fdiv_constant_sel_constants:
 ; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    addis 4, 2, .LCPI47_0@toc@ha
 ; NO_ISEL-NEXT:    addis 3, 2, .LCPI47_1@toc@ha

 define double @frem_constant_sel_constants(i1 %cond) {
 ; ISEL-LABEL: frem_constant_sel_constants:
 ; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    addis 4, 2, .LCPI49_0@toc@ha
 ; ISEL-NEXT:    addis 3, 2, .LCPI49_1@toc@ha
 ; ISEL-NEXT:    addi 4, 4, .LCPI49_0@toc@l
 ; ISEL-NEXT:    addi 3, 3, .LCPI49_1@toc@l
-; ISEL-NEXT:    isel 3, 3, 4, 1
+; ISEL-NEXT:    iselgt 3, 3, 4
 ; ISEL-NEXT:    lfdx 1, 0, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: frem_constant_sel_constants:
 ; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    addis 4, 2, .LCPI49_0@toc@ha
 ; NO_ISEL-NEXT:    addis 3, 2, .LCPI49_1@toc@ha

llvm/test/CodeGen/PowerPC/setcc-logic.ll

 }
 
 define i1 @and_icmps_const_1bit_diff(i32 %x) {
 ; CHECK-LABEL: and_icmps_const_1bit_diff:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi 3, 3, -4625
 ; CHECK-NEXT:    rlwinm 3, 3, 0, 28, 26
 ; CHECK-NEXT:    cntlzw 3, 3
-; CHECK-NEXT:    nor 3, 3, 3
+; CHECK-NEXT:    not 3, 3
 ; CHECK-NEXT:    rlwinm 3, 3, 27, 31, 31
 ; CHECK-NEXT:    blr
   %a = icmp ne i32 %x, 4625
   %b = icmp ne i32 %x, 4641
   %r = and i1 %a, %b
   ret i1 %r
 }
 

llvm/test/CodeGen/PowerPC/sms-phi-2.ll

 ; CHECK-NEXT:    stbu 3, -1(7)
 ; CHECK-NEXT:    mr 3, 8
 ; CHECK-NEXT:    bdz .LBB0_3
 ; CHECK-NEXT:    .p2align 4
 ; CHECK-NEXT:  .LBB0_2: #
 ; CHECK-NEXT:    mr 3, 9
 ; CHECK-NEXT:    mullw 9, 9, 4
 ; CHECK-NEXT:    divw 10, 3, 4
-; CHECK-NEXT:    subf 8, 9, 8
+; CHECK-NEXT:    sub 8, 8, 9
 ; CHECK-NEXT:    cmplwi 8, 10
 ; CHECK-NEXT:    isel 9, 6, 5, 0
 ; CHECK-NEXT:    add 8, 9, 8
 ; CHECK-NEXT:    mr 9, 10
 ; CHECK-NEXT:    stbu 8, -1(7)
 ; CHECK-NEXT:    mr 8, 3
 ; CHECK-NEXT:    bdnz .LBB0_2
 ; CHECK-NEXT:  .LBB0_3:

llvm/test/CodeGen/PowerPC/spe.ll

 ; CHECK-NEXT:    efscmpeq 1, 4, 4
 ; CHECK-NEXT:    li 5, 1
 ; CHECK-NEXT:    crand 20, 5, 1
 ; CHECK-NEXT:    bc 12, 20, .LBB13_2
 ; CHECK-NEXT:  # %bb.1: # %entry
 ; CHECK-NEXT:    ori 3, 5, 0
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB13_2: # %entry
-; CHECK-NEXT:    addi 3, 0, 0
+; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    blr
   entry:
   %r = fcmp uno float %a, %b
   ret i1 %r
 }
 
 define i1 @test_fcmpord(float %a, float %b) {
 ; CHECK-LABEL: test_fcmpord:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    efscmpeq 0, 4, 4
 ; CHECK-NEXT:    efscmpeq 1, 3, 3
 ; CHECK-NEXT:    li 5, 1
 ; CHECK-NEXT:    crnand 20, 5, 1
 ; CHECK-NEXT:    bc 12, 20, .LBB14_2
 ; CHECK-NEXT:  # %bb.1: # %entry
 ; CHECK-NEXT:    ori 3, 5, 0
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB14_2: # %entry
-; CHECK-NEXT:    addi 3, 0, 0
+; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    blr
   entry:
   %r = fcmp ord float %a, %b
   ret i1 %r
 }
 
 define i1 @test_fcmpueq(float %a, float %b) {
 ; CHECK-LABEL: test_fcmpueq:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    efscmpeq 0, 3, 3
 ; CHECK-NEXT:    efscmpeq 1, 4, 4
 ; CHECK-NEXT:    crnand 20, 5, 1
 ; CHECK-NEXT:    efscmpeq 0, 3, 4
 ; CHECK-NEXT:    li 5, 1
 ; CHECK-NEXT:    crnor 20, 1, 20
 ; CHECK-NEXT:    bc 12, 20, .LBB15_2
 ; CHECK-NEXT:  # %bb.1: # %entry
 ; CHECK-NEXT:    ori 3, 5, 0
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB15_2: # %entry
-; CHECK-NEXT:    addi 3, 0, 0
+; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    blr
   entry:
   %r = fcmp ueq float %a, %b
   ret i1 %r
 }
 
 define i1 @test_fcmpne(float %a, float %b) {
 ; CHECK-LABEL: test_fcmpne:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    efscmpeq 0, 4, 4
 ; CHECK-NEXT:    efscmpeq 1, 3, 3
 ; CHECK-NEXT:    crand 20, 5, 1
 ; CHECK-NEXT:    efscmpeq 0, 3, 4
 ; CHECK-NEXT:    li 5, 1
 ; CHECK-NEXT:    crorc 20, 1, 20
 ; CHECK-NEXT:    bc 12, 20, .LBB16_2
 ; CHECK-NEXT:  # %bb.1: # %entry
 ; CHECK-NEXT:    ori 3, 5, 0
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB16_2: # %entry
-; CHECK-NEXT:    addi 3, 0, 0
+; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    blr
   entry:
   %r = fcmp one float %a, %b
   ret i1 %r
 }
 
 define i32 @test_fcmpune(float %a, float %b) {
 ; CHECK-LABEL: test_fcmpune:

 ; CHECK-NEXT:    efscmplt 0, 3, 4
 ; CHECK-NEXT:    li 5, 1
 ; CHECK-NEXT:    crnor 20, 1, 20
 ; CHECK-NEXT:    bc 12, 20, .LBB19_2
 ; CHECK-NEXT:  # %bb.1: # %entry
 ; CHECK-NEXT:    ori 3, 5, 0
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB19_2: # %entry
-; CHECK-NEXT:    addi 3, 0, 0
+; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    blr
   entry:
   %r = fcmp ult float %a, %b
   ret i1 %r
 }
 
 define i32 @test_fcmpge(float %a, float %b) {
 ; CHECK-LABEL: test_fcmpge:

 ; CHECK-NEXT:    efdcmpeq 0, 3, 3
 ; CHECK-NEXT:    efdcmpeq 1, 5, 5
 ; CHECK-NEXT:    crand 20, 5, 1
 ; CHECK-NEXT:    bc 12, 20, .LBB35_2
 ; CHECK-NEXT:  # %bb.1: # %entry
 ; CHECK-NEXT:    ori 3, 7, 0
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB35_2: # %entry
-; CHECK-NEXT:    addi 3, 0, 0
+; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    blr
   entry:
   %r = fcmp uno double %a, %b
   ret i1 %r
 }
 
 define i1 @test_dcmpord(double %a, double %b) {
 ; CHECK-LABEL: test_dcmpord:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    evmergelo 3, 3, 4
 ; CHECK-NEXT:    evmergelo 4, 5, 6
 ; CHECK-NEXT:    li 7, 1
 ; CHECK-NEXT:    efdcmpeq 0, 4, 4
 ; CHECK-NEXT:    efdcmpeq 1, 3, 3
 ; CHECK-NEXT:    crnand 20, 5, 1
 ; CHECK-NEXT:    bc 12, 20, .LBB36_2
 ; CHECK-NEXT:  # %bb.1: # %entry
 ; CHECK-NEXT:    ori 3, 7, 0
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB36_2: # %entry
-; CHECK-NEXT:    addi 3, 0, 0
+; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    blr
   entry:
   %r = fcmp ord double %a, %b
   ret i1 %r
 }
 
 define i32 @test_dcmpgt(double %a, double %b) {
 ; CHECK-LABEL: test_dcmpgt:

 ; CHECK-NEXT:    efdcmpeq 5, 3, 4
 ; CHECK-NEXT:    crand 24, 5, 1
 ; CHECK-NEXT:    crorc 20, 21, 24
 ; CHECK-NEXT:    bc 12, 20, .LBB43_2
 ; CHECK-NEXT:  # %bb.1: # %entry
 ; CHECK-NEXT:    ori 3, 7, 0
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB43_2: # %entry
-; CHECK-NEXT:    addi 3, 0, 0
+; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    blr
   entry:
   %r = fcmp one double %a, %b
   ret i1 %r
 }
 
 define i32 @test_dcmpune(double %a, double %b) {
 ; CHECK-LABEL: test_dcmpune:

 ; CHECK-NEXT:    efdcmplt 5, 3, 4
 ; CHECK-NEXT:    crand 24, 5, 1
 ; CHECK-NEXT:    crorc 20, 21, 24
 ; CHECK-NEXT:    bc 12, 20, .LBB47_2
 ; CHECK-NEXT:  # %bb.1: # %entry
 ; CHECK-NEXT:    ori 3, 7, 0
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB47_2: # %entry
-; CHECK-NEXT:    addi 3, 0, 0
+; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    blr
   entry:
   %r = fcmp oge double %a, %b
   ret i1 %r
 }
 
 define i32 @test_dcmpuge(double %a, double %b) {
 ; CHECK-LABEL: test_dcmpuge:

llvm/test/CodeGen/PowerPC/srem-lkk.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu -mcpu=ppc64 < %s | FileCheck -check-prefixes=CHECK,CHECK64 %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu -mcpu=ppc < %s | FileCheck -check-prefixes=CHECK,CHECK32 %s
 
 define i32 @fold_srem_positive_odd(i32 %x) {
 ; CHECK-LABEL: fold_srem_positive_odd:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lis 4, -21386
 ; CHECK-NEXT:    ori 4, 4, 37253
 ; CHECK-NEXT:    mulhw 4, 3, 4
 ; CHECK-NEXT:    add 4, 4, 3
 ; CHECK-NEXT:    srwi 5, 4, 31
 ; CHECK-NEXT:    srawi 4, 4, 6
 ; CHECK-NEXT:    add 4, 4, 5
 ; CHECK-NEXT:    mulli 4, 4, 95
-; CHECK-NEXT:    subf 3, 4, 3
+; CHECK-NEXT:    sub 3, 3, 4
 ; CHECK-NEXT:    blr
   %1 = srem i32 %x, 95
   ret i32 %1
 }
 
 
 define i32 @fold_srem_positive_even(i32 %x) {
 ; CHECK-LABEL: fold_srem_positive_even:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lis 4, 15827
 ; CHECK-NEXT:    ori 4, 4, 36849
 ; CHECK-NEXT:    mulhw 4, 3, 4
 ; CHECK-NEXT:    srwi 5, 4, 31
 ; CHECK-NEXT:    srawi 4, 4, 8
 ; CHECK-NEXT:    add 4, 4, 5
 ; CHECK-NEXT:    mulli 4, 4, 1060
-; CHECK-NEXT:    subf 3, 4, 3
+; CHECK-NEXT:    sub 3, 3, 4
 ; CHECK-NEXT:    blr
   %1 = srem i32 %x, 1060
   ret i32 %1
 }
 
 
 define i32 @fold_srem_negative_odd(i32 %x) {
 ; CHECK-LABEL: fold_srem_negative_odd:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lis 4, -23206
 ; CHECK-NEXT:    ori 4, 4, 65445
 ; CHECK-NEXT:    mulhw 4, 3, 4
 ; CHECK-NEXT:    srwi 5, 4, 31
 ; CHECK-NEXT:    srawi 4, 4, 8
 ; CHECK-NEXT:    add 4, 4, 5
 ; CHECK-NEXT:    mulli 4, 4, -723
-; CHECK-NEXT:    subf 3, 4, 3
+; CHECK-NEXT:    sub 3, 3, 4
 ; CHECK-NEXT:    blr
   %1 = srem i32 %x, -723
   ret i32 %1
 }
 
 
 define i32 @fold_srem_negative_even(i32 %x) {
 ; CHECK-LABEL: fold_srem_negative_even:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lis 4, -731
 ; CHECK-NEXT:    ori 4, 4, 62439
 ; CHECK-NEXT:    mulhw 4, 3, 4
 ; CHECK-NEXT:    srwi 5, 4, 31
 ; CHECK-NEXT:    srawi 4, 4, 8
 ; CHECK-NEXT:    add 4, 4, 5
 ; CHECK-NEXT:    mulli 4, 4, -22981
-; CHECK-NEXT:    subf 3, 4, 3
+; CHECK-NEXT:    sub 3, 3, 4
 ; CHECK-NEXT:    blr
   %1 = srem i32 %x, -22981
   ret i32 %1
 }
 
 
 ; Don't fold if we can combine srem with sdiv.
 define i32 @combine_srem_sdiv(i32 %x) {
 ; CHECK-LABEL: combine_srem_sdiv:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lis 4, -21386
 ; CHECK-NEXT:    ori 4, 4, 37253
 ; CHECK-NEXT:    mulhw 4, 3, 4
 ; CHECK-NEXT:    add 4, 4, 3
 ; CHECK-NEXT:    srwi 5, 4, 31
 ; CHECK-NEXT:    srawi 4, 4, 6
 ; CHECK-NEXT:    add 4, 4, 5
 ; CHECK-NEXT:    mulli 5, 4, 95
-; CHECK-NEXT:    subf 3, 5, 3
+; CHECK-NEXT:    sub 3, 3, 5
 ; CHECK-NEXT:    add 3, 3, 4
 ; CHECK-NEXT:    blr
   %1 = srem i32 %x, 95
   %2 = sdiv i32 %x, 95
   %3 = add i32 %1, %2
   ret i32 %3
 }
 
 ; Don't fold for divisors that are a power of two.
 define i32 @dont_fold_srem_power_of_two(i32 %x) {
 ; CHECK-LABEL: dont_fold_srem_power_of_two:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    srawi 4, 3, 6
 ; CHECK-NEXT:    addze 4, 4
 ; CHECK-NEXT:    slwi 4, 4, 6
-; CHECK-NEXT:    subf 3, 4, 3
+; CHECK-NEXT:    sub 3, 3, 4
 ; CHECK-NEXT:    blr
   %1 = srem i32 %x, 64
   ret i32 %1
 }
 
 ; Don't fold if the divisor is one.
 define i32 @dont_fold_srem_one(i32 %x) {
 ; CHECK-LABEL: dont_fold_srem_one:

llvm/test/CodeGen/PowerPC/stack-guard-reassign.ll

 ; RUN: llc -O0 --frame-pointer=none -mtriple=powerpc-- -o - %S/../Inputs/stack-guard-reassign.ll | FileCheck %s
 
 ; Verify that the offset assigned to the stack protector is at the top of the
 ; frame, covering the locals.
 ; CHECK-LABEL: fn:
 ; CHECK:      mflr 0
 ; CHECK-NEXT: stw 0, 4(1)
 ; CHECK-NEXT: lis 0, -2
 ; CHECK-NEXT: ori 0, 0, 65488
 ; CHECK-NEXT: stwux 1, 1, 0
-; CHECK-NEXT: subf 0, 0, 1
+; CHECK-NEXT: sub 0, 1, 0
 ; CHECK-NEXT: lis 4, __stack_chk_guard@ha
 ; CHECK-NEXT: lwz 5, __stack_chk_guard@l(4)
 ; CHECK-NEXT: lis 6, 1
 ; CHECK-NEXT: ori 6, 6, 44
 ; CHECK-NEXT: stwx 5, 1, 6

llvm/test/CodeGen/PowerPC/stack-realign.ll

 ; CHECK-FP: blr
 
 ; CHECK-32-LABEL: @goo
 ; CHECK-32-DAG: mflr [[LR:[0-9]+]]
 ; CHECK-32-DAG: clrlwi [[REG:[0-9]+]], 1, 27
 ; CHECK-32-DAG: stw [[LR]], 4(1)
 ; CHECK-32-DAG: subfic 0, [[REG]], -64
 ; CHECK-32: stwux 1, 1, 0
-; CHECK-32: subf 0, 0, 1
+; CHECK-32: sub 0, 1, 0
 ; CHECK-32: addic 0, 0, -4
 ; CHECK-32: stwx 31, 0, 0
 ; CHECK-32: addic 0, 0, -4
 ; CHECK-32: stwx 30, 0, 0
 ; CHECK-32: addic 30, 0, 8
 
 ; CHECK-32-PIC-LABEL: @goo
 ; CHECK-32-PIC-DAG: mflr [[LR:[0-9]+]]
 ; CHECK-32-PIC-DAG: clrlwi [[REG:[0-9]+]], 1, 27
 ; CHECK-32-PIC-DAG: stw [[LR]], 4(1)
 ; CHECK-32-PIC-DAG: subfic 0, [[REG]], -64
 ; CHECK-32-PIC:     stwux 1, 1, 0
-; CHECK-32-PIC:     subf 0, 0, 1
+; CHECK-32-PIC:     sub 0, 1, 0
 ; CHECK-32-PIC:     addic 0, 0, -4
 ; CHECK-32-PIC:     stwx 31, 0, 0
 ; CHECK-32-PIC:     addic 0, 0, -4
 ; CHECK-32-PIC:     stwx 30, 0, 0
 ; CHECK-32-PIC:     addic 0, 0, -4
 ; CHECK-32-PIC:     stwx 29, 0, 0
 ; CHECK-32-PIC:     addic 29, 0, 12
 

 
 ; CHECK-32-DAG: lis [[REG1:[0-9]+]], -13
 ; CHECK-32-DAG: clrlwi [[REG3:[0-9]+]], 1, 27
 ; CHECK-32-DAG: mflr [[LR:[0-9]+]]
 ; CHECK-32-DAG: ori [[REG2:[0-9]+]], [[REG1]], 51904
 ; CHECK-32-DAG: stw [[LR]], 4(1)
 ; CHECK-32-DAG: subfc 0, [[REG3]], [[REG2]]
 ; CHECK-32:     stwux 1, 1, 0
-; CHECK-32:     subf 0, 0, 1
+; CHECK-32:     sub 0, 1, 0
 ; CHECK-32:     addic 0, 0, -4
 ; CHECK-32:     stwx 31, 0, 0
 ; CHECK-32:     addic 0, 0, -4
 ; CHECK-32:     stwx 30, 0, 0
 ; CHECK-32:     addic 30, 0, 8
 
 ; CHECK-32: blr
 
 ; CHECK-32-PIC-LABEL: @hoo
 
 ; CHECK-32-PIC-DAG: lis [[REG1:[0-9]+]], -13
 ; CHECK-32-PIC-DAG: clrlwi [[REG3:[0-9]+]], 1, 27
 ; CHECK-32-PIC-DAG: mflr {{[0-9]+}}
 ; CHECK-32-PIC-DAG: ori [[REG2:[0-9]+]], [[REG1]], 51904
 ; CHECK-32-PIC-DAG: stw 0, 4(1)
 ; CHECK-32-PIC-DAG: subfc 0, [[REG3]], [[REG2]]
 ; CHECK-32-PIC:     stwux 1, 1, 0
-; CHECK-32-PIC:     subf 0, 0, 1
+; CHECK-32-PIC:     sub 0, 1, 0
 ; CHECK-32-PIC:     addic 0, 0, -4
 ; CHECK-32-PIC:     stwx 31, 0, 0
 ; CHECK-32-PIC:     addic 0, 0, -8
 ; CHECK-32-PIC:     stwx 29, 0, 0
 ; CHECK-32-PIC:     addic 29, 0, 12
 
 ; CHECK-32: blr
 

llvm/test/CodeGen/PowerPC/sub-of-not.ll

; PPC64LE-NEXT:    blr
   %t0 = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
   %t1 = sub <4 x i32> %y, %t0
   ret <4 x i32> %t1
 }
 
 define <2 x i64> @vector_i128_i64(<2 x i64> %x, <2 x i64> %y) nounwind {
 ; PPC32-LABEL: vector_i128_i64:
 ; PPC32:       # %bb.0:
-; PPC32-NEXT:    nor 4, 4, 4
-; PPC32-NEXT:    nor 3, 3, 3
+; PPC32-NEXT:    not 4, 4
+; PPC32-NEXT:    not 3, 3
 ; PPC32-NEXT:    subfc 4, 4, 8
-; PPC32-NEXT:    nor 6, 6, 6
+; PPC32-NEXT:    not 6, 6
 ; PPC32-NEXT:    subfe 3, 3, 7
-; PPC32-NEXT:    nor 5, 5, 5
+; PPC32-NEXT:    not 5, 5
 ; PPC32-NEXT:    subfc 6, 6, 10
 ; PPC32-NEXT:    subfe 5, 5, 9
 ; PPC32-NEXT:    blr
 ;
 ; PPC64BE-LABEL: vector_i128_i64:
 ; PPC64BE:       # %bb.0:
 ; PPC64BE-NEXT:    add 3, 5, 3
 ; PPC64BE-NEXT:    add 4, 6, 4

llvm/test/CodeGen/PowerPC/umulo-128-legalisation-lowering.ll

 ; PPC64-NEXT:    crorc 20, 20, 2
 ; PPC64-NEXT:    crnor 20, 20, 21
 ; PPC64-NEXT:    mulld 4, 4, 6
 ; PPC64-NEXT:    bc 12, 20, .LBB0_2
 ; PPC64-NEXT:  # %bb.1: # %start
 ; PPC64-NEXT:    ori 5, 7, 0
 ; PPC64-NEXT:    blr
 ; PPC64-NEXT:  .LBB0_2: # %start
-; PPC64-NEXT:    addi 5, 0, 0
+; PPC64-NEXT:    li 5, 0
 ; PPC64-NEXT:    blr
 ;
 ; PPC32-LABEL: muloti_test:
 ; PPC32:       # %bb.0: # %start
 ; PPC32-NEXT:    mflr 0
 ; PPC32-NEXT:    stw 0, 4(1)
 ; PPC32-NEXT:    stwu 1, -80(1)
 ; PPC32-NEXT:    stw 26, 56(1) # 4-byte Folded Spill

 ; PPC32-NEXT:    cror 20, 20, 24
 ; PPC32-NEXT:    crnor 20, 20, 12
 ; PPC32-NEXT:    li 3, 1
 ; PPC32-NEXT:    bc 12, 20, .LBB0_2
 ; PPC32-NEXT:  # %bb.1: # %start
 ; PPC32-NEXT:    ori 7, 3, 0
 ; PPC32-NEXT:    b .LBB0_3
 ; PPC32-NEXT:  .LBB0_2: # %start
-; PPC32-NEXT:    addi 7, 0, 0
+; PPC32-NEXT:    li 7, 0
 ; PPC32-NEXT:  .LBB0_3: # %start
 ; PPC32-NEXT:    mr 3, 8
 ; PPC32-NEXT:    mtcrf 32, 12 # cr2
 ; PPC32-NEXT:    mtcrf 16, 12 # cr3
 ; PPC32-NEXT:    lwz 30, 72(1) # 4-byte Folded Reload
 ; PPC32-NEXT:    lwz 29, 68(1) # 4-byte Folded Reload
 ; PPC32-NEXT:    lwz 28, 64(1) # 4-byte Folded Reload
 ; PPC32-NEXT:    lwz 27, 60(1) # 4-byte Folded Reload

llvm/test/CodeGen/PowerPC/urem-lkk.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu -mcpu=ppc64 < %s | FileCheck -check-prefixes=CHECK,CHECK64 %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu -mcpu=ppc < %s | FileCheck -check-prefixes=CHECK,CHECK32 %s
 
 define i32 @fold_urem_positive_odd(i32 %x) {
 ; CHECK-LABEL: fold_urem_positive_odd:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lis 4, 22765
 ; CHECK-NEXT:    ori 4, 4, 8969
 ; CHECK-NEXT:    mulhwu 4, 3, 4
-; CHECK-NEXT:    subf 5, 4, 3
+; CHECK-NEXT:    sub 5, 3, 4
 ; CHECK-NEXT:    srwi 5, 5, 1
 ; CHECK-NEXT:    add 4, 5, 4
 ; CHECK-NEXT:    srwi 4, 4, 6
 ; CHECK-NEXT:    mulli 4, 4, 95
-; CHECK-NEXT:    subf 3, 4, 3
+; CHECK-NEXT:    sub 3, 3, 4
 ; CHECK-NEXT:    blr
   %1 = urem i32 %x, 95
   ret i32 %1
 }
 
 
 define i32 @fold_urem_positive_even(i32 %x) {
 ; CHECK-LABEL: fold_urem_positive_even:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lis 4, -2226
 ; CHECK-NEXT:    ori 4, 4, 16323
 ; CHECK-NEXT:    mulhwu 4, 3, 4
 ; CHECK-NEXT:    srwi 4, 4, 10
 ; CHECK-NEXT:    mulli 4, 4, 1060
-; CHECK-NEXT:    subf 3, 4, 3
+; CHECK-NEXT:    sub 3, 3, 4
 ; CHECK-NEXT:    blr
   %1 = urem i32 %x, 1060
   ret i32 %1
 }
 
 
 ; Don't fold if we can combine urem with udiv.
 define i32 @combine_urem_udiv(i32 %x) {
 ; CHECK-LABEL: combine_urem_udiv:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lis 4, 22765
 ; CHECK-NEXT:    ori 4, 4, 8969
 ; CHECK-NEXT:    mulhwu 4, 3, 4
-; CHECK-NEXT:    subf 5, 4, 3
+; CHECK-NEXT:    sub 5, 3, 4
 ; CHECK-NEXT:    srwi 5, 5, 1
 ; CHECK-NEXT:    add 4, 5, 4
 ; CHECK-NEXT:    srwi 4, 4, 6
 ; CHECK-NEXT:    mulli 5, 4, 95
-; CHECK-NEXT:    subf 3, 5, 3
+; CHECK-NEXT:    sub 3, 3, 5
 ; CHECK-NEXT:    add 3, 3, 4
 ; CHECK-NEXT:    blr
   %1 = urem i32 %x, 95
   %2 = udiv i32 %x, 95
   %3 = add i32 %1, %2
   ret i32 %3
 }
 

llvm/test/CodeGen/PowerPC/urem-vector-lkk.ll

 
 define <4 x i16> @fold_urem_vec_1(<4 x i16> %x) {
 ; P9LE-LABEL: fold_urem_vec_1:
 ; P9LE:       # %bb.0:
 ; P9LE-NEXT:    li r3, 4
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    lis r5, 21399
 ; P9LE-NEXT:    ori r5, r5, 33437
-; P9LE-NEXT:    rlwinm r4, r3, 0, 16, 31
+; P9LE-NEXT:    clrlwi r4, r3, 16
 ; P9LE-NEXT:    mulld r4, r4, r5
 ; P9LE-NEXT:    lis r5, 16727
 ; P9LE-NEXT:    ori r5, r5, 2287
 ; P9LE-NEXT:    rldicl r4, r4, 27, 37
 ; P9LE-NEXT:    mulli r4, r4, 98
 ; P9LE-NEXT:    subf r3, r4, r3
 ; P9LE-NEXT:    mtvsrd f0, r3
 ; P9LE-NEXT:    li r3, 6
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
-; P9LE-NEXT:    rlwinm r4, r3, 0, 16, 31
+; P9LE-NEXT:    clrlwi r4, r3, 16
 ; P9LE-NEXT:    mulld r4, r4, r5
 ; P9LE-NEXT:    lis r5, 8456
 ; P9LE-NEXT:    ori r5, r5, 16913
 ; P9LE-NEXT:    rldicl r4, r4, 24, 40
 ; P9LE-NEXT:    mulli r4, r4, 1003
 ; P9LE-NEXT:    subf r3, r4, r3
 ; P9LE-NEXT:    xxswapd v3, vs0
 ; P9LE-NEXT:    mtvsrd f0, r3

 ; P9BE-NEXT:    vmrghh v3, v4, v3
 ; P9BE-NEXT:    mtvsrd v4, r3
 ; P9BE-NEXT:    li r3, 0
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    rlwinm r3, r3, 0, 16, 31
 ; P9BE-NEXT:    clrldi r4, r3, 32
 ; P9BE-NEXT:    mulld r4, r4, r5
 ; P9BE-NEXT:    rldicl r4, r4, 32, 32
-; P9BE-NEXT:    subf r5, r4, r3
+; P9BE-NEXT:    sub r5, r3, r4
 ; P9BE-NEXT:    srwi r5, r5, 1
 ; P9BE-NEXT:    add r4, r5, r4
 ; P9BE-NEXT:    srwi r4, r4, 6
 ; P9BE-NEXT:    mulli r4, r4, 95
 ; P9BE-NEXT:    subf r3, r4, r3
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v2, r3
 ; P9BE-NEXT:    vmrghh v2, v2, v4
 ; P9BE-NEXT:    vmrghw v2, v2, v3
 ; P9BE-NEXT:    blr
 ;
 ; P8LE-LABEL: fold_urem_vec_1:
 ; P8LE:       # %bb.0:
 ; P8LE-NEXT:    xxswapd vs0, v2
 ; P8LE-NEXT:    lis r3, 22765
 ; P8LE-NEXT:    lis r8, 21399
 ; P8LE-NEXT:    ori r3, r3, 8969
 ; P8LE-NEXT:    ori r8, r8, 33437
 ; P8LE-NEXT:    mfvsrd r4, f0
 ; P8LE-NEXT:    clrldi r5, r4, 48
 ; P8LE-NEXT:    rldicl r9, r4, 32, 48
 ; P8LE-NEXT:    rlwinm r6, r5, 0, 16, 31
 ; P8LE-NEXT:    rldicl r10, r4, 16, 48
-; P8LE-NEXT:    rlwinm r11, r9, 0, 16, 31
+; P8LE-NEXT:    clrlwi r11, r9, 16
 ; P8LE-NEXT:    clrldi r7, r6, 32
-; P8LE-NEXT:    rlwinm r12, r10, 0, 16, 31
+; P8LE-NEXT:    clrlwi r12, r10, 16
 ; P8LE-NEXT:    mulld r3, r7, r3
 ; P8LE-NEXT:    lis r7, 16727
 ; P8LE-NEXT:    ori r7, r7, 2287
 ; P8LE-NEXT:    mulld r8, r11, r8
 ; P8LE-NEXT:    lis r11, 8456
 ; P8LE-NEXT:    rldicl r4, r4, 48, 48
 ; P8LE-NEXT:    mulld r7, r12, r7
 ; P8LE-NEXT:    ori r11, r11, 16913

 ; P8BE-NEXT:    lis r10, 8456
 ; P8BE-NEXT:    rldicl r4, r4, 32, 48
 ; P8BE-NEXT:    mulld r8, r11, r8
 ; P8BE-NEXT:    ori r10, r10, 16913
 ; P8BE-NEXT:    rlwinm r11, r4, 30, 18, 31
 ; P8BE-NEXT:    rldicl r3, r3, 32, 32
 ; P8BE-NEXT:    rlwinm r4, r4, 0, 16, 31
 ; P8BE-NEXT:    mulld r10, r11, r10
-; P8BE-NEXT:    subf r11, r3, r5
+; P8BE-NEXT:    sub r11, r5, r3
 ; P8BE-NEXT:    srwi r11, r11, 1
 ; P8BE-NEXT:    rldicl r9, r9, 24, 40
 ; P8BE-NEXT:    add r3, r11, r3
 ; P8BE-NEXT:    rldicl r8, r8, 27, 37
 ; P8BE-NEXT:    srwi r3, r3, 6
 ; P8BE-NEXT:    mulli r9, r9, 1003
 ; P8BE-NEXT:    rldicl r10, r10, 30, 34
 ; P8BE-NEXT:    mulli r8, r8, 98

 ; P9BE-NEXT:    li r3, 6
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    rlwinm r3, r3, 0, 16, 31
 ; P9BE-NEXT:    lis r5, 22765
 ; P9BE-NEXT:    ori r5, r5, 8969
 ; P9BE-NEXT:    clrldi r4, r3, 32
 ; P9BE-NEXT:    mulld r4, r4, r5
 ; P9BE-NEXT:    rldicl r4, r4, 32, 32
-; P9BE-NEXT:    subf r6, r4, r3
+; P9BE-NEXT:    sub r6, r3, r4
 ; P9BE-NEXT:    srwi r6, r6, 1
 ; P9BE-NEXT:    add r4, r6, r4
 ; P9BE-NEXT:    srwi r4, r4, 6
 ; P9BE-NEXT:    mulli r4, r4, 95
 ; P9BE-NEXT:    subf r3, r4, r3
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v3, r3
 ; P9BE-NEXT:    li r3, 4
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    rlwinm r3, r3, 0, 16, 31
 ; P9BE-NEXT:    clrldi r4, r3, 32
 ; P9BE-NEXT:    mulld r4, r4, r5
 ; P9BE-NEXT:    rldicl r4, r4, 32, 32
-; P9BE-NEXT:    subf r6, r4, r3
+; P9BE-NEXT:    sub r6, r3, r4
 ; P9BE-NEXT:    srwi r6, r6, 1
 ; P9BE-NEXT:    add r4, r6, r4
 ; P9BE-NEXT:    srwi r4, r4, 6
 ; P9BE-NEXT:    mulli r4, r4, 95
 ; P9BE-NEXT:    subf r3, r4, r3
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v4, r3
 ; P9BE-NEXT:    li r3, 2
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    rlwinm r3, r3, 0, 16, 31
 ; P9BE-NEXT:    clrldi r4, r3, 32
 ; P9BE-NEXT:    mulld r4, r4, r5
 ; P9BE-NEXT:    rldicl r4, r4, 32, 32
-; P9BE-NEXT:    subf r6, r4, r3
+; P9BE-NEXT:    sub r6, r3, r4
 ; P9BE-NEXT:    srwi r6, r6, 1
 ; P9BE-NEXT:    add r4, r6, r4
 ; P9BE-NEXT:    srwi r4, r4, 6
 ; P9BE-NEXT:    mulli r4, r4, 95
 ; P9BE-NEXT:    subf r3, r4, r3
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    vmrghh v3, v4, v3
 ; P9BE-NEXT:    mtvsrd v4, r3
 ; P9BE-NEXT:    li r3, 0
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    rlwinm r3, r3, 0, 16, 31
 ; P9BE-NEXT:    clrldi r4, r3, 32
 ; P9BE-NEXT:    mulld r4, r4, r5
 ; P9BE-NEXT:    rldicl r4, r4, 32, 32
-; P9BE-NEXT:    subf r5, r4, r3
+; P9BE-NEXT:    sub r5, r3, r4
 ; P9BE-NEXT:    srwi r5, r5, 1
 ; P9BE-NEXT:    add r4, r5, r4
 ; P9BE-NEXT:    srwi r4, r4, 6
 ; P9BE-NEXT:    mulli r4, r4, 95
 ; P9BE-NEXT:    subf r3, r4, r3
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v2, r3
 ; P9BE-NEXT:    vmrghh v2, v2, v4

 ; P8BE-NEXT:    rlwinm r4, r4, 0, 16, 31
 ; P8BE-NEXT:    clrldi r10, r7, 32
 ; P8BE-NEXT:    mulld r9, r9, r3
 ; P8BE-NEXT:    clrldi r11, r4, 32
 ; P8BE-NEXT:    mulld r10, r10, r3
 ; P8BE-NEXT:    mulld r3, r11, r3
 ; P8BE-NEXT:    rldicl r8, r8, 32, 32
 ; P8BE-NEXT:    rldicl r9, r9, 32, 32
-; P8BE-NEXT:    subf r11, r8, r5
+; P8BE-NEXT:    sub r11, r5, r8
 ; P8BE-NEXT:    rldicl r10, r10, 32, 32
-; P8BE-NEXT:    subf r12, r9, r6
+; P8BE-NEXT:    sub r12, r6, r9
 ; P8BE-NEXT:    srwi r11, r11, 1
 ; P8BE-NEXT:    rldicl r3, r3, 32, 32
 ; P8BE-NEXT:    add r8, r11, r8
-; P8BE-NEXT:    subf r11, r10, r7
+; P8BE-NEXT:    sub r11, r7, r10
 ; P8BE-NEXT:    srwi r12, r12, 1
 ; P8BE-NEXT:    add r9, r12, r9
-; P8BE-NEXT:    subf r12, r3, r4
+; P8BE-NEXT:    sub r12, r4, r3
 ; P8BE-NEXT:    srwi r11, r11, 1
 ; P8BE-NEXT:    srwi r8, r8, 6
 ; P8BE-NEXT:    add r10, r11, r10
 ; P8BE-NEXT:    srwi r11, r12, 1
 ; P8BE-NEXT:    srwi r9, r9, 6
 ; P8BE-NEXT:    add r3, r11, r3
 ; P8BE-NEXT:    srwi r10, r10, 6
 ; P8BE-NEXT:    srwi r3, r3, 6

 ; P9BE-NEXT:    vmrghh v3, v4, v3
 ; P9BE-NEXT:    mtvsrd v4, r3
 ; P9BE-NEXT:    li r3, 0
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    rlwinm r3, r3, 0, 16, 31
 ; P9BE-NEXT:    clrldi r8, r3, 32
 ; P9BE-NEXT:    mulld r6, r8, r6
 ; P9BE-NEXT:    rldicl r6, r6, 32, 32
-; P9BE-NEXT:    subf r8, r6, r3
+; P9BE-NEXT:    sub r8, r3, r6
 ; P9BE-NEXT:    srwi r8, r8, 1
 ; P9BE-NEXT:    add r6, r8, r6
 ; P9BE-NEXT:    srwi r6, r6, 6
 ; P9BE-NEXT:    mulli r8, r6, 95
 ; P9BE-NEXT:    subf r3, r8, r3
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v2, r3
 ; P9BE-NEXT:    sldi r3, r4, 48

 ; P8BE-NEXT:    rldicl r12, r12, 32, 32
 ; P8BE-NEXT:    subf r8, r11, r8
 ; P8BE-NEXT:    rldicl r5, r5, 32, 32
 ; P8BE-NEXT:    subf r9, r12, r9
 ; P8BE-NEXT:    srwi r8, r8, 1
 ; P8BE-NEXT:    rldicl r0, r0, 32, 32
 ; P8BE-NEXT:    add r8, r8, r11
 ; P8BE-NEXT:    srwi r9, r9, 1
-; P8BE-NEXT:    subf r11, r5, r6
+; P8BE-NEXT:    sub r11, r6, r5
 ; P8BE-NEXT:    subf r10, r0, r10
 ; P8BE-NEXT:    add r9, r9, r12
 ; P8BE-NEXT:    srwi r8, r8, 6
 ; P8BE-NEXT:    srwi r11, r11, 1
 ; P8BE-NEXT:    srwi r10, r10, 1
 ; P8BE-NEXT:    srwi r9, r9, 6
 ; P8BE-NEXT:    add r5, r11, r5
 ; P8BE-NEXT:    mulli r12, r8, 95

 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    rlwinm r3, r3, 0, 16, 31
 ; P9BE-NEXT:    lis r5, 22765
 ; P9BE-NEXT:    ori r5, r5, 8969
 ; P9BE-NEXT:    vmrghh v3, v4, v3
 ; P9BE-NEXT:    clrldi r4, r3, 32
 ; P9BE-NEXT:    mulld r4, r4, r5
 ; P9BE-NEXT:    rldicl r4, r4, 32, 32
-; P9BE-NEXT:    subf r5, r4, r3
+; P9BE-NEXT:    sub r5, r3, r4
 ; P9BE-NEXT:    srwi r5, r5, 1
 ; P9BE-NEXT:    add r4, r5, r4
 ; P9BE-NEXT:    srwi r4, r4, 6
 ; P9BE-NEXT:    mulli r4, r4, 95
 ; P9BE-NEXT:    subf r3, r4, r3
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v4, r3
 ; P9BE-NEXT:    li r3, 4

 ; P8BE-NEXT:    ori r3, r3, 8969
 ; P8BE-NEXT:    clrldi r5, r4, 48
 ; P8BE-NEXT:    rldicl r7, r4, 16, 48
 ; P8BE-NEXT:    rlwinm r5, r5, 0, 16, 31
 ; P8BE-NEXT:    rlwinm r7, r7, 0, 26, 31
 ; P8BE-NEXT:    clrldi r6, r5, 32
 ; P8BE-NEXT:    mulld r3, r6, r3
 ; P8BE-NEXT:    rldicl r3, r3, 32, 32
-; P8BE-NEXT:    subf r6, r3, r5
+; P8BE-NEXT:    sub r6, r5, r3
 ; P8BE-NEXT:    srwi r6, r6, 1
 ; P8BE-NEXT:    add r3, r6, r3
 ; P8BE-NEXT:    rldicl r6, r4, 32, 48
 ; P8BE-NEXT:    srwi r3, r3, 6
 ; P8BE-NEXT:    rldicl r4, r4, 48, 48
 ; P8BE-NEXT:    rlwinm r6, r6, 0, 27, 31
 ; P8BE-NEXT:    mulli r3, r3, 95
 ; P8BE-NEXT:    sldi r6, r6, 48

 ; P9LE:       # %bb.0:
 ; P9LE-NEXT:    li r3, 4
 ; P9LE-NEXT:    li r5, 0
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    oris r6, r5, 45590
 ; P9LE-NEXT:    oris r5, r5, 51306
 ; P9LE-NEXT:    ori r6, r6, 17097
 ; P9LE-NEXT:    ori r5, r5, 30865
-; P9LE-NEXT:    rlwinm r4, r3, 0, 16, 31
+; P9LE-NEXT:    clrlwi r4, r3, 16
 ; P9LE-NEXT:    mulld r4, r4, r6
 ; P9LE-NEXT:    lis r6, 24749
 ; P9LE-NEXT:    ori r6, r6, 47143
 ; P9LE-NEXT:    rldicl r4, r4, 28, 36
 ; P9LE-NEXT:    mulli r4, r4, 23
 ; P9LE-NEXT:    subf r3, r4, r3
 ; P9LE-NEXT:    mtvsrd f0, r3
 ; P9LE-NEXT:    li r3, 6
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
-; P9LE-NEXT:    rlwinm r4, r3, 0, 16, 31
+; P9LE-NEXT:    clrlwi r4, r3, 16
 ; P9LE-NEXT:    mulld r4, r4, r6
 ; P9LE-NEXT:    rldicl r4, r4, 21, 43
 ; P9LE-NEXT:    mulli r4, r4, 5423
 ; P9LE-NEXT:    subf r3, r4, r3
 ; P9LE-NEXT:    xxswapd v3, vs0
 ; P9LE-NEXT:    mtvsrd f0, r3
 ; P9LE-NEXT:    li r3, 2
 ; P9LE-NEXT:    vextuhrx r3, r3, v2

 ; P8LE-NEXT:    oris r5, r3, 45590
 ; P8LE-NEXT:    ori r8, r8, 47143
 ; P8LE-NEXT:    oris r3, r3, 51306
 ; P8LE-NEXT:    ori r5, r5, 17097
 ; P8LE-NEXT:    ori r3, r3, 30865
 ; P8LE-NEXT:    mfvsrd r4, f0
 ; P8LE-NEXT:    rldicl r6, r4, 32, 48
 ; P8LE-NEXT:    rldicl r7, r4, 16, 48
-; P8LE-NEXT:    rlwinm r9, r6, 0, 16, 31
+; P8LE-NEXT:    clrlwi r9, r6, 16
 ; P8LE-NEXT:    rldicl r4, r4, 48, 48
 ; P8LE-NEXT:    mulld r5, r9, r5
-; P8LE-NEXT:    rlwinm r9, r7, 0, 16, 31
+; P8LE-NEXT:    clrlwi r9, r7, 16
 ; P8LE-NEXT:    mulld r8, r9, r8
 ; P8LE-NEXT:    rlwinm r9, r4, 31, 17, 31
 ; P8LE-NEXT:    mulld r3, r9, r3
 ; P8LE-NEXT:    rldicl r5, r5, 28, 36
 ; P8LE-NEXT:    rldicl r8, r8, 21, 43
 ; P8LE-NEXT:    mulli r5, r5, 23
 ; P8LE-NEXT:    rldicl r3, r3, 24, 40
 ; P8LE-NEXT:    mulli r8, r8, 5423

llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ext.txt

 0x3c 0x43 0xff 0x80
 
 # CHECK: addic 2, 3, -128
 0x30 0x43 0xff 0x80
 
 # CHECK: addic. 2, 3, -128
 0x34 0x43 0xff 0x80
 
-# CHECK: subf 2, 4, 3
+# CHECK: sub 2, 3, 4
 0x7c 0x44 0x18 0x50
 
-# CHECK: subf. 2, 4, 3
+# CHECK: sub. 2, 3, 4
 0x7c 0x44 0x18 0x51
 
-# CHECK: subfc 2, 4, 3
+# CHECK: subc 2, 3, 4
 0x7c 0x44 0x18 0x10
 
-# CHECK: subfc. 2, 4, 3
+# CHECK: subc. 2, 3, 4
 0x7c 0x44 0x18 0x11
 
 # CHECK: cmpdi 2, 3, 128
 0x2d 0x23 0x00 0x80
 
 # CHECK: cmpdi 3, 128
 0x2c 0x23 0x00 0x80
 

 0x38 0x40 0x00 0x80
 
 # CHECK: lis 2, 128
 0x3c 0x40 0x00 0x80
 
 # CHECK: mr 2, 3
 0x7c 0x62 0x1b 0x78
 
-# CHECK: or. 2, 3, 3
+# CHECK: mr. 2, 3
 0x7c 0x62 0x1b 0x79
 
-# CHECK: nor 2, 3, 3
+# CHECK: not 2, 3
 0x7c 0x62 0x18 0xf8
 
-# CHECK: nor. 2, 3, 3
+# CHECK: not. 2, 3
 0x7c 0x62 0x18 0xf9
 
-# CHECK: mtcrf 255, 2
+# CHECK: mtcr 2
 0x7c 0x4f 0xf1 0x20
 
 # CHECK: dss 3
 0x7c 0x60 0x06 0x6c
 # CHECK: dssall
 0x7e 0x00 0x06 0x6c
 # CHECK: dst 12, 11, 3
 0x7c 0x6c 0x5a 0xac

llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-p8htm.txt

 # RUN: llvm-mc --disassemble %s -triple powerpc64-unknown-unknown -mcpu=pwr8 | FileCheck %s
 
 # CHECK: tbegin. 1
 0x7c 0x20 0x05 0x1d
 
 # CHECK: tbegin. 0
 0x7c 0x00 0x05 0x1d
 
-# CHECK: tend. 0
+# CHECK: tend.
 0x7c 0x00 0x05 0x5d
 
-# CHECK: tend. 1
+# CHECK: tendall.
 0x7e 0x00 0x05 0x5d
 
 # CHECK: tabort. 3
 0x7c 0x03 0x07 0x1d
 
 # CHECK: tabortdc. 9, 0, 0
 0x7d 0x20 0x06 0x5d
 
 # CHECK: tabortdci. 1, 0, 3
 0x7c 0x20 0x1e 0xdd
 
 # CHECK: tabortwc. 0, 4, 3
 0x7c 0x04 0x1e 0x1d
 
 # CHECK: tabortwci. 0, 4, 2
 0x7c 0x04 0x16 0x9d
 
-# CHECK: tsr. 1
+# CHECK: tresume.
 0x7c 0x20 0x05 0xdd
 
-# CHECK: tsr. 0
+# CHECK: tsuspend.
 0x7c 0x00 0x05 0xdd
 
 # CHECK: tcheck 0
 0x7c 0x00 0x05 0x9c
 
 # CHECK: treclaim. 3
 0x7c 0x03 0x07 0x5d
 
 # CHECK: trechkpt.
 0x7c 0x00 0x07 0xdd

llvm/test/MC/Disassembler/PowerPC/ppc64-encoding.txt

 0x44 0x00 0x00 0x02
 
 # CHECK: clrbhrb
 0x7c 0x00 0x03 0x5c
 
 # CHECK: mfbhrbe 9, 983
 0x7d 0x3e 0xba 0x5c
 
-# CHECK: rfebb 1
+# CHECK: rfebb
 0x4c 0x00 0x09 0x24
 
 # CHECK: lbz 2, 128(4)                   
 0x88 0x44 0x00 0x80
 
 # CHECK: lbzx 2, 3, 4                    
 0x7c 0x43 0x20 0xae
 

 0x7c 0x43 0x22 0x15
 
 # CHECK: addo 2, 3, 4
 0x7c 0x43 0x26 0x14
 
 # CHECK: addo. 2, 3, 4
 0x7c 0x43 0x26 0x15
 
-# CHECK: subf 2, 3, 4                    
+# CHECK: sub 2, 4, 3                     
 0x7c 0x43 0x20 0x50
 
-# CHECK: subf. 2, 3, 4                   
+# CHECK: sub. 2, 4, 3                    
 0x7c 0x43 0x20 0x51
 
 # CHECK: subfo 2, 3, 4
 0x7c 0x43 0x24 0x50
 
 # CHECK: subfo. 2, 3, 4
 0x7c 0x43 0x24 0x51
 

 0x7c 0x43 0x20 0x15
 
 # CHECK: addco 2, 3, 4
 0x7c 0x43 0x24 0x14
 
 # CHECK: addco. 2, 3, 4
 0x7c 0x43 0x24 0x15
 
-# CHECK: subfc 2, 3, 4                   
+# CHECK: subc 2, 4, 3                    
 0x7c 0x43 0x20 0x10
 
-# CHECK: subfc 2, 3, 4                   
-0x7c 0x43 0x20 0x10
+# CHECK: subc. 2, 4, 3                   
+0x7c 0x43 0x20 0x11
 
 # CHECK: subfco 2, 3, 4
 0x7c 0x43 0x24 0x10
 
 # CHECK: subfco. 2, 3, 4
 0x7c 0x43 0x24 0x11
 
 # CHECK: adde 2, 3, 4                    

llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding.txt

 0x02 0x00 0x00 0x44
 
 # CHECK: clrbhrb
 0x5c 0x03 0x00 0x7c
 
 # CHECK: mfbhrbe 9, 983
 0x5c 0xba 0x3e 0x7d
 
-# CHECK: rfebb 1
+# CHECK: rfebb
 0x24 0x09 0x00 0x4c
 
 # CHECK: lbz 2, 128(4)
 0x80 0x00 0x44 0x88
 
 # CHECK: lbzx 2, 3, 4
 0xae 0x20 0x43 0x7c
 

 0x15 0x22 0x43 0x7c
 
 # CHECK: addo 2, 3, 4
 0x14 0x26 0x43 0x7c
 
 # CHECK: addo. 2, 3, 4
 0x15 0x26 0x43 0x7c
 
-# CHECK: subf 2, 3, 4
+# CHECK: sub 2, 4, 3
 0x50 0x20 0x43 0x7c
 
-# CHECK: subf. 2, 3, 4
+# CHECK: sub. 2, 4, 3
 0x51 0x20 0x43 0x7c
 
 # CHECK: subfo 2, 3, 4
 0x50 0x24 0x43 0x7c
 
 # CHECK: subfo. 2, 3, 4
 0x51 0x24 0x43 0x7c
 

 0x15 0x20 0x43 0x7c
 
 # CHECK: addco 2, 3, 4
 0x14 0x24 0x43 0x7c
 
 # CHECK: addco. 2, 3, 4
 0x15 0x24 0x43 0x7c
 
-# CHECK: subfc 2, 3, 4
+# CHECK: subc 2, 4, 3
 0x10 0x20 0x43 0x7c
 
-# CHECK: subfc 2, 3, 4
-0x10 0x20 0x43 0x7c
+# CHECK: subc. 2, 4, 3
+0x11 0x20 0x43 0x7c
 
 # CHECK: subfco 2, 3, 4
 0x10 0x24 0x43 0x7c
 
 # CHECK: subfco. 2, 3, 4
 0x11 0x24 0x43 0x7c
 
 # CHECK: adde 2, 3, 4

llvm/test/MC/PowerPC/htm.s

 # RUN: llvm-mc -triple powerpc64-unknown-linux-gnu --show-encoding %s | FileCheck -check-prefix=CHECK-BE %s
 # RUN: llvm-mc -triple powerpc64le-unknown-linux-gnu --show-encoding %s | FileCheck -check-prefix=CHECK-LE %s
 
 # CHECK-BE: tbegin. 0                      # encoding: [0x7c,0x00,0x05,0x1d]
 # CHECK-LE: tbegin. 0                      # encoding: [0x1d,0x05,0x00,0x7c]
             tbegin. 0
 # CHECK-BE: tbegin. 1                      # encoding: [0x7c,0x20,0x05,0x1d]
 # CHECK-LE: tbegin. 1                      # encoding: [0x1d,0x05,0x20,0x7c]
             tbegin. 1
 
-# CHECK-BE: tend. 0                        # encoding: [0x7c,0x00,0x05,0x5d]
-# CHECK-LE: tend. 0                        # encoding: [0x5d,0x05,0x00,0x7c]
+# CHECK-BE: tend.                          # encoding: [0x7c,0x00,0x05,0x5d]
+# CHECK-LE: tend.                          # encoding: [0x5d,0x05,0x00,0x7c]
             tend. 0
-# CHECK-BE: tend. 1                        # encoding: [0x7e,0x00,0x05,0x5d]
-# CHECK-LE: tend. 1                        # encoding: [0x5d,0x05,0x00,0x7e]
+# CHECK-BE: tendall.                       # encoding: [0x7e,0x00,0x05,0x5d]
+# CHECK-LE: tendall.                       # encoding: [0x5d,0x05,0x00,0x7e]
             tend. 1
 
 # CHECK-BE: tabort. 9                      # encoding: [0x7c,0x09,0x07,0x1d]
 # CHECK-LE: tabort. 9                      # encoding: [0x1d,0x07,0x09,0x7c]
             tabort. 9
 # CHECK-BE: tabortdc. 0, 9, 9              # encoding: [0x7c,0x09,0x4e,0x5d]
 # CHECK-LE: tabortdc. 0, 9, 9              # encoding: [0x5d,0x4e,0x09,0x7c]
             tabortdc. 0, 9, 9
 # CHECK-BE: tabortdci. 0, 9, 0             # encoding: [0x7c,0x09,0x06,0xdd]
 # CHECK-LE: tabortdci. 0, 9, 0             # encoding: [0xdd,0x06,0x09,0x7c]
             tabortdci. 0, 9, 0
 # CHECK-BE: tabortwc. 0, 9, 9              # encoding: [0x7c,0x09,0x4e,0x1d]
 # CHECK-LE: tabortwc. 0, 9, 9              # encoding: [0x1d,0x4e,0x09,0x7c]
             tabortwc. 0, 9, 9
 # CHECK-BE: tabortwci. 0, 9, 0             # encoding: [0x7c,0x09,0x06,0x9d]
 # CHECK-LE: tabortwci. 0, 9, 0             # encoding: [0x9d,0x06,0x09,0x7c]
             tabortwci. 0, 9, 0
 
-# CHECK-BE: tsr. 0                         # encoding: [0x7c,0x00,0x05,0xdd]
-# CHECK-LE: tsr. 0                         # encoding: [0xdd,0x05,0x00,0x7c]
+# CHECK-BE: tsuspend.                      # encoding: [0x7c,0x00,0x05,0xdd]
+# CHECK-LE: tsuspend.                      # encoding: [0xdd,0x05,0x00,0x7c]
             tsr. 0
-# CHECK-BE: tsr. 1                         # encoding: [0x7c,0x20,0x05,0xdd]
-# CHECK-LE: tsr. 1                         # encoding: [0xdd,0x05,0x20,0x7c]
+# CHECK-BE: tresume.                       # encoding: [0x7c,0x20,0x05,0xdd]
+# CHECK-LE: tresume.                       # encoding: [0xdd,0x05,0x20,0x7c]
             tsr. 1
 
 # CHECK-BE: tcheck 0                       # encoding: [0x7c,0x00,0x05,0x9c]
 # CHECK-LE: tcheck 0                       # encoding: [0x9c,0x05,0x00,0x7c]
             tcheck 0
 # CHECK-BE: tcheck 3                       # encoding: [0x7d,0x80,0x05,0x9c]
 # CHECK-LE: tcheck 3                       # encoding: [0x9c,0x05,0x80,0x7d]
             tcheck 3
 
 # CHECK-BE: treclaim. 9                    # encoding: [0x7c,0x09,0x07,0x5d]
 # CHECK-LE: treclaim. 9                    # encoding: [0x5d,0x07,0x09,0x7c]
             treclaim. 9
 # CHECK-BE: trechkpt.                      # encoding: [0x7c,0x00,0x07,0xdd]
 # CHECK-LE: trechkpt.                      # encoding: [0xdd,0x07,0x00,0x7c]
             trechkpt.

llvm/test/MC/PowerPC/ppc64-encoding.s

 # Branch history rolling buffer
 
 # CHECK-BE: clrbhrb                         # encoding: [0x7c,0x00,0x03,0x5c]
 # CHECK-LE: clrbhrb                         # encoding: [0x5c,0x03,0x00,0x7c]
             clrbhrb
 # CHECK-BE: mfbhrbe 9, 983                  # encoding: [0x7d,0x3e,0xba,0x5c]
 # CHECK-LE: mfbhrbe 9, 983                  # encoding: [0x5c,0xba,0x3e,0x7d]
             mfbhrbe 9, 983
-# CHECK-BE: rfebb 1                         # encoding: [0x4c,0x00,0x09,0x24]
-# CHECK-LE: rfebb 1                         # encoding: [0x24,0x09,0x00,0x4c]
+# CHECK-BE: rfebb                           # encoding: [0x4c,0x00,0x09,0x24]
+# CHECK-LE: rfebb                           # encoding: [0x24,0x09,0x00,0x4c]
             rfebb 1
 
 # Fixed-point facility
 
 # Fixed-point load instructions
 
 # CHECK-BE: lbz 2, 128(4)                   # encoding: [0x88,0x44,0x00,0x80]
 # CHECK-LE: lbz 2, 128(4)                   # encoding: [0x80,0x00,0x44,0x88]

 # CHECK-LE: add. 2, 3, 4                    # encoding: [0x15,0x22,0x43,0x7c]
             add. 2, 3, 4
 # CHECK-BE: addo 2, 3, 4                    # encoding: [0x7c,0x43,0x26,0x14]
 # CHECK-LE: addo 2, 3, 4                    # encoding: [0x14,0x26,0x43,0x7c]
             addo 2, 3, 4
 # CHECK-BE: addo. 2, 3, 4                   # encoding: [0x7c,0x43,0x26,0x15]
 # CHECK-LE: addo. 2, 3, 4                   # encoding: [0x15,0x26,0x43,0x7c]
             addo. 2, 3, 4
-# CHECK-BE: subf 2, 3, 4                    # encoding: [0x7c,0x43,0x20,0x50]
-# CHECK-LE: subf 2, 3, 4                    # encoding: [0x50,0x20,0x43,0x7c]
+# CHECK-BE: sub 2, 4, 3                     # encoding: [0x7c,0x43,0x20,0x50]
+# CHECK-LE: sub 2, 4, 3                     # encoding: [0x50,0x20,0x43,0x7c]
             subf 2, 3, 4
-# CHECK-BE: subf. 2, 3, 4                   # encoding: [0x7c,0x43,0x20,0x51]
-# CHECK-LE: subf. 2, 3, 4                   # encoding: [0x51,0x20,0x43,0x7c]
+# CHECK-BE: sub. 2, 4, 3                    # encoding: [0x7c,0x43,0x20,0x51]
+# CHECK-LE: sub. 2, 4, 3                    # encoding: [0x51,0x20,0x43,0x7c]
             subf. 2, 3, 4
 # CHECK-BE: subfo 2, 3, 4                   # encoding: [0x7c,0x43,0x24,0x50]
 # CHECK-LE: subfo 2, 3, 4                   # encoding: [0x50,0x24,0x43,0x7c]
             subfo 2, 3, 4
 # CHECK-BE: subfo. 2, 3, 4                  # encoding: [0x7c,0x43,0x24,0x51]
 # CHECK-LE: subfo. 2, 3, 4                  # encoding: [0x51,0x24,0x43,0x7c]
             subfo. 2, 3, 4
 # CHECK-BE: addic 2, 3, 128                 # encoding: [0x30,0x43,0x00,0x80]

 # CHECK-LE: addc. 2, 3, 4                   # encoding: [0x15,0x20,0x43,0x7c]
             addc. 2, 3, 4
 # CHECK-BE: addco 2, 3, 4                   # encoding: [0x7c,0x43,0x24,0x14]
 # CHECK-LE: addco 2, 3, 4                   # encoding: [0x14,0x24,0x43,0x7c]
             addco 2, 3, 4
 # CHECK-BE: addco. 2, 3, 4                  # encoding: [0x7c,0x43,0x24,0x15]
 # CHECK-LE: addco. 2, 3, 4                  # encoding: [0x15,0x24,0x43,0x7c]
             addco. 2, 3, 4
-# CHECK-BE: subfc 2, 3, 4                   # encoding: [0x7c,0x43,0x20,0x10]
-# CHECK-LE: subfc 2, 3, 4                   # encoding: [0x10,0x20,0x43,0x7c]
+# CHECK-BE: subc 2, 4, 3                    # encoding: [0x7c,0x43,0x20,0x10]
+# CHECK-LE: subc 2, 4, 3                    # encoding: [0x10,0x20,0x43,0x7c]
             subfc 2, 3, 4
-# CHECK-BE: subfc 2, 3, 4                   # encoding: [0x7c,0x43,0x20,0x10]
-# CHECK-LE: subfc 2, 3, 4                   # encoding: [0x10,0x20,0x43,0x7c]
+# CHECK-BE: subc 2, 4, 3                    # encoding: [0x7c,0x43,0x20,0x10]
+# CHECK-LE: subc 2, 4, 3                    # encoding: [0x10,0x20,0x43,0x7c]
             subfc 2, 3, 4
 # CHECK-BE: subfco 2, 3, 4                  # encoding: [0x7c,0x43,0x24,0x10]
 # CHECK-LE: subfco 2, 3, 4                  # encoding: [0x10,0x24,0x43,0x7c]
             subfco 2, 3, 4
 # CHECK-BE: subfco. 2, 3, 4                 # encoding: [0x7c,0x43,0x24,0x11]
 # CHECK-LE: subfco. 2, 3, 4                 # encoding: [0x11,0x24,0x43,0x7c]
             subfco. 2, 3, 4
 

llvm/test/MC/PowerPC/ppc64-operands.s

 # CHECK-BE: add 0, 0, 0                     # encoding: [0x7c,0x00,0x02,0x14]
 # CHECK-LE: add 0, 0, 0                     # encoding: [0x14,0x02,0x00,0x7c]
             add 0, 0, 0
 
 # CHECK-BE: add 31, 31, 31                  # encoding: [0x7f,0xff,0xfa,0x14]
 # CHECK-LE: add 31, 31, 31                  # encoding: [0x14,0xfa,0xff,0x7f]
             add 31, 31, 31
 
-# CHECK-BE: addi 1, 0, 0                    # encoding: [0x38,0x20,0x00,0x00]
-# CHECK-LE: addi 1, 0, 0                    # encoding: [0x00,0x00,0x20,0x38]
+# CHECK-BE: li 1, 0                         # encoding: [0x38,0x20,0x00,0x00]
+# CHECK-LE: li 1, 0                         # encoding: [0x00,0x00,0x20,0x38]
             addi 1, 0, 0
 
-# CHECK-BE: addi 1, 0, 0                    # encoding: [0x38,0x20,0x00,0x00]
-# CHECK-LE: addi 1, 0, 0                    # encoding: [0x00,0x00,0x20,0x38]
+# CHECK-BE: li 1, 0                         # encoding: [0x38,0x20,0x00,0x00]
+# CHECK-LE: li 1, 0                         # encoding: [0x00,0x00,0x20,0x38]
             addi 1, %r0, 0
 
 # Signed 16-bit immediate operands
 
 # CHECK-BE: addi 1, 2, 0                    # encoding: [0x38,0x22,0x00,0x00]
 # CHECK-LE: addi 1, 2, 0                    # encoding: [0x00,0x00,0x22,0x38]
             addi 1, 2, 0
 
-# CHECK-BE: addi 1, 0, -32768               # encoding: [0x38,0x20,0x80,0x00]
-# CHECK-LE: addi 1, 0, -32768               # encoding: [0x00,0x80,0x20,0x38]
+# CHECK-BE: li 1, -32768                    # encoding: [0x38,0x20,0x80,0x00]
+# CHECK-LE: li 1, -32768                    # encoding: [0x00,0x80,0x20,0x38]
             addi 1, 0, -32768
 
-# CHECK-BE: addi 1, 0, 32767                # encoding: [0x38,0x20,0x7f,0xff]
-# CHECK-LE: addi 1, 0, 32767                # encoding: [0xff,0x7f,0x20,0x38]
+# CHECK-BE: li 1, 32767                     # encoding: [0x38,0x20,0x7f,0xff]
+# CHECK-LE: li 1, 32767                     # encoding: [0xff,0x7f,0x20,0x38]
             addi 1, 0, 32767
 
 # Unsigned 16-bit immediate operands
 
 # CHECK-BE: ori 1, 2, 0                     # encoding: [0x60,0x41,0x00,0x00]
 # CHECK-LE: ori 1, 2, 0                     # encoding: [0x00,0x00,0x41,0x60]
             ori 1, 2, 0
 
 # CHECK-BE: ori 1, 2, 65535                 # encoding: [0x60,0x41,0xff,0xff]
 # CHECK-LE: ori 1, 2, 65535                 # encoding: [0xff,0xff,0x41,0x60]
             ori 1, 2, 65535
 
 # Signed 16-bit immediate operands (extended range for addis)
 
-# CHECK-BE: addis 1, 0, 0                   # encoding: [0x3c,0x20,0x00,0x00]
-# CHECK-LE: addis 1, 0, 0                   # encoding: [0x00,0x00,0x20,0x3c]
+# CHECK-BE: lis 1, 0                        # encoding: [0x3c,0x20,0x00,0x00]
+# CHECK-LE: lis 1, 0                        # encoding: [0x00,0x00,0x20,0x3c]
             addis 1, 0, -65536
 
-# CHECK-BE: addis 1, 0, -1                  # encoding: [0x3c,0x20,0xff,0xff]
-# CHECK-LE: addis 1, 0, -1                  # encoding: [0xff,0xff,0x20,0x3c]
+# CHECK-BE: lis 1, -1                       # encoding: [0x3c,0x20,0xff,0xff]
+# CHECK-LE: lis 1, -1                       # encoding: [0xff,0xff,0x20,0x3c]
             addis 1, 0, 65535
 
 # D-Form memory operands
 
 # CHECK-BE: lwz 1, 0(0)                     # encoding: [0x80,0x20,0x00,0x00]
 # CHECK-LE: lwz 1, 0(0)                     # encoding: [0x00,0x00,0x20,0x80]
             lwz 1, 0(0)