[PowerPC] Add some InstAlias definitions

[ZhangKang]

Summary

This patch add the InstAlias definitions for below instructions.

ADDI ADDIS ADDI8 ADDIS8
RLWINM8
ISEL ISEL8
OR OR_rec ORI ORI8 XORI8
CNTLZW8 CNTLZW8_rec
TEND TSR
RFEBB
NOR NOR_rec
MTCRF
SUBF SUBF_rec SUBFC SUBFC_rec
RLDICL_32_64
TW

[ZhangKang]

ping

[steven.zhang]

LGTM. I trust in you that you have done a fully test for this patch and check it carefully with PowerISA.

[ZhangKang]

Rebase.

lld/test/ELF/ppc32-call-stub-pic.s

 ## Operand of addi: 0x100a8-.glink = 24
 # CHECK-NEXT:         addis 11, 11, 0
 # CHECK-NEXT:         mflr 0
 # CHECK-NEXT:         bcl 20, 31, 0x[[#%x,NEXT:]]
 # CHECK-NEXT: [[#%x,NEXT]]: addi 11, 11, 24
 
 # CHECK-NEXT: mflr 12
 # CHECK-NEXT: mtlr 0
-# CHECK-NEXT: subf 11, 12, 11
+# CHECK-NEXT: sub 11, 11, 12
 
 ## Operand of lwz in -pie mode: &.got[1] - 0x100a8 = 0x20088+4 - 0x100a8 = 65536*1-28
 # CHECK-NEXT:  addis 12, 12, 1
 # PIE-NEXT:    lwz 0, 192(12)
 # SHARED-NEXT: lwz 0, 184(12)
 
 # PIE-NEXT:    lwz 12, 196(12)
 # SHARED-NEXT: lwz 12, 188(12)

llvm/lib/Target/PowerPC/PPCInstr64Bit.td

 def ISEL8   : AForm_4<31, 15,
                      (outs g8rc:$rT), (ins g8rc_nox0:$rA, g8rc:$rB, crbitrc:$cond),
                      "isel $rT, $rA, $rB, $cond", IIC_IntISEL,
                      []>;
 }  // Interpretation64Bit
 }  // hasSideEffects = 0
 }  // End FXU Operations.
 
+def : InstAlias<"li $rD, $imm", (ADDI8 g8rc:$rD, ZERO8, s16imm64:$imm)>;
+def : InstAlias<"lis $rD, $imm", (ADDIS8 g8rc:$rD, ZERO8, s17imm64:$imm)>;
+
 def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
 def : InstAlias<"mr. $rA, $rB", (OR8_rec g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
 
 def : InstAlias<"not $rA, $rB", (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
 def : InstAlias<"not. $rA, $rB", (NOR8_rec g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
 
 def : InstAlias<"mtcr $rA", (MTCRF8 255, g8rc:$rA)>;
 
 def : InstAlias<"sub $rA, $rB, $rC", (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
 def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8_rec g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
 def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
 def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8_rec g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
 
 def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM8 g8rc:$rA, g8rc:$rS, u5imm:$n, 0, 31)>;
 def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINM8_rec g8rc:$rA, g8rc:$rS, u5imm:$n, 0, 31)>;
 def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM8 g8rc:$rA, g8rc:$rS, g8rc:$rB, 0, 31)>;
 def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNM8_rec g8rc:$rA, g8rc:$rS, g8rc:$rB, 0, 31)>;
+def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM8 g8rc:$rA, g8rc:$rS, 0, u5imm:$n, 31)>;
+def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINM8_rec g8rc:$rA, g8rc:$rS, 0, u5imm:$n, 31)>;
+
+def : InstAlias<"isellt $rT, $rA, $rB",
+                (ISEL8 g8rc:$rT, g8rc_nox0:$rA, g8rc:$rB, CR0LT)>;
+def : InstAlias<"iselgt $rT, $rA, $rB",
+                (ISEL8 g8rc:$rT, g8rc_nox0:$rA, g8rc:$rB, CR0GT)>;
+def : InstAlias<"iseleq $rT, $rA, $rB",
+                (ISEL8 g8rc:$rT, g8rc_nox0:$rA, g8rc:$rB, CR0EQ)>;
+
+def : InstAlias<"nop", (ORI8 X0, X0, 0)>;
+def : InstAlias<"xnop", (XORI8 X0, X0, 0)>;
+
+def : InstAlias<"cntlzw $rA, $rS", (CNTLZW8 g8rc:$rA, g8rc:$rS)>;
+def : InstAlias<"cntlzw. $rA, $rS", (CNTLZW8_rec g8rc:$rA, g8rc:$rS)>;
 
 //===----------------------------------------------------------------------===//
 // Load/Store instructions.
 //
 
 
 // Sign extending loads.
 let PPC970_Unit = 2 in {

llvm/lib/Target/PowerPC/PPCInstrHTM.td

def : Pat<(int_ppc_tsuspend),
           (TSR 0)>;
 
 def : Pat<(i64 (int_ppc_ttest)),
           (RLDICL (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
                                       (TABORTWCI 0, (LI 0), 0), sub_32)),
                    36, 28)>;
 
 } // [HasHTM]
+
+def : InstAlias<"tend.", (TEND 0)>, Requires<[HasHTM]>;
+def : InstAlias<"tendall.", (TEND 1)>, Requires<[HasHTM]>;
+def : InstAlias<"tsuspend.", (TSR 0)>, Requires<[HasHTM]>;
+def : InstAlias<"tresume.", (TSR 1)>, Requires<[HasHTM]>;

llvm/lib/Target/PowerPC/PPCInstrInfo.td

def MFBHRBE : XFXForm_3p<31, 302, (outs gprc:$rD),
                          [(set i32:$rD,
                                (PPCmfbhrbe imm:$imm, imm:$dmy))]>,
                          PPC970_DGroup_First;
 
 def RFEBB : XLForm_S<19, 146, (outs), (ins u1imm:$imm), "rfebb $imm",
                      IIC_BrB, [(PPCrfebb (i32 imm:$imm))]>,
                      PPC970_DGroup_Single;
 
+def : InstAlias<"rfebb", (RFEBB 1)>;
+
 // DCB* instructions.
 def DCBA   : DCB_Form<758, 0, (outs), (ins memrr:$dst), "dcba $dst",
                       IIC_LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
                       PPC970_DGroup_Single;
 def DCBI   : DCB_Form<470, 0, (outs), (ins memrr:$dst), "dcbi $dst",
                       IIC_LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
                       PPC970_DGroup_Single;
 def DCBST  : DCB_Form<54, 0, (outs), (ins memrr:$dst), "dcbst $dst",
def LI  : DForm_2_r0<14, (outs gprc:$rD), (ins s16imm:$imm),
                        "li $rD, $imm", IIC_IntSimple,
                        [(set i32:$rD, imm32SExt16:$imm)]>;
   def LIS : DForm_2_r0<15, (outs gprc:$rD), (ins s17imm:$imm),
                        "lis $rD, $imm", IIC_IntSimple,
                        [(set i32:$rD, imm16ShiftedSExt:$imm)]>;
 }
 }
 
+def : InstAlias<"li $rD, $imm", (ADDI gprc:$rD, ZERO, s16imm:$imm)>;
+def : InstAlias<"lis $rD, $imm", (ADDIS gprc:$rD, ZERO, s17imm:$imm)>;
+
 let PPC970_Unit = 1 in {  // FXU Operations.
 let Defs = [CR0] in {
 def ANDI_rec : DForm_4<28, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
                     "andi. $dst, $src1, $src2", IIC_IntGeneral,
                     [(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>,
                     isRecordForm;
 def ANDIS_rec : DForm_4<29, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
                     "andis. $dst, $src1, $src2", IIC_IntGeneral,

 defm SRW  : XForm_6r<31, 536, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
                      "srw", "$rA, $rS, $rB", IIC_IntGeneral,
                      [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>;
 defm SRAW : XForm_6rc<31, 792, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
                       "sraw", "$rA, $rS, $rB", IIC_IntShift,
                       [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>;
 }
 
+def : InstAlias<"mr $rA, $rB", (OR gprc:$rA, gprc:$rB, gprc:$rB)>;
+def : InstAlias<"mr. $rA, $rB", (OR_rec gprc:$rA, gprc:$rB, gprc:$rB)>;
+
+def : InstAlias<"not $rA, $rS", (NOR gprc:$rA, gprc:$rS, gprc:$rS)>;
+def : InstAlias<"not. $rA, $rS", (NOR_rec gprc:$rA, gprc:$rS, gprc:$rS)>;
+
+def : InstAlias<"nop", (ORI R0, R0, 0)>;
+
 let PPC970_Unit = 1 in {  // FXU Operations.
 let hasSideEffects = 0 in {
 defm SRAWI : XForm_10rc<31, 824, (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH),
                         "srawi", "$rA, $rS, $SH", IIC_IntShift,
                         [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>;
 defm CNTLZW : XForm_11r<31,  26, (outs gprc:$rA), (ins gprc:$rS),
                         "cntlzw", "$rA, $rS", IIC_IntGeneral,
                         [(set i32:$rA, (ctlz i32:$rS))]>;
def MFCR : XFXForm_3<31, 19, (outs gprc:$rT), (ins),
                      "mfcr $rT", IIC_SprMFCR>,
                      PPC970_MicroCode, PPC970_Unit_CRU;
 } // hasExtraSrcRegAllocReq = 1
 
 def MCRXRX : X_BF3<31, 576, (outs crrc:$BF), (ins),
                    "mcrxrx $BF", IIC_BrMCRX>, Requires<[IsISA3_0]>;
 } // hasSideEffects = 0
 
+def : InstAlias<"mtcr $rA", (MTCRF 255, gprc:$rA)>;
+
 let Predicates = [HasFPU] in {
 // Custom inserter instruction to perform FADD in round-to-zero mode.
 let Uses = [RM] in {
   def FADDrtz: PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "",
                       [(set f64:$FRT, (PPCfaddrtz f64:$FRA, f64:$FRB))]>;
 }
 
 // The above pseudo gets expanded to make use of the following instructions
defm SUBFME : XOForm_3rc<31, 232, 0, (outs gprc:$rT), (ins gprc:$rA),
                          "subfme", "$rT, $rA", IIC_IntGeneral,
                          [(set i32:$rT, (sube -1, i32:$rA))]>;
 defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$rT), (ins gprc:$rA),
                          "subfze", "$rT, $rA", IIC_IntGeneral,
                          [(set i32:$rT, (sube 0, i32:$rA))]>;
 }
 }
 
+def : InstAlias<"sub $rA, $rB, $rC", (SUBF gprc:$rA, gprc:$rC, gprc:$rB)>;
+def : InstAlias<"sub. $rA, $rB, $rC", (SUBF_rec gprc:$rA, gprc:$rC, gprc:$rB)>;
+def : InstAlias<"subc $rA, $rB, $rC", (SUBFC gprc:$rA, gprc:$rC, gprc:$rB)>;
+def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC_rec gprc:$rA, gprc:$rC, gprc:$rB)>;
+
 // A-Form instructions.  Most of the instructions executed in the FPU are of
 // this type.
 //
 let PPC970_Unit = 3, hasSideEffects = 0, Predicates = [HasFPU] in {  // FPU Operations.
 let Uses = [RM] in {
 let isCommutable = 1 in {
   defm FMADD : AForm_1r<63, 29, 
                       (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
def CLRRWI : PPCAsmPseudo<"clrrwi $rA, $rS, $n",
                           (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
 def CLRRWI_rec : PPCAsmPseudo<"clrrwi. $rA, $rS, $n",
                            (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
 def CLRLSLWI : PPCAsmPseudo<"clrlslwi $rA, $rS, $b, $n",
                             (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
 def CLRLSLWI_rec : PPCAsmPseudo<"clrlslwi. $rA, $rS, $b, $n",
                              (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
 
+def : InstAlias<"isellt $rT, $rA, $rB",
+                (ISEL gprc:$rT, gprc_nor0:$rA, gprc:$rB, CR0LT)>;
+def : InstAlias<"iselgt $rT, $rA, $rB",
+                (ISEL gprc:$rT, gprc_nor0:$rA, gprc:$rB, CR0GT)>;
+def : InstAlias<"iseleq $rT, $rA, $rB",
+                (ISEL gprc:$rT, gprc_nor0:$rA, gprc:$rB, CR0EQ)>;
+
 def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
 def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINM_rec gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
 def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
 def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNM_rec gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
 def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
 def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINM_rec gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
 
 def : InstAlias<"cntlzw $rA, $rS", (CNTLZW gprc:$rA, gprc:$rS)>;
def CLRRDI_rec : PPCAsmPseudo<"clrrdi. $rA, $rS, $n",
                            (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
 def CLRLSLDI : PPCAsmPseudo<"clrlsldi $rA, $rS, $b, $n",
                             (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
 def CLRLSLDI_rec : PPCAsmPseudo<"clrlsldi. $rA, $rS, $b, $n",
                              (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
 def SUBPCIS : PPCAsmPseudo<"subpcis $RT, $D", (ins g8rc:$RT, s16imm:$D)>;
 
 def : InstAlias<"rotldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
+def : InstAlias<"rotldi $rA, $rS, $n",
+                (RLDICL_32_64 g8rc:$rA, gprc:$rS, u6imm:$n, 0)>;
 def : InstAlias<"rotldi. $rA, $rS, $n", (RLDICL_rec g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
 def : InstAlias<"rotld $rA, $rS, $rB", (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
 def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCL_rec g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
 def : InstAlias<"clrldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
 def : InstAlias<"clrldi $rA, $rS, $n",
                 (RLDICL_32_64 g8rc:$rA, gprc:$rS, 0, u6imm:$n)>;
 def : InstAlias<"clrldi. $rA, $rS, $n", (RLDICL_rec g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
 def : InstAlias<"lnia $RT", (ADDPCIS g8rc:$RT, 0)>;

 def : InstAlias<"cmp $bf, 0, $rA, $rB", (CMPW crrc:$bf, gprc:$rA, gprc:$rB)>;
 def : InstAlias<"cmpli $bf, 0, $rA, $imm", (CMPLWI crrc:$bf, gprc:$rA, u16imm:$imm)>;
 def : InstAlias<"cmpl $bf, 0, $rA, $rB", (CMPLW crrc:$bf, gprc:$rA, gprc:$rB)>;
 def : InstAlias<"cmpi $bf, 1, $rA, $imm", (CMPDI crrc:$bf, g8rc:$rA, s16imm64:$imm)>;
 def : InstAlias<"cmp $bf, 1, $rA, $rB", (CMPD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
 def : InstAlias<"cmpli $bf, 1, $rA, $imm", (CMPLDI crrc:$bf, g8rc:$rA, u16imm64:$imm)>;
 def : InstAlias<"cmpl $bf, 1, $rA, $rB", (CMPLD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
 
+def : InstAlias<"trap", (TW 31, R0, R0)>;
+
 multiclass TrapExtendedMnemonic<string name, int to> {
   def : InstAlias<"td"#name#"i $rA, $imm", (TDI to, g8rc:$rA, s16imm:$imm)>;
   def : InstAlias<"td"#name#" $rA, $rB", (TD to, g8rc:$rA, g8rc:$rB)>;
   def : InstAlias<"tw"#name#"i $rA, $imm", (TWI to, gprc:$rA, s16imm:$imm)>;
   def : InstAlias<"tw"#name#" $rA, $rB", (TW to, gprc:$rA, gprc:$rB)>;
 }
 defm : TrapExtendedMnemonic<"lt", 16>;
 defm : TrapExtendedMnemonic<"le", 20>;

llvm/test/CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll

 ; RUN: llc -verify-machineinstrs < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs < %s -regalloc=fast -optimize-regalloc=0 | FileCheck %s
 ; The first argument of subfc must not be the same as any other register.
 
 ; CHECK: APP
-; CHECK: subfc [[REG:[0-9]+]],
+; CHECK: subc [[REG:[0-9]+]],
 ; CHECK-NOT: [[REG]]
 ; CHECK: NO_APP
 ; PR1357
 
 ;target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
 target triple = "powerpc-unknown-linux-gnu"
 
 ;long long test(int A, int B, int C) {

llvm/test/CodeGen/PowerPC/2009-09-18-carrybit.ll

 ; RUN: llc -verify-machineinstrs < %s | FileCheck %s
 ; ModuleID = '<stdin>'
 target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
 target triple = "powerpc-unknown-linux-gnu.6"
 
 define i64 @foo(i64 %r.0.ph, i64 %q.0.ph, i32 %sr1.1.ph) nounwind {
 entry:
 ; CHECK-LABEL: foo:
-; CHECK: subfc
+; CHECK: subc
 ; CHECK: subfe
-; CHECK: subfc
+; CHECK: subc
 ; CHECK: subfe
   %tmp0 = add i64 %r.0.ph, -1                           ; <i64> [#uses=1]
   br label %bb40
 
 bb40:                                             ; preds = %bb40, %entry
   %indvar = phi i32 [ 0, %entry ], [ %indvar.next, %bb40 ] ; <i32> [#uses=1]
   %carry.0274 = phi i32 [ 0, %entry ], [%tmp122, %bb40 ] ; <i32> [#uses=1]
   %r.0273 = phi i64 [ %r.0.ph, %entry ], [ %tmp124, %bb40 ] ; <i64> [#uses=2]

llvm/test/CodeGen/PowerPC/2010-02-12-saveCR.ll

 ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu -break-anti-dependencies=none | FileCheck %s
 ; ModuleID = 'hh.c'
 ;;;;; target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128-n32"
 target triple = "powerpc-unknown-linux-gnu.6"
 
 define void @foo() nounwind {
 entry:
 ; Note that part of what is being checked here is proper register reuse.
 ; CHECK: mfcr [[T1:[0-9]+]]
-; CHECK-DAG: subf 0, 0, 1
+; CHECK-DAG: sub 0, 1, 0
 ; CHECK-DAG: ori [[T2:[0-9]+]], [[T2]], 34492
 ; CHECK-DAG: stwx [[T1]], 1, [[T2]]
 ; CHECK-DAG: addi 3, 1, 28
 ; CHECK: bl bar
   %x = alloca [100000 x i8]                       ; <[100000 x i8]*> [#uses=1]
   %"alloca point" = bitcast i32 0 to i32          ; <i32> [#uses=0]
   %x1 = bitcast [100000 x i8]* %x to i8*          ; <i8*> [#uses=1]
   call void @bar(i8* %x1) nounwind

llvm/test/CodeGen/PowerPC/CompareEliminationSpillIssue.ll

entry:
   %sub = sub nsw i32 %add, %c
   %conv = sext i32 %sub to i64
   tail call void @call(i64 %conv)
   tail call void asm sideeffect "#Do Nothing", "~{r0},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15},~{r16},~{r17},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29},~{r30},~{r31}"()
   %cmp = icmp sle i32 %add, %c
   %conv1 = zext i1 %cmp to i32
   ret i32 %conv1
 ; CHECK-LABEL: test
-; CHECK: subf r3,
+; CHECK: sub r3,
 ; CHECK: extsw r3,
 ; CHECK: bl call
 ; CHECK: sub r3,
 ; CHECK: rldicl r3, r3, 1, 63
 ; CHECK: std r3, [[OFF:[0-9]+]](r1)
 ; CHECK: #APP
 ; CHECK: ld r3, [[OFF]](r1)
 ; CHECK: xori r3, r3, 1

llvm/test/CodeGen/PowerPC/atomics-regression.ll

; PPC64LE-NEXT:    blr
   ret i64 %ret
 }
 
 define i8 @test160(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test160:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB160_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB160_1
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i8* %ptr, i8 %val monotonic
   ret i8 %ret
 }
 
 define i8 @test161(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test161:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB161_1:
 ; PPC64LE-NEXT:    lbarx 3, 0, 5
-; PPC64LE-NEXT:    subf 6, 4, 3
+; PPC64LE-NEXT:    sub 6, 3, 4
 ; PPC64LE-NEXT:    stbcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB161_1
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i8* %ptr, i8 %val acquire
   ret i8 %ret
 }
 
 define i8 @test162(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test162:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB162_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB162_1
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i8* %ptr, i8 %val release
   ret i8 %ret
 }
 
 define i8 @test163(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test163:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB163_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB163_1
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i8* %ptr, i8 %val acq_rel
   ret i8 %ret
 }
 
 define i8 @test164(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test164:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB164_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB164_1
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i8* %ptr, i8 %val seq_cst
   ret i8 %ret
 }
 
 define i16 @test165(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test165:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB165_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB165_1
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i16* %ptr, i16 %val monotonic
   ret i16 %ret
 }
 
 define i16 @test166(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test166:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB166_1:
 ; PPC64LE-NEXT:    lharx 3, 0, 5
-; PPC64LE-NEXT:    subf 6, 4, 3
+; PPC64LE-NEXT:    sub 6, 3, 4
 ; PPC64LE-NEXT:    sthcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB166_1
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i16* %ptr, i16 %val acquire
   ret i16 %ret
 }
 
 define i16 @test167(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test167:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB167_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB167_1
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i16* %ptr, i16 %val release
   ret i16 %ret
 }
 
 define i16 @test168(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test168:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB168_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB168_1
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i16* %ptr, i16 %val acq_rel
   ret i16 %ret
 }
 
 define i16 @test169(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test169:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB169_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB169_1
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i16* %ptr, i16 %val seq_cst
   ret i16 %ret
 }
 
 define i32 @test170(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test170:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB170_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB170_1
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i32* %ptr, i32 %val monotonic
   ret i32 %ret
 }
 
 define i32 @test171(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test171:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB171_1:
 ; PPC64LE-NEXT:    lwarx 3, 0, 5
-; PPC64LE-NEXT:    subf 6, 4, 3
+; PPC64LE-NEXT:    sub 6, 3, 4
 ; PPC64LE-NEXT:    stwcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB171_1
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i32* %ptr, i32 %val acquire
   ret i32 %ret
 }
 
 define i32 @test172(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test172:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB172_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB172_1
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i32* %ptr, i32 %val release
   ret i32 %ret
 }
 
 define i32 @test173(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test173:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB173_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB173_1
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i32* %ptr, i32 %val acq_rel
   ret i32 %ret
 }
 
 define i32 @test174(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test174:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB174_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB174_1
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i32* %ptr, i32 %val seq_cst
   ret i32 %ret
; PPC64LE-NEXT:    blr
   ret i64 %ret
 }
 
 define i8 @test380(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test380:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB380_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB380_1
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i8* %ptr, i8 %val syncscope("singlethread") monotonic
   ret i8 %ret
 }
 
 define i8 @test381(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test381:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB381_1:
 ; PPC64LE-NEXT:    lbarx 3, 0, 5
-; PPC64LE-NEXT:    subf 6, 4, 3
+; PPC64LE-NEXT:    sub 6, 3, 4
 ; PPC64LE-NEXT:    stbcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB381_1
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i8* %ptr, i8 %val syncscope("singlethread") acquire
   ret i8 %ret
 }
 
 define i8 @test382(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test382:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB382_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB382_1
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i8* %ptr, i8 %val syncscope("singlethread") release
   ret i8 %ret
 }
 
 define i8 @test383(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test383:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB383_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB383_1
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i8* %ptr, i8 %val syncscope("singlethread") acq_rel
   ret i8 %ret
 }
 
 define i8 @test384(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test384:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB384_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB384_1
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i8* %ptr, i8 %val syncscope("singlethread") seq_cst
   ret i8 %ret
 }
 
 define i16 @test385(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test385:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB385_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB385_1
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i16* %ptr, i16 %val syncscope("singlethread") monotonic
   ret i16 %ret
 }
 
 define i16 @test386(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test386:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB386_1:
 ; PPC64LE-NEXT:    lharx 3, 0, 5
-; PPC64LE-NEXT:    subf 6, 4, 3
+; PPC64LE-NEXT:    sub 6, 3, 4
 ; PPC64LE-NEXT:    sthcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB386_1
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i16* %ptr, i16 %val syncscope("singlethread") acquire
   ret i16 %ret
 }
 
 define i16 @test387(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test387:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB387_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB387_1
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i16* %ptr, i16 %val syncscope("singlethread") release
   ret i16 %ret
 }
 
 define i16 @test388(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test388:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB388_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB388_1
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i16* %ptr, i16 %val syncscope("singlethread") acq_rel
   ret i16 %ret
 }
 
 define i16 @test389(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test389:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB389_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB389_1
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i16* %ptr, i16 %val syncscope("singlethread") seq_cst
   ret i16 %ret
 }
 
 define i32 @test390(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test390:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB390_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB390_1
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i32* %ptr, i32 %val syncscope("singlethread") monotonic
   ret i32 %ret
 }
 
 define i32 @test391(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test391:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB391_1:
 ; PPC64LE-NEXT:    lwarx 3, 0, 5
-; PPC64LE-NEXT:    subf 6, 4, 3
+; PPC64LE-NEXT:    sub 6, 3, 4
 ; PPC64LE-NEXT:    stwcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB391_1
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i32* %ptr, i32 %val syncscope("singlethread") acquire
   ret i32 %ret
 }
 
 define i32 @test392(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test392:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB392_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB392_1
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i32* %ptr, i32 %val syncscope("singlethread") release
   ret i32 %ret
 }
 
 define i32 @test393(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test393:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB393_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB393_1
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i32* %ptr, i32 %val syncscope("singlethread") acq_rel
   ret i32 %ret
 }
 
 define i32 @test394(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test394:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB394_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB394_1
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw sub i32* %ptr, i32 %val syncscope("singlethread") seq_cst
   ret i32 %ret

llvm/test/CodeGen/PowerPC/crbits.ll

 ; CHECK: crnor
 ; CHECK: crnor
 ; CHECK: crnand [[REG4:[0-9]+]],
 ; CHECK: isel 3, 0, [[REG1]], [[REG4]]
 ; CHECK-NO-ISEL-LABEL: @test1
 ; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
 ; CHECK-NO-ISEL-NEXT: blr
 ; CHECK-NO-ISEL-NEXT: [[TRUE]]
-; CHECK-NO-ISEL-NEXT: addi 3, 0, 0
+; CHECK-NO-ISEL-NEXT: li 3, 0
 ; CHECK-NO-ISEL-NEXT: blr
 ; CHECK: blr
 }
 
 ; Function Attrs: nounwind readnone
 define zeroext i1 @test2(float %v1, float %v2) #0 {
 entry:
   %cmp = fcmp oge float %v1, %v2

 ; Function Attrs: nounwind readnone
 define signext i32 @test7(i1 zeroext %v2, i32 signext %i1, i32 signext %i2) #0 {
 entry:
   %cond = select i1 %v2, i32 %i1, i32 %i2
   ret i32 %cond
 
 ; CHECK-LABEL: @test7
 ; CHECK: andi. {{[0-9]+}}, 3, 1
-; CHECK: isel 3, 4, 5, 1
+; CHECK: iselgt 3, 4, 5
 ; CHECK: blr
 }
 
 define signext i32 @exttest7(i32 signext %a) #0 {
 entry:
   %cmp = icmp eq i32 %a, 5
   %cond = select i1 %cmp, i32 7, i32 8
   ret i32 %cond
 
 ; CHECK-LABEL: @exttest7
 ; CHECK-DAG: cmpwi 3, 5
 ; CHECK-DAG: li [[REG1:[0-9]+]], 8
 ; CHECK-DAG: li [[REG2:[0-9]+]], 7
-; CHECK: isel 3, [[REG2]], [[REG1]],
+; CHECK: iseleq 3, [[REG2]], [[REG1]]
 ; CHECK-NOT: rldicl
 ; CHECK: blr
 }
 
 define zeroext i32 @exttest8() #0 {
 entry:
   %v0 = load i64, i64* undef, align 8
   %sub = sub i64 80, %v0

llvm/test/CodeGen/PowerPC/eqv-andc-orc-nor.ll

 ; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | \
 ; RUN:   grep eqv | count 3
 ; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=g5 | \
 ; RUN:   grep andc | count 3
 ; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | \
 ; RUN:   grep orc | count 2
 ; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=g5 | \
-; RUN:   grep nor | count 3
+; RUN:   grep nor | count 2
 ; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | \
 ; RUN:   grep nand | count 1
 
 define i32 @EQV1(i32 %X, i32 %Y) nounwind {
   %A = xor i32 %X, %Y   ; <i32> [#uses=1]
   %B = xor i32 %A, -1   ; <i32> [#uses=1]
   ret i32 %B
 }

llvm/test/CodeGen/PowerPC/expand-contiguous-isel.ll

_ZNK4llvm9StringRef6substrEmm.exit:
   %BracketDepth.1 = phi i64 [ %dec, %if.end10 ], [ 0, %_ZNK4llvm9StringRef6substrEmm.exit.loopexit ], [ %BracketDepth.0.ph, %_ZNK4llvm9StringRef6substrEmm.exit.loopexit132 ]
   %sub.i = add i64 %.sink76, -1
   %add.ptr.i = getelementptr inbounds i8, i8* %7, i64 1
   %8 = ptrtoint i8* %add.ptr.i to i64
   br label %while.cond.outer
 
 ; CHECK-LABEL: @_Z3fn1N4llvm9StringRefE
 ; Unecessary ISEL (all the registers are the same) is always removed
-; CHECK-GEN-ISEL-TRUE-NOT: isel [[SAME:r[0-9]+]], [[SAME]], [[SAME]]
-; CHECK-GEN-ISEL-TRUE: isel [[SAME:r[0-9]+]], {{r[0-9]+}}, [[SAME]]
+; CHECK-GEN-ISEL-TRUE-NOT: iseleq [[SAME:r[0-9]+]], [[SAME]], [[SAME]]
+; CHECK-GEN-ISEL-TRUE: iseleq [[SAME:r[0-9]+]], {{r[0-9]+}}, [[SAME]]
 ; CHECK: bc 12, eq, [[TRUE:.LBB[0-9]+]]
 ; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
 ; CHECK-NEXT: [[TRUE]]
 ; CHECK-NEXT: # in Loop: Header
 ; CHECK-NEXT: addi {{r[0-9]+}}, {{r[0-9]+}}, 0
 ; CHECK-NEXT: [[SUCCESSOR]]
 }
 
 
 
 declare void @exit(i32 signext)
 declare signext i32 @memcmp(i8* nocapture, i8* nocapture, i64)
 declare void @__assert_fail(i8*, i8*, i32 zeroext, i8*)

llvm/test/CodeGen/PowerPC/expand-isel.ll

 ; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]]
 ; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
 ; CHECK-NEXT:  [[TRUE]]
 ; CHECK-NEXT: addi r4, r3, 0
 ; CHECK-NEXT: addi r6, r5, 0
 ; CHECK-NEXT:  [[SUCCESSOR]]
 ; CHECK-NEXT: add r4, r4, r6
 ; CHECK-NEXT: add r3, r3, r4
-; CHECK-NEXT: subf r3, r5, r3
+; CHECK-NEXT: sub r3, r3, r5
 ; CHECK-NEXT: extsw r3, r3
 ; CHECK-NEXT: blr
 }
 
 
 @b = local_unnamed_addr global i32 0, align 4
 @a = local_unnamed_addr global i32 0, align 4
 ; Function Attrs: norecurse nounwind readonly

llvm/test/CodeGen/PowerPC/f128-compare.ll

 entry:
   %0 = load fp128, fp128* @a_qp, align 16
   %1 = load fp128, fp128* @b_qp, align 16
   %cmp = fcmp ogt fp128 %0, %1
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 ; CHECK-LABEL: greater_qp
 ; CHECK: xscmpuqp
-; CHECK: isel r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, gt
+; CHECK: iselgt r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}
 ; CHECK: blr
 }
 
 ; Function Attrs: noinline nounwind optnone
 define signext i32 @less_qp() {
 entry:
   %0 = load fp128, fp128* @a_qp, align 16
   %1 = load fp128, fp128* @b_qp, align 16
   %cmp = fcmp olt fp128 %0, %1
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 ; CHECK-LABEL: less_qp
 ; CHECK: xscmpuqp
-; CHECK: isel r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, lt
+; CHECK: isellt r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}
 ; CHECK: blr
 }
 
 ; Function Attrs: noinline nounwind optnone
 define signext i32 @greater_eq_qp() {
 entry:
   %0 = load fp128, fp128* @a_qp, align 16
   %1 = load fp128, fp128* @b_qp, align 16

 entry:
   %0 = load fp128, fp128* @a_qp, align 16
   %1 = load fp128, fp128* @b_qp, align 16
   %cmp = fcmp oeq fp128 %0, %1
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 ; CHECK-LABEL: equal_qp
 ; CHECK: xscmpuqp
-; CHECK: isel r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, eq
+; CHECK: iseleq r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}
 ; CHECK: blr
 }
 
 ; Function Attrs: noinline nounwind optnone
 define signext i32 @not_greater_qp() {
 entry:
   %0 = load fp128, fp128* @a_qp, align 16
   %1 = load fp128, fp128* @b_qp, align 16
   %cmp = fcmp ogt fp128 %0, %1
   %lnot = xor i1 %cmp, true
   %lnot.ext = zext i1 %lnot to i32
   ret i32 %lnot.ext
 ; CHECK-LABEL: not_greater_qp
 ; CHECK: xscmpuqp
-; CHECK: isel r{{[0-9]+}}, 0, r{{[0-9]+}}, gt
+; CHECK: iselgt r{{[0-9]+}}, 0, r{{[0-9]+}}
 ; CHECK: blr
 }
 
 ; Function Attrs: noinline nounwind optnone
 define signext i32 @not_less_qp() {
 entry:
   %0 = load fp128, fp128* @a_qp, align 16
   %1 = load fp128, fp128* @b_qp, align 16
   %cmp = fcmp olt fp128 %0, %1
   %lnot = xor i1 %cmp, true
   %lnot.ext = zext i1 %lnot to i32
   ret i32 %lnot.ext
 ; CHECK-LABEL: not_less_qp
 ; CHECK: xscmpuqp
-; CHECK: isel r{{[0-9]+}}, 0, r{{[0-9]+}}, lt
+; CHECK: isellt r{{[0-9]+}}, 0, r{{[0-9]+}}
 ; CHECK: blr
 }
 
 ; Function Attrs: noinline nounwind optnone
 define signext i32 @not_greater_eq_qp() {
 entry:
   %0 = load fp128, fp128* @a_qp, align 16
   %1 = load fp128, fp128* @b_qp, align 16

 entry:
   %0 = load fp128, fp128* @a_qp, align 16
   %1 = load fp128, fp128* @b_qp, align 16
   %cmp = fcmp une fp128 %0, %1
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 ; CHECK-LABEL: not_equal_qp
 ; CHECK: xscmpuqp
-; CHECK: isel r{{[0-9]+}}, 0, r{{[0-9]+}}, eq
+; CHECK: iseleq r{{[0-9]+}}, 0, r{{[0-9]+}}
 ; CHECK: blr
 }
 
 ; Function Attrs: norecurse nounwind readonly
 define fp128 @greater_sel_qp() {
 entry:
   %0 = load fp128, fp128* @a_qp, align 16
   %1 = load fp128, fp128* @b_qp, align 16

llvm/test/CodeGen/PowerPC/fast-isel-binary.ll

 
 ; Test sub with non-legal types
 
 define void @sub_i8(i8 %a, i8 %b) nounwind {
 entry:
 ; ELF64: sub_i8
   %a.addr = alloca i8, align 4
   %0 = sub i8 %a, %b
-; ELF64: subf
+; ELF64: sub
   store i8 %0, i8* %a.addr, align 4
   ret void
 }
 
 define void @sub_i8_imm(i8 %a) nounwind {
 entry:
 ; ELF64: sub_i8_imm
   %a.addr = alloca i8, align 4
   %0 = sub i8 %a, 22;
 ; ELF64: addi
   store i8 %0, i8* %a.addr, align 4
   ret void
 }
 
 define void @sub_i16(i16 %a, i16 %b) nounwind {
 entry:
 ; ELF64: sub_i16
   %a.addr = alloca i16, align 4
   %0 = sub i16 %a, %b
-; ELF64: subf
+; ELF64: sub
   store i16 %0, i16* %a.addr, align 4
   ret void
 }
 
 define void @sub_i16_imm(i16 %a) nounwind {
 entry:
 ; ELF64: sub_i16_imm
   %a.addr = alloca i16, align 4
   %0 = sub i16 %a, 247;
 ; ELF64: addi
   store i16 %0, i16* %a.addr, align 4
   ret void
 }
 
 define void @sub_i16_badimm(i16 %a) nounwind {
 entry:
 ; ELF64: sub_i16_imm
   %a.addr = alloca i16, align 4
   %0 = sub i16 %a, -32768;
-; ELF64: subf
+; ELF64: sub
   store i16 %0, i16* %a.addr, align 4
   ret void
 }

llvm/test/CodeGen/PowerPC/fold-remove-li.ll

 ; NOTE: This test verifies that a redundant load immediate of zero is folded
 ; NOTE: from its use in an isel and deleted as it is no longer in use.
 ; RUN:  llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN:      -ppc-asm-full-reg-names -verify-machineinstrs < %s | FileCheck %s
 ; RUN:  llc -mcpu=pwr9 -mtriple=powerpc64-unknown-linux-gnu \
 ; RUN:      -ppc-asm-full-reg-names -verify-machineinstrs < %s | FileCheck %s
 
 %0 = type { i32, i16 }
 
 @val = common dso_local local_unnamed_addr global %0* null, align 8
 
 define dso_local signext i32 @redunLoadImm(%0* %arg) {
 ; CHECK-LABEL: redunLoadImm:
 ; verify that the load immediate has been folded into the isel and deleted
 ; CHECK-NOT:   li r[[REG1:[0-9]+]], 0
-; CHECK:       isel r[[REG2:[0-9]+]], 0, r[[REG3:[0-9]+]], eq
+; CHECK:       iseleq r[[REG2:[0-9]+]], 0, r[[REG3:[0-9]+]]
 
 bb:
   %tmp = icmp eq %0* %arg, null
   br i1 %tmp, label %bb9, label %bb1
 
 bb1:                                              ; preds = %bb
   %tmp2 = getelementptr inbounds %0, %0* %arg, i64 0, i32 1
   br label %bb3

llvm/test/CodeGen/PowerPC/fold-zero.ll

 ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-crbits | FileCheck %s
 ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck --check-prefix=CHECK-CRB %s
 ; RUN: llc -verify-machineinstrs -ppc-gen-isel=false < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck --check-prefix=CHECK-NO-ISEL %s
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
 define i32 @test1(i1 %a, i32 %c) nounwind  {
   %x = select i1 %a, i32 %c, i32 0
   ret i32 %x
 
 ; CHECK-LABEL: @test1
 ; CHECK-NOT: li {{[0-9]+}}, 0
-; CHECK: isel 3, 0,
+; CHECK: iseleq 3, 0,
 ; CHECK: blr
 ; CHECK-NO-ISEL-LABEL: @test1
 ; CHECK-NO-ISEL: li 3, 0
 ; CHECK-NO-ISEL-NEXT: bc 12, 1, [[TRUE:.LBB[0-9]+]]
 ; CHECK-NO-ISEL-NEXT: blr
 ; CHECK-NO-ISEL-NEXT: [[TRUE]]
 ; CHECK-NO-ISEL-NEXT: addi 3, 4, 0
 ; CHECK-NO-ISEL-NEXT: blr
 }
 
 define i32 @test2(i1 %a, i32 %c) nounwind  {
   %x = select i1 %a, i32 0, i32 %c
   ret i32 %x
 
 ; CHECK-CRB-LABEL: @test2
 ; CHECK-CRB-NOT: li {{[0-9]+}}, 0
-; CHECK-CRB: isel 3, 0,
+; CHECK-CRB: iselgt 3, 0,
 ; CHECK-CRB: blr
 ; CHECK-NO-ISEL-LABEL: @test2
 ; CHECK-NO-ISEL: bc 12, 1, [[TRUE:.LBB[0-9]+]]
 ; CHECK-NO-ISEL: ori 3, 4, 0
 ; CHECK-NO-ISEL-NEXT: blr
 ; CHECK-NO-ISEL-NEXT: [[TRUE]]
-; CHECK-NO-ISEL-NEXT: addi 3, 0, 0
+; CHECK-NO-ISEL-NEXT: li 3, 0
 ; CHECK-NO-ISEL-NEXT: blr
 }
 

llvm/test/CodeGen/PowerPC/funnel-shift.ll

 define i32 @fshl_i32(i32 %x, i32 %y, i32 %z) {
 ; CHECK-LABEL: fshl_i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    andi. 5, 5, 31
 ; CHECK-NEXT:    subfic 6, 5, 32
 ; CHECK-NEXT:    slw 5, 3, 5
 ; CHECK-NEXT:    srw 4, 4, 6
 ; CHECK-NEXT:    or 4, 5, 4
-; CHECK-NEXT:    isel 3, 3, 4, 2
+; CHECK-NEXT:    iseleq 3, 3, 4
 ; CHECK-NEXT:    blr
   %f = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 %z)
   ret i32 %f
 }
 
 ; Verify that weird types are minimally supported.
 declare i37 @llvm.fshl.i37(i37, i37, i37)
 define i37 @fshl_i37(i37 %x, i37 %y, i37 %z) {

 ; CHECK-NEXT:    mulhdu 6, 5, 6
 ; CHECK-NEXT:    rldicl 6, 6, 59, 5
 ; CHECK-NEXT:    mulli 6, 6, 37
 ; CHECK-NEXT:    sub. 5, 5, 6
 ; CHECK-NEXT:    subfic 6, 5, 37
 ; CHECK-NEXT:    sld 5, 3, 5
 ; CHECK-NEXT:    srd 4, 4, 6
 ; CHECK-NEXT:    or 4, 5, 4
-; CHECK-NEXT:    isel 3, 3, 4, 2
+; CHECK-NEXT:    iseleq 3, 3, 4
 ; CHECK-NEXT:    blr
   %f = call i37 @llvm.fshl.i37(i37 %x, i37 %y, i37 %z)
   ret i37 %f
 }
 
 ; extract(concat(0b1110000, 0b1111111) << 2) = 0b1000011
 
 declare i7 @llvm.fshl.i7(i7, i7, i7)

 define i32 @fshr_i32(i32 %x, i32 %y, i32 %z) {
 ; CHECK-LABEL: fshr_i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    andi. 5, 5, 31
 ; CHECK-NEXT:    subfic 6, 5, 32
 ; CHECK-NEXT:    srw 5, 4, 5
 ; CHECK-NEXT:    slw 3, 3, 6
 ; CHECK-NEXT:    or 3, 3, 5
-; CHECK-NEXT:    isel 3, 4, 3, 2
+; CHECK-NEXT:    iseleq 3, 4, 3
 ; CHECK-NEXT:    blr
   %f = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 %z)
   ret i32 %f
 }
 
 ; Verify that weird types are minimally supported.
 declare i37 @llvm.fshr.i37(i37, i37, i37)
 define i37 @fshr_i37(i37 %x, i37 %y, i37 %z) {

 ; CHECK-NEXT:    rldicl 6, 6, 59, 5
 ; CHECK-NEXT:    mulli 6, 6, 37
 ; CHECK-NEXT:    sub. 5, 5, 6
 ; CHECK-NEXT:    clrldi 6, 4, 27
 ; CHECK-NEXT:    subfic 7, 5, 37
 ; CHECK-NEXT:    srd 5, 6, 5
 ; CHECK-NEXT:    sld 3, 3, 7
 ; CHECK-NEXT:    or 3, 3, 5
-; CHECK-NEXT:    isel 3, 4, 3, 2
+; CHECK-NEXT:    iseleq 3, 4, 3
 ; CHECK-NEXT:    blr
   %f = call i37 @llvm.fshr.i37(i37 %x, i37 %y, i37 %z)
   ret i37 %f
 }
 
 ; extract(concat(0b1110000, 0b1111111) >> 2) = 0b0011111
 
 declare i7 @llvm.fshr.i7(i7, i7, i7)

llvm/test/CodeGen/PowerPC/handle-f16-storage-type.ll

 ; SOFT-NEXT:    clrldi r3, r3, 48
 ; SOFT-NEXT:    bl __gnu_h2f_ieee
 ; SOFT-NEXT:    nop
 ; SOFT-NEXT:    li r4, 0
 ; SOFT-NEXT:    bl __nesf2
 ; SOFT-NEXT:    nop
 ; SOFT-NEXT:    cmplwi r3, 0
 ; SOFT-NEXT:    lis r3, 16256
-; SOFT-NEXT:    isel r3, 0, r3, eq
+; SOFT-NEXT:    iseleq r3, 0, r3
 ; SOFT-NEXT:    bl __gnu_f2h_ieee
 ; SOFT-NEXT:    nop
 ; SOFT-NEXT:    addi r1, r1, 32
 ; SOFT-NEXT:    ld r0, 16(r1)
 ; SOFT-NEXT:    mtlr r0
 ; SOFT-NEXT:    blr
   %2 = fcmp une half %0, 0xH0000
   %3 = uitofp i1 %2 to half
   ret half %3
 }
 attributes #0 = { nounwind }

llvm/test/CodeGen/PowerPC/htm.ll

 declare i32 @llvm.ppc.tbegin(i32) #1
 
 
 define zeroext i32 @test2() {
 entry:
   %0 = tail call i32 @llvm.ppc.tend(i32 0)
   ret i32 %0
 ; CHECK-LABEL: @test2
-; CHECK: tend. 0
+; CHECK: tend.
 ; CHECK: mfocrf  {{[0-9]+}}, 128
 }
 
 declare i32 @llvm.ppc.tend(i32)
 
 
 define void @test3() {
 entry:

 define void @test4() {
 entry:
   %0 = tail call i32 @llvm.ppc.tendall()
   %1 = tail call i32 @llvm.ppc.tresume()
   %2 = tail call i32 @llvm.ppc.tsuspend()
   %3 = tail call i64 @llvm.ppc.ttest()
   ret void
 ; CHECK-LABEL: @test4
-; CHECK: tend. 1
-; CHECK: tsr.  1
-; CHECK: tsr.  0
+; CHECK: tendall.
+; CHECK: tresume.
+; CHECK: tsuspend.
 ; CHECK: tabortwci. 0, {{[0-9]+}}, 0
 }
 
 declare i32 @llvm.ppc.tendall()
 declare i32 @llvm.ppc.tresume()
 declare i32 @llvm.ppc.tsuspend()
 declare i64 @llvm.ppc.ttest()
 
entry:
   %1 = tail call i32 @llvm.ppc.treclaim(i32 5)
   %2 = tail call i32 @llvm.ppc.trechkpt()
   %3 = tail call i32 @llvm.ppc.tsr(i32 1)
   ret void
 ; CHECK-LABEL: @test10
 ; CHECK: tcheck [[REG1:[0-9]+]] 
 ; CHECK: treclaim. [[REG2:[0-9]+]] 
 ; CHECK: trechkpt. 
-; CHECK: tsr.  1
+; CHECK: tresume.
 }
 
 declare i32 @llvm.ppc.tcheck()
 declare i32 @llvm.ppc.treclaim(i32)
 declare i32 @llvm.ppc.trechkpt()
 declare i32 @llvm.ppc.tsr(i32)
 

llvm/test/CodeGen/PowerPC/i1-ext-fold.ll

entry:
   %shl = shl nuw nsw i32 %conv, 4
   ret i32 %shl
 
 ; CHECK-LABEL: @foo
 ; CHECK-NO-ISEL-LABEL: @foo
 ; CHECK-DAG: cmpw
 ; CHECK-DAG: li [[REG1:[0-9]+]], 0
 ; CHECK-DAG: li [[REG2:[0-9]+]], 16
-; CHECK: isel 3, [[REG2]], [[REG1]],
+; CHECK: isellt 3, [[REG2]], [[REG1]]
 ; CHECK: blr
 
 ; CHECK-NO-ISEL: bclr 12, 0, 0
 ; CHECK-NO-ISEL: ori 3, 5, 0
 ; CHECK-NO-ISEL-NEXT: blr
 }
 
 ; Function Attrs: nounwind readnone
 define signext i32 @foo2(i32 signext %a, i32 signext %b) #0 {
 entry:
   %cmp = icmp slt i32 %a, %b
   %conv = zext i1 %cmp to i32
   %shl = shl nuw nsw i32 %conv, 4
   %add1 = or i32 %shl, 5
   ret i32 %add1
 
 ; CHECK-LABEL: @foo2
 ; CHECK-NO-ISEL-LABEL: @foo2
 ; CHECK-DAG: cmpw
 ; CHECK-DAG: li [[REG1:[0-9]+]], 5
 ; CHECK-DAG: li [[REG2:[0-9]+]], 21
-; CHECK: isel 3, [[REG2]], [[REG1]],
+; CHECK: isellt 3, [[REG2]], [[REG1]]
 ; CHECK: blr
 
 ; CHECK-NO-ISEL: bclr 12, 0, 0
 ; CHECK-NO-ISEL: ori 3, 5, 0
 ; CHECK-NO-ISEL-NEXT: blr
 }
 
 ; Function Attrs: nounwind readnone
 define signext i32 @foo3(i32 signext %a, i32 signext %b) #0 {
 entry:
   %cmp = icmp sle i32 %a, %b
   %conv = zext i1 %cmp to i32
   %shl = shl nuw nsw i32 %conv, 4
   ret i32 %shl
 
 ; CHECK-LABEL: @foo3
 ; CHECK-NO-ISEL-LABEL: @foo3
 ; CHECK-DAG: cmpw
 ; CHECK-DAG: li [[REG1:[0-9]+]], 16
-; CHECK: isel 3, 0, [[REG1]],
+; CHECK: iselgt 3, 0, [[REG1]]
 ; CHECK: blr
 
 ; CHECK-NO-ISEL: bc 12, 1, [[TRUE:.LBB[0-9]+]]
 ; CHECK-NO-ISEL: ori 3, 5, 0
 ; CHECK-NO-ISEL-NEXT: blr
 ; CHECK-NO-ISEL-NEXT: [[TRUE]]
-; CHECK-NO-ISEL-NEXT: addi 3, 0, 0
+; CHECK-NO-ISEL-NEXT: li 3, 0
 ; CHECK-NO-ISEL-NEXT: blr
 }
 
 attributes #0 = { nounwind readnone }
 

llvm/test/CodeGen/PowerPC/i64_fp_round.ll

 ; Note that only parts of the sequence are checked for here, to allow
 ; for minor code generation differences.
 
 ;CHECK-LABEL: test
 ;CHECK-NO-ISEL-LABEL: test
 ; CHECK: sradi [[REG1:[0-9]+]], 3, 53
 ; CHECK: addi [[REG2:[0-9]+]], [[REG1]], 1
 ; CHECK: cmpldi [[REG2]], 1
-; CHECK: isel [[REG3:[0-9]+]], {{[0-9]+}}, 3, 1
+; CHECK: iselgt [[REG3:[0-9]+]], {{[0-9]+}}, 3
 ; CHECK-NO-ISEL: rldicr [[REG2:[0-9]+]], {{[0-9]+}}, 0, 52
 ; CHECK-NO-ISEL: bc 12, 1, [[TRUE:.LBB[0-9]+]]
 ; CHECK-NO-ISEL: b [[SUCCESSOR:.LBB[0-9]+]]
 ; CHECK-NO-ISEL-NEXT: [[TRUE]]
 ; CHECK-NO-ISEL-NEXT: addi {{[0-9]+}}, [[REG2]], 0
 ; CHECK-NO-ISEL-NEXT: [[SUCCESSOR]]
 ; CHECK-NO-ISEL: std {{[0-9]+}}, -{{[0-9]+}}(1)
 ; CHECK: std [[REG3]], -{{[0-9]+}}(1)
 
 
 ; Also check that with -enable-unsafe-fp-math we do not get that extra
 ; code sequence.  Simply verify that there is no "isel" present.
 
 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-fpcvt -enable-unsafe-fp-math < %s | FileCheck %s -check-prefix=CHECK-UNSAFE
 ; CHECK-UNSAFE-NOT: isel
 

llvm/test/CodeGen/PowerPC/ifcvt.ll

 
 cond.false:                                       ; preds = %sw.epilog
   %add37 = add nsw i32 %conv29, %a
   br label %cond.end
 
 ; CHECK-LABEL: @test
 ; CHECK-NO-ISEL-LABEL: @test
 ; CHECK: add [[REG:[0-9]+]], 
-; CHECK: subf [[REG2:[0-9]+]],
-; CHECK: isel {{[0-9]+}}, [[REG]], [[REG2]],
+; CHECK: sub [[REG2:[0-9]+]],
+; CHECK: iselgt {{[0-9]+}}, [[REG]], [[REG2]]
 ; CHECK-NO-ISEL: bc 12, 1, [[TRUE:.LBB[0-9]+]]
 ; CHECK-NO-ISEL-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
 ; CHECK-NO-ISEL: [[TRUE]]
 ; CHECK-NO-ISEL-NEXT: addi 5, 6, 0
 ; CHECK-NO-ISEL: extsh 5, 5
 ; CHECK-NO-ISEL-NEXT: add 3, 3, 5
 ; CHECK-NO-ISEL-NEXT: blr
 

llvm/test/CodeGen/PowerPC/inc-of-add.ll

; PPC64LE-NEXT:    blr
   %t0 = add <4 x i32> %x, <i32 1, i32 1, i32 1, i32 1>
   %t1 = add <4 x i32> %y, %t0
   ret <4 x i32> %t1
 }
 
 define <2 x i64> @vector_i128_i64(<2 x i64> %x, <2 x i64> %y) nounwind {
 ; PPC32-LABEL: vector_i128_i64:
 ; PPC32:       # %bb.0:
-; PPC32-NEXT:    nor 4, 4, 4
-; PPC32-NEXT:    nor 3, 3, 3
-; PPC32-NEXT:    subfc 4, 4, 8
-; PPC32-NEXT:    nor 6, 6, 6
+; PPC32-NEXT:    not 4, 4
+; PPC32-NEXT:    not 3, 3
+; PPC32-NEXT:    subc 4, 8, 4
+; PPC32-NEXT:    not 6, 6
 ; PPC32-NEXT:    subfe 3, 3, 7
-; PPC32-NEXT:    nor 5, 5, 5
-; PPC32-NEXT:    subfc 6, 6, 10
+; PPC32-NEXT:    not 5, 5
+; PPC32-NEXT:    subc 6, 10, 6
 ; PPC32-NEXT:    subfe 5, 5, 9
 ; PPC32-NEXT:    blr
 ;
 ; PPC64BE-LABEL: vector_i128_i64:
 ; PPC64BE:       # %bb.0:
 ; PPC64BE-NEXT:    add 3, 5, 3
 ; PPC64BE-NEXT:    add 4, 6, 4
 ; PPC64BE-NEXT:    addi 3, 3, 1

llvm/test/CodeGen/PowerPC/loop-instr-form-prepare.ll

 ; CHECK-NEXT:    addi r6, r6, 1
 ; CHECK-NEXT:    bdz .LBB6_9
 ; CHECK-NEXT:  .LBB6_4: #
 ; CHECK-NEXT:    lbzu r0, 1(r5)
 ; CHECK-NEXT:    mulhwu r27, r0, r4
 ; CHECK-NEXT:    rlwinm r26, r27, 0, 0, 30
 ; CHECK-NEXT:    srwi r27, r27, 1
 ; CHECK-NEXT:    add r27, r27, r26
-; CHECK-NEXT:    subf r0, r27, r0
+; CHECK-NEXT:    sub r0, r0, r27
 ; CHECK-NEXT:    cmplwi r0, 1
 ; CHECK-NEXT:    beq cr0, .LBB6_2
 ; CHECK-NEXT:  # %bb.5: #
 ; CHECK-NEXT:    clrlwi r0, r0, 24
 ; CHECK-NEXT:    cmplwi r0, 2
 ; CHECK-NEXT:    bne cr0, .LBB6_7
 ; CHECK-NEXT:  # %bb.6: #
 ; CHECK-NEXT:    ldx r0, r6, r9

llvm/test/CodeGen/PowerPC/machine-pre.ll

 ; CHECK-P9-NEXT:    bl bar
 ; CHECK-P9-NEXT:    nop
 ; CHECK-P9-NEXT:    mr r30, r3
 ; CHECK-P9-NEXT:    mulhw r3, r28, r27
 ; CHECK-P9-NEXT:    srwi r4, r3, 31
 ; CHECK-P9-NEXT:    add r3, r3, r4
 ; CHECK-P9-NEXT:    slwi r4, r3, 1
 ; CHECK-P9-NEXT:    add r3, r3, r4
-; CHECK-P9-NEXT:    subf r3, r3, r28
+; CHECK-P9-NEXT:    sub r3, r28, r3
 ; CHECK-P9-NEXT:    cmplwi r3, 1
 ; CHECK-P9-NEXT:    beq cr0, .LBB1_1
 ; CHECK-P9-NEXT:  # %bb.5: # %while.cond
 ; CHECK-P9-NEXT:    #
 ; CHECK-P9-NEXT:    cmplwi r3, 0
 ; CHECK-P9-NEXT:    bne cr0, .LBB1_3
 ; CHECK-P9-NEXT:  # %bb.6: # %sw.bb
 ; CHECK-P9-NEXT:    #

llvm/test/CodeGen/PowerPC/memcmp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-gnu-linux  < %s | FileCheck %s -check-prefix=CHECK
 
 define signext i32 @memcmp8(i32* nocapture readonly %buffer1, i32* nocapture readonly %buffer2) {
 ; CHECK-LABEL: memcmp8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    ldbrx 3, 0, 3
 ; CHECK-NEXT:    ldbrx 4, 0, 4
 ; CHECK-NEXT:    subc 5, 4, 3
 ; CHECK-NEXT:    subfe 5, 4, 4
 ; CHECK-NEXT:    subc 4, 3, 4
 ; CHECK-NEXT:    subfe 3, 3, 3
 ; CHECK-NEXT:    neg 4, 5
 ; CHECK-NEXT:    neg 3, 3
-; CHECK-NEXT:    subf 3, 3, 4
+; CHECK-NEXT:    sub 3, 4, 3
 ; CHECK-NEXT:    extsw 3, 3
 ; CHECK-NEXT:    blr
   %t0 = bitcast i32* %buffer1 to i8*
   %t1 = bitcast i32* %buffer2 to i8*
   %call = tail call signext i32 @memcmp(i8* %t0, i8* %t1, i64 8)
   ret i32 %call
 }
 
 define signext i32 @memcmp4(i32* nocapture readonly %buffer1, i32* nocapture readonly %buffer2) {
 ; CHECK-LABEL: memcmp4:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lwbrx 3, 0, 3
 ; CHECK-NEXT:    lwbrx 4, 0, 4
 ; CHECK-NEXT:    sub 5, 4, 3
 ; CHECK-NEXT:    sub 3, 3, 4
 ; CHECK-NEXT:    rldicl 4, 5, 1, 63
 ; CHECK-NEXT:    rldicl 3, 3, 1, 63
-; CHECK-NEXT:    subf 3, 3, 4
+; CHECK-NEXT:    sub 3, 4, 3
 ; CHECK-NEXT:    extsw 3, 3
 ; CHECK-NEXT:    blr
   %t0 = bitcast i32* %buffer1 to i8*
   %t1 = bitcast i32* %buffer2 to i8*
   %call = tail call signext i32 @memcmp(i8* %t0, i8* %t1, i64 4)
   ret i32 %call
 }
 
 define signext i32 @memcmp2(i32* nocapture readonly %buffer1, i32* nocapture readonly %buffer2) {
 ; CHECK-LABEL: memcmp2:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lhbrx 3, 0, 3
 ; CHECK-NEXT:    lhbrx 4, 0, 4
-; CHECK-NEXT:    subf 3, 4, 3
+; CHECK-NEXT:    sub 3, 3, 4
 ; CHECK-NEXT:    extsw 3, 3
 ; CHECK-NEXT:    blr
   %t0 = bitcast i32* %buffer1 to i8*
   %t1 = bitcast i32* %buffer2 to i8*
   %call = tail call signext i32 @memcmp(i8* %t0, i8* %t1, i64 2)
   ret i32 %call
 }
 
 define signext i32 @memcmp1(i32* nocapture readonly %buffer1, i32* nocapture readonly %buffer2) {
 ; CHECK-LABEL: memcmp1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lbz 3, 0(3)
 ; CHECK-NEXT:    lbz 4, 0(4)
-; CHECK-NEXT:    subf 3, 4, 3
+; CHECK-NEXT:    sub 3, 3, 4
 ; CHECK-NEXT:    extsw 3, 3
 ; CHECK-NEXT:    blr
   %t0 = bitcast i32* %buffer1 to i8*
   %t1 = bitcast i32* %buffer2 to i8*
   %call = tail call signext i32 @memcmp(i8* %t0, i8* %t1, i64 1) #2
   ret i32 %call
 }
 
 declare signext i32 @memcmp(i8*, i8*, i64)

llvm/test/CodeGen/PowerPC/mul-const.ll

 
 define i32 @test3(i32 %a) {
         %tmp.1 = mul nsw i32 %a, 15         ; <i32> [#uses=1]
         ret i32 %tmp.1
 }
 ; CHECK-LABEL: test3:
 ; CHECK-NOT: mul
 ; CHECK: slwi r[[REG1:[0-9]+]], r3, 4
-; CHECK-NEXT: subf r[[REG2:[0-9]+]], r3, r[[REG1]]
+; CHECK-NEXT: sub r[[REG2:[0-9]+]], r[[REG1]], r3
 
 ; negtive constant
 
 define i32 @test4(i32 %a) {
         %tmp.1 = mul nsw i32 %a, -16         ; <i32> [#uses=1]
         ret i32 %tmp.1
 }
 ; CHECK-LABEL: test4:

 
 define i32 @test6(i32 %a) {
         %tmp.1 = mul nsw i32 %a, -15         ; <i32> [#uses=1]
         ret i32 %tmp.1
 }
 ; CHECK-LABEL: test6:
 ; CHECK-NOT: mul
 ; CHECK: slwi r[[REG1:[0-9]+]], r3, 4
-; CHECK-NEXT: subf r[[REG2:[0-9]+]], r[[REG1]], r3
+; CHECK-NEXT: sub r[[REG2:[0-9]+]], r3, r[[REG1]]
 ; CHECK-NOT: neg
 
 ; boundary case
 
 define i32 @test7(i32 %a) {
         %tmp.1 = mul nsw i32 %a, -2147483648 ; <i32> [#uses=1]
         ret i32 %tmp.1
 }
 ; CHECK-LABEL: test7:
 ; CHECK-NOT: mul
 ; CHECK: slwi r[[REG1:[0-9]+]], r3, 31
 
 define i32 @test8(i32 %a) {
         %tmp.1 = mul nsw i32 %a, 2147483647 ; <i32> [#uses=1]
         ret i32 %tmp.1
 }
 ; CHECK-LABEL: test8:
 ; CHECK-NOT: mul
 ; CHECK: slwi r[[REG1:[0-9]+]], r3, 31
-; CHECK-NEXT: subf r[[REG2:[0-9]+]], r3, r[[REG1]]
+; CHECK-NEXT: sub r[[REG2:[0-9]+]], r[[REG1]], r3

llvm/test/CodeGen/PowerPC/noPermuteFormasking.ll

exitBB: ; preds = %for.body.i.i.i.i.i.i.i.prol.loopexit
   ret void
 }
 
 define signext i32 @andis_bot(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: andis_bot:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    andis. 5, 3, 1
 ; CHECK-NEXT:    li 5, 1
-; CHECK-NEXT:    isel 4, 4, 5, 2
+; CHECK-NEXT:    iseleq 4, 4, 5
 ; CHECK-NEXT:    mullw 3, 4, 3
 ; CHECK-NEXT:    extsw 3, 3
 ; CHECK-NEXT:    blr
 entry:
   %and = and i32 %a, 65536
   %tobool = icmp eq i32 %and, 0
   %mul = select i1 %tobool, i32 %b, i32 1
   %cond = mul nsw i32 %mul, %a
   ret i32 %cond
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @andis_mid(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: andis_mid:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    andis. 5, 3, 252
 ; CHECK-NEXT:    li 5, 1
-; CHECK-NEXT:    isel 4, 4, 5, 2
+; CHECK-NEXT:    iseleq 4, 4, 5
 ; CHECK-NEXT:    mullw 3, 4, 3
 ; CHECK-NEXT:    extsw 3, 3
 ; CHECK-NEXT:    blr
 entry:
   %and = and i32 %a, 16515072
   %tobool = icmp eq i32 %and, 0
   %mul = select i1 %tobool, i32 %b, i32 1
   %cond = mul nsw i32 %mul, %a
   ret i32 %cond
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @andis_top(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: andis_top:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    andis. 5, 3, 64512
 ; CHECK-NEXT:    li 5, 1
-; CHECK-NEXT:    isel 4, 4, 5, 2
+; CHECK-NEXT:    iseleq 4, 4, 5
 ; CHECK-NEXT:    mullw 3, 4, 3
 ; CHECK-NEXT:    extsw 3, 3
 ; CHECK-NEXT:    blr
 entry:
   %tobool = icmp ugt i32 %a, 67108863
   %mul = select i1 %tobool, i32 1, i32 %b
   %cond = mul nsw i32 %mul, %a
   ret i32 %cond

llvm/test/CodeGen/PowerPC/optcmp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -ppc-gpr-icmps=all -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 -mattr=-crbits -disable-ppc-cmp-opt=0 | FileCheck %s
 ; RUN: llc -ppc-gpr-icmps=all -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 -mattr=-crbits -disable-ppc-cmp-opt=0 -ppc-gen-isel=false | FileCheck --check-prefix=CHECK-NO-ISEL %s
 
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
 define signext i32 @foo(i32 signext %a, i32 signext %b, i32* nocapture %c) #0 {
 ; CHECK-LABEL: foo:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpw 3, 4
-; CHECK-NEXT:    isel 6, 3, 4, 1
-; CHECK-NEXT:    subf 4, 4, 3
+; CHECK-NEXT:    iselgt 6, 3, 4
+; CHECK-NEXT:    sub 4, 3, 4
 ; CHECK-NEXT:    extsw 3, 6
 ; CHECK-NEXT:    stw 4, 0(5)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-NO-ISEL-LABEL: foo:
 ; CHECK-NO-ISEL:       # %bb.0: # %entry
 ; CHECK-NO-ISEL-NEXT:    cmpw 3, 4
 ; CHECK-NO-ISEL-NEXT:    bc 12, 1, .LBB0_2
 ; CHECK-NO-ISEL-NEXT:  # %bb.1: # %entry
 ; CHECK-NO-ISEL-NEXT:    ori 6, 4, 0
 ; CHECK-NO-ISEL-NEXT:    b .LBB0_3
 ; CHECK-NO-ISEL-NEXT:  .LBB0_2: # %entry
 ; CHECK-NO-ISEL-NEXT:    addi 6, 3, 0
 ; CHECK-NO-ISEL-NEXT:  .LBB0_3: # %entry
-; CHECK-NO-ISEL-NEXT:    subf 4, 4, 3
+; CHECK-NO-ISEL-NEXT:    sub 4, 3, 4
 ; CHECK-NO-ISEL-NEXT:    extsw 3, 6
 ; CHECK-NO-ISEL-NEXT:    stw 4, 0(5)
 ; CHECK-NO-ISEL-NEXT:    blr
 entry:
   %sub = sub nsw i32 %a, %b
   store i32 %sub, i32* %c, align 4
   %cmp = icmp sgt i32 %a, %b
   %cond = select i1 %cmp, i32 %a, i32 %b
   ret i32 %cond
 }
 
 define signext i32 @foo2(i32 signext %a, i32 signext %b, i32* nocapture %c) #0 {
 ; CHECK-LABEL: foo2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    slw 4, 3, 4
 ; CHECK-NEXT:    li 6, 0
 ; CHECK-NEXT:    li 3, 1
 ; CHECK-NEXT:    cmpwi 4, 0
 ; CHECK-NEXT:    stw 4, 0(5)
-; CHECK-NEXT:    isel 3, 3, 6, 1
+; CHECK-NEXT:    iselgt 3, 3, 6
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-NO-ISEL-LABEL: foo2:
 ; CHECK-NO-ISEL:       # %bb.0: # %entry
 ; CHECK-NO-ISEL-NEXT:    slw 4, 3, 4
 ; CHECK-NO-ISEL-NEXT:    li 6, 0
 ; CHECK-NO-ISEL-NEXT:    li 3, 1
 ; CHECK-NO-ISEL-NEXT:    cmpwi 4, 0
entry:
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }
 
 define i64 @fool(i64 %a, i64 %b, i64* nocapture %c) #0 {
 ; CHECK-LABEL: fool:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub. 6, 3, 4
-; CHECK-NEXT:    isel 3, 3, 4, 1
+; CHECK-NEXT:    iselgt 3, 3, 4
 ; CHECK-NEXT:    std 6, 0(5)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-NO-ISEL-LABEL: fool:
 ; CHECK-NO-ISEL:       # %bb.0: # %entry
 ; CHECK-NO-ISEL-NEXT:    sub. 6, 3, 4
 ; CHECK-NO-ISEL-NEXT:    bc 12, 1, .LBB2_2
 ; CHECK-NO-ISEL-NEXT:  # %bb.1: # %entry
entry:
   %cond = select i1 %cmp, i64 %a, i64 %b
   ret i64 %cond
 }
 
 define i64 @foolb(i64 %a, i64 %b, i64* nocapture %c) #0 {
 ; CHECK-LABEL: foolb:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub. 6, 3, 4
-; CHECK-NEXT:    isel 3, 4, 3, 1
+; CHECK-NEXT:    iselgt 3, 4, 3
 ; CHECK-NEXT:    std 6, 0(5)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-NO-ISEL-LABEL: foolb:
 ; CHECK-NO-ISEL:       # %bb.0: # %entry
 ; CHECK-NO-ISEL-NEXT:    sub. 6, 3, 4
 ; CHECK-NO-ISEL-NEXT:    bc 12, 1, .LBB3_1
 ; CHECK-NO-ISEL-NEXT:    b .LBB3_2
entry:
   %cond = select i1 %cmp, i64 %a, i64 %b
   ret i64 %cond
 }
 
 define i64 @foolc(i64 %a, i64 %b, i64* nocapture %c) #0 {
 ; CHECK-LABEL: foolc:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub. 6, 4, 3
-; CHECK-NEXT:    isel 3, 3, 4, 0
+; CHECK-NEXT:    isellt 3, 3, 4
 ; CHECK-NEXT:    std 6, 0(5)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-NO-ISEL-LABEL: foolc:
 ; CHECK-NO-ISEL:       # %bb.0: # %entry
 ; CHECK-NO-ISEL-NEXT:    sub. 6, 4, 3
 ; CHECK-NO-ISEL-NEXT:    bc 12, 0, .LBB4_2
 ; CHECK-NO-ISEL-NEXT:  # %bb.1: # %entry
entry:
   %cond = select i1 %cmp, i64 %a, i64 %b
   ret i64 %cond
 }
 
 define i64 @foold(i64 %a, i64 %b, i64* nocapture %c) #0 {
 ; CHECK-LABEL: foold:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub. 6, 4, 3
-; CHECK-NEXT:    isel 3, 3, 4, 1
+; CHECK-NEXT:    iselgt 3, 3, 4
 ; CHECK-NEXT:    std 6, 0(5)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-NO-ISEL-LABEL: foold:
 ; CHECK-NO-ISEL:       # %bb.0: # %entry
 ; CHECK-NO-ISEL-NEXT:    sub. 6, 4, 3
 ; CHECK-NO-ISEL-NEXT:    bc 12, 1, .LBB5_2
 ; CHECK-NO-ISEL-NEXT:  # %bb.1: # %entry
entry:
   %cond = select i1 %cmp, i64 %a, i64 %b
   ret i64 %cond
 }
 
 define i64 @foold2(i64 %a, i64 %b, i64* nocapture %c) #0 {
 ; CHECK-LABEL: foold2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub. 6, 3, 4
-; CHECK-NEXT:    isel 3, 3, 4, 0
+; CHECK-NEXT:    isellt 3, 3, 4
 ; CHECK-NEXT:    std 6, 0(5)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-NO-ISEL-LABEL: foold2:
 ; CHECK-NO-ISEL:       # %bb.0: # %entry
 ; CHECK-NO-ISEL-NEXT:    sub. 6, 3, 4
 ; CHECK-NO-ISEL-NEXT:    bc 12, 0, .LBB6_2
 ; CHECK-NO-ISEL-NEXT:  # %bb.1: # %entry

 ; CHECK-NEXT:    ori 7, 8, 3855
 ; CHECK-NEXT:    rldicl 8, 6, 60, 4
 ; CHECK-NEXT:    rldimi 7, 7, 32, 0
 ; CHECK-NEXT:    rldimi 9, 9, 32, 0
 ; CHECK-NEXT:    add 6, 6, 8
 ; CHECK-NEXT:    and 6, 6, 7
 ; CHECK-NEXT:    mulld 6, 6, 9
 ; CHECK-NEXT:    rldicl. 6, 6, 8, 56
-; CHECK-NEXT:    isel 3, 3, 4, 1
+; CHECK-NEXT:    iselgt 3, 3, 4
 ; CHECK-NEXT:    std 6, 0(5)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-NO-ISEL-LABEL: fooct:
 ; CHECK-NO-ISEL:       # %bb.0: # %entry
 ; CHECK-NO-ISEL-NEXT:    lis 6, 21845
 ; CHECK-NO-ISEL-NEXT:    sub 7, 3, 4
 ; CHECK-NO-ISEL-NEXT:    ori 6, 6, 21845

llvm/test/CodeGen/PowerPC/optimize-andiso.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
 ; RUN:   -mcpu=pwr8 -ppc-asm-full-reg-names < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN:   -mcpu=pwr8 -ppc-asm-full-reg-names < %s | FileCheck %s
 define float @floatundisf(i64 %a) {
 ; CHECK-LABEL: floatundisf:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xxlxor f1, f1, f1
 ; CHECK-NEXT:    bclr 12, 4*cr5+lt, 0
 ; CHECK-NEXT:  # %bb.1: # %sw.epilog
 ; CHECK-NEXT:    addi r3, r3, 1
 ; CHECK-NEXT:    li r5, 2
 ; CHECK-NEXT:    andis. r4, r3, 1024
 ; CHECK-NEXT:    li r4, 3
-; CHECK-NEXT:    isel r4, r5, r4, eq
+; CHECK-NEXT:    iseleq r4, r5, r4
 ; CHECK-NEXT:    srd r3, r3, r4
 ; CHECK-NEXT:    clrlwi r3, r3, 9
 ; CHECK-NEXT:    mtfprd f0, r3
 ; CHECK-NEXT:    xxsldwi vs0, vs0, vs0, 1
 ; CHECK-NEXT:    xscvspdpn f1, vs0
 ; CHECK-NEXT:    blr
 entry:
   br i1 undef, label %return, label %sw.epilog

llvm/test/CodeGen/PowerPC/pcrel-call-linkage-leaf.ll

 ; make use of R2.
 define dso_local signext i32 @X2IsCallerSaved(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d, i32 signext %e, i32 signext %f, i32 signext %g, i32 signext %h) local_unnamed_addr {
 ; CHECK-ALL-LABEL: X2IsCallerSaved:
 ; CHECK-S:         .localentry X2IsCallerSaved, 1
 ; CHECK-P9-NOT:    .localentry
 ; CHECK-ALL:       # %bb.0: # %entry
 ; CHECK-S-NEXT:    std r29, -24(r1) # 8-byte Folded Spill
 ; CHECK-S-NEXT:    add r11, r4, r3
-; CHECK-S-NEXT:    subf r29, r9, r8
+; CHECK-S-NEXT:    sub r29, r8, r9
 ; CHECK-S-NEXT:    add r9, r10, r9
-; CHECK-S-NEXT:    subf r10, r3, r10
+; CHECK-S-NEXT:    sub r10, r10, r3
 ; CHECK-S-NEXT:    mullw r3, r4, r3
 ; CHECK-S-NEXT:    mullw r3, r3, r11
 ; CHECK-S-NEXT:    mullw r3, r3, r5
-; CHECK-S-NEXT:    subf r12, r5, r4
+; CHECK-S-NEXT:    sub r12, r4, r5
 ; CHECK-S-NEXT:    mullw r3, r3, r6
 ; CHECK-S-NEXT:    add r0, r6, r5
 ; CHECK-S-NEXT:    mullw r3, r3, r12
 ; CHECK-S-NEXT:    mullw r3, r3, r0
 ; CHECK-S-NEXT:    mullw r3, r3, r7
-; CHECK-S-NEXT:    subf r2, r7, r6
+; CHECK-S-NEXT:    sub r2, r6, r7
 ; CHECK-S-NEXT:    mullw r3, r3, r8
 ; CHECK-S-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; CHECK-S-NEXT:    add r30, r8, r7
 ; CHECK-S-NEXT:    mullw r3, r3, r2
 ; CHECK-S-NEXT:    mullw r3, r3, r30
 ; CHECK-S-NEXT:    mullw r3, r3, r29
 ; CHECK-S-NEXT:    mullw r3, r3, r9
 ; CHECK-S-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload

llvm/test/CodeGen/PowerPC/popcnt-zext.ll

 ; FAST-NEXT:    blr
 ;
 ; SLOW-LABEL: zpop_i8_i16:
 ; SLOW:       # %bb.0:
 ; SLOW-NEXT:    clrlwi 5, 3, 24
 ; SLOW-NEXT:    rotlwi 3, 3, 31
 ; SLOW-NEXT:    andi. 3, 3, 85
 ; SLOW-NEXT:    lis 4, 13107
-; SLOW-NEXT:    subf 3, 3, 5
+; SLOW-NEXT:    sub 3, 5, 3
 ; SLOW-NEXT:    ori 4, 4, 13107
 ; SLOW-NEXT:    rotlwi 5, 3, 30
 ; SLOW-NEXT:    and 3, 3, 4
 ; SLOW-NEXT:    andis. 4, 5, 13107
 ; SLOW-NEXT:    andi. 5, 5, 13107
 ; SLOW-NEXT:    or 4, 5, 4
 ; SLOW-NEXT:    add 3, 3, 4
 ; SLOW-NEXT:    lis 5, 3855

 ; FAST-NEXT:    blr
 ;
 ; SLOW-LABEL: popz_i8_i16:
 ; SLOW:       # %bb.0:
 ; SLOW-NEXT:    clrlwi 5, 3, 24
 ; SLOW-NEXT:    rotlwi 3, 3, 31
 ; SLOW-NEXT:    andi. 3, 3, 85
 ; SLOW-NEXT:    lis 4, 13107
-; SLOW-NEXT:    subf 3, 3, 5
+; SLOW-NEXT:    sub 3, 5, 3
 ; SLOW-NEXT:    ori 4, 4, 13107
 ; SLOW-NEXT:    rotlwi 5, 3, 30
 ; SLOW-NEXT:    and 3, 3, 4
 ; SLOW-NEXT:    andis. 4, 5, 13107
 ; SLOW-NEXT:    andi. 5, 5, 13107
 ; SLOW-NEXT:    or 4, 5, 4
 ; SLOW-NEXT:    add 3, 3, 4
 ; SLOW-NEXT:    lis 5, 3855

 ; FAST-NEXT:    blr
 ;
 ; SLOW-LABEL: zpop_i8_i32:
 ; SLOW:       # %bb.0:
 ; SLOW-NEXT:    clrlwi 5, 3, 24
 ; SLOW-NEXT:    rotlwi 3, 3, 31
 ; SLOW-NEXT:    andi. 3, 3, 85
 ; SLOW-NEXT:    lis 4, 13107
-; SLOW-NEXT:    subf 3, 3, 5
+; SLOW-NEXT:    sub 3, 5, 3
 ; SLOW-NEXT:    ori 4, 4, 13107
 ; SLOW-NEXT:    rotlwi 5, 3, 30
 ; SLOW-NEXT:    and 3, 3, 4
 ; SLOW-NEXT:    andis. 4, 5, 13107
 ; SLOW-NEXT:    andi. 5, 5, 13107
 ; SLOW-NEXT:    or 4, 5, 4
 ; SLOW-NEXT:    add 3, 3, 4
 ; SLOW-NEXT:    lis 5, 3855

 ; FAST-NEXT:    blr
 ;
 ; SLOW-LABEL: popz_i8_32:
 ; SLOW:       # %bb.0:
 ; SLOW-NEXT:    clrlwi 5, 3, 24
 ; SLOW-NEXT:    rotlwi 3, 3, 31
 ; SLOW-NEXT:    andi. 3, 3, 85
 ; SLOW-NEXT:    lis 4, 13107
-; SLOW-NEXT:    subf 3, 3, 5
+; SLOW-NEXT:    sub 3, 5, 3
 ; SLOW-NEXT:    ori 4, 4, 13107
 ; SLOW-NEXT:    rotlwi 5, 3, 30
 ; SLOW-NEXT:    and 3, 3, 4
 ; SLOW-NEXT:    andis. 4, 5, 13107
 ; SLOW-NEXT:    andi. 5, 5, 13107
 ; SLOW-NEXT:    or 4, 5, 4
 ; SLOW-NEXT:    add 3, 3, 4
 ; SLOW-NEXT:    lis 5, 3855

 ; FAST-NEXT:    blr
 ;
 ; SLOW-LABEL: zpop_i16_i32:
 ; SLOW:       # %bb.0:
 ; SLOW-NEXT:    clrlwi 5, 3, 16
 ; SLOW-NEXT:    rotlwi 3, 3, 31
 ; SLOW-NEXT:    andi. 3, 3, 21845
 ; SLOW-NEXT:    lis 4, 13107
-; SLOW-NEXT:    subf 3, 3, 5
+; SLOW-NEXT:    sub 3, 5, 3
 ; SLOW-NEXT:    ori 4, 4, 13107
 ; SLOW-NEXT:    rotlwi 5, 3, 30
 ; SLOW-NEXT:    and 3, 3, 4
 ; SLOW-NEXT:    andis. 4, 5, 13107
 ; SLOW-NEXT:    andi. 5, 5, 13107
 ; SLOW-NEXT:    or 4, 5, 4
 ; SLOW-NEXT:    add 3, 3, 4
 ; SLOW-NEXT:    lis 5, 3855

 ; FAST-NEXT:    blr
 ;
 ; SLOW-LABEL: popz_i16_32:
 ; SLOW:       # %bb.0:
 ; SLOW-NEXT:    clrlwi 5, 3, 16
 ; SLOW-NEXT:    rotlwi 3, 3, 31
 ; SLOW-NEXT:    andi. 3, 3, 21845
 ; SLOW-NEXT:    lis 4, 13107
-; SLOW-NEXT:    subf 3, 3, 5
+; SLOW-NEXT:    sub 3, 5, 3
 ; SLOW-NEXT:    ori 4, 4, 13107
 ; SLOW-NEXT:    rotlwi 5, 3, 30
 ; SLOW-NEXT:    and 3, 3, 4
 ; SLOW-NEXT:    andis. 4, 5, 13107
 ; SLOW-NEXT:    andi. 5, 5, 13107
 ; SLOW-NEXT:    or 4, 5, 4
 ; SLOW-NEXT:    add 3, 3, 4
 ; SLOW-NEXT:    lis 5, 3855

 ;
 ; SLOW-LABEL: popz_i32_i64:
 ; SLOW:       # %bb.0:
 ; SLOW-NEXT:    rotlwi 5, 3, 31
 ; SLOW-NEXT:    andis. 6, 5, 21845
 ; SLOW-NEXT:    andi. 5, 5, 21845
 ; SLOW-NEXT:    or 5, 5, 6
 ; SLOW-NEXT:    lis 4, 13107
-; SLOW-NEXT:    subf 3, 5, 3
+; SLOW-NEXT:    sub 3, 3, 5
 ; SLOW-NEXT:    ori 4, 4, 13107
 ; SLOW-NEXT:    rotlwi 5, 3, 30
 ; SLOW-NEXT:    and 3, 3, 4
 ; SLOW-NEXT:    andis. 4, 5, 13107
 ; SLOW-NEXT:    andi. 5, 5, 13107
 ; SLOW-NEXT:    or 4, 5, 4
 ; SLOW-NEXT:    add 3, 3, 4
 ; SLOW-NEXT:    lis 5, 3855

 ; FAST-NEXT:    blr
 ;
 ; SLOW-LABEL: popa_i16_i64:
 ; SLOW:       # %bb.0:
 ; SLOW-NEXT:    clrlwi 5, 3, 16
 ; SLOW-NEXT:    rotlwi 3, 3, 31
 ; SLOW-NEXT:    andi. 3, 3, 21845
 ; SLOW-NEXT:    lis 4, 13107
-; SLOW-NEXT:    subf 3, 3, 5
+; SLOW-NEXT:    sub 3, 5, 3
 ; SLOW-NEXT:    ori 4, 4, 13107
 ; SLOW-NEXT:    rotlwi 5, 3, 30
 ; SLOW-NEXT:    and 3, 3, 4
 ; SLOW-NEXT:    andis. 4, 5, 13107
 ; SLOW-NEXT:    andi. 5, 5, 13107
 ; SLOW-NEXT:    or 4, 5, 4
 ; SLOW-NEXT:    add 3, 3, 4
 ; SLOW-NEXT:    lis 5, 3855

llvm/test/CodeGen/PowerPC/ppc-crbits-onoff.ll

entry:
   %and = zext i1 %and3 to i32
   ret i32 %and
 
 ; CHECK-LABEL: @crbitsoff
 ; CHECK-NO-ISEL-LABEL: @crbitsoff
 ; CHECK-DAG: cmplwi 3, 0
 ; CHECK-DAG: li [[REG2:[0-9]+]], 1
 ; CHECK-DAG: cntlzw [[REG3:[0-9]+]],
-; CHECK: isel [[REG4:[0-9]+]], 0, [[REG2]]
+; CHECK: iseleq [[REG4:[0-9]+]], 0, [[REG2]]
 ; CHECK-NO-ISEL: bc 12, 2, [[TRUE:.LBB[0-9]+]]
 ; CHECK-NO-ISEL: ori 4, 5, 0
 ; CHECK-NO-ISEL-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
 ; CHECK-NO-ISEL: [[TRUE]]
-; CHECK-NO-ISEL-NEXT: addi 4, 0, 0
+; CHECK-NO-ISEL-NEXT: li 4, 0
 ; CHECK: and 3, [[REG4]], [[REG3]]
 ; CHECK: blr
 }
 
 define signext i32 @crbitson(i32 signext %v1, i32 signext %v2) #1 {
 entry:
   %tobool = icmp ne i32 %v1, 0
   %lnot = icmp eq i32 %v2, 0

llvm/test/CodeGen/PowerPC/ppc64-P9-mod.ll

 ; CHECK-LABEL: modulo_const32_sw
 ; CHECK-NOT: modsw
 ; CHECK: srawi
 ; CHECK-NOT: modsw
 ; CHECK: addze
 ; CHECK-NOT: modsw
 ; CHECK: slwi
 ; CHECK-NOT: modsw
-; CHECK: subf
+; CHECK: sub
 ; CHECK-NOT: modsw
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: modulo_const32_sw
 ; CHECK-PWR8: srawi
 ; CHECK-PWR8: addze
 ; CHECK-PWR8: slwi
-; CHECK-PWR8: subf
+; CHECK-PWR8: sub
 ; CHECK-PWR8: blr
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i32 @modulo_const3_sw(i32 signext %a) local_unnamed_addr {
 entry:
   %rem = srem i32 %a, 3
   ret i32 %rem

llvm/test/CodeGen/PowerPC/ppc64-P9-vabsd.ll

entry:
   %ispos199 = icmp sgt i32 %sub120, -1
   %neg200 = sub nsw i32 0, %sub120
   %15 = select i1 %ispos199, i32 %sub120, i32 %neg200
   %conv122 = trunc i32 %15 to i8
   %vecins123 = insertelement <16 x i8> %vecins115, i8 %conv122, i32 15
   ret <16 x i8> %vecins123
 ; CHECK-LABEL: sub_absv_8_ext
 ; CHECK-NOT: vabsdub
-; CHECK: subf
+; CHECK: sub
 ; CHECK-NOT: vabsdub
 ; CHECK: xor
 ; CHECK-NOT: vabsdub
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: sub_absv_8_ext
-; CHECK-PWR8: subf
+; CHECK-PWR8: sub
 ; CHECK-PWR8: xor
 ; CHECK-PWR8: blr
 }
 
 define <4 x i32> @sub_absv_vec_32(<4 x i32> %a, <4 x i32> %b) local_unnamed_addr {
 entry:
   %sub = sub <4 x i32> %a, %b
   %sub.i = sub <4 x i32> zeroinitializer, %sub

llvm/test/CodeGen/PowerPC/pr44183.ll

 ; CHECK-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std r0, 16(r1)
 ; CHECK-NEXT:    stdu r1, -48(r1)
 ; CHECK-NEXT:    mr r30, r3
 ; CHECK-NEXT:    ld r4, 8(r30)
 ; CHECK-NEXT:    lwz r5, 36(r30)
 ; CHECK-NEXT:    rldicl r4, r4, 60, 4
 ; CHECK-NEXT:    rlwinm r3, r4, 31, 0, 0
-; CHECK-NEXT:    rlwinm r4, r5, 0, 31, 31
+; CHECK-NEXT:    clrlwi r4, r5, 31
 ; CHECK-NEXT:    or r4, r4, r3
 ; CHECK-NEXT:    bl _ZN1llsE1d
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    ld r3, 16(r30)
 ; CHECK-NEXT:    ld r4, 8(r30)
 ; CHECK-NEXT:    rldicl r4, r4, 60, 4
 ; CHECK-NEXT:    sldi r3, r3, 60
 ; CHECK-NEXT:    or r3, r4, r3

llvm/test/CodeGen/PowerPC/remove-redundant-load-imm.ll

 ; PPC64LE-LABEL: redundancy_on_ppc_only:
 ; PPC64LE:       # %bb.0: # %bb
 ; PPC64LE-NEXT:    mflr 0
 ; PPC64LE-NEXT:    andi. 3, 3, 1
 ; PPC64LE-NEXT:    std 0, 16(1)
 ; PPC64LE-NEXT:    stdu 1, -32(1)
 ; PPC64LE-NEXT:    li 3, 1
 ; PPC64LE-NEXT:    li 4, 0
-; PPC64LE-NEXT:    isel 3, 3, 4, 1
+; PPC64LE-NEXT:    iselgt 3, 3, 4
 ; PPC64LE-NEXT:    bl barney.88
 ; PPC64LE-NEXT:    nop
 ; PPC64LE-NEXT:    addi 1, 1, 32
 ; PPC64LE-NEXT:    ld 0, 16(1)
 ; PPC64LE-NEXT:    mtlr 0
 ; PPC64LE-NEXT:    blr
 bb:
   br label %bb10

llvm/test/CodeGen/PowerPC/sat-add.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=powerpc64le-- -verify-machineinstrs | FileCheck %s
 
 ; There are at least 3 potential patterns corresponding to an unsigned saturated add: min, cmp with sum, cmp with not.
 ; Test each of those patterns with i8/i16/i32/i64.
 ; Test each of those with a constant operand and a variable operand.
 ; Test each of those with a 128-bit vector type.
 
 define i8 @unsigned_sat_constant_i8_using_min(i8 %x) {
 ; CHECK-LABEL: unsigned_sat_constant_i8_using_min:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    clrlwi 5, 3, 24
 ; CHECK-NEXT:    li 4, -43
 ; CHECK-NEXT:    cmplwi 5, 213
-; CHECK-NEXT:    isel 3, 3, 4, 0
+; CHECK-NEXT:    isellt 3, 3, 4
 ; CHECK-NEXT:    addi 3, 3, 42
 ; CHECK-NEXT:    blr
   %c = icmp ult i8 %x, -43
   %s = select i1 %c, i8 %x, i8 -43
   %r = add i8 %s, 42
   ret i8 %r
 }
 
 define i8 @unsigned_sat_constant_i8_using_cmp_sum(i8 %x) {
 ; CHECK-LABEL: unsigned_sat_constant_i8_using_cmp_sum:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    clrlwi 3, 3, 24
 ; CHECK-NEXT:    addi 3, 3, 42
 ; CHECK-NEXT:    andi. 4, 3, 256
 ; CHECK-NEXT:    li 4, -1
-; CHECK-NEXT:    isel 3, 3, 4, 2
+; CHECK-NEXT:    iseleq 3, 3, 4
 ; CHECK-NEXT:    blr
   %a = add i8 %x, 42
   %c = icmp ugt i8 %x, %a
   %r = select i1 %c, i8 -1, i8 %a
   ret i8 %r
 }
 
 define i8 @unsigned_sat_constant_i8_using_cmp_notval(i8 %x) {
 ; CHECK-LABEL: unsigned_sat_constant_i8_using_cmp_notval:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    clrlwi 5, 3, 24
 ; CHECK-NEXT:    li 4, -1
 ; CHECK-NEXT:    addi 3, 3, 42
 ; CHECK-NEXT:    cmplwi 5, 213
-; CHECK-NEXT:    isel 3, 4, 3, 1
+; CHECK-NEXT:    iselgt 3, 4, 3
 ; CHECK-NEXT:    blr
   %a = add i8 %x, 42
   %c = icmp ugt i8 %x, -43
   %r = select i1 %c, i8 -1, i8 %a
   ret i8 %r
 }
 
 define i16 @unsigned_sat_constant_i16_using_min(i16 %x) {
 ; CHECK-LABEL: unsigned_sat_constant_i16_using_min:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    clrlwi 5, 3, 16
 ; CHECK-NEXT:    li 4, -43
 ; CHECK-NEXT:    cmplwi 5, 65493
-; CHECK-NEXT:    isel 3, 3, 4, 0
+; CHECK-NEXT:    isellt 3, 3, 4
 ; CHECK-NEXT:    addi 3, 3, 42
 ; CHECK-NEXT:    blr
   %c = icmp ult i16 %x, -43
   %s = select i1 %c, i16 %x, i16 -43
   %r = add i16 %s, 42
   ret i16 %r
 }
 
 define i16 @unsigned_sat_constant_i16_using_cmp_sum(i16 %x) {
 ; CHECK-LABEL: unsigned_sat_constant_i16_using_cmp_sum:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    clrlwi 3, 3, 16
 ; CHECK-NEXT:    addi 3, 3, 42
 ; CHECK-NEXT:    andis. 4, 3, 1
 ; CHECK-NEXT:    li 4, -1
-; CHECK-NEXT:    isel 3, 3, 4, 2
+; CHECK-NEXT:    iseleq 3, 3, 4
 ; CHECK-NEXT:    blr
   %a = add i16 %x, 42
   %c = icmp ugt i16 %x, %a
   %r = select i1 %c, i16 -1, i16 %a
   ret i16 %r
 }
 
 define i16 @unsigned_sat_constant_i16_using_cmp_notval(i16 %x) {
 ; CHECK-LABEL: unsigned_sat_constant_i16_using_cmp_notval:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    clrlwi 5, 3, 16
 ; CHECK-NEXT:    li 4, -1
 ; CHECK-NEXT:    addi 3, 3, 42
 ; CHECK-NEXT:    cmplwi 5, 65493
-; CHECK-NEXT:    isel 3, 4, 3, 1
+; CHECK-NEXT:    iselgt 3, 4, 3
 ; CHECK-NEXT:    blr
   %a = add i16 %x, 42
   %c = icmp ugt i16 %x, -43
   %r = select i1 %c, i16 -1, i16 %a
   ret i16 %r
 }
 
 define i32 @unsigned_sat_constant_i32_using_min(i32 %x) {
 ; CHECK-LABEL: unsigned_sat_constant_i32_using_min:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    li 4, -43
 ; CHECK-NEXT:    cmplw 3, 4
-; CHECK-NEXT:    isel 3, 3, 4, 0
+; CHECK-NEXT:    isellt 3, 3, 4
 ; CHECK-NEXT:    addi 3, 3, 42
 ; CHECK-NEXT:    blr
   %c = icmp ult i32 %x, -43
   %s = select i1 %c, i32 %x, i32 -43
   %r = add i32 %s, 42
   ret i32 %r
 }
 
 define i32 @unsigned_sat_constant_i32_using_cmp_sum(i32 %x) {
 ; CHECK-LABEL: unsigned_sat_constant_i32_using_cmp_sum:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi 5, 3, 42
 ; CHECK-NEXT:    li 4, -1
 ; CHECK-NEXT:    cmplw 5, 3
-; CHECK-NEXT:    isel 3, 4, 5, 0
+; CHECK-NEXT:    isellt 3, 4, 5
 ; CHECK-NEXT:    blr
   %a = add i32 %x, 42
   %c = icmp ugt i32 %x, %a
   %r = select i1 %c, i32 -1, i32 %a
   ret i32 %r
 }
 
 define i32 @unsigned_sat_constant_i32_using_cmp_notval(i32 %x) {
 ; CHECK-LABEL: unsigned_sat_constant_i32_using_cmp_notval:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    li 4, -43
 ; CHECK-NEXT:    addi 5, 3, 42
 ; CHECK-NEXT:    cmplw 3, 4
 ; CHECK-NEXT:    li 3, -1
-; CHECK-NEXT:    isel 3, 3, 5, 1
+; CHECK-NEXT:    iselgt 3, 3, 5
 ; CHECK-NEXT:    blr
   %a = add i32 %x, 42
   %c = icmp ugt i32 %x, -43
   %r = select i1 %c, i32 -1, i32 %a
   ret i32 %r
 }
 
 define i64 @unsigned_sat_constant_i64_using_min(i64 %x) {
 ; CHECK-LABEL: unsigned_sat_constant_i64_using_min:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    li 4, -43
 ; CHECK-NEXT:    cmpld 3, 4
-; CHECK-NEXT:    isel 3, 3, 4, 0
+; CHECK-NEXT:    isellt 3, 3, 4
 ; CHECK-NEXT:    addi 3, 3, 42
 ; CHECK-NEXT:    blr
   %c = icmp ult i64 %x, -43
   %s = select i1 %c, i64 %x, i64 -43
   %r = add i64 %s, 42
   ret i64 %r
 }
 
 define i64 @unsigned_sat_constant_i64_using_cmp_sum(i64 %x) {
 ; CHECK-LABEL: unsigned_sat_constant_i64_using_cmp_sum:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi 5, 3, 42
 ; CHECK-NEXT:    li 4, -1
 ; CHECK-NEXT:    cmpld 5, 3
-; CHECK-NEXT:    isel 3, 4, 5, 0
+; CHECK-NEXT:    isellt 3, 4, 5
 ; CHECK-NEXT:    blr
   %a = add i64 %x, 42
   %c = icmp ugt i64 %x, %a
   %r = select i1 %c, i64 -1, i64 %a
   ret i64 %r
 }
 
 define i64 @unsigned_sat_constant_i64_using_cmp_notval(i64 %x) {
 ; CHECK-LABEL: unsigned_sat_constant_i64_using_cmp_notval:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    li 4, -43
 ; CHECK-NEXT:    addi 5, 3, 42
 ; CHECK-NEXT:    cmpld 3, 4
 ; CHECK-NEXT:    li 3, -1
-; CHECK-NEXT:    isel 3, 3, 5, 1
+; CHECK-NEXT:    iselgt 3, 3, 5
 ; CHECK-NEXT:    blr
   %a = add i64 %x, 42
   %c = icmp ugt i64 %x, -43
   %r = select i1 %c, i64 -1, i64 %a
   ret i64 %r
 }
 
 define i8 @unsigned_sat_variable_i8_using_min(i8 %x, i8 %y) {
 ; CHECK-LABEL: unsigned_sat_variable_i8_using_min:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    nor 5, 4, 4
+; CHECK-NEXT:    not 5, 4
 ; CHECK-NEXT:    clrlwi 6, 3, 24
 ; CHECK-NEXT:    clrlwi 7, 5, 24
 ; CHECK-NEXT:    cmplw 6, 7
-; CHECK-NEXT:    isel 3, 3, 5, 0
+; CHECK-NEXT:    isellt 3, 3, 5
 ; CHECK-NEXT:    add 3, 3, 4
 ; CHECK-NEXT:    blr
   %noty = xor i8 %y, -1
   %c = icmp ult i8 %x, %noty
   %s = select i1 %c, i8 %x, i8 %noty
   %r = add i8 %s, %y
   ret i8 %r
 }
 
 define i8 @unsigned_sat_variable_i8_using_cmp_sum(i8 %x, i8 %y) {
 ; CHECK-LABEL: unsigned_sat_variable_i8_using_cmp_sum:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    clrlwi 4, 4, 24
 ; CHECK-NEXT:    clrlwi 3, 3, 24
 ; CHECK-NEXT:    add 3, 3, 4
 ; CHECK-NEXT:    andi. 4, 3, 256
 ; CHECK-NEXT:    li 4, -1
-; CHECK-NEXT:    isel 3, 3, 4, 2
+; CHECK-NEXT:    iseleq 3, 3, 4
 ; CHECK-NEXT:    blr
   %a = add i8 %x, %y
   %c = icmp ugt i8 %x, %a
   %r = select i1 %c, i8 -1, i8 %a
   ret i8 %r
 }
 
 define i8 @unsigned_sat_variable_i8_using_cmp_notval(i8 %x, i8 %y) {
 ; CHECK-LABEL: unsigned_sat_variable_i8_using_cmp_notval:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    nor 6, 4, 4
+; CHECK-NEXT:    not 6, 4
 ; CHECK-NEXT:    clrlwi 7, 3, 24
 ; CHECK-NEXT:    li 5, -1
 ; CHECK-NEXT:    add 3, 3, 4
 ; CHECK-NEXT:    clrlwi 6, 6, 24
 ; CHECK-NEXT:    cmplw 7, 6
-; CHECK-NEXT:    isel 3, 5, 3, 1
+; CHECK-NEXT:    iselgt 3, 5, 3
 ; CHECK-NEXT:    blr
   %noty = xor i8 %y, -1
   %a = add i8 %x, %y
   %c = icmp ugt i8 %x, %noty
   %r = select i1 %c, i8 -1, i8 %a
   ret i8 %r
 }
 
 define i16 @unsigned_sat_variable_i16_using_min(i16 %x, i16 %y) {
 ; CHECK-LABEL: unsigned_sat_variable_i16_using_min:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    nor 5, 4, 4
+; CHECK-NEXT:    not 5, 4
 ; CHECK-NEXT:    clrlwi 6, 3, 16
 ; CHECK-NEXT:    clrlwi 7, 5, 16
 ; CHECK-NEXT:    cmplw 6, 7
-; CHECK-NEXT:    isel 3, 3, 5, 0
+; CHECK-NEXT:    isellt 3, 3, 5
 ; CHECK-NEXT:    add 3, 3, 4
 ; CHECK-NEXT:    blr
   %noty = xor i16 %y, -1
   %c = icmp ult i16 %x, %noty
   %s = select i1 %c, i16 %x, i16 %noty
   %r = add i16 %s, %y
   ret i16 %r
 }
 
 define i16 @unsigned_sat_variable_i16_using_cmp_sum(i16 %x, i16 %y) {
 ; CHECK-LABEL: unsigned_sat_variable_i16_using_cmp_sum:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    clrlwi 4, 4, 16
 ; CHECK-NEXT:    clrlwi 3, 3, 16
 ; CHECK-NEXT:    add 3, 3, 4
 ; CHECK-NEXT:    andis. 4, 3, 1
 ; CHECK-NEXT:    li 4, -1
-; CHECK-NEXT:    isel 3, 3, 4, 2
+; CHECK-NEXT:    iseleq 3, 3, 4
 ; CHECK-NEXT:    blr
   %a = add i16 %x, %y
   %c = icmp ugt i16 %x, %a
   %r = select i1 %c, i16 -1, i16 %a
   ret i16 %r
 }
 
 define i16 @unsigned_sat_variable_i16_using_cmp_notval(i16 %x, i16 %y) {
 ; CHECK-LABEL: unsigned_sat_variable_i16_using_cmp_notval:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    nor 6, 4, 4
+; CHECK-NEXT:    not 6, 4
 ; CHECK-NEXT:    clrlwi 7, 3, 16
 ; CHECK-NEXT:    li 5, -1
 ; CHECK-NEXT:    add 3, 3, 4
 ; CHECK-NEXT:    clrlwi 6, 6, 16
 ; CHECK-NEXT:    cmplw 7, 6
-; CHECK-NEXT:    isel 3, 5, 3, 1
+; CHECK-NEXT:    iselgt 3, 5, 3
 ; CHECK-NEXT:    blr
   %noty = xor i16 %y, -1
   %a = add i16 %x, %y
   %c = icmp ugt i16 %x, %noty
   %r = select i1 %c, i16 -1, i16 %a
   ret i16 %r
 }
 
 define i32 @unsigned_sat_variable_i32_using_min(i32 %x, i32 %y) {
 ; CHECK-LABEL: unsigned_sat_variable_i32_using_min:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    nor 5, 4, 4
+; CHECK-NEXT:    not 5, 4
 ; CHECK-NEXT:    cmplw 3, 5
-; CHECK-NEXT:    isel 3, 3, 5, 0
+; CHECK-NEXT:    isellt 3, 3, 5
 ; CHECK-NEXT:    add 3, 3, 4
 ; CHECK-NEXT:    blr
   %noty = xor i32 %y, -1
   %c = icmp ult i32 %x, %noty
   %s = select i1 %c, i32 %x, i32 %noty
   %r = add i32 %s, %y
   ret i32 %r
 }
 
 define i32 @unsigned_sat_variable_i32_using_cmp_sum(i32 %x, i32 %y) {
 ; CHECK-LABEL: unsigned_sat_variable_i32_using_cmp_sum:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    add 4, 3, 4
 ; CHECK-NEXT:    li 5, -1
 ; CHECK-NEXT:    cmplw 4, 3
-; CHECK-NEXT:    isel 3, 5, 4, 0
+; CHECK-NEXT:    isellt 3, 5, 4
 ; CHECK-NEXT:    blr
   %a = add i32 %x, %y
   %c = icmp ugt i32 %x, %a
   %r = select i1 %c, i32 -1, i32 %a
   ret i32 %r
 }
 
 define i32 @unsigned_sat_variable_i32_using_cmp_notval(i32 %x, i32 %y) {
 ; CHECK-LABEL: unsigned_sat_variable_i32_using_cmp_notval:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    nor 6, 4, 4
+; CHECK-NEXT:    not 6, 4
 ; CHECK-NEXT:    li 5, -1
 ; CHECK-NEXT:    cmplw 3, 6
 ; CHECK-NEXT:    add 3, 3, 4
-; CHECK-NEXT:    isel 3, 5, 3, 1
+; CHECK-NEXT:    iselgt 3, 5, 3
 ; CHECK-NEXT:    blr
   %noty = xor i32 %y, -1
   %a = add i32 %x, %y
   %c = icmp ugt i32 %x, %noty
   %r = select i1 %c, i32 -1, i32 %a
   ret i32 %r
 }
 
 define i64 @unsigned_sat_variable_i64_using_min(i64 %x, i64 %y) {
 ; CHECK-LABEL: unsigned_sat_variable_i64_using_min:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    not 5, 4
 ; CHECK-NEXT:    cmpld 3, 5
-; CHECK-NEXT:    isel 3, 3, 5, 0
+; CHECK-NEXT:    isellt 3, 3, 5
 ; CHECK-NEXT:    add 3, 3, 4
 ; CHECK-NEXT:    blr
   %noty = xor i64 %y, -1
   %c = icmp ult i64 %x, %noty
   %s = select i1 %c, i64 %x, i64 %noty
   %r = add i64 %s, %y
   ret i64 %r
 }
 
 define i64 @unsigned_sat_variable_i64_using_cmp_sum(i64 %x, i64 %y) {
 ; CHECK-LABEL: unsigned_sat_variable_i64_using_cmp_sum:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    add 4, 3, 4
 ; CHECK-NEXT:    li 5, -1
 ; CHECK-NEXT:    cmpld 4, 3
-; CHECK-NEXT:    isel 3, 5, 4, 0
+; CHECK-NEXT:    isellt 3, 5, 4
 ; CHECK-NEXT:    blr
   %a = add i64 %x, %y
   %c = icmp ugt i64 %x, %a
   %r = select i1 %c, i64 -1, i64 %a
   ret i64 %r
 }
 
 define i64 @unsigned_sat_variable_i64_using_cmp_notval(i64 %x, i64 %y) {
 ; CHECK-LABEL: unsigned_sat_variable_i64_using_cmp_notval:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    not 6, 4
 ; CHECK-NEXT:    li 5, -1
 ; CHECK-NEXT:    cmpld 3, 6
 ; CHECK-NEXT:    add 3, 3, 4
-; CHECK-NEXT:    isel 3, 5, 3, 1
+; CHECK-NEXT:    iselgt 3, 5, 3
 ; CHECK-NEXT:    blr
   %noty = xor i64 %y, -1
   %a = add i64 %x, %y
   %c = icmp ugt i64 %x, %noty
   %r = select i1 %c, i64 -1, i64 %a
   ret i64 %r
 }
 

llvm/test/CodeGen/PowerPC/select_const.ll

 ; select Cond, C1, C2 --> add (mul (zext Cond), C1-C2), C2 --> add (and (sext Cond), C1-C2), C2
 
 define i32 @select_C1_C2(i1 %cond) {
 ; ISEL-LABEL: select_C1_C2:
 ; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, 421
 ; ISEL-NEXT:    li 3, 42
-; ISEL-NEXT:    isel 3, 4, 3, 1
+; ISEL-NEXT:    iselgt 3, 4, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: select_C1_C2:
 ; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    li 4, 421
 ; NO_ISEL-NEXT:    li 3, 42
 ; NO_ISEL-NEXT:    bc 12, 1, .LBB18_1
 ; NO_ISEL-NEXT:    blr
 ; NO_ISEL-NEXT:  .LBB18_1:
 ; NO_ISEL-NEXT:    addi 3, 4, 0
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i32 421, i32 42
   ret i32 %sel
 }
 
 define i32 @select_C1_C2_zeroext(i1 zeroext %cond) {
 ; ISEL-LABEL: select_C1_C2_zeroext:
 ; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, 421
 ; ISEL-NEXT:    li 3, 42
-; ISEL-NEXT:    isel 3, 4, 3, 1
+; ISEL-NEXT:    iselgt 3, 4, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: select_C1_C2_zeroext:
 ; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    li 4, 421
 ; NO_ISEL-NEXT:    li 3, 42
 ; NO_ISEL-NEXT:    bc 12, 1, .LBB19_1
 ; NO_ISEL-NEXT:    blr
 ; NO_ISEL-NEXT:  .LBB19_1:
 ; NO_ISEL-NEXT:    addi 3, 4, 0
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i32 421, i32 42
   ret i32 %sel
 }
 
 define i32 @select_C1_C2_signext(i1 signext %cond) {
 ; ISEL-LABEL: select_C1_C2_signext:
 ; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, 421
 ; ISEL-NEXT:    li 3, 42
-; ISEL-NEXT:    isel 3, 4, 3, 1
+; ISEL-NEXT:    iselgt 3, 4, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: select_C1_C2_signext:
 ; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    li 4, 421
 ; NO_ISEL-NEXT:    li 3, 42
 ; NO_ISEL-NEXT:    bc 12, 1, .LBB20_1
 ; NO_ISEL-NEXT:    blr
 ; NO_ISEL-NEXT:  .LBB20_1:
 ; NO_ISEL-NEXT:    addi 3, 4, 0
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i32 421, i32 42
   ret i32 %sel
 }
 
 ; A binary operator with constant after the select should always get folded into the select.
 
 define i8 @sel_constants_add_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_add_constant:
 ; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, 1
 ; ISEL-NEXT:    li 3, 28
-; ISEL-NEXT:    isel 3, 4, 3, 1
+; ISEL-NEXT:    iselgt 3, 4, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_add_constant:
 ; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    li 4, 1
 ; NO_ISEL-NEXT:    li 3, 28
 ; NO_ISEL-NEXT:    bc 12, 1, .LBB21_1
 ; NO_ISEL-NEXT:    blr
 ; NO_ISEL-NEXT:  .LBB21_1:
 ; NO_ISEL-NEXT:    addi 3, 4, 0
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = add i8 %sel, 5
   ret i8 %bo
 }
 
 define i8 @sel_constants_sub_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_sub_constant:
 ; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, -9
 ; ISEL-NEXT:    li 3, 18
-; ISEL-NEXT:    isel 3, 4, 3, 1
+; ISEL-NEXT:    iselgt 3, 4, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_sub_constant:
 ; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    li 4, -9
 ; NO_ISEL-NEXT:    li 3, 18
 ; NO_ISEL-NEXT:    bc 12, 1, .LBB22_1
 ; NO_ISEL-NEXT:    blr
 ; NO_ISEL-NEXT:  .LBB22_1:
 ; NO_ISEL-NEXT:    addi 3, 4, 0
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = sub i8 %sel, 5
   ret i8 %bo
 }
 
 define i8 @sel_constants_sub_constant_sel_constants(i1 %cond) {
 ; ISEL-LABEL: sel_constants_sub_constant_sel_constants:
 ; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, 9
 ; ISEL-NEXT:    li 3, 2
-; ISEL-NEXT:    isel 3, 4, 3, 1
+; ISEL-NEXT:    iselgt 3, 4, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_sub_constant_sel_constants:
 ; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    li 4, 9
 ; NO_ISEL-NEXT:    li 3, 2
 ; NO_ISEL-NEXT:    bc 12, 1, .LBB23_1
 ; NO_ISEL-NEXT:    blr
 ; NO_ISEL-NEXT:  .LBB23_1:
 ; NO_ISEL-NEXT:    addi 3, 4, 0
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i8 -4, i8 3
   %bo = sub i8 5, %sel
   ret i8 %bo
 }
 
 define i8 @sel_constants_mul_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_mul_constant:
 ; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, -20
 ; ISEL-NEXT:    li 3, 115
-; ISEL-NEXT:    isel 3, 4, 3, 1
+; ISEL-NEXT:    iselgt 3, 4, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_mul_constant:
 ; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    li 4, -20
 ; NO_ISEL-NEXT:    li 3, 115
 ; NO_ISEL-NEXT:    bc 12, 1, .LBB24_1
 ; NO_ISEL-NEXT:    blr
 ; NO_ISEL-NEXT:  .LBB24_1:
 ; NO_ISEL-NEXT:    addi 3, 4, 0
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = mul i8 %sel, 5
   ret i8 %bo
 }
 
 define i8 @sel_constants_sdiv_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_sdiv_constant:
 ; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 3, 4
-; ISEL-NEXT:    isel 3, 0, 3, 1
+; ISEL-NEXT:    iselgt 3, 0, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_sdiv_constant:
 ; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    li 3, 4
 ; NO_ISEL-NEXT:    bc 12, 1, .LBB25_1
 ; NO_ISEL-NEXT:    blr
 ; NO_ISEL-NEXT:  .LBB25_1:
-; NO_ISEL-NEXT:    addi 3, 0, 0
+; NO_ISEL-NEXT:    li 3, 0
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = sdiv i8 %sel, 5
   ret i8 %bo
 }
 
 define i8 @sdiv_constant_sel_constants(i1 %cond) {
 ; ISEL-LABEL: sdiv_constant_sel_constants:
 ; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 3, 5
-; ISEL-NEXT:    isel 3, 0, 3, 1
+; ISEL-NEXT:    iselgt 3, 0, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sdiv_constant_sel_constants:
 ; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    li 3, 5
 ; NO_ISEL-NEXT:    bc 12, 1, .LBB26_1
 ; NO_ISEL-NEXT:    blr
 ; NO_ISEL-NEXT:  .LBB26_1:
-; NO_ISEL-NEXT:    addi 3, 0, 0
+; NO_ISEL-NEXT:    li 3, 0
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i8 121, i8 23
   %bo = sdiv i8 120, %sel
   ret i8 %bo
 }
 
 define i8 @sel_constants_udiv_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_udiv_constant:
 ; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, 50
 ; ISEL-NEXT:    li 3, 4
-; ISEL-NEXT:    isel 3, 4, 3, 1
+; ISEL-NEXT:    iselgt 3, 4, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_udiv_constant:
 ; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    li 4, 50
 ; NO_ISEL-NEXT:    li 3, 4
 ; NO_ISEL-NEXT:    bc 12, 1, .LBB27_1
 ; NO_ISEL-NEXT:    blr
 ; NO_ISEL-NEXT:  .LBB27_1:
 ; NO_ISEL-NEXT:    addi 3, 4, 0
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = udiv i8 %sel, 5
   ret i8 %bo
 }
 
 define i8 @udiv_constant_sel_constants(i1 %cond) {
 ; ISEL-LABEL: udiv_constant_sel_constants:
 ; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 3, 5
-; ISEL-NEXT:    isel 3, 0, 3, 1
+; ISEL-NEXT:    iselgt 3, 0, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: udiv_constant_sel_constants:
 ; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    li 3, 5
 ; NO_ISEL-NEXT:    bc 12, 1, .LBB28_1
 ; NO_ISEL-NEXT:    blr
 ; NO_ISEL-NEXT:  .LBB28_1:
-; NO_ISEL-NEXT:    addi 3, 0, 0
+; NO_ISEL-NEXT:    li 3, 0
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = udiv i8 120, %sel
   ret i8 %bo
 }
 
 define i8 @sel_constants_srem_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_srem_constant:
 ; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, -4
 ; ISEL-NEXT:    li 3, 3
-; ISEL-NEXT:    isel 3, 4, 3, 1
+; ISEL-NEXT:    iselgt 3, 4, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_srem_constant:
 ; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    li 4, -4
 ; NO_ISEL-NEXT:    li 3, 3
 ; NO_ISEL-NEXT:    bc 12, 1, .LBB29_1
 ; NO_ISEL-NEXT:    blr
 ; NO_ISEL-NEXT:  .LBB29_1:
 ; NO_ISEL-NEXT:    addi 3, 4, 0
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = srem i8 %sel, 5
   ret i8 %bo
 }
 
 define i8 @srem_constant_sel_constants(i1 %cond) {
 ; ISEL-LABEL: srem_constant_sel_constants:
 ; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, 120
 ; ISEL-NEXT:    li 3, 5
-; ISEL-NEXT:    isel 3, 4, 3, 1
+; ISEL-NEXT:    iselgt 3, 4, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: srem_constant_sel_constants:
 ; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    li 4, 120
 ; NO_ISEL-NEXT:    li 3, 5
 ; NO_ISEL-NEXT:    bc 12, 1, .LBB30_1

 }
 
 define i8 @urem_constant_sel_constants(i1 %cond) {
 ; ISEL-LABEL: urem_constant_sel_constants:
 ; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, 120
 ; ISEL-NEXT:    li 3, 5
-; ISEL-NEXT:    isel 3, 4, 3, 1
+; ISEL-NEXT:    iselgt 3, 4, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: urem_constant_sel_constants:
 ; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    li 4, 120
 ; NO_ISEL-NEXT:    li 3, 5
 ; NO_ISEL-NEXT:    bc 12, 1, .LBB32_1

 }
 
 define i8 @sel_constants_or_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_or_constant:
 ; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, -3
 ; ISEL-NEXT:    li 3, 23
-; ISEL-NEXT:    isel 3, 4, 3, 1
+; ISEL-NEXT:    iselgt 3, 4, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_or_constant:
 ; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    li 4, -3
 ; NO_ISEL-NEXT:    li 3, 23
 ; NO_ISEL-NEXT:    bc 12, 1, .LBB34_1
 ; NO_ISEL-NEXT:    blr
 ; NO_ISEL-NEXT:  .LBB34_1:
 ; NO_ISEL-NEXT:    addi 3, 4, 0
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = or i8 %sel, 5
   ret i8 %bo
 }
 
 define i8 @sel_constants_xor_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_xor_constant:
 ; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, -7
 ; ISEL-NEXT:    li 3, 18
-; ISEL-NEXT:    isel 3, 4, 3, 1
+; ISEL-NEXT:    iselgt 3, 4, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_xor_constant:
 ; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    li 4, -7
 ; NO_ISEL-NEXT:    li 3, 18
 ; NO_ISEL-NEXT:    bc 12, 1, .LBB35_1
 ; NO_ISEL-NEXT:    blr
 ; NO_ISEL-NEXT:  .LBB35_1:
 ; NO_ISEL-NEXT:    addi 3, 4, 0
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = xor i8 %sel, 5
   ret i8 %bo
 }
 
 define i8 @sel_constants_shl_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_shl_constant:
 ; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, -128
 ; ISEL-NEXT:    li 3, -32
-; ISEL-NEXT:    isel 3, 4, 3, 1
+; ISEL-NEXT:    iselgt 3, 4, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_shl_constant:
 ; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    li 4, -128
 ; NO_ISEL-NEXT:    li 3, -32
 ; NO_ISEL-NEXT:    bc 12, 1, .LBB36_1

 }
 
 define i8 @sel_constants_lshr_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_lshr_constant:
 ; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, 7
 ; ISEL-NEXT:    li 3, 0
-; ISEL-NEXT:    isel 3, 4, 3, 1
+; ISEL-NEXT:    iselgt 3, 4, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_lshr_constant:
 ; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    li 4, 7
 ; NO_ISEL-NEXT:    li 3, 0
 ; NO_ISEL-NEXT:    bc 12, 1, .LBB38_1

 define double @sel_constants_fadd_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_fadd_constant:
 ; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    addis 4, 2, .LCPI42_0@toc@ha
 ; ISEL-NEXT:    addis 3, 2, .LCPI42_1@toc@ha
 ; ISEL-NEXT:    addi 4, 4, .LCPI42_0@toc@l
 ; ISEL-NEXT:    addi 3, 3, .LCPI42_1@toc@l
-; ISEL-NEXT:    isel 3, 3, 4, 1
+; ISEL-NEXT:    iselgt 3, 3, 4
 ; ISEL-NEXT:    lfdx 1, 0, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_fadd_constant:
 ; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    addis 4, 2, .LCPI42_0@toc@ha
 ; NO_ISEL-NEXT:    addis 3, 2, .LCPI42_1@toc@ha

 define double @sel_constants_fsub_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_fsub_constant:
 ; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    addis 4, 2, .LCPI43_0@toc@ha
 ; ISEL-NEXT:    addis 3, 2, .LCPI43_1@toc@ha
 ; ISEL-NEXT:    addi 4, 4, .LCPI43_0@toc@l
 ; ISEL-NEXT:    addi 3, 3, .LCPI43_1@toc@l
-; ISEL-NEXT:    isel 3, 3, 4, 1
+; ISEL-NEXT:    iselgt 3, 3, 4
 ; ISEL-NEXT:    lfdx 1, 0, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_fsub_constant:
 ; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    addis 4, 2, .LCPI43_0@toc@ha
 ; NO_ISEL-NEXT:    addis 3, 2, .LCPI43_1@toc@ha

 define double @fsub_constant_sel_constants(i1 %cond) {
 ; ISEL-LABEL: fsub_constant_sel_constants:
 ; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    addis 4, 2, .LCPI44_0@toc@ha
 ; ISEL-NEXT:    addis 3, 2, .LCPI44_1@toc@ha
 ; ISEL-NEXT:    addi 4, 4, .LCPI44_0@toc@l
 ; ISEL-NEXT:    addi 3, 3, .LCPI44_1@toc@l
-; ISEL-NEXT:    isel 3, 3, 4, 1
+; ISEL-NEXT:    iselgt 3, 3, 4
 ; ISEL-NEXT:    lfdx 1, 0, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: fsub_constant_sel_constants:
 ; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    addis 4, 2, .LCPI44_0@toc@ha
 ; NO_ISEL-NEXT:    addis 3, 2, .LCPI44_1@toc@ha

 define double @sel_constants_fmul_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_fmul_constant:
 ; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    addis 4, 2, .LCPI45_0@toc@ha
 ; ISEL-NEXT:    addis 3, 2, .LCPI45_1@toc@ha
 ; ISEL-NEXT:    addi 4, 4, .LCPI45_0@toc@l
 ; ISEL-NEXT:    addi 3, 3, .LCPI45_1@toc@l
-; ISEL-NEXT:    isel 3, 3, 4, 1
+; ISEL-NEXT:    iselgt 3, 3, 4
 ; ISEL-NEXT:    lfdx 1, 0, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_fmul_constant:
 ; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    addis 4, 2, .LCPI45_0@toc@ha
 ; NO_ISEL-NEXT:    addis 3, 2, .LCPI45_1@toc@ha

 define double @sel_constants_fdiv_constant(i1 %cond) {
 ; ISEL-LABEL: sel_constants_fdiv_constant:
 ; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    addis 4, 2, .LCPI46_0@toc@ha
 ; ISEL-NEXT:    addis 3, 2, .LCPI46_1@toc@ha
 ; ISEL-NEXT:    addi 4, 4, .LCPI46_0@toc@l
 ; ISEL-NEXT:    addi 3, 3, .LCPI46_1@toc@l
-; ISEL-NEXT:    isel 3, 3, 4, 1
+; ISEL-NEXT:    iselgt 3, 3, 4
 ; ISEL-NEXT:    lfdx 1, 0, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_fdiv_constant:
 ; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    addis 4, 2, .LCPI46_0@toc@ha
 ; NO_ISEL-NEXT:    addis 3, 2, .LCPI46_1@toc@ha

 define double @fdiv_constant_sel_constants(i1 %cond) {
 ; ISEL-LABEL: fdiv_constant_sel_constants:
 ; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    addis 4, 2, .LCPI47_0@toc@ha
 ; ISEL-NEXT:    addis 3, 2, .LCPI47_1@toc@ha
 ; ISEL-NEXT:    addi 4, 4, .LCPI47_0@toc@l
 ; ISEL-NEXT:    addi 3, 3, .LCPI47_1@toc@l
-; ISEL-NEXT:    isel 3, 3, 4, 1
+; ISEL-NEXT:    iselgt 3, 3, 4
 ; ISEL-NEXT:    lfdx 1, 0, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: fdiv_constant_sel_constants:
 ; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    addis 4, 2, .LCPI47_0@toc@ha
 ; NO_ISEL-NEXT:    addis 3, 2, .LCPI47_1@toc@ha

 define double @frem_constant_sel_constants(i1 %cond) {
 ; ISEL-LABEL: frem_constant_sel_constants:
 ; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    addis 4, 2, .LCPI49_0@toc@ha
 ; ISEL-NEXT:    addis 3, 2, .LCPI49_1@toc@ha
 ; ISEL-NEXT:    addi 4, 4, .LCPI49_0@toc@l
 ; ISEL-NEXT:    addi 3, 3, .LCPI49_1@toc@l
-; ISEL-NEXT:    isel 3, 3, 4, 1
+; ISEL-NEXT:    iselgt 3, 3, 4
 ; ISEL-NEXT:    lfdx 1, 0, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: frem_constant_sel_constants:
 ; NO_ISEL:       # %bb.0:
 ; NO_ISEL-NEXT:    andi. 3, 3, 1
 ; NO_ISEL-NEXT:    addis 4, 2, .LCPI49_0@toc@ha
 ; NO_ISEL-NEXT:    addis 3, 2, .LCPI49_1@toc@ha

llvm/test/CodeGen/PowerPC/setcc-logic.ll

; CHECK-NEXT:    blr
   %c = and i1 %a, %b
   ret i1 %c
 }
 
 define zeroext i1 @all_sign_bits_clear(i32 %P, i32 %Q)  {
 ; CHECK-LABEL: all_sign_bits_clear:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    or 3, 3, 4
-; CHECK-NEXT:    nor 3, 3, 3
+; CHECK-NEXT:    not 3, 3
 ; CHECK-NEXT:    srwi 3, 3, 31
 ; CHECK-NEXT:    blr
   %a = icmp sgt i32 %P, -1
   %b = icmp sgt i32 %Q, -1
   %c = and i1 %a, %b
   ret i1 %c
 }
 
; CHECK-NEXT:    blr
   %c = or i1 %a, %b
   ret i1 %c
 }
 
 define zeroext i1 @any_sign_bits_clear(i32 %P, i32 %Q)  {
 ; CHECK-LABEL: any_sign_bits_clear:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    and 3, 3, 4
-; CHECK-NEXT:    nor 3, 3, 3
+; CHECK-NEXT:    not 3, 3
 ; CHECK-NEXT:    srwi 3, 3, 31
 ; CHECK-NEXT:    blr
   %a = icmp sgt i32 %P, -1
   %b = icmp sgt i32 %Q, -1
   %c = or i1 %a, %b
   ret i1 %c
 }
 

 }
 
 define i1 @and_icmps_const_1bit_diff(i32 %x) {
 ; CHECK-LABEL: and_icmps_const_1bit_diff:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi 3, 3, -4625
 ; CHECK-NEXT:    rlwinm 3, 3, 0, 28, 26
 ; CHECK-NEXT:    cntlzw 3, 3
-; CHECK-NEXT:    nor 3, 3, 3
+; CHECK-NEXT:    not 3, 3
 ; CHECK-NEXT:    rlwinm 3, 3, 27, 31, 31
 ; CHECK-NEXT:    blr
   %a = icmp ne i32 %x, 4625
   %b = icmp ne i32 %x, 4641
   %r = and i1 %a, %b
   ret i1 %r
 }
 

llvm/test/CodeGen/PowerPC/shift128.ll

 ; CHECK-DAG: subfic [[R0:[0-9]+]], 5, 64
 ; CHECK-DAG: addi [[R1:[0-9]+]], 5, -64
 ; CHECK-DAG: srd [[R2:[0-9]+]], 3, 5
 ; CHECK-DAG: sld [[R3:[0-9]+]], 4, [[R0]]
 ; CHECK-DAG: srad [[R4:[0-9]+]], 4, [[R1]]
 ; CHECK-DAG: or [[R5:[0-9]+]], [[R2]], [[R3]]
 ; CHECK-DAG: cmpwi [[R1]], 1
 ; CHECK-DAG: srad 4, 4, 5
-; CHECK-DAG: isel 3, [[R5]], [[R4]], 0
+; CHECK-DAG: isellt 3, [[R5]], [[R4]]
 ; CHECK: blr
 define i128 @ashr(i128 %x, i128 %y) {
   %r = ashr i128 %x, %y
   ret i128 %r
 }
 ; CHECK-LABEL: shl:
 ; CHECK-DAG: subfic [[R0:[0-9]+]], 5, 64
 ; CHECK-DAG: addi [[R1:[0-9]+]], 5, -64

llvm/test/CodeGen/PowerPC/signbit-shift.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=powerpc64le-- | FileCheck %s
 
 ; If positive...
 
 define i32 @zext_ifpos(i32 %x) {
 ; CHECK-LABEL: zext_ifpos:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    nor 3, 3, 3
+; CHECK-NEXT:    not 3, 3
 ; CHECK-NEXT:    srwi 3, 3, 31
 ; CHECK-NEXT:    blr
   %c = icmp sgt i32 %x, -1
   %e = zext i1 %c to i32
   ret i32 %e
 }
 
 define i32 @add_zext_ifpos(i32 %x) {

 }
 
 define i32 @sel_ifpos_tval_bigger(i32 %x) {
 ; CHECK-LABEL: sel_ifpos_tval_bigger:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    li 4, 41
 ; CHECK-NEXT:    cmpwi 3, -1
 ; CHECK-NEXT:    li 3, 42
-; CHECK-NEXT:    isel 3, 3, 4, 1
+; CHECK-NEXT:    iselgt 3, 3, 4
 ; CHECK-NEXT:    blr
   %c = icmp sgt i32 %x, -1
   %r = select i1 %c, i32 42, i32 41
   ret i32 %r
 }
 
 define i32 @sext_ifpos(i32 %x) {
 ; CHECK-LABEL: sext_ifpos:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    nor 3, 3, 3
+; CHECK-NEXT:    not 3, 3
 ; CHECK-NEXT:    srawi 3, 3, 31
 ; CHECK-NEXT:    blr
   %c = icmp sgt i32 %x, -1
   %e = sext i1 %c to i32
   ret i32 %e
 }
 
 define i32 @add_sext_ifpos(i32 %x) {

 }
 
 define i32 @sel_ifpos_fval_bigger(i32 %x) {
 ; CHECK-LABEL: sel_ifpos_fval_bigger:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    li 4, 42
 ; CHECK-NEXT:    cmpwi 3, -1
 ; CHECK-NEXT:    li 3, 41
-; CHECK-NEXT:    isel 3, 3, 4, 1
+; CHECK-NEXT:    iselgt 3, 3, 4
 ; CHECK-NEXT:    blr
   %c = icmp sgt i32 %x, -1
   %r = select i1 %c, i32 41, i32 42
   ret i32 %r
 }
 
 ; If negative...
 

 }
 
 define i32 @sel_ifneg_tval_bigger(i32 %x) {
 ; CHECK-LABEL: sel_ifneg_tval_bigger:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    li 4, 41
 ; CHECK-NEXT:    cmpwi 3, 0
 ; CHECK-NEXT:    li 3, 42
-; CHECK-NEXT:    isel 3, 3, 4, 0
+; CHECK-NEXT:    isellt 3, 3, 4
 ; CHECK-NEXT:    blr
   %c = icmp slt i32 %x, 0
   %r = select i1 %c, i32 42, i32 41
   ret i32 %r
 }
 
 define i32 @sext_ifneg(i32 %x) {
 ; CHECK-LABEL: sext_ifneg:

 }
 
 define i32 @sel_ifneg_fval_bigger(i32 %x) {
 ; CHECK-LABEL: sel_ifneg_fval_bigger:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    li 4, 42
 ; CHECK-NEXT:    cmpwi 3, 0
 ; CHECK-NEXT:    li 3, 41
-; CHECK-NEXT:    isel 3, 3, 4, 0
+; CHECK-NEXT:    isellt 3, 3, 4
 ; CHECK-NEXT:    blr
   %c = icmp slt i32 %x, 0
   %r = select i1 %c, i32 41, i32 42
   ret i32 %r
 }
 
 define i32 @add_lshr_not(i32 %x) {
 ; CHECK-LABEL: add_lshr_not:

llvm/test/CodeGen/PowerPC/sms-cpy-1.ll

 ; CHECK-NEXT:    mflr 0
 ; CHECK-NEXT:    std 0, 16(1)
 ; CHECK-NEXT:    stdu 1, -128(1)
 ; CHECK-NEXT:    lwz 3, 0(3)
 ; CHECK-NEXT:    addi 3, 3, -1
 ; CHECK-NEXT:    clrldi 4, 3, 32
 ; CHECK-NEXT:    cmplwi 3, 1
 ; CHECK-NEXT:    li 3, 1
-; CHECK-NEXT:    isel 3, 4, 3, 1
+; CHECK-NEXT:    iselgt 3, 4, 3
 ; CHECK-NEXT:    li 4, 2
 ; CHECK-NEXT:    addi 3, 3, -1
 ; CHECK-NEXT:    cmpldi 3, 2
-; CHECK-NEXT:    isel 3, 3, 4, 0
+; CHECK-NEXT:    isellt 3, 3, 4
 ; CHECK-NEXT:    li 4, 0
 ; CHECK-NEXT:    addi 3, 3, 1
 ; CHECK-NEXT:    li 5, 0
 ; CHECK-NEXT:    li 7, -1
 ; CHECK-NEXT:    mtctr 3
 ; CHECK-NEXT:    lbz 5, 0(5)
 ; CHECK-NEXT:    li 3, 1
 ; CHECK-NEXT:    bdz .LBB0_6
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    xori 6, 5, 84
 ; CHECK-NEXT:    clrldi 5, 7, 32
 ; CHECK-NEXT:    lbz 5, 0(5)
 ; CHECK-NEXT:    addi 3, 3, 1
 ; CHECK-NEXT:    addi 8, 7, -1
 ; CHECK-NEXT:    bdz .LBB0_5
 ; CHECK-NEXT:  # %bb.2:
 ; CHECK-NEXT:    cntlzw 6, 6
 ; CHECK-NEXT:    srwi 7, 6, 5
 ; CHECK-NEXT:    xori 6, 5, 84
 ; CHECK-NEXT:    clrldi 5, 8, 32
 ; CHECK-NEXT:    addi 8, 8, -1
 ; CHECK-NEXT:    lbz 5, 0(5)
 ; CHECK-NEXT:    addi 3, 3, 1
 ; CHECK-NEXT:    bdz .LBB0_4
-; CHECK-NEXT:  .LBB0_3: #
+; CHECK-NEXT:  .LBB0_3:
 ; CHECK-NEXT:    clrldi 10, 8, 32
 ; CHECK-NEXT:    cntlzw 9, 6
 ; CHECK-NEXT:    xori 6, 5, 84
 ; CHECK-NEXT:    lbz 5, 0(10)
 ; CHECK-NEXT:    addi 8, 8, -1
 ; CHECK-NEXT:    addi 3, 3, 1
 ; CHECK-NEXT:    add 4, 4, 7
 ; CHECK-NEXT:    srwi 7, 9, 5

llvm/test/CodeGen/PowerPC/sms-phi-2.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs\
 ; RUN:       -mcpu=pwr9 --ppc-enable-pipeliner 2>&1 | FileCheck %s
 
 define void @phi2(i32, i32, i8*) local_unnamed_addr {
 ; CHECK-LABEL: phi2:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    divw 8, 3, 4
 ; CHECK-NEXT:    li 5, 55
 ; CHECK-NEXT:    li 6, 48
 ; CHECK-NEXT:    mtctr 3
 ; CHECK-NEXT:    bdz .LBB0_4
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    divw 9, 8, 4
 ; CHECK-NEXT:    mullw 7, 8, 4
-; CHECK-NEXT:    subf 3, 7, 3
+; CHECK-NEXT:    sub 3, 3, 7
 ; CHECK-NEXT:    cmplwi 3, 10
-; CHECK-NEXT:    isel 7, 6, 5, 0
+; CHECK-NEXT:    isellt 7, 6, 5
 ; CHECK-NEXT:    add 3, 7, 3
 ; CHECK-NEXT:    stbu 3, -1(7)
 ; CHECK-NEXT:    mr 3, 8
 ; CHECK-NEXT:    bdz .LBB0_3
 ; CHECK-NEXT:    .p2align 4
-; CHECK-NEXT:  .LBB0_2: #
+; CHECK-NEXT:  .LBB0_2:
 ; CHECK-NEXT:    mr 3, 9
 ; CHECK-NEXT:    mullw 9, 9, 4
 ; CHECK-NEXT:    divw 10, 3, 4
-; CHECK-NEXT:    subf 8, 9, 8
+; CHECK-NEXT:    sub 8, 8, 9
 ; CHECK-NEXT:    cmplwi 8, 10
-; CHECK-NEXT:    isel 9, 6, 5, 0
+; CHECK-NEXT:    isellt 9, 6, 5
 ; CHECK-NEXT:    add 8, 9, 8
 ; CHECK-NEXT:    mr 9, 10
 ; CHECK-NEXT:    stbu 8, -1(7)
 ; CHECK-NEXT:    mr 8, 3
 ; CHECK-NEXT:    bdnz .LBB0_2
 ; CHECK-NEXT:  .LBB0_3:
 ; CHECK-NEXT:    mr 8, 9
 ; CHECK-NEXT:    b .LBB0_5
 ; CHECK-NEXT:  .LBB0_4:
 ; CHECK-NEXT:    # implicit-def: $x7
 ; CHECK-NEXT:  .LBB0_5:
 ; CHECK-NEXT:    mullw 4, 8, 4
-; CHECK-NEXT:    subf 3, 4, 3
+; CHECK-NEXT:    sub 3, 3, 4
 ; CHECK-NEXT:    cmplwi 3, 10
-; CHECK-NEXT:    isel 4, 6, 5, 0
+; CHECK-NEXT:    isellt 4, 6, 5
 ; CHECK-NEXT:    add 3, 4, 3
 ; CHECK-NEXT:    stbu 3, -1(7)
 ; CHECK-NEXT:    blr
   br label %4
 
 4:                                                ; preds = %4, %3
   %5 = phi i64 [ %7, %4 ], [ undef, %3 ]
   %6 = phi i32 [ %8, %4 ], [ %0, %3 ]

llvm/test/CodeGen/PowerPC/spe.ll

 ; CHECK-NEXT:    efscmpeq 1, 4, 4
 ; CHECK-NEXT:    li 5, 1
 ; CHECK-NEXT:    crand 20, 5, 1
 ; CHECK-NEXT:    bc 12, 20, .LBB13_2
 ; CHECK-NEXT:  # %bb.1: # %entry
 ; CHECK-NEXT:    ori 3, 5, 0
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB13_2: # %entry
-; CHECK-NEXT:    addi 3, 0, 0
+; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    blr
   entry:
   %r = fcmp uno float %a, %b
   ret i1 %r
 }
 
 define i1 @test_fcmpord(float %a, float %b) {
 ; CHECK-LABEL: test_fcmpord:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    efscmpeq 0, 4, 4
 ; CHECK-NEXT:    efscmpeq 1, 3, 3
 ; CHECK-NEXT:    li 5, 1
 ; CHECK-NEXT:    crnand 20, 5, 1
 ; CHECK-NEXT:    bc 12, 20, .LBB14_2
 ; CHECK-NEXT:  # %bb.1: # %entry
 ; CHECK-NEXT:    ori 3, 5, 0
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB14_2: # %entry
-; CHECK-NEXT:    addi 3, 0, 0
+; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    blr
   entry:
   %r = fcmp ord float %a, %b
   ret i1 %r
 }
 
 define i1 @test_fcmpueq(float %a, float %b) {
 ; CHECK-LABEL: test_fcmpueq:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    efscmpeq 0, 3, 3
 ; CHECK-NEXT:    efscmpeq 1, 4, 4
 ; CHECK-NEXT:    crnand 20, 5, 1
 ; CHECK-NEXT:    efscmpeq 0, 3, 4
 ; CHECK-NEXT:    li 5, 1
 ; CHECK-NEXT:    crnor 20, 1, 20
 ; CHECK-NEXT:    bc 12, 20, .LBB15_2
 ; CHECK-NEXT:  # %bb.1: # %entry
 ; CHECK-NEXT:    ori 3, 5, 0
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB15_2: # %entry
-; CHECK-NEXT:    addi 3, 0, 0
+; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    blr
   entry:
   %r = fcmp ueq float %a, %b
   ret i1 %r
 }
 
 define i1 @test_fcmpne(float %a, float %b) {
 ; CHECK-LABEL: test_fcmpne:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    efscmpeq 0, 4, 4
 ; CHECK-NEXT:    efscmpeq 1, 3, 3
 ; CHECK-NEXT:    crand 20, 5, 1
 ; CHECK-NEXT:    efscmpeq 0, 3, 4
 ; CHECK-NEXT:    li 5, 1
 ; CHECK-NEXT:    crorc 20, 1, 20
 ; CHECK-NEXT:    bc 12, 20, .LBB16_2
 ; CHECK-NEXT:  # %bb.1: # %entry
 ; CHECK-NEXT:    ori 3, 5, 0
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB16_2: # %entry
-; CHECK-NEXT:    addi 3, 0, 0
+; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    blr
   entry:
   %r = fcmp one float %a, %b
   ret i1 %r
 }
 
 define i32 @test_fcmpune(float %a, float %b) {
 ; CHECK-LABEL: test_fcmpune:

 ; CHECK-NEXT:    efscmplt 0, 3, 4
 ; CHECK-NEXT:    li 5, 1
 ; CHECK-NEXT:    crnor 20, 1, 20
 ; CHECK-NEXT:    bc 12, 20, .LBB19_2
 ; CHECK-NEXT:  # %bb.1: # %entry
 ; CHECK-NEXT:    ori 3, 5, 0
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB19_2: # %entry
-; CHECK-NEXT:    addi 3, 0, 0
+; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    blr
   entry:
   %r = fcmp ult float %a, %b
   ret i1 %r
 }
 
 define i32 @test_fcmpge(float %a, float %b) {
 ; CHECK-LABEL: test_fcmpge:

 ; CHECK-NEXT:    efdcmpeq 0, 3, 3
 ; CHECK-NEXT:    efdcmpeq 1, 5, 5
 ; CHECK-NEXT:    crand 20, 5, 1
 ; CHECK-NEXT:    bc 12, 20, .LBB35_2
 ; CHECK-NEXT:  # %bb.1: # %entry
 ; CHECK-NEXT:    ori 3, 7, 0
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB35_2: # %entry
-; CHECK-NEXT:    addi 3, 0, 0
+; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    blr
   entry:
   %r = fcmp uno double %a, %b
   ret i1 %r
 }
 
 define i1 @test_dcmpord(double %a, double %b) {
 ; CHECK-LABEL: test_dcmpord:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    evmergelo 3, 3, 4
 ; CHECK-NEXT:    evmergelo 4, 5, 6
 ; CHECK-NEXT:    li 7, 1
 ; CHECK-NEXT:    efdcmpeq 0, 4, 4
 ; CHECK-NEXT:    efdcmpeq 1, 3, 3
 ; CHECK-NEXT:    crnand 20, 5, 1
 ; CHECK-NEXT:    bc 12, 20, .LBB36_2
 ; CHECK-NEXT:  # %bb.1: # %entry
 ; CHECK-NEXT:    ori 3, 7, 0
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB36_2: # %entry
-; CHECK-NEXT:    addi 3, 0, 0
+; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    blr
   entry:
   %r = fcmp ord double %a, %b
   ret i1 %r
 }
 
 define i32 @test_dcmpgt(double %a, double %b) {
 ; CHECK-LABEL: test_dcmpgt:

 ; CHECK-NEXT:    efdcmpeq 5, 3, 4
 ; CHECK-NEXT:    crand 24, 5, 1
 ; CHECK-NEXT:    crorc 20, 21, 24
 ; CHECK-NEXT:    bc 12, 20, .LBB43_2
 ; CHECK-NEXT:  # %bb.1: # %entry
 ; CHECK-NEXT:    ori 3, 7, 0
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB43_2: # %entry
-; CHECK-NEXT:    addi 3, 0, 0
+; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    blr
   entry:
   %r = fcmp one double %a, %b
   ret i1 %r
 }
 
 define i32 @test_dcmpune(double %a, double %b) {
 ; CHECK-LABEL: test_dcmpune:

 ; CHECK-NEXT:    efdcmplt 5, 3, 4
 ; CHECK-NEXT:    crand 24, 5, 1
 ; CHECK-NEXT:    crorc 20, 21, 24
 ; CHECK-NEXT:    bc 12, 20, .LBB47_2
 ; CHECK-NEXT:  # %bb.1: # %entry
 ; CHECK-NEXT:    ori 3, 7, 0
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB47_2: # %entry
-; CHECK-NEXT:    addi 3, 0, 0
+; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    blr
   entry:
   %r = fcmp oge double %a, %b
   ret i1 %r
 }
 
 define i32 @test_dcmpuge(double %a, double %b) {
 ; CHECK-LABEL: test_dcmpuge:

llvm/test/CodeGen/PowerPC/srem-lkk.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu -mcpu=ppc64 < %s | FileCheck -check-prefixes=CHECK,CHECK64 %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu -mcpu=ppc < %s | FileCheck -check-prefixes=CHECK,CHECK32 %s
 
 define i32 @fold_srem_positive_odd(i32 %x) {
 ; CHECK-LABEL: fold_srem_positive_odd:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lis 4, -21386
 ; CHECK-NEXT:    ori 4, 4, 37253
 ; CHECK-NEXT:    mulhw 4, 3, 4
 ; CHECK-NEXT:    add 4, 4, 3
 ; CHECK-NEXT:    srwi 5, 4, 31
 ; CHECK-NEXT:    srawi 4, 4, 6
 ; CHECK-NEXT:    add 4, 4, 5
 ; CHECK-NEXT:    mulli 4, 4, 95
-; CHECK-NEXT:    subf 3, 4, 3
+; CHECK-NEXT:    sub 3, 3, 4
 ; CHECK-NEXT:    blr
   %1 = srem i32 %x, 95
   ret i32 %1
 }
 
 
 define i32 @fold_srem_positive_even(i32 %x) {
 ; CHECK-LABEL: fold_srem_positive_even:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lis 4, 15827
 ; CHECK-NEXT:    ori 4, 4, 36849
 ; CHECK-NEXT:    mulhw 4, 3, 4
 ; CHECK-NEXT:    srwi 5, 4, 31
 ; CHECK-NEXT:    srawi 4, 4, 8
 ; CHECK-NEXT:    add 4, 4, 5
 ; CHECK-NEXT:    mulli 4, 4, 1060
-; CHECK-NEXT:    subf 3, 4, 3
+; CHECK-NEXT:    sub 3, 3, 4
 ; CHECK-NEXT:    blr
   %1 = srem i32 %x, 1060
   ret i32 %1
 }
 
 
 define i32 @fold_srem_negative_odd(i32 %x) {
 ; CHECK-LABEL: fold_srem_negative_odd:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lis 4, -23206
 ; CHECK-NEXT:    ori 4, 4, 65445
 ; CHECK-NEXT:    mulhw 4, 3, 4
 ; CHECK-NEXT:    srwi 5, 4, 31
 ; CHECK-NEXT:    srawi 4, 4, 8
 ; CHECK-NEXT:    add 4, 4, 5
 ; CHECK-NEXT:    mulli 4, 4, -723
-; CHECK-NEXT:    subf 3, 4, 3
+; CHECK-NEXT:    sub 3, 3, 4
 ; CHECK-NEXT:    blr
   %1 = srem i32 %x, -723
   ret i32 %1
 }
 
 
 define i32 @fold_srem_negative_even(i32 %x) {
 ; CHECK-LABEL: fold_srem_negative_even:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lis 4, -731
 ; CHECK-NEXT:    ori 4, 4, 62439
 ; CHECK-NEXT:    mulhw 4, 3, 4
 ; CHECK-NEXT:    srwi 5, 4, 31
 ; CHECK-NEXT:    srawi 4, 4, 8
 ; CHECK-NEXT:    add 4, 4, 5
 ; CHECK-NEXT:    mulli 4, 4, -22981
-; CHECK-NEXT:    subf 3, 4, 3
+; CHECK-NEXT:    sub 3, 3, 4
 ; CHECK-NEXT:    blr
   %1 = srem i32 %x, -22981
   ret i32 %1
 }
 
 
 ; Don't fold if we can combine srem with sdiv.
 define i32 @combine_srem_sdiv(i32 %x) {
 ; CHECK-LABEL: combine_srem_sdiv:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lis 4, -21386
 ; CHECK-NEXT:    ori 4, 4, 37253
 ; CHECK-NEXT:    mulhw 4, 3, 4
 ; CHECK-NEXT:    add 4, 4, 3
 ; CHECK-NEXT:    srwi 5, 4, 31
 ; CHECK-NEXT:    srawi 4, 4, 6
 ; CHECK-NEXT:    add 4, 4, 5
 ; CHECK-NEXT:    mulli 5, 4, 95
-; CHECK-NEXT:    subf 3, 5, 3
+; CHECK-NEXT:    sub 3, 3, 5
 ; CHECK-NEXT:    add 3, 3, 4
 ; CHECK-NEXT:    blr
   %1 = srem i32 %x, 95
   %2 = sdiv i32 %x, 95
   %3 = add i32 %1, %2
   ret i32 %3
 }
 
 ; Don't fold for divisors that are a power of two.
 define i32 @dont_fold_srem_power_of_two(i32 %x) {
 ; CHECK-LABEL: dont_fold_srem_power_of_two:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    srawi 4, 3, 6
 ; CHECK-NEXT:    addze 4, 4
 ; CHECK-NEXT:    slwi 4, 4, 6
-; CHECK-NEXT:    subf 3, 4, 3
+; CHECK-NEXT:    sub 3, 3, 4
 ; CHECK-NEXT:    blr
   %1 = srem i32 %x, 64
   ret i32 %1
 }
 
 ; Don't fold if the divisor is one.
 define i32 @dont_fold_srem_one(i32 %x) {
 ; CHECK-LABEL: dont_fold_srem_one:

llvm/test/CodeGen/PowerPC/srem-vector-lkk.ll

 ; P9LE-NEXT:    extsh r4, r3
 ; P9LE-NEXT:    mulhw r5, r4, r5
 ; P9LE-NEXT:    add r4, r5, r4
 ; P9LE-NEXT:    srwi r5, r4, 31
 ; P9LE-NEXT:    srawi r4, r4, 6
 ; P9LE-NEXT:    add r4, r4, r5
 ; P9LE-NEXT:    lis r5, 31710
 ; P9LE-NEXT:    mulli r4, r4, 95
-; P9LE-NEXT:    subf r3, r4, r3
+; P9LE-NEXT:    sub r3, r3, r4
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 2
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    extsh r4, r3
 ; P9LE-NEXT:    ori r5, r5, 63421
 ; P9LE-NEXT:    mulhw r5, r4, r5
-; P9LE-NEXT:    subf r4, r4, r5
+; P9LE-NEXT:    sub r4, r5, r4
 ; P9LE-NEXT:    srwi r5, r4, 31
 ; P9LE-NEXT:    srawi r4, r4, 6
 ; P9LE-NEXT:    add r4, r4, r5
 ; P9LE-NEXT:    lis r5, 21399
 ; P9LE-NEXT:    mulli r4, r4, -124
-; P9LE-NEXT:    subf r3, r4, r3
+; P9LE-NEXT:    sub r3, r3, r4
 ; P9LE-NEXT:    xxswapd v3, vs0
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 4
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    extsh r4, r3
 ; P9LE-NEXT:    ori r5, r5, 33437
 ; P9LE-NEXT:    mulhw r4, r4, r5
 ; P9LE-NEXT:    srwi r5, r4, 31
 ; P9LE-NEXT:    srawi r4, r4, 5
 ; P9LE-NEXT:    add r4, r4, r5
 ; P9LE-NEXT:    lis r5, -16728
 ; P9LE-NEXT:    mulli r4, r4, 98
-; P9LE-NEXT:    subf r3, r4, r3
+; P9LE-NEXT:    sub r3, r3, r4
 ; P9LE-NEXT:    xxswapd v4, vs0
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 6
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    extsh r4, r3
 ; P9LE-NEXT:    ori r5, r5, 63249
 ; P9LE-NEXT:    mulhw r4, r4, r5
 ; P9LE-NEXT:    srwi r5, r4, 31
 ; P9LE-NEXT:    srawi r4, r4, 8
 ; P9LE-NEXT:    add r4, r4, r5
 ; P9LE-NEXT:    mulli r4, r4, -1003
-; P9LE-NEXT:    subf r3, r4, r3
+; P9LE-NEXT:    sub r3, r3, r4
 ; P9LE-NEXT:    vmrglh v3, v4, v3
 ; P9LE-NEXT:    xxswapd v4, vs0
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    xxswapd v2, vs0
 ; P9LE-NEXT:    vmrglh v2, v2, v4
 ; P9LE-NEXT:    vmrglw v2, v2, v3
 ; P9LE-NEXT:    blr
 ;
 ; P9BE-LABEL: fold_srem_vec_1:
 ; P9BE:       # %bb.0:
 ; P9BE-NEXT:    li r3, 2
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    lis r4, 31710
 ; P9BE-NEXT:    ori r4, r4, 63421
 ; P9BE-NEXT:    extsh r3, r3
 ; P9BE-NEXT:    mulhw r4, r3, r4
-; P9BE-NEXT:    subf r4, r3, r4
+; P9BE-NEXT:    sub r4, r4, r3
 ; P9BE-NEXT:    srwi r5, r4, 31
 ; P9BE-NEXT:    srawi r4, r4, 6
 ; P9BE-NEXT:    add r4, r4, r5
 ; P9BE-NEXT:    mulli r4, r4, -124
-; P9BE-NEXT:    subf r3, r4, r3
+; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    lis r4, -21386
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v3, r3
 ; P9BE-NEXT:    li r3, 0
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    extsh r3, r3
 ; P9BE-NEXT:    ori r4, r4, 37253
 ; P9BE-NEXT:    mulhw r4, r3, r4
 ; P9BE-NEXT:    add r4, r4, r3
 ; P9BE-NEXT:    srwi r5, r4, 31
 ; P9BE-NEXT:    srawi r4, r4, 6
 ; P9BE-NEXT:    add r4, r4, r5
 ; P9BE-NEXT:    mulli r4, r4, 95
-; P9BE-NEXT:    subf r3, r4, r3
+; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    lis r4, -16728
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v4, r3
 ; P9BE-NEXT:    li r3, 6
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    extsh r3, r3
 ; P9BE-NEXT:    ori r4, r4, 63249
 ; P9BE-NEXT:    mulhw r4, r3, r4
 ; P9BE-NEXT:    srwi r5, r4, 31
 ; P9BE-NEXT:    srawi r4, r4, 8
 ; P9BE-NEXT:    add r4, r4, r5
 ; P9BE-NEXT:    mulli r4, r4, -1003
-; P9BE-NEXT:    subf r3, r4, r3
+; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    lis r4, 21399
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    vmrghh v3, v4, v3
 ; P9BE-NEXT:    mtvsrd v4, r3
 ; P9BE-NEXT:    li r3, 4
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    extsh r3, r3
 ; P9BE-NEXT:    ori r4, r4, 33437
 ; P9BE-NEXT:    mulhw r4, r3, r4
 ; P9BE-NEXT:    srwi r5, r4, 31
 ; P9BE-NEXT:    srawi r4, r4, 5
 ; P9BE-NEXT:    add r4, r4, r5
 ; P9BE-NEXT:    mulli r4, r4, 98
-; P9BE-NEXT:    subf r3, r4, r3
+; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v2, r3
 ; P9BE-NEXT:    vmrghh v2, v2, v4
 ; P9BE-NEXT:    vmrghw v2, v3, v2
 ; P9BE-NEXT:    blr
 ;
 ; P8LE-LABEL: fold_srem_vec_1:
 ; P8LE:       # %bb.0:

 ; P8LE-NEXT:    extsh r11, r4
 ; P8LE-NEXT:    extsh r12, r6
 ; P8LE-NEXT:    mulhw r9, r0, r9
 ; P8LE-NEXT:    mulhw r10, r11, r10
 ; P8LE-NEXT:    mulhw r8, r12, r8
 ; P8LE-NEXT:    srwi r12, r3, 31
 ; P8LE-NEXT:    srawi r3, r3, 5
 ; P8LE-NEXT:    add r9, r9, r0
-; P8LE-NEXT:    subf r10, r11, r10
+; P8LE-NEXT:    sub r10, r10, r11
 ; P8LE-NEXT:    add r3, r3, r12
 ; P8LE-NEXT:    srwi r11, r9, 31
 ; P8LE-NEXT:    srawi r9, r9, 6
 ; P8LE-NEXT:    srwi r12, r8, 31
 ; P8LE-NEXT:    srawi r8, r8, 8
 ; P8LE-NEXT:    add r9, r9, r11
 ; P8LE-NEXT:    srwi r11, r10, 31
 ; P8LE-NEXT:    srawi r10, r10, 6
 ; P8LE-NEXT:    add r8, r8, r12
 ; P8LE-NEXT:    mulli r3, r3, 98
 ; P8LE-NEXT:    add r10, r10, r11
 ; P8LE-NEXT:    mulli r8, r8, -1003
 ; P8LE-NEXT:    mulli r9, r9, 95
 ; P8LE-NEXT:    mulli r10, r10, -124
-; P8LE-NEXT:    subf r3, r3, r5
-; P8LE-NEXT:    subf r5, r8, r6
+; P8LE-NEXT:    sub r3, r5, r3
+; P8LE-NEXT:    sub r5, r6, r8
 ; P8LE-NEXT:    mtfprd f0, r3
-; P8LE-NEXT:    subf r3, r9, r7
-; P8LE-NEXT:    subf r4, r10, r4
+; P8LE-NEXT:    sub r3, r7, r9
+; P8LE-NEXT:    sub r4, r4, r10
 ; P8LE-NEXT:    mtfprd f1, r5
 ; P8LE-NEXT:    mtfprd f2, r3
 ; P8LE-NEXT:    xxswapd v2, vs0
 ; P8LE-NEXT:    mtfprd f3, r4
 ; P8LE-NEXT:    xxswapd v3, vs1
 ; P8LE-NEXT:    xxswapd v4, vs2
 ; P8LE-NEXT:    xxswapd v5, vs3
 ; P8LE-NEXT:    vmrglh v2, v3, v2

 ; P8BE-NEXT:    extsh r4, r4
 ; P8BE-NEXT:    mulhw r8, r6, r8
 ; P8BE-NEXT:    mulhw r9, r7, r9
 ; P8BE-NEXT:    mulhw r10, r4, r10
 ; P8BE-NEXT:    srwi r11, r3, 31
 ; P8BE-NEXT:    srawi r3, r3, 8
 ; P8BE-NEXT:    add r3, r3, r11
 ; P8BE-NEXT:    srwi r11, r8, 31
-; P8BE-NEXT:    subf r9, r7, r9
+; P8BE-NEXT:    sub r9, r9, r7
 ; P8BE-NEXT:    srawi r8, r8, 5
 ; P8BE-NEXT:    add r10, r10, r4
 ; P8BE-NEXT:    add r8, r8, r11
 ; P8BE-NEXT:    srwi r11, r9, 31
 ; P8BE-NEXT:    srawi r9, r9, 6
 ; P8BE-NEXT:    mulli r3, r3, -1003
 ; P8BE-NEXT:    add r9, r9, r11
 ; P8BE-NEXT:    srwi r11, r10, 31
 ; P8BE-NEXT:    srawi r10, r10, 6
 ; P8BE-NEXT:    mulli r8, r8, 98
 ; P8BE-NEXT:    add r10, r10, r11
 ; P8BE-NEXT:    mulli r9, r9, -124
 ; P8BE-NEXT:    mulli r10, r10, 95
-; P8BE-NEXT:    subf r3, r3, r5
+; P8BE-NEXT:    sub r3, r5, r3
 ; P8BE-NEXT:    sldi r3, r3, 48
-; P8BE-NEXT:    subf r5, r8, r6
+; P8BE-NEXT:    sub r5, r6, r8
 ; P8BE-NEXT:    mtvsrd v2, r3
-; P8BE-NEXT:    subf r6, r9, r7
+; P8BE-NEXT:    sub r6, r7, r9
 ; P8BE-NEXT:    sldi r3, r5, 48
-; P8BE-NEXT:    subf r4, r10, r4
+; P8BE-NEXT:    sub r4, r4, r10
 ; P8BE-NEXT:    mtvsrd v3, r3
 ; P8BE-NEXT:    sldi r3, r6, 48
 ; P8BE-NEXT:    sldi r4, r4, 48
 ; P8BE-NEXT:    mtvsrd v4, r3
 ; P8BE-NEXT:    mtvsrd v5, r4
 ; P8BE-NEXT:    vmrghh v2, v3, v2
 ; P8BE-NEXT:    vmrghh v3, v5, v4
 ; P8BE-NEXT:    vmrghw v2, v3, v2

 ; P9LE-NEXT:    ori r5, r5, 37253
 ; P9LE-NEXT:    extsh r4, r3
 ; P9LE-NEXT:    mulhw r6, r4, r5
 ; P9LE-NEXT:    add r4, r6, r4
 ; P9LE-NEXT:    srwi r6, r4, 31
 ; P9LE-NEXT:    srawi r4, r4, 6
 ; P9LE-NEXT:    add r4, r4, r6
 ; P9LE-NEXT:    mulli r4, r4, 95
-; P9LE-NEXT:    subf r3, r4, r3
+; P9LE-NEXT:    sub r3, r3, r4
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 2
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    extsh r4, r3
 ; P9LE-NEXT:    mulhw r6, r4, r5
 ; P9LE-NEXT:    add r4, r6, r4
 ; P9LE-NEXT:    srwi r6, r4, 31
 ; P9LE-NEXT:    srawi r4, r4, 6
 ; P9LE-NEXT:    add r4, r4, r6
 ; P9LE-NEXT:    mulli r4, r4, 95
-; P9LE-NEXT:    subf r3, r4, r3
+; P9LE-NEXT:    sub r3, r3, r4
 ; P9LE-NEXT:    xxswapd v3, vs0
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 4
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    extsh r4, r3
 ; P9LE-NEXT:    mulhw r6, r4, r5
 ; P9LE-NEXT:    add r4, r6, r4
 ; P9LE-NEXT:    srwi r6, r4, 31
 ; P9LE-NEXT:    srawi r4, r4, 6
 ; P9LE-NEXT:    add r4, r4, r6
 ; P9LE-NEXT:    mulli r4, r4, 95
-; P9LE-NEXT:    subf r3, r4, r3
+; P9LE-NEXT:    sub r3, r3, r4
 ; P9LE-NEXT:    xxswapd v4, vs0
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 6
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    extsh r4, r3
 ; P9LE-NEXT:    mulhw r5, r4, r5
 ; P9LE-NEXT:    add r4, r5, r4
 ; P9LE-NEXT:    srwi r5, r4, 31
 ; P9LE-NEXT:    srawi r4, r4, 6
 ; P9LE-NEXT:    add r4, r4, r5
 ; P9LE-NEXT:    mulli r4, r4, 95
-; P9LE-NEXT:    subf r3, r4, r3
+; P9LE-NEXT:    sub r3, r3, r4
 ; P9LE-NEXT:    vmrglh v3, v4, v3
 ; P9LE-NEXT:    xxswapd v4, vs0
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    xxswapd v2, vs0
 ; P9LE-NEXT:    vmrglh v2, v2, v4
 ; P9LE-NEXT:    vmrglw v2, v2, v3
 ; P9LE-NEXT:    blr
 ;
 ; P9BE-LABEL: fold_srem_vec_2:
 ; P9BE:       # %bb.0:
 ; P9BE-NEXT:    li r3, 6
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    lis r4, -21386
 ; P9BE-NEXT:    ori r4, r4, 37253
 ; P9BE-NEXT:    extsh r3, r3
 ; P9BE-NEXT:    mulhw r5, r3, r4
 ; P9BE-NEXT:    add r5, r5, r3
 ; P9BE-NEXT:    srwi r6, r5, 31
 ; P9BE-NEXT:    srawi r5, r5, 6
 ; P9BE-NEXT:    add r5, r5, r6
 ; P9BE-NEXT:    mulli r5, r5, 95
-; P9BE-NEXT:    subf r3, r5, r3
+; P9BE-NEXT:    sub r3, r3, r5
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v3, r3
 ; P9BE-NEXT:    li r3, 4
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    extsh r3, r3
 ; P9BE-NEXT:    mulhw r5, r3, r4
 ; P9BE-NEXT:    add r5, r5, r3
 ; P9BE-NEXT:    srwi r6, r5, 31
 ; P9BE-NEXT:    srawi r5, r5, 6
 ; P9BE-NEXT:    add r5, r5, r6
 ; P9BE-NEXT:    mulli r5, r5, 95
-; P9BE-NEXT:    subf r3, r5, r3
+; P9BE-NEXT:    sub r3, r3, r5
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v4, r3
 ; P9BE-NEXT:    li r3, 2
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    extsh r3, r3
 ; P9BE-NEXT:    mulhw r5, r3, r4
 ; P9BE-NEXT:    add r5, r5, r3
 ; P9BE-NEXT:    srwi r6, r5, 31
 ; P9BE-NEXT:    srawi r5, r5, 6
 ; P9BE-NEXT:    add r5, r5, r6
 ; P9BE-NEXT:    mulli r5, r5, 95
-; P9BE-NEXT:    subf r3, r5, r3
+; P9BE-NEXT:    sub r3, r3, r5
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    vmrghh v3, v4, v3
 ; P9BE-NEXT:    mtvsrd v4, r3
 ; P9BE-NEXT:    li r3, 0
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    extsh r3, r3
 ; P9BE-NEXT:    mulhw r4, r3, r4
 ; P9BE-NEXT:    add r4, r4, r3
 ; P9BE-NEXT:    srwi r5, r4, 31
 ; P9BE-NEXT:    srawi r4, r4, 6
 ; P9BE-NEXT:    add r4, r4, r5
 ; P9BE-NEXT:    mulli r4, r4, 95
-; P9BE-NEXT:    subf r3, r4, r3
+; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v2, r3
 ; P9BE-NEXT:    vmrghh v2, v2, v4
 ; P9BE-NEXT:    vmrghw v2, v2, v3
 ; P9BE-NEXT:    blr
 ;
 ; P8LE-LABEL: fold_srem_vec_2:
 ; P8LE:       # %bb.0:

 ; P8LE-NEXT:    add r9, r9, r10
 ; P8LE-NEXT:    srwi r10, r11, 31
 ; P8LE-NEXT:    srawi r11, r11, 6
 ; P8LE-NEXT:    mulli r9, r9, 95
 ; P8LE-NEXT:    add r10, r11, r10
 ; P8LE-NEXT:    srwi r11, r3, 31
 ; P8LE-NEXT:    srawi r3, r3, 6
 ; P8LE-NEXT:    mulli r10, r10, 95
-; P8LE-NEXT:    subf r5, r8, r5
+; P8LE-NEXT:    sub r5, r5, r8
 ; P8LE-NEXT:    add r3, r3, r11
 ; P8LE-NEXT:    mtfprd f0, r5
 ; P8LE-NEXT:    mulli r3, r3, 95
-; P8LE-NEXT:    subf r6, r9, r6
+; P8LE-NEXT:    sub r6, r6, r9
 ; P8LE-NEXT:    mtfprd f1, r6
 ; P8LE-NEXT:    xxswapd v2, vs0
-; P8LE-NEXT:    subf r5, r10, r7
+; P8LE-NEXT:    sub r5, r7, r10
 ; P8LE-NEXT:    mtfprd f2, r5
 ; P8LE-NEXT:    xxswapd v3, vs1
-; P8LE-NEXT:    subf r3, r3, r4
+; P8LE-NEXT:    sub r3, r4, r3
 ; P8LE-NEXT:    mtfprd f3, r3
 ; P8LE-NEXT:    xxswapd v4, vs2
 ; P8LE-NEXT:    vmrglh v2, v3, v2
 ; P8LE-NEXT:    xxswapd v5, vs3
 ; P8LE-NEXT:    vmrglh v3, v5, v4
 ; P8LE-NEXT:    vmrglw v2, v3, v2
 ; P8LE-NEXT:    blr
 ;

 ; P8BE-NEXT:    add r9, r9, r11
 ; P8BE-NEXT:    srwi r11, r10, 31
 ; P8BE-NEXT:    srawi r10, r10, 6
 ; P8BE-NEXT:    mulli r9, r9, 95
 ; P8BE-NEXT:    add r10, r10, r11
 ; P8BE-NEXT:    srwi r11, r3, 31
 ; P8BE-NEXT:    srawi r3, r3, 6
 ; P8BE-NEXT:    mulli r10, r10, 95
-; P8BE-NEXT:    subf r5, r8, r5
+; P8BE-NEXT:    sub r5, r5, r8
 ; P8BE-NEXT:    add r3, r3, r11
 ; P8BE-NEXT:    sldi r5, r5, 48
 ; P8BE-NEXT:    mulli r3, r3, 95
-; P8BE-NEXT:    subf r6, r9, r6
+; P8BE-NEXT:    sub r6, r6, r9
 ; P8BE-NEXT:    mtvsrd v2, r5
 ; P8BE-NEXT:    sldi r6, r6, 48
-; P8BE-NEXT:    subf r7, r10, r7
+; P8BE-NEXT:    sub r7, r7, r10
 ; P8BE-NEXT:    mtvsrd v3, r6
-; P8BE-NEXT:    subf r3, r3, r4
+; P8BE-NEXT:    sub r3, r4, r3
 ; P8BE-NEXT:    sldi r4, r7, 48
 ; P8BE-NEXT:    vmrghh v2, v3, v2
 ; P8BE-NEXT:    sldi r3, r3, 48
 ; P8BE-NEXT:    mtvsrd v4, r4
 ; P8BE-NEXT:    mtvsrd v5, r3
 ; P8BE-NEXT:    vmrghh v3, v5, v4
 ; P8BE-NEXT:    vmrghw v2, v3, v2
 ; P8BE-NEXT:    blr

 ; P9LE-NEXT:    ori r5, r5, 37253
 ; P9LE-NEXT:    extsh r4, r3
 ; P9LE-NEXT:    mulhw r6, r4, r5
 ; P9LE-NEXT:    add r4, r6, r4
 ; P9LE-NEXT:    srwi r6, r4, 31
 ; P9LE-NEXT:    srawi r4, r4, 6
 ; P9LE-NEXT:    add r4, r4, r6
 ; P9LE-NEXT:    mulli r6, r4, 95
-; P9LE-NEXT:    subf r3, r6, r3
+; P9LE-NEXT:    sub r3, r3, r6
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 2
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    extsh r6, r3
 ; P9LE-NEXT:    mulhw r7, r6, r5
 ; P9LE-NEXT:    add r6, r7, r6
 ; P9LE-NEXT:    srwi r7, r6, 31
 ; P9LE-NEXT:    srawi r6, r6, 6
 ; P9LE-NEXT:    add r6, r6, r7
 ; P9LE-NEXT:    mulli r7, r6, 95
-; P9LE-NEXT:    subf r3, r7, r3
+; P9LE-NEXT:    sub r3, r3, r7
 ; P9LE-NEXT:    xxswapd v3, vs0
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 4
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    extsh r7, r3
 ; P9LE-NEXT:    mulhw r8, r7, r5
 ; P9LE-NEXT:    add r7, r8, r7
 ; P9LE-NEXT:    srwi r8, r7, 31
 ; P9LE-NEXT:    srawi r7, r7, 6
 ; P9LE-NEXT:    add r7, r7, r8
 ; P9LE-NEXT:    mulli r8, r7, 95
-; P9LE-NEXT:    subf r3, r8, r3
+; P9LE-NEXT:    sub r3, r3, r8
 ; P9LE-NEXT:    xxswapd v4, vs0
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 6
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    extsh r8, r3
 ; P9LE-NEXT:    mulhw r5, r8, r5
 ; P9LE-NEXT:    add r5, r5, r8
 ; P9LE-NEXT:    srwi r8, r5, 31
 ; P9LE-NEXT:    srawi r5, r5, 6
 ; P9LE-NEXT:    add r5, r5, r8
 ; P9LE-NEXT:    mulli r8, r5, 95
-; P9LE-NEXT:    subf r3, r8, r3
+; P9LE-NEXT:    sub r3, r3, r8
 ; P9LE-NEXT:    vmrglh v3, v4, v3
 ; P9LE-NEXT:    xxswapd v4, vs0
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    xxswapd v2, vs0
 ; P9LE-NEXT:    mtfprd f0, r4
 ; P9LE-NEXT:    vmrglh v2, v2, v4
 ; P9LE-NEXT:    vmrglw v2, v2, v3
 ; P9LE-NEXT:    xxswapd v3, vs0

 ; P9BE-NEXT:    ori r5, r5, 37253
 ; P9BE-NEXT:    extsh r4, r3
 ; P9BE-NEXT:    mulhw r6, r4, r5
 ; P9BE-NEXT:    add r4, r6, r4
 ; P9BE-NEXT:    srwi r6, r4, 31
 ; P9BE-NEXT:    srawi r4, r4, 6
 ; P9BE-NEXT:    add r4, r4, r6
 ; P9BE-NEXT:    mulli r6, r4, 95
-; P9BE-NEXT:    subf r3, r6, r3
+; P9BE-NEXT:    sub r3, r3, r6
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v3, r3
 ; P9BE-NEXT:    li r3, 4
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    extsh r6, r3
 ; P9BE-NEXT:    mulhw r7, r6, r5
 ; P9BE-NEXT:    add r6, r7, r6
 ; P9BE-NEXT:    srwi r7, r6, 31
 ; P9BE-NEXT:    srawi r6, r6, 6
 ; P9BE-NEXT:    add r6, r6, r7
 ; P9BE-NEXT:    mulli r7, r6, 95
-; P9BE-NEXT:    subf r3, r7, r3
+; P9BE-NEXT:    sub r3, r3, r7
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v4, r3
 ; P9BE-NEXT:    li r3, 2
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    extsh r7, r3
 ; P9BE-NEXT:    mulhw r8, r7, r5
 ; P9BE-NEXT:    add r7, r8, r7
 ; P9BE-NEXT:    srwi r8, r7, 31
 ; P9BE-NEXT:    srawi r7, r7, 6
 ; P9BE-NEXT:    add r7, r7, r8
 ; P9BE-NEXT:    mulli r8, r7, 95
-; P9BE-NEXT:    subf r3, r8, r3
+; P9BE-NEXT:    sub r3, r3, r8
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    vmrghh v3, v4, v3
 ; P9BE-NEXT:    mtvsrd v4, r3
 ; P9BE-NEXT:    li r3, 0
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    extsh r3, r3
 ; P9BE-NEXT:    mulhw r5, r3, r5
 ; P9BE-NEXT:    add r5, r5, r3
 ; P9BE-NEXT:    srwi r8, r5, 31
 ; P9BE-NEXT:    srawi r5, r5, 6
 ; P9BE-NEXT:    add r5, r5, r8
 ; P9BE-NEXT:    mulli r8, r5, 95
-; P9BE-NEXT:    subf r3, r8, r3
+; P9BE-NEXT:    sub r3, r3, r8
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v2, r3
 ; P9BE-NEXT:    sldi r3, r4, 48
 ; P9BE-NEXT:    vmrghh v2, v2, v4
 ; P9BE-NEXT:    vmrghw v2, v2, v3
 ; P9BE-NEXT:    mtvsrd v3, r3
 ; P9BE-NEXT:    sldi r3, r6, 48
 ; P9BE-NEXT:    mtvsrd v4, r3

 ; P8LE-NEXT:    xxswapd v2, vs0
 ; P8LE-NEXT:    mtfprd f2, r10
 ; P8LE-NEXT:    mulli r9, r10, 95
 ; P8LE-NEXT:    add r4, r4, r8
 ; P8LE-NEXT:    xxswapd v3, vs1
 ; P8LE-NEXT:    mtfprd f3, r4
 ; P8LE-NEXT:    mulli r4, r4, 95
 ; P8LE-NEXT:    xxswapd v1, vs2
-; P8LE-NEXT:    subf r3, r12, r3
+; P8LE-NEXT:    sub r3, r3, r12
 ; P8LE-NEXT:    mtfprd f0, r3
-; P8LE-NEXT:    subf r6, r11, r6
+; P8LE-NEXT:    sub r6, r6, r11
 ; P8LE-NEXT:    xxswapd v6, vs3
-; P8LE-NEXT:    subf r3, r9, r7
+; P8LE-NEXT:    sub r3, r7, r9
 ; P8LE-NEXT:    mtfprd f1, r6
 ; P8LE-NEXT:    mtfprd f4, r3
-; P8LE-NEXT:    subf r3, r4, r5
+; P8LE-NEXT:    sub r3, r5, r4
 ; P8LE-NEXT:    mtfprd f5, r3
 ; P8LE-NEXT:    xxswapd v4, vs1
 ; P8LE-NEXT:    vmrglh v2, v3, v2
 ; P8LE-NEXT:    xxswapd v3, vs0
 ; P8LE-NEXT:    xxswapd v5, vs4
 ; P8LE-NEXT:    xxswapd v0, vs5
 ; P8LE-NEXT:    vmrglh v3, v4, v3
 ; P8LE-NEXT:    vmrglh v4, v0, v5

 ; P8BE-NEXT:    mulli r0, r9, 95
 ; P8BE-NEXT:    sldi r9, r9, 48
 ; P8BE-NEXT:    sldi r8, r8, 48
 ; P8BE-NEXT:    mtvsrd v3, r9
 ; P8BE-NEXT:    mulli r9, r4, 95
 ; P8BE-NEXT:    mtvsrd v2, r8
 ; P8BE-NEXT:    mulli r8, r10, 95
 ; P8BE-NEXT:    sldi r10, r10, 48
-; P8BE-NEXT:    subf r3, r12, r3
+; P8BE-NEXT:    sub r3, r3, r12
 ; P8BE-NEXT:    mtvsrd v4, r10
-; P8BE-NEXT:    subf r6, r0, r6
+; P8BE-NEXT:    sub r6, r6, r0
 ; P8BE-NEXT:    sldi r3, r3, 48
 ; P8BE-NEXT:    vmrghh v2, v3, v2
 ; P8BE-NEXT:    sldi r6, r6, 48
 ; P8BE-NEXT:    mtvsrd v3, r3
-; P8BE-NEXT:    subf r3, r9, r5
-; P8BE-NEXT:    subf r7, r8, r7
+; P8BE-NEXT:    sub r3, r5, r9
+; P8BE-NEXT:    sub r7, r7, r8
 ; P8BE-NEXT:    mtvsrd v5, r6
 ; P8BE-NEXT:    sldi r3, r3, 48
 ; P8BE-NEXT:    sldi r5, r7, 48
 ; P8BE-NEXT:    mtvsrd v1, r3
 ; P8BE-NEXT:    sldi r3, r4, 48
 ; P8BE-NEXT:    mtvsrd v0, r5
 ; P8BE-NEXT:    vmrghh v3, v5, v3
 ; P8BE-NEXT:    mtvsrd v5, r3

 ; P9LE-LABEL: dont_fold_srem_power_of_two:
 ; P9LE:       # %bb.0:
 ; P9LE-NEXT:    li r3, 0
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    extsh r4, r3
 ; P9LE-NEXT:    srawi r4, r4, 6
 ; P9LE-NEXT:    addze r4, r4
 ; P9LE-NEXT:    slwi r4, r4, 6
-; P9LE-NEXT:    subf r3, r4, r3
+; P9LE-NEXT:    sub r3, r3, r4
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 2
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    extsh r4, r3
 ; P9LE-NEXT:    srawi r4, r4, 5
 ; P9LE-NEXT:    addze r4, r4
 ; P9LE-NEXT:    slwi r4, r4, 5
-; P9LE-NEXT:    subf r3, r4, r3
+; P9LE-NEXT:    sub r3, r3, r4
 ; P9LE-NEXT:    xxswapd v3, vs0
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 6
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    lis r5, -21386
 ; P9LE-NEXT:    ori r5, r5, 37253
 ; P9LE-NEXT:    xxswapd v4, vs0
 ; P9LE-NEXT:    extsh r4, r3
 ; P9LE-NEXT:    mulhw r5, r4, r5
 ; P9LE-NEXT:    add r4, r5, r4
 ; P9LE-NEXT:    srwi r5, r4, 31
 ; P9LE-NEXT:    srawi r4, r4, 6
 ; P9LE-NEXT:    add r4, r4, r5
 ; P9LE-NEXT:    mulli r4, r4, 95
-; P9LE-NEXT:    subf r3, r4, r3
+; P9LE-NEXT:    sub r3, r3, r4
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 4
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    extsh r4, r3
 ; P9LE-NEXT:    srawi r4, r4, 3
 ; P9LE-NEXT:    addze r4, r4
 ; P9LE-NEXT:    slwi r4, r4, 3
-; P9LE-NEXT:    subf r3, r4, r3
+; P9LE-NEXT:    sub r3, r3, r4
 ; P9LE-NEXT:    vmrglh v3, v4, v3
 ; P9LE-NEXT:    xxswapd v4, vs0
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    xxswapd v2, vs0
 ; P9LE-NEXT:    vmrglh v2, v4, v2
 ; P9LE-NEXT:    vmrglw v2, v2, v3
 ; P9LE-NEXT:    blr
 ;
 ; P9BE-LABEL: dont_fold_srem_power_of_two:
 ; P9BE:       # %bb.0:
 ; P9BE-NEXT:    li r3, 2
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    extsh r3, r3
 ; P9BE-NEXT:    srawi r4, r3, 5
 ; P9BE-NEXT:    addze r4, r4
 ; P9BE-NEXT:    slwi r4, r4, 5
-; P9BE-NEXT:    subf r3, r4, r3
+; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v3, r3
 ; P9BE-NEXT:    li r3, 0
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    extsh r3, r3
 ; P9BE-NEXT:    srawi r4, r3, 6
 ; P9BE-NEXT:    addze r4, r4
 ; P9BE-NEXT:    slwi r4, r4, 6
-; P9BE-NEXT:    subf r3, r4, r3
+; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    lis r4, -21386
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v4, r3
 ; P9BE-NEXT:    li r3, 6
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    extsh r3, r3
 ; P9BE-NEXT:    ori r4, r4, 37253
 ; P9BE-NEXT:    mulhw r4, r3, r4
 ; P9BE-NEXT:    add r4, r4, r3
 ; P9BE-NEXT:    srwi r5, r4, 31
 ; P9BE-NEXT:    srawi r4, r4, 6
 ; P9BE-NEXT:    add r4, r4, r5
 ; P9BE-NEXT:    mulli r4, r4, 95
-; P9BE-NEXT:    subf r3, r4, r3
+; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    vmrghh v3, v4, v3
 ; P9BE-NEXT:    mtvsrd v4, r3
 ; P9BE-NEXT:    li r3, 4
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    extsh r3, r3
 ; P9BE-NEXT:    srawi r4, r3, 3
 ; P9BE-NEXT:    addze r4, r4
 ; P9BE-NEXT:    slwi r4, r4, 3
-; P9BE-NEXT:    subf r3, r4, r3
+; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v2, r3
 ; P9BE-NEXT:    vmrghh v2, v2, v4
 ; P9BE-NEXT:    vmrghw v2, v3, v2
 ; P9BE-NEXT:    blr
 ;
 ; P8LE-LABEL: dont_fold_srem_power_of_two:
 ; P8LE:       # %bb.0:

 ; P8LE-NEXT:    srawi r8, r8, 6
 ; P8LE-NEXT:    extsh r10, r9
 ; P8LE-NEXT:    addze r8, r8
 ; P8LE-NEXT:    rldicl r4, r4, 32, 48
 ; P8LE-NEXT:    srawi r10, r10, 5
 ; P8LE-NEXT:    slwi r8, r8, 6
 ; P8LE-NEXT:    add r3, r3, r6
 ; P8LE-NEXT:    addze r6, r10
-; P8LE-NEXT:    subf r7, r8, r7
+; P8LE-NEXT:    sub r7, r7, r8
 ; P8LE-NEXT:    srwi r10, r3, 31
 ; P8LE-NEXT:    srawi r3, r3, 6
 ; P8LE-NEXT:    mtfprd f0, r7
 ; P8LE-NEXT:    slwi r6, r6, 5
 ; P8LE-NEXT:    add r3, r3, r10
 ; P8LE-NEXT:    extsh r10, r4
-; P8LE-NEXT:    subf r6, r6, r9
+; P8LE-NEXT:    sub r6, r9, r6
 ; P8LE-NEXT:    mulli r3, r3, 95
 ; P8LE-NEXT:    srawi r8, r10, 3
 ; P8LE-NEXT:    mtfprd f1, r6
 ; P8LE-NEXT:    xxswapd v2, vs0
 ; P8LE-NEXT:    addze r7, r8
 ; P8LE-NEXT:    xxswapd v3, vs1
-; P8LE-NEXT:    subf r3, r3, r5
+; P8LE-NEXT:    sub r3, r5, r3
 ; P8LE-NEXT:    slwi r5, r7, 3
-; P8LE-NEXT:    subf r4, r5, r4
+; P8LE-NEXT:    sub r4, r4, r5
 ; P8LE-NEXT:    mtfprd f2, r3
 ; P8LE-NEXT:    mtfprd f3, r4
 ; P8LE-NEXT:    xxswapd v4, vs2
 ; P8LE-NEXT:    vmrglh v2, v3, v2
 ; P8LE-NEXT:    xxswapd v5, vs3
 ; P8LE-NEXT:    vmrglh v3, v4, v5
 ; P8LE-NEXT:    vmrglw v2, v3, v2
 ; P8LE-NEXT:    blr

 ; P8BE-NEXT:    extsh r7, r7
 ; P8BE-NEXT:    addze r8, r8
 ; P8BE-NEXT:    rldicl r4, r4, 48, 48
 ; P8BE-NEXT:    srawi r9, r7, 6
 ; P8BE-NEXT:    extsh r4, r4
 ; P8BE-NEXT:    slwi r8, r8, 5
 ; P8BE-NEXT:    add r3, r3, r5
 ; P8BE-NEXT:    addze r9, r9
-; P8BE-NEXT:    subf r6, r8, r6
+; P8BE-NEXT:    sub r6, r6, r8
 ; P8BE-NEXT:    srwi r10, r3, 31
 ; P8BE-NEXT:    srawi r3, r3, 6
 ; P8BE-NEXT:    slwi r8, r9, 6
 ; P8BE-NEXT:    add r3, r3, r10
 ; P8BE-NEXT:    srawi r9, r4, 3
-; P8BE-NEXT:    subf r7, r8, r7
+; P8BE-NEXT:    sub r7, r7, r8
 ; P8BE-NEXT:    mulli r3, r3, 95
 ; P8BE-NEXT:    sldi r6, r6, 48
 ; P8BE-NEXT:    addze r8, r9
 ; P8BE-NEXT:    mtvsrd v2, r6
 ; P8BE-NEXT:    slwi r6, r8, 3
-; P8BE-NEXT:    subf r4, r6, r4
+; P8BE-NEXT:    sub r4, r4, r6
 ; P8BE-NEXT:    sldi r4, r4, 48
-; P8BE-NEXT:    subf r3, r3, r5
+; P8BE-NEXT:    sub r3, r5, r3
 ; P8BE-NEXT:    sldi r5, r7, 48
 ; P8BE-NEXT:    mtvsrd v5, r4
 ; P8BE-NEXT:    sldi r3, r3, 48
 ; P8BE-NEXT:    mtvsrd v3, r5
 ; P8BE-NEXT:    mtvsrd v4, r3
 ; P8BE-NEXT:    vmrghh v2, v3, v2
 ; P8BE-NEXT:    vmrghh v3, v5, v4
 ; P8BE-NEXT:    vmrghw v2, v2, v3

 ; P9LE-NEXT:    extsh r4, r3
 ; P9LE-NEXT:    mulhw r5, r4, r5
 ; P9LE-NEXT:    add r4, r5, r4
 ; P9LE-NEXT:    srwi r5, r4, 31
 ; P9LE-NEXT:    srawi r4, r4, 9
 ; P9LE-NEXT:    add r4, r4, r5
 ; P9LE-NEXT:    lis r5, -19946
 ; P9LE-NEXT:    mulli r4, r4, 654
-; P9LE-NEXT:    subf r3, r4, r3
+; P9LE-NEXT:    sub r3, r3, r4
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 4
 ; P9LE-NEXT:    ori r5, r5, 17097
 ; P9LE-NEXT:    xxlxor v3, v3, v3
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    extsh r4, r3
 ; P9LE-NEXT:    mulhw r5, r4, r5
 ; P9LE-NEXT:    add r4, r5, r4
 ; P9LE-NEXT:    srwi r5, r4, 31
 ; P9LE-NEXT:    srawi r4, r4, 4
 ; P9LE-NEXT:    add r4, r4, r5
 ; P9LE-NEXT:    lis r5, 24749
 ; P9LE-NEXT:    mulli r4, r4, 23
-; P9LE-NEXT:    subf r3, r4, r3
+; P9LE-NEXT:    sub r3, r3, r4
 ; P9LE-NEXT:    xxswapd v4, vs0
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 6
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    extsh r4, r3
 ; P9LE-NEXT:    ori r5, r5, 47143
 ; P9LE-NEXT:    mulhw r4, r4, r5
 ; P9LE-NEXT:    srwi r5, r4, 31
 ; P9LE-NEXT:    srawi r4, r4, 11
 ; P9LE-NEXT:    add r4, r4, r5
 ; P9LE-NEXT:    mulli r4, r4, 5423
-; P9LE-NEXT:    subf r3, r4, r3
+; P9LE-NEXT:    sub r3, r3, r4
 ; P9LE-NEXT:    vmrglh v3, v4, v3
 ; P9LE-NEXT:    xxswapd v4, vs0
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    xxswapd v2, vs0
 ; P9LE-NEXT:    vmrglh v2, v2, v4
 ; P9LE-NEXT:    vmrglw v2, v2, v3
 ; P9LE-NEXT:    blr
 ;
 ; P9BE-LABEL: dont_fold_srem_one:
 ; P9BE:       # %bb.0:
 ; P9BE-NEXT:    li r3, 4
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    lis r4, -19946
 ; P9BE-NEXT:    ori r4, r4, 17097
 ; P9BE-NEXT:    extsh r3, r3
 ; P9BE-NEXT:    mulhw r4, r3, r4
 ; P9BE-NEXT:    add r4, r4, r3
 ; P9BE-NEXT:    srwi r5, r4, 31
 ; P9BE-NEXT:    srawi r4, r4, 4
 ; P9BE-NEXT:    add r4, r4, r5
 ; P9BE-NEXT:    mulli r4, r4, 23
-; P9BE-NEXT:    subf r3, r4, r3
+; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    lis r4, 24749
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v3, r3
 ; P9BE-NEXT:    li r3, 6
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    extsh r3, r3
 ; P9BE-NEXT:    ori r4, r4, 47143
 ; P9BE-NEXT:    mulhw r4, r3, r4
 ; P9BE-NEXT:    srwi r5, r4, 31
 ; P9BE-NEXT:    srawi r4, r4, 11
 ; P9BE-NEXT:    add r4, r4, r5
 ; P9BE-NEXT:    mulli r4, r4, 5423
-; P9BE-NEXT:    subf r3, r4, r3
+; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    lis r4, -14230
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v4, r3
 ; P9BE-NEXT:    li r3, 2
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    extsh r3, r3
 ; P9BE-NEXT:    ori r4, r4, 30865
 ; P9BE-NEXT:    mulhw r4, r3, r4
 ; P9BE-NEXT:    add r4, r4, r3
 ; P9BE-NEXT:    srwi r5, r4, 31
 ; P9BE-NEXT:    srawi r4, r4, 9
 ; P9BE-NEXT:    add r4, r4, r5
 ; P9BE-NEXT:    mulli r4, r4, 654
-; P9BE-NEXT:    subf r3, r4, r3
+; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v2, r3
 ; P9BE-NEXT:    li r3, 0
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    vmrghh v3, v3, v4
 ; P9BE-NEXT:    mtvsrd v4, r3
 ; P9BE-NEXT:    vmrghh v2, v4, v2
 ; P9BE-NEXT:    vmrghw v2, v2, v3

 ; P8LE-NEXT:    add r3, r3, r10
 ; P8LE-NEXT:    add r7, r7, r9
 ; P8LE-NEXT:    srwi r9, r8, 31
 ; P8LE-NEXT:    srawi r8, r8, 9
 ; P8LE-NEXT:    mulli r3, r3, 5423
 ; P8LE-NEXT:    add r8, r8, r9
 ; P8LE-NEXT:    mulli r7, r7, 23
 ; P8LE-NEXT:    mulli r8, r8, 654
-; P8LE-NEXT:    subf r3, r3, r5
+; P8LE-NEXT:    sub r3, r5, r3
 ; P8LE-NEXT:    mtfprd f0, r3
-; P8LE-NEXT:    subf r3, r7, r6
-; P8LE-NEXT:    subf r4, r8, r4
+; P8LE-NEXT:    sub r3, r6, r7
+; P8LE-NEXT:    sub r4, r4, r8
 ; P8LE-NEXT:    mtfprd f1, r3
 ; P8LE-NEXT:    mtfprd f2, r4
 ; P8LE-NEXT:    xxswapd v2, vs0
 ; P8LE-NEXT:    xxswapd v3, vs1
 ; P8LE-NEXT:    xxswapd v4, vs2
 ; P8LE-NEXT:    vmrglh v2, v2, v3
 ; P8LE-NEXT:    vmrglh v3, v4, v5
 ; P8LE-NEXT:    vmrglw v2, v2, v3

 ; P8BE-NEXT:    add r6, r6, r9
 ; P8BE-NEXT:    srwi r9, r8, 31
 ; P8BE-NEXT:    srawi r8, r8, 9
 ; P8BE-NEXT:    mulli r5, r5, 5423
 ; P8BE-NEXT:    add r8, r8, r9
 ; P8BE-NEXT:    mulli r6, r6, 23
 ; P8BE-NEXT:    li r9, 0
 ; P8BE-NEXT:    mulli r8, r8, 654
-; P8BE-NEXT:    subf r4, r5, r4
+; P8BE-NEXT:    sub r4, r4, r5
 ; P8BE-NEXT:    sldi r5, r9, 48
 ; P8BE-NEXT:    mtvsrd v2, r5
-; P8BE-NEXT:    subf r5, r6, r7
+; P8BE-NEXT:    sub r5, r7, r6
 ; P8BE-NEXT:    sldi r4, r4, 48
-; P8BE-NEXT:    subf r3, r8, r3
+; P8BE-NEXT:    sub r3, r3, r8
 ; P8BE-NEXT:    mtvsrd v3, r4
 ; P8BE-NEXT:    sldi r4, r5, 48
 ; P8BE-NEXT:    sldi r3, r3, 48
 ; P8BE-NEXT:    mtvsrd v4, r4
 ; P8BE-NEXT:    mtvsrd v5, r3
 ; P8BE-NEXT:    vmrghh v3, v4, v3
 ; P8BE-NEXT:    vmrghh v2, v2, v5
 ; P8BE-NEXT:    vmrghw v2, v2, v3

 ; P9LE-NEXT:    extsh r4, r3
 ; P9LE-NEXT:    mulhw r5, r4, r5
 ; P9LE-NEXT:    add r4, r5, r4
 ; P9LE-NEXT:    srwi r5, r4, 31
 ; P9LE-NEXT:    srawi r4, r4, 4
 ; P9LE-NEXT:    add r4, r4, r5
 ; P9LE-NEXT:    lis r5, 24749
 ; P9LE-NEXT:    mulli r4, r4, 23
-; P9LE-NEXT:    subf r3, r4, r3
+; P9LE-NEXT:    sub r3, r3, r4
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 6
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    extsh r4, r3
 ; P9LE-NEXT:    ori r5, r5, 47143
 ; P9LE-NEXT:    mulhw r4, r4, r5
 ; P9LE-NEXT:    srwi r5, r4, 31
 ; P9LE-NEXT:    srawi r4, r4, 11
 ; P9LE-NEXT:    add r4, r4, r5
 ; P9LE-NEXT:    mulli r4, r4, 5423
-; P9LE-NEXT:    subf r3, r4, r3
+; P9LE-NEXT:    sub r3, r3, r4
 ; P9LE-NEXT:    xxswapd v3, vs0
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 2
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    extsh r4, r3
 ; P9LE-NEXT:    srawi r4, r4, 15
 ; P9LE-NEXT:    addze r4, r4
 ; P9LE-NEXT:    slwi r4, r4, 15
-; P9LE-NEXT:    subf r3, r4, r3
+; P9LE-NEXT:    sub r3, r3, r4
 ; P9LE-NEXT:    xxswapd v4, vs0
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    xxswapd v2, vs0
 ; P9LE-NEXT:    vmrglh v3, v4, v3
 ; P9LE-NEXT:    xxlxor v4, v4, v4
 ; P9LE-NEXT:    vmrglh v2, v2, v4
 ; P9LE-NEXT:    vmrglw v2, v3, v2
 ; P9LE-NEXT:    blr
 ;
 ; P9BE-LABEL: dont_fold_urem_i16_smax:
 ; P9BE:       # %bb.0:
 ; P9BE-NEXT:    li r3, 4
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    lis r4, -19946
 ; P9BE-NEXT:    ori r4, r4, 17097
 ; P9BE-NEXT:    extsh r3, r3
 ; P9BE-NEXT:    mulhw r4, r3, r4
 ; P9BE-NEXT:    add r4, r4, r3
 ; P9BE-NEXT:    srwi r5, r4, 31
 ; P9BE-NEXT:    srawi r4, r4, 4
 ; P9BE-NEXT:    add r4, r4, r5
 ; P9BE-NEXT:    mulli r4, r4, 23
-; P9BE-NEXT:    subf r3, r4, r3
+; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    lis r4, 24749
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v3, r3
 ; P9BE-NEXT:    li r3, 6
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    extsh r3, r3
 ; P9BE-NEXT:    ori r4, r4, 47143
 ; P9BE-NEXT:    mulhw r4, r3, r4
 ; P9BE-NEXT:    srwi r5, r4, 31
 ; P9BE-NEXT:    srawi r4, r4, 11
 ; P9BE-NEXT:    add r4, r4, r5
 ; P9BE-NEXT:    mulli r4, r4, 5423
-; P9BE-NEXT:    subf r3, r4, r3
+; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v4, r3
 ; P9BE-NEXT:    li r3, 2
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    extsh r3, r3
 ; P9BE-NEXT:    srawi r4, r3, 15
 ; P9BE-NEXT:    addze r4, r4
 ; P9BE-NEXT:    slwi r4, r4, 15
-; P9BE-NEXT:    subf r3, r4, r3
+; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v2, r3
 ; P9BE-NEXT:    li r3, 0
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    vmrghh v3, v3, v4
 ; P9BE-NEXT:    mtvsrd v4, r3
 ; P9BE-NEXT:    vmrghh v2, v4, v2
 ; P9BE-NEXT:    vmrghw v2, v2, v3

 ; P8LE-NEXT:    add r4, r4, r8
 ; P8LE-NEXT:    srwi r8, r5, 31
 ; P8LE-NEXT:    srawi r5, r5, 4
 ; P8LE-NEXT:    mulli r4, r4, 5423
 ; P8LE-NEXT:    add r5, r5, r8
 ; P8LE-NEXT:    extsh r8, r3
 ; P8LE-NEXT:    mulli r5, r5, 23
 ; P8LE-NEXT:    srawi r8, r8, 15
-; P8LE-NEXT:    subf r4, r4, r6
+; P8LE-NEXT:    sub r4, r6, r4
 ; P8LE-NEXT:    addze r6, r8
 ; P8LE-NEXT:    mtfprd f0, r4
 ; P8LE-NEXT:    slwi r4, r6, 15
-; P8LE-NEXT:    subf r5, r5, r7
-; P8LE-NEXT:    subf r3, r4, r3
+; P8LE-NEXT:    sub r5, r7, r5
+; P8LE-NEXT:    sub r3, r3, r4
 ; P8LE-NEXT:    mtfprd f1, r5
 ; P8LE-NEXT:    xxswapd v2, vs0
 ; P8LE-NEXT:    mtfprd f2, r3
 ; P8LE-NEXT:    xxswapd v3, vs1
 ; P8LE-NEXT:    xxswapd v4, vs2
 ; P8LE-NEXT:    vmrglh v2, v2, v3
 ; P8LE-NEXT:    vmrglh v3, v4, v5
 ; P8LE-NEXT:    vmrglw v2, v2, v3

 ; P8BE-NEXT:    add r4, r4, r8
 ; P8BE-NEXT:    srwi r8, r5, 31
 ; P8BE-NEXT:    srawi r5, r5, 4
 ; P8BE-NEXT:    mulli r4, r4, 5423
 ; P8BE-NEXT:    add r5, r5, r8
 ; P8BE-NEXT:    li r8, 0
 ; P8BE-NEXT:    mulli r5, r5, 23
 ; P8BE-NEXT:    srawi r9, r3, 15
-; P8BE-NEXT:    subf r4, r4, r6
+; P8BE-NEXT:    sub r4, r6, r4
 ; P8BE-NEXT:    sldi r6, r8, 48
 ; P8BE-NEXT:    addze r8, r9
 ; P8BE-NEXT:    mtvsrd v2, r6
 ; P8BE-NEXT:    slwi r6, r8, 15
 ; P8BE-NEXT:    sldi r4, r4, 48
-; P8BE-NEXT:    subf r5, r5, r7
-; P8BE-NEXT:    subf r3, r6, r3
+; P8BE-NEXT:    sub r5, r7, r5
+; P8BE-NEXT:    sub r3, r3, r6
 ; P8BE-NEXT:    mtvsrd v3, r4
 ; P8BE-NEXT:    sldi r4, r5, 48
 ; P8BE-NEXT:    sldi r3, r3, 48
 ; P8BE-NEXT:    mtvsrd v4, r4
 ; P8BE-NEXT:    mtvsrd v5, r3
 ; P8BE-NEXT:    vmrghh v3, v4, v3
 ; P8BE-NEXT:    vmrghh v2, v2, v5
 ; P8BE-NEXT:    vmrghw v2, v2, v3

llvm/test/CodeGen/PowerPC/stack-guard-reassign.ll

 ; RUN: llc -O0 --frame-pointer=none -mtriple=powerpc-- -o - %S/../Inputs/stack-guard-reassign.ll | FileCheck %s
 
 ; Verify that the offset assigned to the stack protector is at the top of the
 ; frame, covering the locals.
 ; CHECK-LABEL: fn:
 ; CHECK:      mflr 0
 ; CHECK-NEXT: stw 0, 4(1)
 ; CHECK-NEXT: lis 0, -2
 ; CHECK-NEXT: ori 0, 0, 65488
 ; CHECK-NEXT: stwux 1, 1, 0
-; CHECK-NEXT: subf 0, 0, 1
+; CHECK-NEXT: sub 0, 1, 0
 ; CHECK-NEXT: lis 4, __stack_chk_guard@ha
 ; CHECK-NEXT: lwz 5, __stack_chk_guard@l(4)
 ; CHECK-NEXT: lis 6, 1
 ; CHECK-NEXT: ori 6, 6, 44
 ; CHECK-NEXT: stwx 5, 1, 6

llvm/test/CodeGen/PowerPC/stack-realign.ll

 ; CHECK-FP: blr
 
 ; CHECK-32-LABEL: @goo
 ; CHECK-32-DAG: mflr [[LR:[0-9]+]]
 ; CHECK-32-DAG: clrlwi [[REG:[0-9]+]], 1, 27
 ; CHECK-32-DAG: stw [[LR]], 4(1)
 ; CHECK-32-DAG: subfic 0, [[REG]], -64
 ; CHECK-32: stwux 1, 1, 0
-; CHECK-32: subf 0, 0, 1
+; CHECK-32: sub 0, 1, 0
 ; CHECK-32: addic 0, 0, -4
 ; CHECK-32: stwx 31, 0, 0
 ; CHECK-32: addic 0, 0, -4
 ; CHECK-32: stwx 30, 0, 0
 ; CHECK-32: addic 30, 0, 8
 
 ; CHECK-32-PIC-LABEL: @goo
 ; CHECK-32-PIC-DAG: mflr [[LR:[0-9]+]]
 ; CHECK-32-PIC-DAG: clrlwi [[REG:[0-9]+]], 1, 27
 ; CHECK-32-PIC-DAG: stw [[LR]], 4(1)
 ; CHECK-32-PIC-DAG: subfic 0, [[REG]], -64
 ; CHECK-32-PIC:     stwux 1, 1, 0
-; CHECK-32-PIC:     subf 0, 0, 1
+; CHECK-32-PIC:     sub 0, 1, 0
 ; CHECK-32-PIC:     addic 0, 0, -4
 ; CHECK-32-PIC:     stwx 31, 0, 0
 ; CHECK-32-PIC:     addic 0, 0, -4
 ; CHECK-32-PIC:     stwx 30, 0, 0
 ; CHECK-32-PIC:     addic 0, 0, -4
 ; CHECK-32-PIC:     stwx 29, 0, 0
 ; CHECK-32-PIC:     addic 29, 0, 12
 

 
 ; CHECK-32-LABEL: @hoo
 
 ; CHECK-32-DAG: lis [[REG1:[0-9]+]], -13
 ; CHECK-32-DAG: clrlwi [[REG3:[0-9]+]], 1, 27
 ; CHECK-32-DAG: mflr [[LR:[0-9]+]]
 ; CHECK-32-DAG: ori [[REG2:[0-9]+]], [[REG1]], 51904
 ; CHECK-32-DAG: stw [[LR]], 4(1)
-; CHECK-32-DAG: subfc 0, [[REG3]], [[REG2]]
+; CHECK-32-DAG: subc 0, [[REG2]], [[REG3]]
 ; CHECK-32:     stwux 1, 1, 0
-; CHECK-32:     subf 0, 0, 1
+; CHECK-32:     sub 0, 1, 0
 ; CHECK-32:     addic 0, 0, -4
 ; CHECK-32:     stwx 31, 0, 0
 ; CHECK-32:     addic 0, 0, -4
 ; CHECK-32:     stwx 30, 0, 0
 ; CHECK-32:     addic 30, 0, 8
 
 ; CHECK-32: blr
 
 ; CHECK-32-PIC-LABEL: @hoo
 
 ; CHECK-32-PIC-DAG: lis [[REG1:[0-9]+]], -13
 ; CHECK-32-PIC-DAG: clrlwi [[REG3:[0-9]+]], 1, 27
 ; CHECK-32-PIC-DAG: mflr {{[0-9]+}}
 ; CHECK-32-PIC-DAG: ori [[REG2:[0-9]+]], [[REG1]], 51904
 ; CHECK-32-PIC-DAG: stw 0, 4(1)
-; CHECK-32-PIC-DAG: subfc 0, [[REG3]], [[REG2]]
+; CHECK-32-PIC-DAG: subc 0, [[REG2]], [[REG3]]
 ; CHECK-32-PIC:     stwux 1, 1, 0
-; CHECK-32-PIC:     subf 0, 0, 1
+; CHECK-32-PIC:     sub 0, 1, 0
 ; CHECK-32-PIC:     addic 0, 0, -4
 ; CHECK-32-PIC:     stwx 31, 0, 0
 ; CHECK-32-PIC:     addic 0, 0, -8
 ; CHECK-32-PIC:     stwx 29, 0, 0
 ; CHECK-32-PIC:     addic 29, 0, 12
 
 ; CHECK-32: blr
 

llvm/test/CodeGen/PowerPC/store-combine.ll

 ; p[3] = (m >> 32) & 0xFF;
 ; p[2] = (m >> 40) & 0xFF;
 ; p[1] = (m >> 48) & 0xFF;
 ; p[0] = (m >> 56) & 0xFF;
 define void @store_i64_by_i8_bswap_uses(i32 signext %t, i8* %p) {
 ; CHECK-PPC64LE-LABEL: store_i64_by_i8_bswap_uses:
 ; CHECK-PPC64LE:       # %bb.0: # %entry
 ; CHECK-PPC64LE-NEXT:    slwi 5, 3, 3
-; CHECK-PPC64LE-NEXT:    subf 3, 3, 5
+; CHECK-PPC64LE-NEXT:    sub 3, 5, 3
 ; CHECK-PPC64LE-NEXT:    extsw 3, 3
 ; CHECK-PPC64LE-NEXT:    stdbrx 3, 0, 4
 ; CHECK-PPC64LE-NEXT:    blr
 ;
 ; CHECK-PPC64-LABEL: store_i64_by_i8_bswap_uses:
 ; CHECK-PPC64:       # %bb.0: # %entry
 ; CHECK-PPC64-NEXT:    slwi 5, 3, 3
-; CHECK-PPC64-NEXT:    subf 3, 3, 5
+; CHECK-PPC64-NEXT:    sub 3, 5, 3
 ; CHECK-PPC64-NEXT:    extsw 3, 3
 ; CHECK-PPC64-NEXT:    stdx 3, 0, 4
 ; CHECK-PPC64-NEXT:    blr
 entry:
   %mul = mul nsw i32 %t, 7
   %conv = sext i32 %mul to i64
   %conv1 = trunc i32 %mul to i8
   %arrayidx = getelementptr inbounds i8, i8* %p, i64 7

llvm/test/CodeGen/PowerPC/sub-of-not.ll

; PPC64LE-NEXT:    blr
   %t0 = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
   %t1 = sub <4 x i32> %y, %t0
   ret <4 x i32> %t1
 }
 
 define <2 x i64> @vector_i128_i64(<2 x i64> %x, <2 x i64> %y) nounwind {
 ; PPC32-LABEL: vector_i128_i64:
 ; PPC32:       # %bb.0:
-; PPC32-NEXT:    nor 4, 4, 4
-; PPC32-NEXT:    nor 3, 3, 3
-; PPC32-NEXT:    subfc 4, 4, 8
-; PPC32-NEXT:    nor 6, 6, 6
+; PPC32-NEXT:    not 4, 4
+; PPC32-NEXT:    not 3, 3
+; PPC32-NEXT:    subc 4, 8, 4
+; PPC32-NEXT:    not 6, 6
 ; PPC32-NEXT:    subfe 3, 3, 7
-; PPC32-NEXT:    nor 5, 5, 5
-; PPC32-NEXT:    subfc 6, 6, 10
+; PPC32-NEXT:    not 5, 5
+; PPC32-NEXT:    subc 6, 10, 6
 ; PPC32-NEXT:    subfe 5, 5, 9
 ; PPC32-NEXT:    blr
 ;
 ; PPC64BE-LABEL: vector_i128_i64:
 ; PPC64BE:       # %bb.0:
 ; PPC64BE-NEXT:    add 3, 5, 3
 ; PPC64BE-NEXT:    add 4, 6, 4
 ; PPC64BE-NEXT:    addi 3, 3, 1

llvm/test/CodeGen/PowerPC/subc.ll

 ; All of these should be codegen'd without loading immediates
 ; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -o %t
-; RUN: grep subfc %t | count 1
+; RUN: grep subc %t | count 1
 ; RUN: grep subfe %t | count 1
 ; RUN: grep subfze %t | count 1
 ; RUN: grep subfme %t | count 1
 ; RUN: grep subfic %t | count 2
 
 define i64 @sub_ll(i64 %a, i64 %b) {
 entry:
   %tmp.2 = sub i64 %a, %b   ; <i64> [#uses=1]

llvm/test/CodeGen/PowerPC/subreg-postra.ll

wait_on_buffer.exit1319:                          ; preds = %while.body392
   call void @__brelse(i32* %3) #1
   br i1 %inp8, label %while.end418, label %while.body392
 
 ; CHECK-LABEL: @jbd2_journal_commit_transaction
 ; CHECK-NO-ISEL-LABEL: @jbd2_journal_commit_transaction
 ; CHECK: andi.
 ; CHECK: crmove
 ; CHECK: stdcx.
-; CHECK: isel {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}},
+; CHECK: iselgt {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 ; CHECK-NO-ISEL: bc 12, 1, [[TRUE:.LBB[0-9]+]]
 ; CHECK-NO-ISEL: ori 30, 3, 0
 ; CHECK-NO-ISEL: b [[SUCCESSOR:.LBB[0-9]+]]
 
 
 while.end418:                                     ; preds = %wait_on_buffer.exit1319, %do.body378
   %err.4.lcssa = phi i32 [ %inp2, %do.body378 ], [ %.err.4, %wait_on_buffer.exit1319 ]
   br i1 %inp7, label %if.end421, label %if.then420

llvm/test/CodeGen/PowerPC/umulo-128-legalisation-lowering.ll

 ; PPC64-NEXT:    crorc 20, 20, 2
 ; PPC64-NEXT:    crnor 20, 20, 21
 ; PPC64-NEXT:    mulld 4, 4, 6
 ; PPC64-NEXT:    bc 12, 20, .LBB0_2
 ; PPC64-NEXT:  # %bb.1: # %start
 ; PPC64-NEXT:    ori 5, 7, 0
 ; PPC64-NEXT:    blr
 ; PPC64-NEXT:  .LBB0_2: # %start
-; PPC64-NEXT:    addi 5, 0, 0
+; PPC64-NEXT:    li 5, 0
 ; PPC64-NEXT:    blr
 ;
 ; PPC32-LABEL: muloti_test:
 ; PPC32:       # %bb.0: # %start
 ; PPC32-NEXT:    mflr 0
 ; PPC32-NEXT:    stw 0, 4(1)
 ; PPC32-NEXT:    stwu 1, -80(1)
 ; PPC32-NEXT:    stw 26, 56(1) # 4-byte Folded Spill

 ; PPC32-NEXT:    cror 20, 20, 24
 ; PPC32-NEXT:    crnor 20, 20, 12
 ; PPC32-NEXT:    li 3, 1
 ; PPC32-NEXT:    bc 12, 20, .LBB0_2
 ; PPC32-NEXT:  # %bb.1: # %start
 ; PPC32-NEXT:    ori 7, 3, 0
 ; PPC32-NEXT:    b .LBB0_3
 ; PPC32-NEXT:  .LBB0_2: # %start
-; PPC32-NEXT:    addi 7, 0, 0
+; PPC32-NEXT:    li 7, 0
 ; PPC32-NEXT:  .LBB0_3: # %start
 ; PPC32-NEXT:    mr 3, 8
 ; PPC32-NEXT:    mtcrf 32, 12 # cr2
 ; PPC32-NEXT:    mtcrf 16, 12 # cr3
 ; PPC32-NEXT:    lwz 30, 72(1) # 4-byte Folded Reload
 ; PPC32-NEXT:    lwz 29, 68(1) # 4-byte Folded Reload
 ; PPC32-NEXT:    lwz 28, 64(1) # 4-byte Folded Reload
 ; PPC32-NEXT:    lwz 27, 60(1) # 4-byte Folded Reload

llvm/test/CodeGen/PowerPC/urem-lkk.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu -mcpu=ppc64 < %s | FileCheck -check-prefixes=CHECK,CHECK64 %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu -mcpu=ppc < %s | FileCheck -check-prefixes=CHECK,CHECK32 %s
 
 define i32 @fold_urem_positive_odd(i32 %x) {
 ; CHECK-LABEL: fold_urem_positive_odd:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lis 4, 22765
 ; CHECK-NEXT:    ori 4, 4, 8969
 ; CHECK-NEXT:    mulhwu 4, 3, 4
-; CHECK-NEXT:    subf 5, 4, 3
+; CHECK-NEXT:    sub 5, 3, 4
 ; CHECK-NEXT:    srwi 5, 5, 1
 ; CHECK-NEXT:    add 4, 5, 4
 ; CHECK-NEXT:    srwi 4, 4, 6
 ; CHECK-NEXT:    mulli 4, 4, 95
-; CHECK-NEXT:    subf 3, 4, 3
+; CHECK-NEXT:    sub 3, 3, 4
 ; CHECK-NEXT:    blr
   %1 = urem i32 %x, 95
   ret i32 %1
 }
 
 
 define i32 @fold_urem_positive_even(i32 %x) {
 ; CHECK-LABEL: fold_urem_positive_even:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lis 4, -2226
 ; CHECK-NEXT:    ori 4, 4, 16323
 ; CHECK-NEXT:    mulhwu 4, 3, 4
 ; CHECK-NEXT:    srwi 4, 4, 10
 ; CHECK-NEXT:    mulli 4, 4, 1060
-; CHECK-NEXT:    subf 3, 4, 3
+; CHECK-NEXT:    sub 3, 3, 4
 ; CHECK-NEXT:    blr
   %1 = urem i32 %x, 1060
   ret i32 %1
 }
 
 
 ; Don't fold if we can combine urem with udiv.
 define i32 @combine_urem_udiv(i32 %x) {
 ; CHECK-LABEL: combine_urem_udiv:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lis 4, 22765
 ; CHECK-NEXT:    ori 4, 4, 8969
 ; CHECK-NEXT:    mulhwu 4, 3, 4
-; CHECK-NEXT:    subf 5, 4, 3
+; CHECK-NEXT:    sub 5, 3, 4
 ; CHECK-NEXT:    srwi 5, 5, 1
 ; CHECK-NEXT:    add 4, 5, 4
 ; CHECK-NEXT:    srwi 4, 4, 6
 ; CHECK-NEXT:    mulli 5, 4, 95
-; CHECK-NEXT:    subf 3, 5, 3
+; CHECK-NEXT:    sub 3, 3, 5
 ; CHECK-NEXT:    add 3, 3, 4
 ; CHECK-NEXT:    blr
   %1 = urem i32 %x, 95
   %2 = udiv i32 %x, 95
   %3 = add i32 %1, %2
   ret i32 %3
 }
 

llvm/test/CodeGen/PowerPC/urem-vector-lkk.ll

 ; P9LE-NEXT:    lis r5, 21399
 ; P9LE-NEXT:    ori r5, r5, 33437
 ; P9LE-NEXT:    clrlwi r4, r3, 16
 ; P9LE-NEXT:    mulhwu r4, r4, r5
 ; P9LE-NEXT:    lis r5, 16727
 ; P9LE-NEXT:    ori r5, r5, 2287
 ; P9LE-NEXT:    srwi r4, r4, 5
 ; P9LE-NEXT:    mulli r4, r4, 98
-; P9LE-NEXT:    subf r3, r4, r3
+; P9LE-NEXT:    sub r3, r3, r4
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 6
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    clrlwi r4, r3, 16
 ; P9LE-NEXT:    mulhwu r4, r4, r5
 ; P9LE-NEXT:    lis r5, 8456
 ; P9LE-NEXT:    ori r5, r5, 16913
 ; P9LE-NEXT:    srwi r4, r4, 8
 ; P9LE-NEXT:    mulli r4, r4, 1003
-; P9LE-NEXT:    subf r3, r4, r3
+; P9LE-NEXT:    sub r3, r3, r4
 ; P9LE-NEXT:    xxswapd v3, vs0
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 2
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    rlwinm r4, r3, 30, 18, 31
 ; P9LE-NEXT:    mulhwu r4, r4, r5
 ; P9LE-NEXT:    lis r5, 22765
 ; P9LE-NEXT:    ori r5, r5, 8969
 ; P9LE-NEXT:    srwi r4, r4, 2
 ; P9LE-NEXT:    mulli r4, r4, 124
-; P9LE-NEXT:    subf r3, r4, r3
+; P9LE-NEXT:    sub r3, r3, r4
 ; P9LE-NEXT:    xxswapd v4, vs0
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 0
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    clrlwi r4, r3, 16
 ; P9LE-NEXT:    mulhwu r5, r4, r5
-; P9LE-NEXT:    subf r4, r5, r4
+; P9LE-NEXT:    sub r4, r4, r5
 ; P9LE-NEXT:    srwi r4, r4, 1
 ; P9LE-NEXT:    add r4, r4, r5
 ; P9LE-NEXT:    srwi r4, r4, 6
 ; P9LE-NEXT:    mulli r4, r4, 95
-; P9LE-NEXT:    subf r3, r4, r3
+; P9LE-NEXT:    sub r3, r3, r4
 ; P9LE-NEXT:    vmrglh v3, v4, v3
 ; P9LE-NEXT:    xxswapd v4, vs0
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    xxswapd v2, vs0
 ; P9LE-NEXT:    vmrglh v2, v4, v2
 ; P9LE-NEXT:    vmrglw v2, v3, v2
 ; P9LE-NEXT:    blr
 ;
 ; P9BE-LABEL: fold_urem_vec_1:
 ; P9BE:       # %bb.0:
 ; P9BE-NEXT:    li r3, 6
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    lis r4, 16727
 ; P9BE-NEXT:    ori r4, r4, 2287
 ; P9BE-NEXT:    clrlwi r3, r3, 16
 ; P9BE-NEXT:    mulhwu r4, r3, r4
 ; P9BE-NEXT:    srwi r4, r4, 8
 ; P9BE-NEXT:    mulli r4, r4, 1003
-; P9BE-NEXT:    subf r3, r4, r3
+; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    lis r4, 21399
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v3, r3
 ; P9BE-NEXT:    li r3, 4
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    clrlwi r3, r3, 16
 ; P9BE-NEXT:    ori r4, r4, 33437
 ; P9BE-NEXT:    mulhwu r4, r3, r4
 ; P9BE-NEXT:    srwi r4, r4, 5
 ; P9BE-NEXT:    mulli r4, r4, 98
-; P9BE-NEXT:    subf r3, r4, r3
+; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v4, r3
 ; P9BE-NEXT:    li r3, 2
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    lis r5, 8456
 ; P9BE-NEXT:    ori r5, r5, 16913
 ; P9BE-NEXT:    vmrghh v3, v4, v3
 ; P9BE-NEXT:    clrlwi r4, r3, 16
 ; P9BE-NEXT:    rlwinm r3, r3, 30, 18, 31
 ; P9BE-NEXT:    mulhwu r3, r3, r5
 ; P9BE-NEXT:    srwi r3, r3, 2
 ; P9BE-NEXT:    mulli r3, r3, 124
-; P9BE-NEXT:    subf r3, r3, r4
+; P9BE-NEXT:    sub r3, r4, r3
 ; P9BE-NEXT:    lis r4, 22765
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v4, r3
 ; P9BE-NEXT:    li r3, 0
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    clrlwi r3, r3, 16
 ; P9BE-NEXT:    ori r4, r4, 8969
 ; P9BE-NEXT:    mulhwu r4, r3, r4
-; P9BE-NEXT:    subf r5, r4, r3
+; P9BE-NEXT:    sub r5, r3, r4
 ; P9BE-NEXT:    srwi r5, r5, 1
 ; P9BE-NEXT:    add r4, r5, r4
 ; P9BE-NEXT:    srwi r4, r4, 6
 ; P9BE-NEXT:    mulli r4, r4, 95
-; P9BE-NEXT:    subf r3, r4, r3
+; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v2, r3
 ; P9BE-NEXT:    vmrghh v2, v2, v4
 ; P9BE-NEXT:    vmrghw v2, v2, v3
 ; P9BE-NEXT:    blr
 ;
 ; P8LE-LABEL: fold_urem_vec_1:
 ; P8LE:       # %bb.0:

 ; P8LE-NEXT:    clrlwi r12, r8, 16
 ; P8LE-NEXT:    mulhwu r7, r11, r7
 ; P8LE-NEXT:    lis r11, 8456
 ; P8LE-NEXT:    rldicl r4, r4, 48, 48
 ; P8LE-NEXT:    mulhwu r10, r12, r10
 ; P8LE-NEXT:    ori r11, r11, 16913
 ; P8LE-NEXT:    rlwinm r12, r4, 30, 18, 31
 ; P8LE-NEXT:    mulhwu r11, r12, r11
-; P8LE-NEXT:    subf r9, r3, r9
+; P8LE-NEXT:    sub r9, r9, r3
 ; P8LE-NEXT:    srwi r9, r9, 1
 ; P8LE-NEXT:    srwi r7, r7, 5
 ; P8LE-NEXT:    add r3, r9, r3
 ; P8LE-NEXT:    srwi r9, r10, 8
 ; P8LE-NEXT:    srwi r3, r3, 6
 ; P8LE-NEXT:    mulli r7, r7, 98
 ; P8LE-NEXT:    srwi r10, r11, 2
 ; P8LE-NEXT:    mulli r9, r9, 1003
 ; P8LE-NEXT:    mulli r3, r3, 95
 ; P8LE-NEXT:    mulli r10, r10, 124
-; P8LE-NEXT:    subf r5, r7, r5
-; P8LE-NEXT:    subf r7, r9, r8
+; P8LE-NEXT:    sub r5, r5, r7
+; P8LE-NEXT:    sub r7, r8, r9
 ; P8LE-NEXT:    mtfprd f0, r5
-; P8LE-NEXT:    subf r3, r3, r6
-; P8LE-NEXT:    subf r4, r10, r4
+; P8LE-NEXT:    sub r3, r6, r3
+; P8LE-NEXT:    sub r4, r4, r10
 ; P8LE-NEXT:    mtfprd f1, r7
 ; P8LE-NEXT:    mtfprd f2, r3
 ; P8LE-NEXT:    xxswapd v2, vs0
 ; P8LE-NEXT:    mtfprd f3, r4
 ; P8LE-NEXT:    xxswapd v3, vs1
 ; P8LE-NEXT:    xxswapd v4, vs2
 ; P8LE-NEXT:    xxswapd v5, vs3
 ; P8LE-NEXT:    vmrglh v2, v3, v2

 ; P8BE-NEXT:    mulhwu r3, r6, r3
 ; P8BE-NEXT:    rldicl r4, r4, 32, 48
 ; P8BE-NEXT:    clrlwi r8, r8, 16
 ; P8BE-NEXT:    mulhwu r7, r5, r7
 ; P8BE-NEXT:    rlwinm r11, r4, 30, 18, 31
 ; P8BE-NEXT:    clrlwi r4, r4, 16
 ; P8BE-NEXT:    mulhwu r9, r8, r9
 ; P8BE-NEXT:    mulhwu r10, r11, r10
-; P8BE-NEXT:    subf r11, r3, r6
+; P8BE-NEXT:    sub r11, r6, r3
 ; P8BE-NEXT:    srwi r11, r11, 1
 ; P8BE-NEXT:    srwi r7, r7, 8
 ; P8BE-NEXT:    add r3, r11, r3
 ; P8BE-NEXT:    srwi r9, r9, 5
 ; P8BE-NEXT:    srwi r10, r10, 2
 ; P8BE-NEXT:    mulli r7, r7, 1003
 ; P8BE-NEXT:    srwi r3, r3, 6
 ; P8BE-NEXT:    mulli r9, r9, 98
 ; P8BE-NEXT:    mulli r3, r3, 95
 ; P8BE-NEXT:    mulli r10, r10, 124
-; P8BE-NEXT:    subf r5, r7, r5
-; P8BE-NEXT:    subf r7, r9, r8
+; P8BE-NEXT:    sub r5, r5, r7
+; P8BE-NEXT:    sub r7, r8, r9
 ; P8BE-NEXT:    sldi r5, r5, 48
-; P8BE-NEXT:    subf r3, r3, r6
-; P8BE-NEXT:    subf r4, r10, r4
+; P8BE-NEXT:    sub r3, r6, r3
+; P8BE-NEXT:    sub r4, r4, r10
 ; P8BE-NEXT:    mtvsrd v2, r5
 ; P8BE-NEXT:    sldi r5, r7, 48
 ; P8BE-NEXT:    sldi r3, r3, 48
 ; P8BE-NEXT:    sldi r4, r4, 48
 ; P8BE-NEXT:    mtvsrd v3, r5
 ; P8BE-NEXT:    mtvsrd v4, r3
 ; P8BE-NEXT:    mtvsrd v5, r4
 ; P8BE-NEXT:    vmrghh v2, v3, v2
 ; P8BE-NEXT:    vmrghh v3, v4, v5
 ; P8BE-NEXT:    vmrghw v2, v3, v2
 ; P8BE-NEXT:    blr
   %1 = urem <4 x i16> %x, <i16 95, i16 124, i16 98, i16 1003>
   ret <4 x i16> %1
 }
 
 define <4 x i16> @fold_urem_vec_2(<4 x i16> %x) {
 ; P9LE-LABEL: fold_urem_vec_2:
 ; P9LE:       # %bb.0:
 ; P9LE-NEXT:    li r3, 0
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    lis r5, 22765
 ; P9LE-NEXT:    ori r5, r5, 8969
 ; P9LE-NEXT:    clrlwi r4, r3, 16
 ; P9LE-NEXT:    mulhwu r6, r4, r5
-; P9LE-NEXT:    subf r4, r6, r4
+; P9LE-NEXT:    sub r4, r4, r6
 ; P9LE-NEXT:    srwi r4, r4, 1
 ; P9LE-NEXT:    add r4, r4, r6
 ; P9LE-NEXT:    srwi r4, r4, 6
 ; P9LE-NEXT:    mulli r4, r4, 95
-; P9LE-NEXT:    subf r3, r4, r3
+; P9LE-NEXT:    sub r3, r3, r4
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 2
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    clrlwi r4, r3, 16
 ; P9LE-NEXT:    mulhwu r6, r4, r5
-; P9LE-NEXT:    subf r4, r6, r4
+; P9LE-NEXT:    sub r4, r4, r6
 ; P9LE-NEXT:    srwi r4, r4, 1
 ; P9LE-NEXT:    add r4, r4, r6
 ; P9LE-NEXT:    srwi r4, r4, 6
 ; P9LE-NEXT:    mulli r4, r4, 95
-; P9LE-NEXT:    subf r3, r4, r3
+; P9LE-NEXT:    sub r3, r3, r4
 ; P9LE-NEXT:    xxswapd v3, vs0
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 4
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    clrlwi r4, r3, 16
 ; P9LE-NEXT:    mulhwu r6, r4, r5
-; P9LE-NEXT:    subf r4, r6, r4
+; P9LE-NEXT:    sub r4, r4, r6
 ; P9LE-NEXT:    srwi r4, r4, 1
 ; P9LE-NEXT:    add r4, r4, r6
 ; P9LE-NEXT:    srwi r4, r4, 6
 ; P9LE-NEXT:    mulli r4, r4, 95
-; P9LE-NEXT:    subf r3, r4, r3
+; P9LE-NEXT:    sub r3, r3, r4
 ; P9LE-NEXT:    xxswapd v4, vs0
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 6
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    clrlwi r4, r3, 16
 ; P9LE-NEXT:    mulhwu r5, r4, r5
-; P9LE-NEXT:    subf r4, r5, r4
+; P9LE-NEXT:    sub r4, r4, r5
 ; P9LE-NEXT:    srwi r4, r4, 1
 ; P9LE-NEXT:    add r4, r4, r5
 ; P9LE-NEXT:    srwi r4, r4, 6
 ; P9LE-NEXT:    mulli r4, r4, 95
-; P9LE-NEXT:    subf r3, r4, r3
+; P9LE-NEXT:    sub r3, r3, r4
 ; P9LE-NEXT:    vmrglh v3, v4, v3
 ; P9LE-NEXT:    xxswapd v4, vs0
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    xxswapd v2, vs0
 ; P9LE-NEXT:    vmrglh v2, v2, v4
 ; P9LE-NEXT:    vmrglw v2, v2, v3
 ; P9LE-NEXT:    blr
 ;
 ; P9BE-LABEL: fold_urem_vec_2:
 ; P9BE:       # %bb.0:
 ; P9BE-NEXT:    li r3, 6
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    lis r4, 22765
 ; P9BE-NEXT:    ori r4, r4, 8969
 ; P9BE-NEXT:    clrlwi r3, r3, 16
 ; P9BE-NEXT:    mulhwu r5, r3, r4
-; P9BE-NEXT:    subf r6, r5, r3
+; P9BE-NEXT:    sub r6, r3, r5
 ; P9BE-NEXT:    srwi r6, r6, 1
 ; P9BE-NEXT:    add r5, r6, r5
 ; P9BE-NEXT:    srwi r5, r5, 6
 ; P9BE-NEXT:    mulli r5, r5, 95
-; P9BE-NEXT:    subf r3, r5, r3
+; P9BE-NEXT:    sub r3, r3, r5
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v3, r3
 ; P9BE-NEXT:    li r3, 4
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    clrlwi r3, r3, 16
 ; P9BE-NEXT:    mulhwu r5, r3, r4
-; P9BE-NEXT:    subf r6, r5, r3
+; P9BE-NEXT:    sub r6, r3, r5
 ; P9BE-NEXT:    srwi r6, r6, 1
 ; P9BE-NEXT:    add r5, r6, r5
 ; P9BE-NEXT:    srwi r5, r5, 6
 ; P9BE-NEXT:    mulli r5, r5, 95
-; P9BE-NEXT:    subf r3, r5, r3
+; P9BE-NEXT:    sub r3, r3, r5
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v4, r3
 ; P9BE-NEXT:    li r3, 2
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    clrlwi r3, r3, 16
 ; P9BE-NEXT:    mulhwu r5, r3, r4
-; P9BE-NEXT:    subf r6, r5, r3
+; P9BE-NEXT:    sub r6, r3, r5
 ; P9BE-NEXT:    srwi r6, r6, 1
 ; P9BE-NEXT:    add r5, r6, r5
 ; P9BE-NEXT:    srwi r5, r5, 6
 ; P9BE-NEXT:    mulli r5, r5, 95
-; P9BE-NEXT:    subf r3, r5, r3
+; P9BE-NEXT:    sub r3, r3, r5
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    vmrghh v3, v4, v3
 ; P9BE-NEXT:    mtvsrd v4, r3
 ; P9BE-NEXT:    li r3, 0
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    clrlwi r3, r3, 16
 ; P9BE-NEXT:    mulhwu r4, r3, r4
-; P9BE-NEXT:    subf r5, r4, r3
+; P9BE-NEXT:    sub r5, r3, r4
 ; P9BE-NEXT:    srwi r5, r5, 1
 ; P9BE-NEXT:    add r4, r5, r4
 ; P9BE-NEXT:    srwi r4, r4, 6
 ; P9BE-NEXT:    mulli r4, r4, 95
-; P9BE-NEXT:    subf r3, r4, r3
+; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v2, r3
 ; P9BE-NEXT:    vmrghh v2, v2, v4
 ; P9BE-NEXT:    vmrghw v2, v2, v3
 ; P9BE-NEXT:    blr
 ;
 ; P8LE-LABEL: fold_urem_vec_2:
 ; P8LE:       # %bb.0:

 ; P8LE-NEXT:    clrlwi r9, r6, 16
 ; P8LE-NEXT:    rldicl r4, r4, 16, 48
 ; P8LE-NEXT:    mulhwu r10, r8, r3
 ; P8LE-NEXT:    clrlwi r11, r7, 16
 ; P8LE-NEXT:    clrlwi r0, r4, 16
 ; P8LE-NEXT:    mulhwu r12, r9, r3
 ; P8LE-NEXT:    mulhwu r30, r11, r3
 ; P8LE-NEXT:    mulhwu r3, r0, r3
-; P8LE-NEXT:    subf r8, r10, r8
+; P8LE-NEXT:    sub r8, r8, r10
 ; P8LE-NEXT:    srwi r8, r8, 1
-; P8LE-NEXT:    subf r9, r12, r9
+; P8LE-NEXT:    sub r9, r9, r12
 ; P8LE-NEXT:    add r8, r8, r10
-; P8LE-NEXT:    subf r10, r30, r11
-; P8LE-NEXT:    subf r11, r3, r0
+; P8LE-NEXT:    sub r10, r11, r30
+; P8LE-NEXT:    sub r11, r0, r3
 ; P8LE-NEXT:    srwi r9, r9, 1
 ; P8LE-NEXT:    srwi r10, r10, 1
 ; P8LE-NEXT:    srwi r11, r11, 1
 ; P8LE-NEXT:    add r9, r9, r12
 ; P8LE-NEXT:    srwi r8, r8, 6
 ; P8LE-NEXT:    add r10, r10, r30
 ; P8LE-NEXT:    add r3, r11, r3
 ; P8LE-NEXT:    srwi r9, r9, 6
 ; P8LE-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
 ; P8LE-NEXT:    mulli r8, r8, 95
 ; P8LE-NEXT:    srwi r10, r10, 6
 ; P8LE-NEXT:    srwi r3, r3, 6
 ; P8LE-NEXT:    mulli r9, r9, 95
 ; P8LE-NEXT:    mulli r10, r10, 95
 ; P8LE-NEXT:    mulli r3, r3, 95
-; P8LE-NEXT:    subf r5, r8, r5
-; P8LE-NEXT:    subf r6, r9, r6
+; P8LE-NEXT:    sub r5, r5, r8
+; P8LE-NEXT:    sub r6, r6, r9
 ; P8LE-NEXT:    mtfprd f0, r5
-; P8LE-NEXT:    subf r5, r10, r7
-; P8LE-NEXT:    subf r3, r3, r4
+; P8LE-NEXT:    sub r5, r7, r10
+; P8LE-NEXT:    sub r3, r4, r3
 ; P8LE-NEXT:    mtfprd f1, r6
 ; P8LE-NEXT:    mtfprd f2, r5
 ; P8LE-NEXT:    xxswapd v2, vs0
 ; P8LE-NEXT:    mtfprd f3, r3
 ; P8LE-NEXT:    xxswapd v3, vs1
 ; P8LE-NEXT:    xxswapd v4, vs2
 ; P8LE-NEXT:    xxswapd v5, vs3
 ; P8LE-NEXT:    vmrglh v2, v3, v2

 ; P8BE-NEXT:    clrlwi r6, r6, 16
 ; P8BE-NEXT:    mulhwu r8, r5, r3
 ; P8BE-NEXT:    rldicl r4, r4, 16, 48
 ; P8BE-NEXT:    clrlwi r7, r7, 16
 ; P8BE-NEXT:    mulhwu r9, r6, r3
 ; P8BE-NEXT:    clrlwi r4, r4, 16
 ; P8BE-NEXT:    mulhwu r10, r7, r3
 ; P8BE-NEXT:    mulhwu r3, r4, r3
-; P8BE-NEXT:    subf r11, r8, r5
-; P8BE-NEXT:    subf r12, r9, r6
+; P8BE-NEXT:    sub r11, r5, r8
+; P8BE-NEXT:    sub r12, r6, r9
 ; P8BE-NEXT:    srwi r11, r11, 1
 ; P8BE-NEXT:    add r8, r11, r8
-; P8BE-NEXT:    subf r11, r10, r7
+; P8BE-NEXT:    sub r11, r7, r10
 ; P8BE-NEXT:    srwi r12, r12, 1
 ; P8BE-NEXT:    add r9, r12, r9
-; P8BE-NEXT:    subf r12, r3, r4
+; P8BE-NEXT:    sub r12, r4, r3
 ; P8BE-NEXT:    srwi r11, r11, 1
 ; P8BE-NEXT:    srwi r8, r8, 6
 ; P8BE-NEXT:    add r10, r11, r10
 ; P8BE-NEXT:    srwi r11, r12, 1
 ; P8BE-NEXT:    srwi r9, r9, 6
 ; P8BE-NEXT:    add r3, r11, r3
 ; P8BE-NEXT:    srwi r10, r10, 6
 ; P8BE-NEXT:    srwi r3, r3, 6
 ; P8BE-NEXT:    mulli r8, r8, 95
 ; P8BE-NEXT:    mulli r9, r9, 95
 ; P8BE-NEXT:    mulli r10, r10, 95
 ; P8BE-NEXT:    mulli r3, r3, 95
-; P8BE-NEXT:    subf r5, r8, r5
-; P8BE-NEXT:    subf r6, r9, r6
-; P8BE-NEXT:    subf r7, r10, r7
-; P8BE-NEXT:    subf r3, r3, r4
+; P8BE-NEXT:    sub r5, r5, r8
+; P8BE-NEXT:    sub r6, r6, r9
+; P8BE-NEXT:    sub r7, r7, r10
+; P8BE-NEXT:    sub r3, r4, r3
 ; P8BE-NEXT:    sldi r5, r5, 48
 ; P8BE-NEXT:    sldi r6, r6, 48
 ; P8BE-NEXT:    sldi r4, r7, 48
 ; P8BE-NEXT:    mtvsrd v2, r5
 ; P8BE-NEXT:    sldi r3, r3, 48
 ; P8BE-NEXT:    mtvsrd v3, r6
 ; P8BE-NEXT:    mtvsrd v4, r4
 ; P8BE-NEXT:    mtvsrd v5, r3

 ; P9LE-LABEL: combine_urem_udiv:
 ; P9LE:       # %bb.0:
 ; P9LE-NEXT:    li r3, 0
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    lis r5, 22765
 ; P9LE-NEXT:    ori r5, r5, 8969
 ; P9LE-NEXT:    clrlwi r4, r3, 16
 ; P9LE-NEXT:    mulhwu r6, r4, r5
-; P9LE-NEXT:    subf r4, r6, r4
+; P9LE-NEXT:    sub r4, r4, r6
 ; P9LE-NEXT:    srwi r4, r4, 1
 ; P9LE-NEXT:    add r4, r4, r6
 ; P9LE-NEXT:    srwi r4, r4, 6
 ; P9LE-NEXT:    mulli r6, r4, 95
-; P9LE-NEXT:    subf r3, r6, r3
+; P9LE-NEXT:    sub r3, r3, r6
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 2
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    clrlwi r6, r3, 16
 ; P9LE-NEXT:    mulhwu r7, r6, r5
-; P9LE-NEXT:    subf r6, r7, r6
+; P9LE-NEXT:    sub r6, r6, r7
 ; P9LE-NEXT:    srwi r6, r6, 1
 ; P9LE-NEXT:    add r6, r6, r7
 ; P9LE-NEXT:    srwi r6, r6, 6
 ; P9LE-NEXT:    mulli r7, r6, 95
-; P9LE-NEXT:    subf r3, r7, r3
+; P9LE-NEXT:    sub r3, r3, r7
 ; P9LE-NEXT:    xxswapd v3, vs0
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 4
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    clrlwi r7, r3, 16
 ; P9LE-NEXT:    mulhwu r8, r7, r5
-; P9LE-NEXT:    subf r7, r8, r7
+; P9LE-NEXT:    sub r7, r7, r8
 ; P9LE-NEXT:    srwi r7, r7, 1
 ; P9LE-NEXT:    add r7, r7, r8
 ; P9LE-NEXT:    srwi r7, r7, 6
 ; P9LE-NEXT:    mulli r8, r7, 95
-; P9LE-NEXT:    subf r3, r8, r3
+; P9LE-NEXT:    sub r3, r3, r8
 ; P9LE-NEXT:    xxswapd v4, vs0
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 6
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    clrlwi r8, r3, 16
 ; P9LE-NEXT:    mulhwu r5, r8, r5
-; P9LE-NEXT:    subf r8, r5, r8
+; P9LE-NEXT:    sub r8, r8, r5
 ; P9LE-NEXT:    srwi r8, r8, 1
 ; P9LE-NEXT:    add r5, r8, r5
 ; P9LE-NEXT:    srwi r5, r5, 6
 ; P9LE-NEXT:    mulli r8, r5, 95
-; P9LE-NEXT:    subf r3, r8, r3
+; P9LE-NEXT:    sub r3, r3, r8
 ; P9LE-NEXT:    vmrglh v3, v4, v3
 ; P9LE-NEXT:    xxswapd v4, vs0
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    xxswapd v2, vs0
 ; P9LE-NEXT:    mtfprd f0, r4
 ; P9LE-NEXT:    vmrglh v2, v2, v4
 ; P9LE-NEXT:    vmrglw v2, v2, v3
 ; P9LE-NEXT:    xxswapd v3, vs0

 ; P9BE-LABEL: combine_urem_udiv:
 ; P9BE:       # %bb.0:
 ; P9BE-NEXT:    li r3, 6
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    lis r5, 22765
 ; P9BE-NEXT:    ori r5, r5, 8969
 ; P9BE-NEXT:    clrlwi r4, r3, 16
 ; P9BE-NEXT:    mulhwu r6, r4, r5
-; P9BE-NEXT:    subf r4, r6, r4
+; P9BE-NEXT:    sub r4, r4, r6
 ; P9BE-NEXT:    srwi r4, r4, 1
 ; P9BE-NEXT:    add r4, r4, r6
 ; P9BE-NEXT:    srwi r4, r4, 6
 ; P9BE-NEXT:    mulli r6, r4, 95
-; P9BE-NEXT:    subf r3, r6, r3
+; P9BE-NEXT:    sub r3, r3, r6
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v3, r3
 ; P9BE-NEXT:    li r3, 4
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    clrlwi r6, r3, 16
 ; P9BE-NEXT:    mulhwu r7, r6, r5
-; P9BE-NEXT:    subf r6, r7, r6
+; P9BE-NEXT:    sub r6, r6, r7
 ; P9BE-NEXT:    srwi r6, r6, 1
 ; P9BE-NEXT:    add r6, r6, r7
 ; P9BE-NEXT:    srwi r6, r6, 6
 ; P9BE-NEXT:    mulli r7, r6, 95
-; P9BE-NEXT:    subf r3, r7, r3
+; P9BE-NEXT:    sub r3, r3, r7
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v4, r3
 ; P9BE-NEXT:    li r3, 2
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    clrlwi r7, r3, 16
 ; P9BE-NEXT:    mulhwu r8, r7, r5
-; P9BE-NEXT:    subf r7, r8, r7
+; P9BE-NEXT:    sub r7, r7, r8
 ; P9BE-NEXT:    srwi r7, r7, 1
 ; P9BE-NEXT:    add r7, r7, r8
 ; P9BE-NEXT:    srwi r7, r7, 6
 ; P9BE-NEXT:    mulli r8, r7, 95
-; P9BE-NEXT:    subf r3, r8, r3
+; P9BE-NEXT:    sub r3, r3, r8
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    vmrghh v3, v4, v3
 ; P9BE-NEXT:    mtvsrd v4, r3
 ; P9BE-NEXT:    li r3, 0
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    clrlwi r3, r3, 16
 ; P9BE-NEXT:    mulhwu r5, r3, r5
-; P9BE-NEXT:    subf r8, r5, r3
+; P9BE-NEXT:    sub r8, r3, r5
 ; P9BE-NEXT:    srwi r8, r8, 1
 ; P9BE-NEXT:    add r5, r8, r5
 ; P9BE-NEXT:    srwi r5, r5, 6
 ; P9BE-NEXT:    mulli r8, r5, 95
-; P9BE-NEXT:    subf r3, r8, r3
+; P9BE-NEXT:    sub r3, r3, r8
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v2, r3
 ; P9BE-NEXT:    sldi r3, r4, 48
 ; P9BE-NEXT:    vmrghh v2, v2, v4
 ; P9BE-NEXT:    vmrghw v2, v2, v3
 ; P9BE-NEXT:    mtvsrd v3, r3
 ; P9BE-NEXT:    sldi r3, r6, 48
 ; P9BE-NEXT:    mtvsrd v4, r3

 ; P8LE-NEXT:    clrlwi r9, r6, 16
 ; P8LE-NEXT:    mulhwu r10, r8, r4
 ; P8LE-NEXT:    clrlwi r11, r7, 16
 ; P8LE-NEXT:    rldicl r5, r5, 16, 48
 ; P8LE-NEXT:    mulhwu r12, r9, r4
 ; P8LE-NEXT:    mulhwu r0, r11, r4
 ; P8LE-NEXT:    clrlwi r30, r5, 16
 ; P8LE-NEXT:    mulhwu r4, r30, r4
-; P8LE-NEXT:    subf r8, r10, r8
+; P8LE-NEXT:    sub r8, r8, r10
 ; P8LE-NEXT:    srwi r8, r8, 1
-; P8LE-NEXT:    subf r9, r12, r9
+; P8LE-NEXT:    sub r9, r9, r12
 ; P8LE-NEXT:    add r8, r8, r10
-; P8LE-NEXT:    subf r10, r0, r11
+; P8LE-NEXT:    sub r10, r11, r0
 ; P8LE-NEXT:    srwi r9, r9, 1
 ; P8LE-NEXT:    srwi r10, r10, 1
-; P8LE-NEXT:    subf r11, r4, r30
+; P8LE-NEXT:    sub r11, r30, r4
 ; P8LE-NEXT:    add r9, r9, r12
 ; P8LE-NEXT:    srwi r8, r8, 6
 ; P8LE-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
 ; P8LE-NEXT:    add r10, r10, r0
 ; P8LE-NEXT:    srwi r11, r11, 1
 ; P8LE-NEXT:    srwi r9, r9, 6
 ; P8LE-NEXT:    mtfprd f0, r8
 ; P8LE-NEXT:    mulli r12, r8, 95
 ; P8LE-NEXT:    srwi r10, r10, 6
 ; P8LE-NEXT:    add r4, r11, r4
 ; P8LE-NEXT:    mtfprd f1, r9
 ; P8LE-NEXT:    mulli r8, r9, 95
 ; P8LE-NEXT:    mulli r9, r10, 95
 ; P8LE-NEXT:    srwi r4, r4, 6
 ; P8LE-NEXT:    xxswapd v2, vs0
 ; P8LE-NEXT:    mtfprd f2, r10
 ; P8LE-NEXT:    mtfprd f3, r4
 ; P8LE-NEXT:    mulli r4, r4, 95
 ; P8LE-NEXT:    xxswapd v3, vs1
 ; P8LE-NEXT:    xxswapd v1, vs2
-; P8LE-NEXT:    subf r3, r12, r3
+; P8LE-NEXT:    sub r3, r3, r12
 ; P8LE-NEXT:    xxswapd v6, vs3
 ; P8LE-NEXT:    mtfprd f0, r3
-; P8LE-NEXT:    subf r3, r9, r7
-; P8LE-NEXT:    subf r6, r8, r6
+; P8LE-NEXT:    sub r3, r7, r9
+; P8LE-NEXT:    sub r6, r6, r8
 ; P8LE-NEXT:    mtfprd f4, r3
-; P8LE-NEXT:    subf r3, r4, r5
+; P8LE-NEXT:    sub r3, r5, r4
 ; P8LE-NEXT:    mtfprd f1, r6
 ; P8LE-NEXT:    mtfprd f5, r3
 ; P8LE-NEXT:    xxswapd v5, vs4
 ; P8LE-NEXT:    vmrglh v2, v3, v2
 ; P8LE-NEXT:    xxswapd v3, vs0
 ; P8LE-NEXT:    xxswapd v4, vs1
 ; P8LE-NEXT:    xxswapd v0, vs5
 ; P8LE-NEXT:    vmrglh v3, v4, v3

 ; P8BE-NEXT:    clrlwi r9, r6, 16
 ; P8BE-NEXT:    rldicl r5, r5, 16, 48
 ; P8BE-NEXT:    mulhwu r10, r8, r4
 ; P8BE-NEXT:    clrlwi r11, r7, 16
 ; P8BE-NEXT:    mulhwu r12, r9, r4
 ; P8BE-NEXT:    clrlwi r5, r5, 16
 ; P8BE-NEXT:    mulhwu r0, r11, r4
 ; P8BE-NEXT:    mulhwu r4, r5, r4
-; P8BE-NEXT:    subf r8, r10, r8
-; P8BE-NEXT:    subf r9, r12, r9
+; P8BE-NEXT:    sub r8, r8, r10
+; P8BE-NEXT:    sub r9, r9, r12
 ; P8BE-NEXT:    srwi r8, r8, 1
 ; P8BE-NEXT:    add r8, r8, r10
-; P8BE-NEXT:    subf r10, r0, r11
+; P8BE-NEXT:    sub r10, r11, r0
 ; P8BE-NEXT:    srwi r9, r9, 1
-; P8BE-NEXT:    subf r11, r4, r5
+; P8BE-NEXT:    sub r11, r5, r4
 ; P8BE-NEXT:    add r9, r9, r12
 ; P8BE-NEXT:    srwi r8, r8, 6
 ; P8BE-NEXT:    srwi r11, r11, 1
 ; P8BE-NEXT:    srwi r10, r10, 1
 ; P8BE-NEXT:    srwi r9, r9, 6
 ; P8BE-NEXT:    mulli r12, r8, 95
 ; P8BE-NEXT:    add r4, r11, r4
 ; P8BE-NEXT:    add r10, r10, r0
 ; P8BE-NEXT:    mulli r11, r9, 95
 ; P8BE-NEXT:    srwi r4, r4, 6
 ; P8BE-NEXT:    srwi r10, r10, 6
 ; P8BE-NEXT:    sldi r9, r9, 48
 ; P8BE-NEXT:    sldi r8, r8, 48
 ; P8BE-NEXT:    mtvsrd v3, r9
 ; P8BE-NEXT:    mulli r9, r4, 95
 ; P8BE-NEXT:    mtvsrd v2, r8
 ; P8BE-NEXT:    mulli r8, r10, 95
-; P8BE-NEXT:    subf r3, r12, r3
-; P8BE-NEXT:    subf r6, r11, r6
+; P8BE-NEXT:    sub r3, r3, r12
+; P8BE-NEXT:    sub r6, r6, r11
 ; P8BE-NEXT:    sldi r3, r3, 48
 ; P8BE-NEXT:    vmrghh v2, v3, v2
 ; P8BE-NEXT:    sldi r6, r6, 48
 ; P8BE-NEXT:    sldi r10, r10, 48
 ; P8BE-NEXT:    mtvsrd v3, r3
-; P8BE-NEXT:    subf r3, r9, r5
-; P8BE-NEXT:    subf r7, r8, r7
+; P8BE-NEXT:    sub r3, r5, r9
+; P8BE-NEXT:    sub r7, r7, r8
 ; P8BE-NEXT:    mtvsrd v5, r6
 ; P8BE-NEXT:    sldi r3, r3, 48
 ; P8BE-NEXT:    sldi r5, r7, 48
 ; P8BE-NEXT:    mtvsrd v1, r3
 ; P8BE-NEXT:    sldi r3, r4, 48
 ; P8BE-NEXT:    mtvsrd v4, r10
 ; P8BE-NEXT:    mtvsrd v0, r5
 ; P8BE-NEXT:    vmrghh v3, v5, v3

 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 6
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    lis r5, 22765
 ; P9LE-NEXT:    ori r5, r5, 8969
 ; P9LE-NEXT:    xxswapd v4, vs0
 ; P9LE-NEXT:    clrlwi r4, r3, 16
 ; P9LE-NEXT:    mulhwu r5, r4, r5
-; P9LE-NEXT:    subf r4, r5, r4
+; P9LE-NEXT:    sub r4, r4, r5
 ; P9LE-NEXT:    srwi r4, r4, 1
 ; P9LE-NEXT:    add r4, r4, r5
 ; P9LE-NEXT:    srwi r4, r4, 6
 ; P9LE-NEXT:    mulli r4, r4, 95
-; P9LE-NEXT:    subf r3, r4, r3
+; P9LE-NEXT:    sub r3, r3, r4
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 4
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    clrlwi r3, r3, 29
 ; P9LE-NEXT:    vmrglh v3, v4, v3
 ; P9LE-NEXT:    xxswapd v4, vs0
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    xxswapd v2, vs0

 ; P9BE-NEXT:    mtvsrd v4, r3
 ; P9BE-NEXT:    li r3, 6
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    lis r4, 22765
 ; P9BE-NEXT:    ori r4, r4, 8969
 ; P9BE-NEXT:    vmrghh v3, v4, v3
 ; P9BE-NEXT:    clrlwi r3, r3, 16
 ; P9BE-NEXT:    mulhwu r4, r3, r4
-; P9BE-NEXT:    subf r5, r4, r3
+; P9BE-NEXT:    sub r5, r3, r4
 ; P9BE-NEXT:    srwi r5, r5, 1
 ; P9BE-NEXT:    add r4, r5, r4
 ; P9BE-NEXT:    srwi r4, r4, 6
 ; P9BE-NEXT:    mulli r4, r4, 95
-; P9BE-NEXT:    subf r3, r4, r3
+; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v4, r3
 ; P9BE-NEXT:    li r3, 4
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    clrlwi r3, r3, 29
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v2, r3
 ; P9BE-NEXT:    vmrghh v2, v2, v4
 ; P9BE-NEXT:    vmrghw v2, v3, v2
 ; P9BE-NEXT:    blr
 ;
 ; P8LE-LABEL: dont_fold_urem_power_of_two:
 ; P8LE:       # %bb.0:
 ; P8LE-NEXT:    xxswapd vs0, v2
 ; P8LE-NEXT:    lis r3, 22765
 ; P8LE-NEXT:    ori r3, r3, 8969
 ; P8LE-NEXT:    mffprd r4, f0
 ; P8LE-NEXT:    rldicl r5, r4, 16, 48
 ; P8LE-NEXT:    rldicl r7, r4, 48, 48
 ; P8LE-NEXT:    clrlwi r6, r5, 16
 ; P8LE-NEXT:    mulhwu r3, r6, r3
-; P8LE-NEXT:    subf r6, r3, r6
+; P8LE-NEXT:    sub r6, r6, r3
 ; P8LE-NEXT:    srwi r6, r6, 1
 ; P8LE-NEXT:    add r3, r6, r3
 ; P8LE-NEXT:    clrldi r6, r4, 48
 ; P8LE-NEXT:    srwi r3, r3, 6
 ; P8LE-NEXT:    clrlwi r6, r6, 26
 ; P8LE-NEXT:    mulli r3, r3, 95
 ; P8LE-NEXT:    rldicl r4, r4, 32, 48
 ; P8LE-NEXT:    mtfprd f0, r6
 ; P8LE-NEXT:    clrlwi r6, r7, 27
 ; P8LE-NEXT:    clrlwi r4, r4, 29
 ; P8LE-NEXT:    mtfprd f1, r6
 ; P8LE-NEXT:    mtfprd f3, r4
 ; P8LE-NEXT:    xxswapd v2, vs0
 ; P8LE-NEXT:    xxswapd v3, vs1
-; P8LE-NEXT:    subf r3, r3, r5
+; P8LE-NEXT:    sub r3, r5, r3
 ; P8LE-NEXT:    xxswapd v5, vs3
 ; P8LE-NEXT:    mtfprd f2, r3
 ; P8LE-NEXT:    vmrglh v2, v3, v2
 ; P8LE-NEXT:    xxswapd v4, vs2
 ; P8LE-NEXT:    vmrglh v3, v4, v5
 ; P8LE-NEXT:    vmrglw v2, v3, v2
 ; P8LE-NEXT:    blr
 ;
 ; P8BE-LABEL: dont_fold_urem_power_of_two:
 ; P8BE:       # %bb.0:
 ; P8BE-NEXT:    mfvsrd r4, v2
 ; P8BE-NEXT:    lis r3, 22765
 ; P8BE-NEXT:    ori r3, r3, 8969
 ; P8BE-NEXT:    clrldi r5, r4, 48
 ; P8BE-NEXT:    rldicl r7, r4, 16, 48
 ; P8BE-NEXT:    clrlwi r5, r5, 16
 ; P8BE-NEXT:    clrlwi r7, r7, 26
 ; P8BE-NEXT:    mulhwu r3, r5, r3
-; P8BE-NEXT:    subf r6, r3, r5
+; P8BE-NEXT:    sub r6, r5, r3
 ; P8BE-NEXT:    srwi r6, r6, 1
 ; P8BE-NEXT:    add r3, r6, r3
 ; P8BE-NEXT:    rldicl r6, r4, 32, 48
 ; P8BE-NEXT:    srwi r3, r3, 6
 ; P8BE-NEXT:    rldicl r4, r4, 48, 48
 ; P8BE-NEXT:    clrlwi r6, r6, 27
 ; P8BE-NEXT:    mulli r3, r3, 95
 ; P8BE-NEXT:    sldi r6, r6, 48
 ; P8BE-NEXT:    clrlwi r4, r4, 29
 ; P8BE-NEXT:    mtvsrd v2, r6
 ; P8BE-NEXT:    sldi r6, r7, 48
 ; P8BE-NEXT:    sldi r4, r4, 48
 ; P8BE-NEXT:    mtvsrd v3, r6
 ; P8BE-NEXT:    mtvsrd v5, r4
-; P8BE-NEXT:    subf r3, r3, r5
+; P8BE-NEXT:    sub r3, r5, r3
 ; P8BE-NEXT:    vmrghh v2, v3, v2
 ; P8BE-NEXT:    sldi r3, r3, 48
 ; P8BE-NEXT:    mtvsrd v4, r3
 ; P8BE-NEXT:    vmrghh v3, v5, v4
 ; P8BE-NEXT:    vmrghw v2, v2, v3
 ; P8BE-NEXT:    blr
   %1 = urem <4 x i16> %x, <i16 64, i16 32, i16 8, i16 95>
   ret <4 x i16> %1
 }
 
 ; Don't fold if the divisor is one.
 define <4 x i16> @dont_fold_urem_one(<4 x i16> %x) {
 ; P9LE-LABEL: dont_fold_urem_one:
 ; P9LE:       # %bb.0:
 ; P9LE-NEXT:    li r3, 4
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    lis r5, -19946
 ; P9LE-NEXT:    ori r5, r5, 17097
 ; P9LE-NEXT:    clrlwi r4, r3, 16
 ; P9LE-NEXT:    mulhwu r4, r4, r5
 ; P9LE-NEXT:    lis r5, 24749
 ; P9LE-NEXT:    ori r5, r5, 47143
 ; P9LE-NEXT:    srwi r4, r4, 4
 ; P9LE-NEXT:    mulli r4, r4, 23
-; P9LE-NEXT:    subf r3, r4, r3
+; P9LE-NEXT:    sub r3, r3, r4
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 6
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    clrlwi r4, r3, 16
 ; P9LE-NEXT:    mulhwu r4, r4, r5
 ; P9LE-NEXT:    lis r5, -14230
 ; P9LE-NEXT:    ori r5, r5, 30865
 ; P9LE-NEXT:    srwi r4, r4, 11
 ; P9LE-NEXT:    mulli r4, r4, 5423
-; P9LE-NEXT:    subf r3, r4, r3
+; P9LE-NEXT:    sub r3, r3, r4
 ; P9LE-NEXT:    xxswapd v3, vs0
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 2
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    rlwinm r4, r3, 31, 17, 31
 ; P9LE-NEXT:    mulhwu r4, r4, r5
 ; P9LE-NEXT:    srwi r4, r4, 8
 ; P9LE-NEXT:    mulli r4, r4, 654
-; P9LE-NEXT:    subf r3, r4, r3
+; P9LE-NEXT:    sub r3, r3, r4
 ; P9LE-NEXT:    xxswapd v4, vs0
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    xxswapd v2, vs0
 ; P9LE-NEXT:    vmrglh v3, v4, v3
 ; P9LE-NEXT:    xxlxor v4, v4, v4
 ; P9LE-NEXT:    vmrglh v2, v2, v4
 ; P9LE-NEXT:    vmrglw v2, v3, v2
 ; P9LE-NEXT:    blr
 ;
 ; P9BE-LABEL: dont_fold_urem_one:
 ; P9BE:       # %bb.0:
 ; P9BE-NEXT:    li r3, 6
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    lis r4, 24749
 ; P9BE-NEXT:    ori r4, r4, 47143
 ; P9BE-NEXT:    clrlwi r3, r3, 16
 ; P9BE-NEXT:    mulhwu r4, r3, r4
 ; P9BE-NEXT:    srwi r4, r4, 11
 ; P9BE-NEXT:    mulli r4, r4, 5423
-; P9BE-NEXT:    subf r3, r4, r3
+; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    lis r4, -19946
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v3, r3
 ; P9BE-NEXT:    li r3, 4
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    clrlwi r3, r3, 16
 ; P9BE-NEXT:    ori r4, r4, 17097
 ; P9BE-NEXT:    mulhwu r4, r3, r4
 ; P9BE-NEXT:    srwi r4, r4, 4
 ; P9BE-NEXT:    mulli r4, r4, 23
-; P9BE-NEXT:    subf r3, r4, r3
+; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v4, r3
 ; P9BE-NEXT:    li r3, 2
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    lis r5, -14230
 ; P9BE-NEXT:    ori r5, r5, 30865
 ; P9BE-NEXT:    vmrghh v3, v4, v3
 ; P9BE-NEXT:    clrlwi r4, r3, 16
 ; P9BE-NEXT:    rlwinm r3, r3, 31, 17, 31
 ; P9BE-NEXT:    mulhwu r3, r3, r5
 ; P9BE-NEXT:    srwi r3, r3, 8
 ; P9BE-NEXT:    mulli r3, r3, 654
-; P9BE-NEXT:    subf r3, r3, r4
+; P9BE-NEXT:    sub r3, r4, r3
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v2, r3
 ; P9BE-NEXT:    li r3, 0
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v4, r3
 ; P9BE-NEXT:    vmrghh v2, v4, v2
 ; P9BE-NEXT:    vmrghw v2, v2, v3
 ; P9BE-NEXT:    blr

 ; P8LE-NEXT:    rlwinm r8, r4, 31, 17, 31
 ; P8LE-NEXT:    mulhwu r8, r8, r9
 ; P8LE-NEXT:    srwi r3, r3, 4
 ; P8LE-NEXT:    srwi r7, r7, 11
 ; P8LE-NEXT:    mulli r3, r3, 23
 ; P8LE-NEXT:    srwi r8, r8, 8
 ; P8LE-NEXT:    mulli r7, r7, 5423
 ; P8LE-NEXT:    mulli r8, r8, 654
-; P8LE-NEXT:    subf r3, r3, r5
-; P8LE-NEXT:    subf r5, r7, r6
+; P8LE-NEXT:    sub r3, r5, r3
+; P8LE-NEXT:    sub r5, r6, r7
 ; P8LE-NEXT:    mtfprd f0, r3
-; P8LE-NEXT:    subf r3, r8, r4
+; P8LE-NEXT:    sub r3, r4, r8
 ; P8LE-NEXT:    mtfprd f1, r5
 ; P8LE-NEXT:    mtfprd f2, r3
 ; P8LE-NEXT:    xxswapd v2, vs0
 ; P8LE-NEXT:    xxswapd v3, vs1
 ; P8LE-NEXT:    xxswapd v4, vs2
 ; P8LE-NEXT:    vmrglh v2, v3, v2
 ; P8LE-NEXT:    vmrglh v3, v4, v5
 ; P8LE-NEXT:    vmrglw v2, v2, v3

 ; P8BE-NEXT:    mulhwu r8, r9, r8
 ; P8BE-NEXT:    li r9, 0
 ; P8BE-NEXT:    srwi r3, r3, 11
 ; P8BE-NEXT:    srwi r7, r7, 4
 ; P8BE-NEXT:    mulli r3, r3, 5423
 ; P8BE-NEXT:    srwi r8, r8, 8
 ; P8BE-NEXT:    mulli r7, r7, 23
 ; P8BE-NEXT:    mulli r8, r8, 654
-; P8BE-NEXT:    subf r3, r3, r5
+; P8BE-NEXT:    sub r3, r5, r3
 ; P8BE-NEXT:    sldi r5, r9, 48
 ; P8BE-NEXT:    mtvsrd v2, r5
-; P8BE-NEXT:    subf r5, r7, r6
+; P8BE-NEXT:    sub r5, r6, r7
 ; P8BE-NEXT:    sldi r3, r3, 48
-; P8BE-NEXT:    subf r4, r8, r4
+; P8BE-NEXT:    sub r4, r4, r8
 ; P8BE-NEXT:    sldi r5, r5, 48
 ; P8BE-NEXT:    mtvsrd v3, r3
 ; P8BE-NEXT:    sldi r3, r4, 48
 ; P8BE-NEXT:    mtvsrd v4, r5
 ; P8BE-NEXT:    mtvsrd v5, r3
 ; P8BE-NEXT:    vmrghh v3, v4, v3
 ; P8BE-NEXT:    vmrghh v2, v2, v5
 ; P8BE-NEXT:    vmrghw v2, v2, v3

llvm/test/CodeGen/PowerPC/use-cr-result-of-dom-icmp-st.ll

 ; CHECK-NEXT:    sld r5, r3, r4
 ; CHECK-NEXT:    cmpdi r5, -2
 ; CHECK-NEXT:    ble cr0, .LBB0_2
 ; CHECK-NEXT:  # %bb.1: # %return
 ; CHECK-NEXT:    mr r3, r4
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB0_2: # %if.end
 ; CHECK-NEXT:    li r5, 1
-; CHECK-NEXT:    isel r4, r5, r4, lt
+; CHECK-NEXT:    isellt r4, r5, r4
 ; CHECK-NEXT:    mulld r3, r4, r3
 ; CHECK-NEXT:    blr
 entry:
   %shl = shl i64 %a, %b
   %cmp = icmp sgt i64 %shl, -2
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry

 ; CHECK-NEXT:    sld r5, r3, r4
 ; CHECK-NEXT:    cmpdi r5, -1
 ; CHECK-NEXT:    ble cr0, .LBB1_2
 ; CHECK-NEXT:  # %bb.1: # %return
 ; CHECK-NEXT:    mr r3, r4
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB1_2: # %if.end
 ; CHECK-NEXT:    li r5, 1
-; CHECK-NEXT:    isel r4, r5, r4, lt
+; CHECK-NEXT:    isellt r4, r5, r4
 ; CHECK-NEXT:    mulld r3, r4, r3
 ; CHECK-NEXT:    blr
 entry:
   %shl = shl i64 %a, %b
   %cmp = icmp sgt i64 %shl, -1
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry

 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sld. r5, r3, r4
 ; CHECK-NEXT:    ble cr0, .LBB2_2
 ; CHECK-NEXT:  # %bb.1: # %return
 ; CHECK-NEXT:    mr r3, r4
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB2_2: # %if.end
 ; CHECK-NEXT:    li r5, 1
-; CHECK-NEXT:    isel r4, r5, r4, lt
+; CHECK-NEXT:    isellt r4, r5, r4
 ; CHECK-NEXT:    mulld r3, r4, r3
 ; CHECK-NEXT:    blr
 entry:
   %shl = shl i64 %a, %b
   %cmp = icmp sgt i64 %shl, 0
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry

 ; CHECK-NEXT:    sld r5, r3, r4
 ; CHECK-NEXT:    cmpdi r5, 1
 ; CHECK-NEXT:    ble cr0, .LBB3_2
 ; CHECK-NEXT:  # %bb.1: # %return
 ; CHECK-NEXT:    mr r3, r4
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB3_2: # %if.end
 ; CHECK-NEXT:    li r5, 1
-; CHECK-NEXT:    isel r4, r5, r4, lt
+; CHECK-NEXT:    isellt r4, r5, r4
 ; CHECK-NEXT:    mulld r3, r4, r3
 ; CHECK-NEXT:    blr
 entry:
   %shl = shl i64 %a, %b
   %cmp = icmp sgt i64 %shl, 1
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry

 ; CHECK-NEXT:    sld r5, r3, r4
 ; CHECK-NEXT:    cmpdi r5, 2
 ; CHECK-NEXT:    ble cr0, .LBB4_2
 ; CHECK-NEXT:  # %bb.1: # %return
 ; CHECK-NEXT:    mr r3, r4
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB4_2: # %if.end
 ; CHECK-NEXT:    li r5, 1
-; CHECK-NEXT:    isel r4, r5, r4, lt
+; CHECK-NEXT:    isellt r4, r5, r4
 ; CHECK-NEXT:    mulld r3, r4, r3
 ; CHECK-NEXT:    blr
 entry:
   %shl = shl i64 %a, %b
   %cmp = icmp sgt i64 %shl, 2
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry

 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpdi r3, -2
 ; CHECK-NEXT:    ble cr0, .LBB5_2
 ; CHECK-NEXT:  # %bb.1: # %return
 ; CHECK-NEXT:    mr r3, r4
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB5_2: # %if.end
 ; CHECK-NEXT:    li r5, 1
-; CHECK-NEXT:    isel r4, r5, r4, lt
+; CHECK-NEXT:    isellt r4, r5, r4
 ; CHECK-NEXT:    mulld r3, r4, r3
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i64 %a, -2
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry
   %cmp1 = icmp eq i64 %a, -2

 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpdi r3, -1
 ; CHECK-NEXT:    ble cr0, .LBB6_2
 ; CHECK-NEXT:  # %bb.1: # %return
 ; CHECK-NEXT:    mr r3, r4
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB6_2: # %if.end
 ; CHECK-NEXT:    li r5, 1
-; CHECK-NEXT:    isel r4, r5, r4, lt
+; CHECK-NEXT:    isellt r4, r5, r4
 ; CHECK-NEXT:    mulld r3, r4, r3
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i64 %a, -1
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry
   %cmp1 = icmp eq i64 %a, -1

 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpdi r3, 0
 ; CHECK-NEXT:    ble cr0, .LBB7_2
 ; CHECK-NEXT:  # %bb.1: # %return
 ; CHECK-NEXT:    mr r3, r4
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB7_2: # %if.end
 ; CHECK-NEXT:    li r5, 1
-; CHECK-NEXT:    isel r4, r5, r4, lt
+; CHECK-NEXT:    isellt r4, r5, r4
 ; CHECK-NEXT:    mulld r3, r4, r3
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i64 %a, 0
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry
   %cmp1 = icmp eq i64 %a, 0

 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpdi r3, 1
 ; CHECK-NEXT:    ble cr0, .LBB8_2
 ; CHECK-NEXT:  # %bb.1: # %return
 ; CHECK-NEXT:    mr r3, r4
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB8_2: # %if.end
 ; CHECK-NEXT:    li r5, 1
-; CHECK-NEXT:    isel r4, r5, r4, lt
+; CHECK-NEXT:    isellt r4, r5, r4
 ; CHECK-NEXT:    mulld r3, r4, r3
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i64 %a, 1
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry
   %cmp1 = icmp eq i64 %a, 1

 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpdi r3, 2
 ; CHECK-NEXT:    ble cr0, .LBB9_2
 ; CHECK-NEXT:  # %bb.1: # %return
 ; CHECK-NEXT:    mr r3, r4
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB9_2: # %if.end
 ; CHECK-NEXT:    li r5, 1
-; CHECK-NEXT:    isel r4, r5, r4, lt
+; CHECK-NEXT:    isellt r4, r5, r4
 ; CHECK-NEXT:    mulld r3, r4, r3
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i64 %a, 2
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry
   %cmp1 = icmp eq i64 %a, 2
   %mul = select i1 %cmp1, i64 %b, i64 1
   %spec.select = mul nsw i64 %mul, %a
   ret i64 %spec.select
 
 return:                                           ; preds = %entry
   ret i64 %b
 }
 
 define i64 @i_a_op_b__2(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: i_a_op_b__2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    slw r5, r3, r4
 ; CHECK-NEXT:    cmpwi r5, -2
 ; CHECK-NEXT:    bgt cr0, .LBB10_2
 ; CHECK-NEXT:  # %bb.1: # %if.end
 ; CHECK-NEXT:    li r5, 1
-; CHECK-NEXT:    isel r4, r5, r4, lt
+; CHECK-NEXT:    isellt r4, r5, r4
 ; CHECK-NEXT:    mullw r4, r4, r3
 ; CHECK-NEXT:  .LBB10_2: # %return
 ; CHECK-NEXT:    extsw r3, r4
 ; CHECK-NEXT:    blr
 entry:
   %shl = shl i32 %a, %b
   %cmp = icmp sgt i32 %shl, -2
   br i1 %cmp, label %return, label %if.end

 ; CHECK-NEXT:    slw r5, r3, r4
 ; CHECK-NEXT:    cmpwi r5, -1
 ; CHECK-NEXT:    ble cr0, .LBB11_2
 ; CHECK-NEXT:  # %bb.1: # %return
 ; CHECK-NEXT:    extsw r3, r4
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB11_2: # %if.end
 ; CHECK-NEXT:    li r5, 1
-; CHECK-NEXT:    isel r4, r5, r4, lt
+; CHECK-NEXT:    isellt r4, r5, r4
 ; CHECK-NEXT:    mullw r4, r4, r3
 ; CHECK-NEXT:    extsw r3, r4
 ; CHECK-NEXT:    blr
 entry:
   %shl = shl i32 %a, %b
   %cmp = icmp sgt i32 %shl, -1
   br i1 %cmp, label %return, label %if.end
 

 ; CHECK-NEXT:    slw r5, r3, r4
 ; CHECK-NEXT:    cmpwi r5, 0
 ; CHECK-NEXT:    ble cr0, .LBB12_2
 ; CHECK-NEXT:  # %bb.1: # %return
 ; CHECK-NEXT:    extsw r3, r4
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB12_2: # %if.end
 ; CHECK-NEXT:    li r5, 1
-; CHECK-NEXT:    isel r4, r5, r4, lt
+; CHECK-NEXT:    isellt r4, r5, r4
 ; CHECK-NEXT:    mullw r4, r4, r3
 ; CHECK-NEXT:    extsw r3, r4
 ; CHECK-NEXT:    blr
 entry:
   %shl = shl i32 %a, %b
   %cmp = icmp sgt i32 %shl, 0
   br i1 %cmp, label %return, label %if.end
 

 define i64 @i_a_op_b_1(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: i_a_op_b_1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    slw r5, r3, r4
 ; CHECK-NEXT:    cmpwi r5, 1
 ; CHECK-NEXT:    bgt cr0, .LBB13_2
 ; CHECK-NEXT:  # %bb.1: # %if.end
 ; CHECK-NEXT:    li r5, 1
-; CHECK-NEXT:    isel r4, r5, r4, lt
+; CHECK-NEXT:    isellt r4, r5, r4
 ; CHECK-NEXT:    mullw r4, r4, r3
 ; CHECK-NEXT:  .LBB13_2: # %return
 ; CHECK-NEXT:    extsw r3, r4
 ; CHECK-NEXT:    blr
 entry:
   %shl = shl i32 %a, %b
   %cmp = icmp sgt i32 %shl, 1
   br i1 %cmp, label %return, label %if.end

 define i64 @i_a_op_b_2(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: i_a_op_b_2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    slw r5, r3, r4
 ; CHECK-NEXT:    cmpwi r5, 2
 ; CHECK-NEXT:    bgt cr0, .LBB14_2
 ; CHECK-NEXT:  # %bb.1: # %if.end
 ; CHECK-NEXT:    li r5, 1
-; CHECK-NEXT:    isel r4, r5, r4, lt
+; CHECK-NEXT:    isellt r4, r5, r4
 ; CHECK-NEXT:    mullw r4, r4, r3
 ; CHECK-NEXT:  .LBB14_2: # %return
 ; CHECK-NEXT:    extsw r3, r4
 ; CHECK-NEXT:    blr
 entry:
   %shl = shl i32 %a, %b
   %cmp = icmp sgt i32 %shl, 2
   br i1 %cmp, label %return, label %if.end

 
 define i64 @i_a__2(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: i_a__2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpwi r3, -2
 ; CHECK-NEXT:    bgt cr0, .LBB15_2
 ; CHECK-NEXT:  # %bb.1: # %if.end
 ; CHECK-NEXT:    li r5, 1
-; CHECK-NEXT:    isel r4, r5, r4, lt
+; CHECK-NEXT:    isellt r4, r5, r4
 ; CHECK-NEXT:    mullw r4, r4, r3
 ; CHECK-NEXT:  .LBB15_2: # %return
 ; CHECK-NEXT:    extsw r3, r4
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i32 %a, -2
   br i1 %cmp, label %return, label %if.end
 

 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpwi r3, -1
 ; CHECK-NEXT:    ble cr0, .LBB16_2
 ; CHECK-NEXT:  # %bb.1: # %return
 ; CHECK-NEXT:    extsw r3, r4
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB16_2: # %if.end
 ; CHECK-NEXT:    li r5, 1
-; CHECK-NEXT:    isel r4, r5, r4, lt
+; CHECK-NEXT:    isellt r4, r5, r4
 ; CHECK-NEXT:    mullw r4, r4, r3
 ; CHECK-NEXT:    extsw r3, r4
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i32 %a, -1
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry

 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpwi r3, 0
 ; CHECK-NEXT:    ble cr0, .LBB17_2
 ; CHECK-NEXT:  # %bb.1: # %return
 ; CHECK-NEXT:    extsw r3, r4
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB17_2: # %if.end
 ; CHECK-NEXT:    li r5, 1
-; CHECK-NEXT:    isel r4, r5, r4, lt
+; CHECK-NEXT:    isellt r4, r5, r4
 ; CHECK-NEXT:    mullw r4, r4, r3
 ; CHECK-NEXT:    extsw r3, r4
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i32 %a, 0
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry

 
 define i64 @i_a_1(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: i_a_1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpwi r3, 1
 ; CHECK-NEXT:    bgt cr0, .LBB18_2
 ; CHECK-NEXT:  # %bb.1: # %if.end
 ; CHECK-NEXT:    li r5, 1
-; CHECK-NEXT:    isel r4, r5, r4, lt
+; CHECK-NEXT:    isellt r4, r5, r4
 ; CHECK-NEXT:    mullw r4, r4, r3
 ; CHECK-NEXT:  .LBB18_2: # %return
 ; CHECK-NEXT:    extsw r3, r4
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i32 %a, 1
   br i1 %cmp, label %return, label %if.end
 

 
 define i64 @i_a_2(i32 signext %a, i32 signext %b) {
 ; CHECK-LABEL: i_a_2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpwi r3, 2
 ; CHECK-NEXT:    bgt cr0, .LBB19_2
 ; CHECK-NEXT:  # %bb.1: # %if.end
 ; CHECK-NEXT:    li r5, 1
-; CHECK-NEXT:    isel r4, r5, r4, lt
+; CHECK-NEXT:    isellt r4, r5, r4
 ; CHECK-NEXT:    mullw r4, r4, r3
 ; CHECK-NEXT:  .LBB19_2: # %return
 ; CHECK-NEXT:    extsw r3, r4
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp sgt i32 %a, 2
   br i1 %cmp, label %return, label %if.end
 

llvm/test/CodeGen/PowerPC/vec-min-max.ll

 ; NOP8VEC-NEXT:    stxvd2x 0, 0, 3
 ; NOP8VEC-NEXT:    stxvd2x 1, 0, 4
 ; NOP8VEC-NEXT:    ld 3, -24(1)
 ; NOP8VEC-NEXT:    ld 4, -40(1)
 ; NOP8VEC-NEXT:    ld 6, -48(1)
 ; NOP8VEC-NEXT:    cmpd 4, 3
 ; NOP8VEC-NEXT:    li 3, 0
 ; NOP8VEC-NEXT:    li 4, -1
-; NOP8VEC-NEXT:    isel 5, 4, 3, 1
+; NOP8VEC-NEXT:    iselgt 5, 4, 3
 ; NOP8VEC-NEXT:    std 5, -8(1)
 ; NOP8VEC-NEXT:    ld 5, -32(1)
 ; NOP8VEC-NEXT:    cmpd 6, 5
-; NOP8VEC-NEXT:    isel 3, 4, 3, 1
+; NOP8VEC-NEXT:    iselgt 3, 4, 3
 ; NOP8VEC-NEXT:    std 3, -16(1)
 ; NOP8VEC-NEXT:    addi 3, 1, -16
 ; NOP8VEC-NEXT:    lxvd2x 0, 0, 3
 ; NOP8VEC-NEXT:    xxswapd 36, 0
 ; NOP8VEC-NEXT:    xxsel 34, 35, 34, 36
 ; NOP8VEC-NEXT:    blr
 entry:
   %0 = icmp sgt <2 x i64> %a, %b

 ; NOP8VEC-NEXT:    stxvd2x 0, 0, 3
 ; NOP8VEC-NEXT:    stxvd2x 1, 0, 4
 ; NOP8VEC-NEXT:    ld 3, -24(1)
 ; NOP8VEC-NEXT:    ld 4, -40(1)
 ; NOP8VEC-NEXT:    ld 6, -48(1)
 ; NOP8VEC-NEXT:    cmpd 4, 3
 ; NOP8VEC-NEXT:    li 3, 0
 ; NOP8VEC-NEXT:    li 4, -1
-; NOP8VEC-NEXT:    isel 5, 4, 3, 0
+; NOP8VEC-NEXT:    isellt 5, 4, 3
 ; NOP8VEC-NEXT:    std 5, -8(1)
 ; NOP8VEC-NEXT:    ld 5, -32(1)
 ; NOP8VEC-NEXT:    cmpd 6, 5
-; NOP8VEC-NEXT:    isel 3, 4, 3, 0
+; NOP8VEC-NEXT:    isellt 3, 4, 3
 ; NOP8VEC-NEXT:    std 3, -16(1)
 ; NOP8VEC-NEXT:    addi 3, 1, -16
 ; NOP8VEC-NEXT:    lxvd2x 0, 0, 3
 ; NOP8VEC-NEXT:    xxswapd 36, 0
 ; NOP8VEC-NEXT:    xxsel 34, 35, 34, 36
 ; NOP8VEC-NEXT:    blr
 entry:
   %0 = icmp slt <2 x i64> %a, %b

llvm/test/CodeGen/PowerPC/vsx.ll

 ; CHECK-NEXT:    stxvd2x v3, 0, r3
 ; CHECK-NEXT:    stxvd2x v2, 0, r4
 ; CHECK-NEXT:    ld r3, -24(r1)
 ; CHECK-NEXT:    ld r4, -40(r1)
 ; CHECK-NEXT:    ld r6, -48(r1)
 ; CHECK-NEXT:    cmpld r4, r3
 ; CHECK-NEXT:    li r3, 0
 ; CHECK-NEXT:    li r4, -1
-; CHECK-NEXT:    isel r5, r4, r3, lt
+; CHECK-NEXT:    isellt r5, r4, r3
 ; CHECK-NEXT:    std r5, -8(r1)
 ; CHECK-NEXT:    ld r5, -32(r1)
 ; CHECK-NEXT:    cmpld r6, r5
-; CHECK-NEXT:    isel r3, r4, r3, lt
+; CHECK-NEXT:    isellt r3, r4, r3
 ; CHECK-NEXT:    std r3, -16(r1)
 ; CHECK-NEXT:    addi r3, r1, -16
 ; CHECK-NEXT:    lxvd2x v2, 0, r3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-REG-LABEL: test67:
 ; CHECK-REG:       # %bb.0:
 ; CHECK-REG-NEXT:    addi r3, r1, -32
 ; CHECK-REG-NEXT:    addi r4, r1, -48
 ; CHECK-REG-NEXT:    stxvd2x v3, 0, r3
 ; CHECK-REG-NEXT:    stxvd2x v2, 0, r4
 ; CHECK-REG-NEXT:    ld r3, -24(r1)
 ; CHECK-REG-NEXT:    ld r4, -40(r1)
 ; CHECK-REG-NEXT:    ld r6, -48(r1)
 ; CHECK-REG-NEXT:    cmpld r4, r3
 ; CHECK-REG-NEXT:    li r3, 0
 ; CHECK-REG-NEXT:    li r4, -1
-; CHECK-REG-NEXT:    isel r5, r4, r3, lt
+; CHECK-REG-NEXT:    isellt r5, r4, r3
 ; CHECK-REG-NEXT:    std r5, -8(r1)
 ; CHECK-REG-NEXT:    ld r5, -32(r1)
 ; CHECK-REG-NEXT:    cmpld r6, r5
-; CHECK-REG-NEXT:    isel r3, r4, r3, lt
+; CHECK-REG-NEXT:    isellt r3, r4, r3
 ; CHECK-REG-NEXT:    std r3, -16(r1)
 ; CHECK-REG-NEXT:    addi r3, r1, -16
 ; CHECK-REG-NEXT:    lxvd2x v2, 0, r3
 ; CHECK-REG-NEXT:    blr
 ;
 ; CHECK-FISL-LABEL: test67:
 ; CHECK-FISL:       # %bb.0:
 ; CHECK-FISL-NEXT:    addi r3, r1, -32
 ; CHECK-FISL-NEXT:    stxvd2x v3, 0, r3
 ; CHECK-FISL-NEXT:    addi r3, r1, -48
 ; CHECK-FISL-NEXT:    stxvd2x v2, 0, r3
 ; CHECK-FISL-NEXT:    ld r3, -24(r1)
 ; CHECK-FISL-NEXT:    ld r4, -40(r1)
 ; CHECK-FISL-NEXT:    cmpld r4, r3
 ; CHECK-FISL-NEXT:    li r3, 0
 ; CHECK-FISL-NEXT:    li r4, -1
-; CHECK-FISL-NEXT:    isel r5, r4, r3, lt
+; CHECK-FISL-NEXT:    isellt r5, r4, r3
 ; CHECK-FISL-NEXT:    std r5, -8(r1)
 ; CHECK-FISL-NEXT:    ld r5, -32(r1)
 ; CHECK-FISL-NEXT:    ld r6, -48(r1)
 ; CHECK-FISL-NEXT:    cmpld r6, r5
-; CHECK-FISL-NEXT:    isel r3, r4, r3, lt
+; CHECK-FISL-NEXT:    isellt r3, r4, r3
 ; CHECK-FISL-NEXT:    std r3, -16(r1)
 ; CHECK-FISL-NEXT:    addi r3, r1, -16
 ; CHECK-FISL-NEXT:    lxvd2x vs0, 0, r3
 ; CHECK-FISL-NEXT:    xxlor v2, vs0, vs0
 ; CHECK-FISL-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: test67:
 ; CHECK-LE:       # %bb.0:

llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ext.txt

 0x3c 0x43 0xff 0x80
 
 # CHECK: addic 2, 3, -128
 0x30 0x43 0xff 0x80
 
 # CHECK: addic. 2, 3, -128
 0x34 0x43 0xff 0x80
 
-# CHECK: subf 2, 4, 3
+# CHECK: sub 2, 3, 4
 0x7c 0x44 0x18 0x50
 
-# CHECK: subf. 2, 4, 3
+# CHECK: sub. 2, 3, 4
 0x7c 0x44 0x18 0x51
 
-# CHECK: subfc 2, 4, 3
+# CHECK: subc 2, 3, 4
 0x7c 0x44 0x18 0x10
 
-# CHECK: subfc. 2, 4, 3
+# CHECK: subc. 2, 3, 4
 0x7c 0x44 0x18 0x11
 
 # CHECK: cmpdi 2, 3, 128
 0x2d 0x23 0x00 0x80
 
 # CHECK: cmpdi 3, 128
 0x2c 0x23 0x00 0x80
 

 0x38 0x40 0x00 0x80
 
 # CHECK: lis 2, 128
 0x3c 0x40 0x00 0x80
 
 # CHECK: mr 2, 3
 0x7c 0x62 0x1b 0x78
 
-# CHECK: or. 2, 3, 3
+# CHECK: mr. 2, 3
 0x7c 0x62 0x1b 0x79
 
-# CHECK: nor 2, 3, 3
+# CHECK: not 2, 3
 0x7c 0x62 0x18 0xf8
 
-# CHECK: nor. 2, 3, 3
+# CHECK: not. 2, 3
 0x7c 0x62 0x18 0xf9
 
-# CHECK: mtcrf 255, 2
+# CHECK: mtcr 2
 0x7c 0x4f 0xf1 0x20
 
 # CHECK: dss 3
 0x7c 0x60 0x06 0x6c
 # CHECK: dssall
 0x7e 0x00 0x06 0x6c
 # CHECK: dst 12, 11, 3
 0x7c 0x6c 0x5a 0xac

llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-p8htm.txt

 # RUN: llvm-mc --disassemble %s -triple powerpc64-unknown-unknown -mcpu=pwr8 | FileCheck %s
 
 # CHECK: tbegin. 1
 0x7c 0x20 0x05 0x1d
 
 # CHECK: tbegin. 0
 0x7c 0x00 0x05 0x1d
 
-# CHECK: tend. 0
+# CHECK: tend.
 0x7c 0x00 0x05 0x5d
 
-# CHECK: tend. 1
+# CHECK: tendall.
 0x7e 0x00 0x05 0x5d
 
 # CHECK: tabort. 3
 0x7c 0x03 0x07 0x1d
 
 # CHECK: tabortdc. 9, 0, 0
 0x7d 0x20 0x06 0x5d
 
 # CHECK: tabortdci. 1, 0, 3
 0x7c 0x20 0x1e 0xdd
 
 # CHECK: tabortwc. 0, 4, 3
 0x7c 0x04 0x1e 0x1d
 
 # CHECK: tabortwci. 0, 4, 2
 0x7c 0x04 0x16 0x9d
 
-# CHECK: tsr. 1
+# CHECK: tresume.
 0x7c 0x20 0x05 0xdd
 
-# CHECK: tsr. 0
+# CHECK: tsuspend.
 0x7c 0x00 0x05 0xdd
 
 # CHECK: tcheck 0
 0x7c 0x00 0x05 0x9c
 
 # CHECK: treclaim. 3
 0x7c 0x03 0x07 0x5d
 
 # CHECK: trechkpt.
 0x7c 0x00 0x07 0xdd

llvm/test/MC/Disassembler/PowerPC/ppc64-encoding.txt

 0x44 0x00 0x00 0x02
 
 # CHECK: clrbhrb
 0x7c 0x00 0x03 0x5c
 
 # CHECK: mfbhrbe 9, 983
 0x7d 0x3e 0xba 0x5c
 
-# CHECK: rfebb 1
+# CHECK: rfebb
 0x4c 0x00 0x09 0x24
 
 # CHECK: lbz 2, 128(4)                   
 0x88 0x44 0x00 0x80
 
 # CHECK: lbzx 2, 3, 4                    
 0x7c 0x43 0x20 0xae
 

 0x7c 0x43 0x22 0x15
 
 # CHECK: addo 2, 3, 4
 0x7c 0x43 0x26 0x14
 
 # CHECK: addo. 2, 3, 4
 0x7c 0x43 0x26 0x15
 
-# CHECK: subf 2, 3, 4                    
+# CHECK: sub 2, 4, 3                     
 0x7c 0x43 0x20 0x50
 
-# CHECK: subf. 2, 3, 4                   
+# CHECK: sub. 2, 4, 3                    
 0x7c 0x43 0x20 0x51
 
 # CHECK: subfo 2, 3, 4
 0x7c 0x43 0x24 0x50
 
 # CHECK: subfo. 2, 3, 4
 0x7c 0x43 0x24 0x51
 

 0x7c 0x43 0x20 0x15
 
 # CHECK: addco 2, 3, 4
 0x7c 0x43 0x24 0x14
 
 # CHECK: addco. 2, 3, 4
 0x7c 0x43 0x24 0x15
 
-# CHECK: subfc 2, 3, 4                   
+# CHECK: subc 2, 4, 3                    
 0x7c 0x43 0x20 0x10
 
-# CHECK: subfc 2, 3, 4                   
-0x7c 0x43 0x20 0x10
+# CHECK: subc. 2, 4, 3                   
+0x7c 0x43 0x20 0x11
 
 # CHECK: subfco 2, 3, 4
 0x7c 0x43 0x24 0x10
 
 # CHECK: subfco. 2, 3, 4
 0x7c 0x43 0x24 0x11
 
 # CHECK: adde 2, 3, 4                    

llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding.txt

 0x02 0x00 0x00 0x44
 
 # CHECK: clrbhrb
 0x5c 0x03 0x00 0x7c
 
 # CHECK: mfbhrbe 9, 983
 0x5c 0xba 0x3e 0x7d
 
-# CHECK: rfebb 1
+# CHECK: rfebb
 0x24 0x09 0x00 0x4c
 
 # CHECK: lbz 2, 128(4)
 0x80 0x00 0x44 0x88
 
 # CHECK: lbzx 2, 3, 4
 0xae 0x20 0x43 0x7c
 

 0x15 0x22 0x43 0x7c
 
 # CHECK: addo 2, 3, 4
 0x14 0x26 0x43 0x7c
 
 # CHECK: addo. 2, 3, 4
 0x15 0x26 0x43 0x7c
 
-# CHECK: subf 2, 3, 4
+# CHECK: sub 2, 4, 3
 0x50 0x20 0x43 0x7c
 
-# CHECK: subf. 2, 3, 4
+# CHECK: sub. 2, 4, 3
 0x51 0x20 0x43 0x7c
 
 # CHECK: subfo 2, 3, 4
 0x50 0x24 0x43 0x7c
 
 # CHECK: subfo. 2, 3, 4
 0x51 0x24 0x43 0x7c
 

 0x15 0x20 0x43 0x7c
 
 # CHECK: addco 2, 3, 4
 0x14 0x24 0x43 0x7c
 
 # CHECK: addco. 2, 3, 4
 0x15 0x24 0x43 0x7c
 
-# CHECK: subfc 2, 3, 4
+# CHECK: subc 2, 4, 3
 0x10 0x20 0x43 0x7c
 
-# CHECK: subfc 2, 3, 4
-0x10 0x20 0x43 0x7c
+# CHECK: subc. 2, 4, 3
+0x11 0x20 0x43 0x7c
 
 # CHECK: subfco 2, 3, 4
 0x10 0x24 0x43 0x7c
 
 # CHECK: subfco. 2, 3, 4
 0x11 0x24 0x43 0x7c
 
 # CHECK: adde 2, 3, 4

llvm/test/MC/PowerPC/htm.s

 # RUN: llvm-mc -triple powerpc64-unknown-linux-gnu --show-encoding %s | FileCheck -check-prefix=CHECK-BE %s
 # RUN: llvm-mc -triple powerpc64le-unknown-linux-gnu --show-encoding %s | FileCheck -check-prefix=CHECK-LE %s
 
 # CHECK-BE: tbegin. 0                      # encoding: [0x7c,0x00,0x05,0x1d]
 # CHECK-LE: tbegin. 0                      # encoding: [0x1d,0x05,0x00,0x7c]
             tbegin. 0
 # CHECK-BE: tbegin. 1                      # encoding: [0x7c,0x20,0x05,0x1d]
 # CHECK-LE: tbegin. 1                      # encoding: [0x1d,0x05,0x20,0x7c]
             tbegin. 1
 
-# CHECK-BE: tend. 0                        # encoding: [0x7c,0x00,0x05,0x5d]
-# CHECK-LE: tend. 0                        # encoding: [0x5d,0x05,0x00,0x7c]
+# CHECK-BE: tend.                          # encoding: [0x7c,0x00,0x05,0x5d]
+# CHECK-LE: tend.                          # encoding: [0x5d,0x05,0x00,0x7c]
             tend. 0
-# CHECK-BE: tend. 1                        # encoding: [0x7e,0x00,0x05,0x5d]
-# CHECK-LE: tend. 1                        # encoding: [0x5d,0x05,0x00,0x7e]
+# CHECK-BE: tendall.                       # encoding: [0x7e,0x00,0x05,0x5d]
+# CHECK-LE: tendall.                       # encoding: [0x5d,0x05,0x00,0x7e]
             tend. 1
 
 # CHECK-BE: tabort. 9                      # encoding: [0x7c,0x09,0x07,0x1d]
 # CHECK-LE: tabort. 9                      # encoding: [0x1d,0x07,0x09,0x7c]
             tabort. 9
 # CHECK-BE: tabortdc. 0, 9, 9              # encoding: [0x7c,0x09,0x4e,0x5d]
 # CHECK-LE: tabortdc. 0, 9, 9              # encoding: [0x5d,0x4e,0x09,0x7c]
             tabortdc. 0, 9, 9
 # CHECK-BE: tabortdci. 0, 9, 0             # encoding: [0x7c,0x09,0x06,0xdd]
 # CHECK-LE: tabortdci. 0, 9, 0             # encoding: [0xdd,0x06,0x09,0x7c]
             tabortdci. 0, 9, 0
 # CHECK-BE: tabortwc. 0, 9, 9              # encoding: [0x7c,0x09,0x4e,0x1d]
 # CHECK-LE: tabortwc. 0, 9, 9              # encoding: [0x1d,0x4e,0x09,0x7c]
             tabortwc. 0, 9, 9
 # CHECK-BE: tabortwci. 0, 9, 0             # encoding: [0x7c,0x09,0x06,0x9d]
 # CHECK-LE: tabortwci. 0, 9, 0             # encoding: [0x9d,0x06,0x09,0x7c]
             tabortwci. 0, 9, 0
 
-# CHECK-BE: tsr. 0                         # encoding: [0x7c,0x00,0x05,0xdd]
-# CHECK-LE: tsr. 0                         # encoding: [0xdd,0x05,0x00,0x7c]
+# CHECK-BE: tsuspend.                      # encoding: [0x7c,0x00,0x05,0xdd]
+# CHECK-LE: tsuspend.                      # encoding: [0xdd,0x05,0x00,0x7c]
             tsr. 0
-# CHECK-BE: tsr. 1                         # encoding: [0x7c,0x20,0x05,0xdd]
-# CHECK-LE: tsr. 1                         # encoding: [0xdd,0x05,0x20,0x7c]
+# CHECK-BE: tresume.                       # encoding: [0x7c,0x20,0x05,0xdd]
+# CHECK-LE: tresume.                       # encoding: [0xdd,0x05,0x20,0x7c]
             tsr. 1
 
 # CHECK-BE: tcheck 0                       # encoding: [0x7c,0x00,0x05,0x9c]
 # CHECK-LE: tcheck 0                       # encoding: [0x9c,0x05,0x00,0x7c]
             tcheck 0
 # CHECK-BE: tcheck 3                       # encoding: [0x7d,0x80,0x05,0x9c]
 # CHECK-LE: tcheck 3                       # encoding: [0x9c,0x05,0x80,0x7d]
             tcheck 3
 
 # CHECK-BE: treclaim. 9                    # encoding: [0x7c,0x09,0x07,0x5d]
 # CHECK-LE: treclaim. 9                    # encoding: [0x5d,0x07,0x09,0x7c]
             treclaim. 9
 # CHECK-BE: trechkpt.                      # encoding: [0x7c,0x00,0x07,0xdd]
 # CHECK-LE: trechkpt.                      # encoding: [0xdd,0x07,0x00,0x7c]
             trechkpt.

llvm/test/MC/PowerPC/ppc64-encoding.s

 # Branch history rolling buffer
 
 # CHECK-BE: clrbhrb                         # encoding: [0x7c,0x00,0x03,0x5c]
 # CHECK-LE: clrbhrb                         # encoding: [0x5c,0x03,0x00,0x7c]
             clrbhrb
 # CHECK-BE: mfbhrbe 9, 983                  # encoding: [0x7d,0x3e,0xba,0x5c]
 # CHECK-LE: mfbhrbe 9, 983                  # encoding: [0x5c,0xba,0x3e,0x7d]
             mfbhrbe 9, 983
-# CHECK-BE: rfebb 1                         # encoding: [0x4c,0x00,0x09,0x24]
-# CHECK-LE: rfebb 1                         # encoding: [0x24,0x09,0x00,0x4c]
+# CHECK-BE: rfebb                           # encoding: [0x4c,0x00,0x09,0x24]
+# CHECK-LE: rfebb                           # encoding: [0x24,0x09,0x00,0x4c]
             rfebb 1
 
 # Fixed-point facility
 
 # Fixed-point load instructions
 
 # CHECK-BE: lbz 2, 128(4)                   # encoding: [0x88,0x44,0x00,0x80]
 # CHECK-LE: lbz 2, 128(4)                   # encoding: [0x80,0x00,0x44,0x88]

 # CHECK-LE: add. 2, 3, 4                    # encoding: [0x15,0x22,0x43,0x7c]
             add. 2, 3, 4
 # CHECK-BE: addo 2, 3, 4                    # encoding: [0x7c,0x43,0x26,0x14]
 # CHECK-LE: addo 2, 3, 4                    # encoding: [0x14,0x26,0x43,0x7c]
             addo 2, 3, 4
 # CHECK-BE: addo. 2, 3, 4                   # encoding: [0x7c,0x43,0x26,0x15]
 # CHECK-LE: addo. 2, 3, 4                   # encoding: [0x15,0x26,0x43,0x7c]
             addo. 2, 3, 4
-# CHECK-BE: subf 2, 3, 4                    # encoding: [0x7c,0x43,0x20,0x50]
-# CHECK-LE: subf 2, 3, 4                    # encoding: [0x50,0x20,0x43,0x7c]
+# CHECK-BE: sub 2, 4, 3                     # encoding: [0x7c,0x43,0x20,0x50]
+# CHECK-LE: sub 2, 4, 3                     # encoding: [0x50,0x20,0x43,0x7c]
             subf 2, 3, 4
-# CHECK-BE: subf. 2, 3, 4                   # encoding: [0x7c,0x43,0x20,0x51]
-# CHECK-LE: subf. 2, 3, 4                   # encoding: [0x51,0x20,0x43,0x7c]
+# CHECK-BE: sub. 2, 4, 3                    # encoding: [0x7c,0x43,0x20,0x51]
+# CHECK-LE: sub. 2, 4, 3                    # encoding: [0x51,0x20,0x43,0x7c]
             subf. 2, 3, 4
 # CHECK-BE: subfo 2, 3, 4                   # encoding: [0x7c,0x43,0x24,0x50]
 # CHECK-LE: subfo 2, 3, 4                   # encoding: [0x50,0x24,0x43,0x7c]
             subfo 2, 3, 4
 # CHECK-BE: subfo. 2, 3, 4                  # encoding: [0x7c,0x43,0x24,0x51]
 # CHECK-LE: subfo. 2, 3, 4                  # encoding: [0x51,0x24,0x43,0x7c]
             subfo. 2, 3, 4
 # CHECK-BE: addic 2, 3, 128                 # encoding: [0x30,0x43,0x00,0x80]

 # CHECK-LE: addc. 2, 3, 4                   # encoding: [0x15,0x20,0x43,0x7c]
             addc. 2, 3, 4
 # CHECK-BE: addco 2, 3, 4                   # encoding: [0x7c,0x43,0x24,0x14]
 # CHECK-LE: addco 2, 3, 4                   # encoding: [0x14,0x24,0x43,0x7c]
             addco 2, 3, 4
 # CHECK-BE: addco. 2, 3, 4                  # encoding: [0x7c,0x43,0x24,0x15]
 # CHECK-LE: addco. 2, 3, 4                  # encoding: [0x15,0x24,0x43,0x7c]
             addco. 2, 3, 4
-# CHECK-BE: subfc 2, 3, 4                   # encoding: [0x7c,0x43,0x20,0x10]
-# CHECK-LE: subfc 2, 3, 4                   # encoding: [0x10,0x20,0x43,0x7c]
+# CHECK-BE: subc 2, 4, 3                    # encoding: [0x7c,0x43,0x20,0x10]
+# CHECK-LE: subc 2, 4, 3                    # encoding: [0x10,0x20,0x43,0x7c]
             subfc 2, 3, 4
-# CHECK-BE: subfc 2, 3, 4                   # encoding: [0x7c,0x43,0x20,0x10]
-# CHECK-LE: subfc 2, 3, 4                   # encoding: [0x10,0x20,0x43,0x7c]
+# CHECK-BE: subc 2, 4, 3                    # encoding: [0x7c,0x43,0x20,0x10]
+# CHECK-LE: subc 2, 4, 3                    # encoding: [0x10,0x20,0x43,0x7c]
             subfc 2, 3, 4
 # CHECK-BE: subfco 2, 3, 4                  # encoding: [0x7c,0x43,0x24,0x10]
 # CHECK-LE: subfco 2, 3, 4                  # encoding: [0x10,0x24,0x43,0x7c]
             subfco 2, 3, 4
 # CHECK-BE: subfco. 2, 3, 4                 # encoding: [0x7c,0x43,0x24,0x11]
 # CHECK-LE: subfco. 2, 3, 4                 # encoding: [0x11,0x24,0x43,0x7c]
             subfco. 2, 3, 4
 

llvm/test/MC/PowerPC/ppc64-operands.s

 # CHECK-BE: add 0, 0, 0                     # encoding: [0x7c,0x00,0x02,0x14]
 # CHECK-LE: add 0, 0, 0                     # encoding: [0x14,0x02,0x00,0x7c]
             add 0, 0, 0
 
 # CHECK-BE: add 31, 31, 31                  # encoding: [0x7f,0xff,0xfa,0x14]
 # CHECK-LE: add 31, 31, 31                  # encoding: [0x14,0xfa,0xff,0x7f]
             add 31, 31, 31
 
-# CHECK-BE: addi 1, 0, 0                    # encoding: [0x38,0x20,0x00,0x00]
-# CHECK-LE: addi 1, 0, 0                    # encoding: [0x00,0x00,0x20,0x38]
+# CHECK-BE: li 1, 0                         # encoding: [0x38,0x20,0x00,0x00]
+# CHECK-LE: li 1, 0                         # encoding: [0x00,0x00,0x20,0x38]
             addi 1, 0, 0
 
-# CHECK-BE: addi 1, 0, 0                    # encoding: [0x38,0x20,0x00,0x00]
-# CHECK-LE: addi 1, 0, 0                    # encoding: [0x00,0x00,0x20,0x38]
+# CHECK-BE: li 1, 0                         # encoding: [0x38,0x20,0x00,0x00]
+# CHECK-LE: li 1, 0                         # encoding: [0x00,0x00,0x20,0x38]
             addi 1, %r0, 0
 
 # Signed 16-bit immediate operands
 
 # CHECK-BE: addi 1, 2, 0                    # encoding: [0x38,0x22,0x00,0x00]
 # CHECK-LE: addi 1, 2, 0                    # encoding: [0x00,0x00,0x22,0x38]
             addi 1, 2, 0
 
-# CHECK-BE: addi 1, 0, -32768               # encoding: [0x38,0x20,0x80,0x00]
-# CHECK-LE: addi 1, 0, -32768               # encoding: [0x00,0x80,0x20,0x38]
+# CHECK-BE: li 1, -32768                    # encoding: [0x38,0x20,0x80,0x00]
+# CHECK-LE: li 1, -32768                    # encoding: [0x00,0x80,0x20,0x38]
             addi 1, 0, -32768
 
-# CHECK-BE: addi 1, 0, 32767                # encoding: [0x38,0x20,0x7f,0xff]
-# CHECK-LE: addi 1, 0, 32767                # encoding: [0xff,0x7f,0x20,0x38]
+# CHECK-BE: li 1, 32767                     # encoding: [0x38,0x20,0x7f,0xff]
+# CHECK-LE: li 1, 32767                     # encoding: [0xff,0x7f,0x20,0x38]
             addi 1, 0, 32767
 
 # Unsigned 16-bit immediate operands
 
 # CHECK-BE: ori 1, 2, 0                     # encoding: [0x60,0x41,0x00,0x00]
 # CHECK-LE: ori 1, 2, 0                     # encoding: [0x00,0x00,0x41,0x60]
             ori 1, 2, 0
 
 # CHECK-BE: ori 1, 2, 65535                 # encoding: [0x60,0x41,0xff,0xff]
 # CHECK-LE: ori 1, 2, 65535                 # encoding: [0xff,0xff,0x41,0x60]
             ori 1, 2, 65535
 
 # Signed 16-bit immediate operands (extended range for addis)
 
-# CHECK-BE: addis 1, 0, 0                   # encoding: [0x3c,0x20,0x00,0x00]
-# CHECK-LE: addis 1, 0, 0                   # encoding: [0x00,0x00,0x20,0x3c]
+# CHECK-BE: lis 1, 0                        # encoding: [0x3c,0x20,0x00,0x00]
+# CHECK-LE: lis 1, 0                        # encoding: [0x00,0x00,0x20,0x3c]
             addis 1, 0, -65536
 
-# CHECK-BE: addis 1, 0, -1                  # encoding: [0x3c,0x20,0xff,0xff]
-# CHECK-LE: addis 1, 0, -1                  # encoding: [0xff,0xff,0x20,0x3c]
+# CHECK-BE: lis 1, -1                       # encoding: [0x3c,0x20,0xff,0xff]
+# CHECK-LE: lis 1, -1                       # encoding: [0xff,0xff,0x20,0x3c]
             addis 1, 0, 65535
 
 # D-Form memory operands
 
 # CHECK-BE: lwz 1, 0(0)                     # encoding: [0x80,0x20,0x00,0x00]
 # CHECK-LE: lwz 1, 0(0)                     # encoding: [0x00,0x00,0x20,0x80]
             lwz 1, 0(0)